Desktop 5th Gen Core Family Datasheet Vol 1

Desktop 5th Generation Intel® Core™
Processor Family
Datasheet – Volume 1 of 2
Supporting 5th Generation Intel® Core™ Processor based on

Desktop H-Processor Line
June 2015
Order No.: 332376-001v1

You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described
herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed
herein.
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All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and
roadmaps.
The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or visit http://
www.intel.com/design/literature.htm.
Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn
more at http://www.intel.com/ or from the OEM or retailer.
No computer system can be absolutely secure.
Intel® Hyper-Threading Technology (Intel® HT Technology) is available on select Intel® Core™ processors. It requires an Intel® HT Technology enabled
system. Consult your PC manufacturer. Performance will vary depending on the specific hardware and software used. Not available on Intel® Core™
i5-750. For more information including details on which processors support Intel® HT Technology, visit http://www.intel.com/info/hyperthreading.
Intel® High Definition Audio (Intel® HD Audio) requires an Intel® HD Audio enabled system. Consult your PC manufacturer for more information.
Sound quality will depend on equipment and actual implementation. For more information about Intel® HD Audio, refer to http://www.intel.com/
design/chipsets/hdaudio.htm.
Intel® 64 architecture requires a system with a 64-bit enabled processor, chipset, BIOS and software. Performance will vary depending on the specific
hardware and software you use. Consult your PC manufacturer for more information. For more information, visit http://www.intel.com/
content/www/us/en/architecture-and-technology/microarchitecture/intel-64-architecture-general.html.
Intel® Virtualization Technology (Intel® VT) requires a computer system with an enabled Intel® processor, BIOS, and virtual machine monitor (VMM).
Functionality, performance or other benefits will vary depending on hardware and software configurations. Software applications may not be
compatible with all operating systems. Consult your PC manufacturer. For more information, visit http://www.intel.com/go/virtualization.
The original equipment manufacturer must provide TPM functionality, which requires a TPM-supported BIOS. TPM functionality must be initialized and
may not be available in all countries.
For Enhanced Intel SpeedStep® Technology, see the Processor Spec Finder at http://ark.intel.com/ or contact your Intel representative for more
information.
Intel® AES-NI requires a computer system with an AES-NI enabled processor, as well as non-Intel software to execute the instructions in the correct
sequence. AES-NI is available on select Intel® processors. For availability, consult your reseller or system manufacturer. For more information, see
http://software.intel.com/en-us/articles/intel-advanced-encryption-standard-instructions-aes-ni/.
Intel® Active Management Technology (Intel® AMT) should be used by a knowledgeable IT administrator and requires enabled systems, software,
activation, and connection to a corporate network. Intel AMT functionality on mobile systems may be limited in some situations. Your results will
depend on your specific implementation. Learn more by visiting Intel® Active Management Technology.
No computer system can provide absolute security under all conditions. Intel® Trusted Execution Technology (Intel® TXT) requires a computer with
Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured
launched environment (MLE). Intel TXT also requires the system to contain a TPM v1.s. For more information, visit http://www.intel.com/technology/
security.
Requires a system with Intel® Turbo Boost Technology. Intel Turbo Boost Technology and Intel Turbo Boost Technology 2.0 are only available on select
Intel® processors. Consult your PC manufacturer. Performance varies depending on hardware, software, and system configuration. For more
information, visit https://www-ssl.intel.com/content/www/us/en/architecture-and-technology/turbo-boost/turbo-boost-technology.html.
Intel® Advanced Vector Extensions (Intel® AVX) are designed to achieve higher throughput to certain integer and floating point operations. Due to
varying processor power characteristics, utilizing AVX instructions may cause a) some parts to operate at less than the rated frequency and b) some
parts with Intel® Turbo Boost Technology 2.0 to not achieve any or maximum turbo frequencies. Performance varies depending on hardware, software,
and system configuration and you should consult your system manufacturer for more information. Intel® Advanced Vector Extensions refers to Intel®
AVX, Intel® AVX2 or Intel® AVX-512. For more information on Intel® Turbo Boost Technology 2.0, visit https://www-ssl.intel.com/content/www/us/en/
architecture-and-technology/turbo-boost/turbo-boost-technology.html
Intel, Intel Core, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2015, Intel Corporation. All rights reserved.
Desktop 5th Generation Intel® Core™ Processor Family

Datasheet – Volume 1 of 2 June 2015
2 Order No.: 332376-001v1
Contents—Processor
Contents
Revision History..................................................................................................................9
1.0 Introduction................................................................................................................10
1.1 Supported Technologies.........................................................................................11
1.2 Interfaces............................................................................................................ 12
1.3 Power Management Support...................................................................................12
1.4 Thermal Management Support................................................................................13
1.5 Package Support...................................................................................................13
1.6 Processor Testability............................................................................................. 13
1.7 Terminology.........................................................................................................13
1.8 Related Documents............................................................................................... 17
2.0 Interfaces................................................................................................................... 18
2.1 System Memory Interface...................................................................................... 18
2.1.1 System Memory Technology Supported.......................................................19
2.1.2 System Memory Timing Support................................................................. 20
2.1.3 System Memory Organization Modes........................................................... 20
2.1.4 System Memory Frequency........................................................................ 22
2.1.5 Intel® Fast Memory Access (Intel® FMA) Technology Enhancements............... 22
2.1.6 Data Scrambling....................................................................................... 22
2.2 PCI Express* Interface.......................................................................................... 23
2.2.1 PCI Express* Support................................................................................ 23
2.2.2 PCI Express* Architecture.......................................................................... 24
2.2.3 PCI Express* Configuration Mechanism........................................................ 24
2.3 Direct Media Interface (DMI).................................................................................. 26
2.4 Processor Graphics................................................................................................28
2.5 Processor Graphics Controller (GT)..........................................................................28
2.5.1 3D and Video Engines for Graphics Processing.............................................. 29
2.5.2 Multi Graphics Controllers Multi-Monitor Support........................................... 31
2.6 Digital Display Interface (DDI)................................................................................31
2.7 Intel® Flexible Display Interface (Intel® FDI)............................................................ 37
2.8 Platform Environmental Control Interface (PECI)....................................................... 37
2.8.1 PECI Bus Architecture................................................................................37
3.0 Technologies............................................................................................................... 39
3.1 Intel® Virtualization Technology (Intel® VT)............................................................. 39
3.2 Intel® Trusted Execution Technology (Intel® TXT)..................................................... 43
3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)....................................... 44
3.4 Intel® Turbo Boost Technology 2.0..........................................................................45
3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)................................................45
3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI).......................46
3.7 Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)..... 46
3.8 Intel® 64 Architecture x2APIC................................................................................ 47
3.9 Power Aware Interrupt Routing (PAIR).................................................................... 48
3.10 Execute Disable Bit..............................................................................................48
3.11 Supervisor Mode Execution Protection (SMEP)........................................................48

June 2015 Datasheet – Volume 1 of 2
Order No.: 332376-001v1 3
Processor—Contents
4.0 Power Management.................................................................................................... 49

4.1 Advanced Configuration and Power Interface (ACPI) States Supported......................... 50
4.2 Processor Core Power Management......................................................................... 51
4.2.1 Enhanced Intel SpeedStep® Technology Key Features....................................51
4.2.2 Low-Power Idle States............................................................................... 52
4.2.3 Requesting Low-Power Idle States...............................................................53
4.2.4 Core C-State Rules....................................................................................54
4.2.5 Package C-States......................................................................................55
4.2.6 Package C-States and Display Resolutions.................................................... 58
4.3 Integrated Memory Controller (IMC) Power Management............................................60
4.3.1 Disabling Unused System Memory Outputs................................................... 60
4.3.2 DRAM Power Management and Initialization..................................................60
4.3.3 DRAM Running Average Power Limitation (RAPL) .........................................63
4.3.4 DDR Electrical Power Gating (EPG).............................................................. 63
4.4 PCI Express* Power Management............................................................................63
4.5 Direct Media Interface (DMI) Power Management...................................................... 63
4.6 Graphics Power Management..................................................................................63
4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)................................63
4.6.2 Graphics Render C-State............................................................................63
4.6.3 Intel® Graphics Dynamic Frequency............................................................ 64
5.0 Thermal Management................................................................................................. 65
5.1 Desktop Processor Thermal Profiles......................................................................... 66
5.1.1 Processor Thermal Profile........................................................................... 67
5.2 Thermal Metrology................................................................................................ 68
5.3 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1.............................. 68
5.4 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0.............................. 70
5.5 Thermal Specifications...........................................................................................71
5.6 Processor Temperature..........................................................................................72
5.7 Adaptive Thermal Monitor...................................................................................... 72
5.8 THERMTRIP# Signal.............................................................................................. 75
5.9 Digital Thermal Sensor.......................................................................................... 76
5.9.1 Digital Thermal Sensor Accuracy (Taccuracy)................................................76
5.10 Intel® Turbo Boost Technology Thermal Considerations............................................77
5.10.1 Intel® Turbo Boost Technology Power Control and Reporting.........................77
5.10.2 Package Power Control.............................................................................78
6.0 Signal Description....................................................................................................... 79
6.1 System Memory Interface Signals........................................................................... 79
6.2 Memory Reference and Compensation Signals.......................................................... 81
6.3 Reset and Miscellaneous Signals............................................................................. 82
6.4 PCI Express* Interface Signals............................................................................... 83
6.5 Display Interface Signals....................................................................................... 83
6.6 Direct Media Interface (DMI).................................................................................. 83
6.7 Phase Locked Loop (PLL) Signals.............................................................................84
6.8 Testability Signals.................................................................................................84
6.9 Error and Thermal Protection Signals....................................................................... 85
6.10 Power Sequencing Signals.................................................................................... 85
6.11 Processor Power Signals.......................................................................................86
6.12 Sense Signals..................................................................................................... 86
6.13 Ground and Non-Critical to Function (NCTF) Signals.................................................86

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Contents—Processor
6.14 Processor Internal Pull-Up / Pull-Down Terminations................................................ 87

7.0 Electrical Specifications.............................................................................................. 88
7.1 Integrated Voltage Regulator..................................................................................88
7.2 Power and Ground Lands ...................................................................................... 88
7.3 VCC Voltage Identification (VID).............................................................................. 88
7.4 Reserved or Unused Signals................................................................................... 93
7.5 Signal Groups.......................................................................................................93
7.6 Test Access Port (TAP) Connection.......................................................................... 95
7.7 DC Specifications................................................................................................. 95
7.8 Voltage and Current Specifications.......................................................................... 96
8.0 Package Specifications..............................................................................................102
8.1 LGA Package Specifications.................................................................................. 102
8.1.1 Package Mechanical Drawing.................................................................... 102
8.1.2 Processor Component Keep-Out Zone........................................................ 102
8.1.3 Package Loading Specifications................................................................. 103
8.1.4 Package Handling Guidelines.................................................................... 103
8.1.5 Package Insertion Specifications................................................................103
8.1.6 Processor Mass Specification.....................................................................104
8.1.7 Processor Materials..................................................................................104
8.1.8 Processor Markings..................................................................................104
8.1.9 Processor Land Coordinates...................................................................... 104
8.1.10 Processor Storage Specifications..............................................................106
8.2 BGA Package Specifications.................................................................................. 107
8.2.1 Package Mechanical Specifications............................................................. 107
8.2.2 Package Loading Specifications................................................................. 108
8.2.3 Package Storage Specifications................................................................. 108
9.0 Processor Ball and Signal Information...................................................................... 109

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Processor—Figures
Figures
1 Platform Block Diagram ........................................................................................... 11
2 Intel® Flex Memory Technology Operations................................................................. 21
3 PCI Express* Related Register Structures in the Processor............................................ 25
4 PCI Express* Typical Operation 16 Lanes Mapping....................................................... 26
5 Processor Graphics Controller Unit Block Diagram........................................................ 29
6 Processor Display Architecture...................................................................................32
7 DisplayPort* Overview............................................................................................. 33
8 HDMI* Overview..................................................................................................... 34
9 PECI Host-Clients Connection Example....................................................................... 38
10 Device to Domain Mapping Structures........................................................................ 42
11 Processor Power States............................................................................................ 49
12 Idle Power Management Breakdown of the Processor Cores .......................................... 52
13 Thread and Core C-State Entry and Exit......................................................................53
14 Package C-State Entry and Exit................................................................................. 57
15 Thermal Test Vehicle Thermal Profile for Processor ...................................................... 67
16 Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location..................68
17 Digital Thermal Sensor (DTS) 1.1 Definition Points....................................................... 69
18 Digital Thermal Sensor (DTS) Thermal Profile Definition................................................71
19 Package Power Control............................................................................................. 78
20 Processor Package Assembly Sketch.........................................................................102
21 Processor Top-Side Markings................................................................................... 104
22 Processor Package Land Coordinates........................................................................ 105
23 2014 Processor Package Land/Pin Side Components................................................... 106

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Tables—Processor
Tables
1 Terminology........................................................................................................... 13
2 Related Documents..................................................................................................17
3 Supported UDIMM Module Configurations....................................................................19
4 Supported SO-DIMM Module Configurations (AIO Only)................................................ 20
5 DDR3 / DDR3L System Memory Timing Support...........................................................20
6 PCI Express* Supported Configurations in Desktop Products..........................................23
7 Processor Supported Audio Formats over HDMI*and DisplayPort*.................................. 35
8 Valid Three Display Configurations through the Processor..............................................36
9 DisplayPort and embedded DisplayPort* Resolutions for 1, 2, 4 Lanes – Link Data
Rate of RBR, HBR, and HBR2.....................................................................................36
10 System States.........................................................................................................50
11 Processor Core / Package State Support..................................................................... 50
12 Integrated Memory Controller States..........................................................................50
13 PCI Express* Link States.......................................................................................... 50
14 Direct Media Interface (DMI) States........................................................................... 51
15 G, S, and C Interface State Combinations .................................................................. 51
16 D, S, and C Interface State Combination.....................................................................51
17 Coordination of Thread Power States at the Core Level................................................. 53
18 Coordination of Core Power States at the Package Level............................................... 56
19 Deepest Package C-State Available............................................................................ 59
20 Desktop Processor Thermal Specifications................................................................... 66
21 Thermal Test Vehicle Thermal Profile for Processor ......................................................67
22 Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above TCONTROL............. 70
23 Thermal Margin Slope.............................................................................................. 71
24 Boundary Conditions, Performance Targets, and TCASE Specifications.............................. 72
25 Signal Description Buffer Types................................................................................. 79
26 Memory Channel A Signals........................................................................................79
27 Memory Channel B Signals........................................................................................80
28 Memory Reference and Compensation Signals............................................................. 81
29 Reset and Miscellaneous Signals................................................................................ 82
30 PCI Express* Graphics Interface Signals..................................................................... 83
31 Display Interface Signals.......................................................................................... 83
32 Direct Media Interface (DMI) – Processor to PCH Serial Interface................................... 83
33 Phase Locked Loop (PLL) Signals............................................................................... 84
34 Testability Signals....................................................................................................84
35 Error and Thermal Protection Signals..........................................................................85
36 Power Sequencing Signals........................................................................................ 85
37 Processor Power Signals........................................................................................... 86
38 Sense Signals......................................................................................................... 86
39 Ground and Non-Critical to Function (NCTF) Signals..................................................... 86
40 Processor Internal Pull-Up / Pull-Down Terminations.................................................... 87
41 Voltage Regulator (VR) 12.5 Voltage Identification....................................................... 89
42 Signal Groups......................................................................................................... 93
43 Processor Core Active and Idle Mode DC Voltage and Current Specifications.................... 96
44 Memory Controller (VDDQ) Supply DC Voltage and Current Specifications.........................97
45 VCCIO_OUT, VCOMP_OUT, and VCCIO_TERM ............................................................. 97
46 DDR3 / DDR3L Signal Group DC Specifications............................................................ 98
47 Digital Display Interface Group DC Specifications......................................................... 99
48 embedded DisplayPort* (eDP*) Group DC Specifications............................................. 100
49 CMOS Signal Group DC Specifications....................................................................... 100
50 GTL Signal Group and Open Drain Signal Group DC Specifications................................ 100
51 PCI Express* DC Specifications................................................................................101
52 Processor Loading Specifications.............................................................................. 103
53 Package Handling Guidelines................................................................................... 103

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Processor—Tables
54 Processor Materials................................................................................................ 104

55 Processor Storage Specifications.............................................................................. 106
56 Package Mechanical Attributes................................................................................. 107
57 Package Loading Specifications................................................................................ 108
58 BGA Package Storage Conditions............................................................................. 108
59 Processor LGA1150 Ball List by Signal Name..............................................................109
60 BGA1364 Processor Ball List by Signal Name............................................................. 120

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Revision History—Processor
Revision History
Revision Description Date
001 • Initial Release June 2015

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Processor—Introduction
1.0 Introduction
The 5th Generation Intel® Core™ processors based on Desktop H-Processor Line are
64-bit, multi-core processors built on 14-nanometer process technology.
The processors are designed for a two-chip platform consisting of a processor and
Platform Controller Hub (PCH). The processors are designed to be used with the Intel®
9 Series chipset. These processors are "drop-in" compatible with the Desktop 4th
Generation Intel® Core™ processor family. See the following figure for an example
platform block diagram.
Throughout this document, the 5th Generation Intel® Core™ processor based on
Desktop H-Processor Line may be referred to simply as "processor".
Throughout this document, the Desktop 5th Generation Intel® Core™ processor family
refers to the Desktop 5th Generation Intel® Core™ i7-5775C, i7-5775R, i5-5675C,
i5-5675R, and i5-5575R processors.
Note: Refer to the processor Specification Update document for additional SKU details.

10 Order No.: 332376-001v1
Introduction—Processor
Figure 1. Platform Block Diagram
PCI Express* 3.0 2 DIMMs / CH
CH A
Digital Display Processor System Memory
CH B
Interface (DDI)
(3 interfaces)
Intel® Flexible Display

Direct Media Interface 2.0
Interface (Intel® FDI)
(DMI 2.0) (x4)
(x2)
USB 3.0 Analog Display

(up to 6 Ports) (VGA)
USB 2.0
Integrated LAN
(8 Ports)
Platform Controller
Hub (PCH)
SATA, 6 GB/s PCI Express* 2.0
(up to 6 Ports) (up to 8 Ports)
SPI Intel® High

SPI Flash
Definition Audio
(Intel® HD Audio)
LPC
Trusted Platform SMBus 2.0
Module (TPM) 1.2
GPIOs
Super IO / EC
1.1 Supported Technologies

• On-package Cache Memory integrated within the processor based on Mobile H-
Processor line with up to GT3 graphics
• Intel® Virtualization Technology (Intel® VT)
• Intel® Active Management Technology 10.0 (Intel® AMT )
• Intel® Trusted Execution Technology (Intel® TXT)
• Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
• Intel® Hyper-Threading Technology (Intel® HT Technology)
• Intel® 64 Architecture

Order No.: 332376-001v1 11
• Execute Disable Bit

• Intel® Turbo Boost Technology 2.0
• Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)
• Intel® Device Protection Technology with Intel® Advanced Encryption Standard
New Instructions (Intel® AES-NI)
• PCLMULQDQ Instruction
• Intel® Device Protection Technology with Intel® Secure Key
• Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-
NI)
• PAIR – Power Aware Interrupt Routing
• SMEP – Supervisor Mode Execution Protection
• SMAP - Supervisor Mode Access Protection
• Intel® Device Protection Technology with Boot Guard
• DRAM Bit-Error Recovery (DBER)
• Enhanced Intel Speedstep® Technology
Note: The availability of the features may vary between processor SKUs.
1.2 Interfaces
The processor supports the following interfaces:
• DDR3/DDR3L
• Direct Media Interface (DMI)
• Digital Display Interface (DDI)
• PCI Express*
1.3 Power Management Support
Processor Core
• Full support of ACPI C-states as implemented by the following processor C-states:
— C0, C1, C1E, C3, C6
• Enhanced Intel SpeedStep® Technology
System
• S0, S3, S4, S5
Memory Controller
• Conditional self-refresh
• Dynamic power-down
PCI Express*
• L0s and L1 ASPM power management capability

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DMI
• L0s and L1 ASPM power management capability
Processor Graphics Controller

• Intel® Rapid Memory Power Management (Intel® RMPM)
• Intel® Smart 2D Display Technology (Intel® S2DDT)
• Graphics Render C-state (RC6)
• Intel® Seamless Display Refresh Rate Switching with eDP port
• Intel® Display Power Saving Technology (Intel® DPST)
1.4 Thermal Management Support

• Digital Thermal Sensor
• Adaptive Thermal Monitor
• THERMTRIP# and PROCHOT# support
• On-Demand Mode
• Memory Open and Closed Loop Throttling
• Memory Thermal Throttling
• External Thermal Sensor (TS-on-DIMM and TS-on-Board)
• Render Thermal Throttling
• Fan speed control with DTS
1.5 Package Support

The Desktop processor is available in the following packages:
• 37.5 x 37.5 mm Flip Chip Land Grid Array (FCLGA 1150). The socket type is
LGA1150
• 37.5 mm x 32 mm BGA package (BGA1364)
1.6 Processor Testability

The processor includes boundary-scan for board and system level testability.
1.7 Terminology
Table 1. Terminology
Term Description
APD Active Power-down
B/D/F Bus/Device/Function
BGA Ball Grid Array
BLC Backlight Compensation
BLT Block Level Transfer

continued...

Order No.: 332376-001v1 13
Term Description
BPP Bits per pixel
CKE Clock Enable
CLTM Closed Loop Thermal Management
DDI Digital Display Interface
DDR3 Third-generation Double Data Rate SDRAM memory technology
DLL Delay-Locked Loop
DMA Direct Memory Access
DMI Direct Media Interface
DP DisplayPort*
DTS Digital Thermal Sensor
Digital Visual Interface. DVI* is the interface specified by the DDWG (Digital Display
DVI*
Working Group)
EC Embedded Controller
ECC Error Correction Code
eDP* embedded DisplayPort*
EPG Electrical Power Gating
EU Execution Unit
FMA Floating-point fused Multiply Add instructions
FSC Fan Speed Control
HDCP High-bandwidth Digital Content Protection
HDMI* High Definition Multimedia Interface
HFM High Frequency Mode
iDCT Inverse Discrete Cosine Transform
IHS Integrated Heat Spreader
GFX Graphics
GSA Graphics in System Agent
GUI Graphical User Interface
IMC Integrated Memory Controller
Intel®64 64-bit memory extensions to the IA-32 architecture

Technology
Intel® DPST Intel Display Power Saving Technology
Intel® FDI Intel Flexible Display Interface
Intel® TSX-NI Intel Transactional Synchronization Extensions - New Instructions
Intel® TXT Intel Trusted Execution Technology
Intel Virtualization Technology. Processor virtualization, when used in conjunction

Intel® VT with Virtual Machine Monitor software, enables multiple, robust independent software
environments inside a single platform.
continued...

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Term Description
Intel Virtualization Technology (Intel VT) for Directed I/O. Intel VT-d is a hardware
assist, under system software (Virtual Machine Manager or OS) control, for enabling
Intel® VT-d
I/O device virtualization. Intel VT-d also brings robust security by providing protection
from errant DMAs by using DMA remapping, a key feature of Intel VT-d.
IOV I/O Virtualization
ISI Inter-Symbol Interference
ITPM Integrated Trusted Platform Module
LCD Liquid Crystal Display
Low Frequency Mode. LFM is Pn in the P-state table. It can be read at MSR CEh
LFM
[47:40].
LFP Local Flat Panel
LPDDR3 Low-Power Third-generation Double Data Rate SDRAM memory technology
MCP Multi-Chip Package
Minimum Frequency Mode. MFM is the minimum ratio supported by the processor and
MFM
can be read from MSR CEh [55:48].
MLE Measured Launched Environment
MLC Mid-Level Cache
MSI Message Signaled Interrupt
MSL Moisture Sensitive Labeling
MSR Model Specific Registers
Non-Critical to Function. NCTF locations are typically redundant ground or non-critical

NCTF reserved, so the loss of the solder joint continuity at end of life conditions will not
affect the overall product functionality.
ODT On-Die Termination
OLTM Open Loop Thermal Management
Platform Compatibility Guide (PCG) (previously known as FMB) provides a design

PCG
target for meeting all planned processor frequency requirements.
Platform Controller Hub. The chipset with centralized platform capabilities including
PCH the main I/O interfaces along with display connectivity, audio features, power
management, manageability, security, and storage features.
The Platform Environment Control Interface (PECI) is a one-wire interface that

PECI provides a communication channel between Intel processor and chipset components
to external monitoring devices.
Case-to-ambient thermal characterization parameter (psi). A measure of thermal

Ψ ca solution performance using total package power. Defined as (TCASE - TLA ) / Total
Package Power.
PCI Express* Graphics. External Graphics using PCI Express* Architecture. It is a

PEG high-speed serial interface where configuration is software compatible with the
existing PCI specifications.
PL1, PL2 Power Limit 1 and Power Limit 2
PPD Pre-charge Power-down
Processor The 64-bit multi-core component (package)

continued...

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Term Description
The term “processor core” refers to Si die itself, which can contain multiple execution
Processor Core cores. Each execution core has an instruction cache, data cache, and 256-KB L2
cache. All execution cores share the L3 cache.
Processor Graphics Intel Processor Graphics
A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC. These
Rank
devices are usually, but not always, mounted on a single side of a SO-DIMM.
SCI System Control Interrupt. SCI is used in the ACPI protocol.
SF Strips and Fans
SMM System Management Mode
SMX Safer Mode Extensions
A non-operational state. The processor may be installed in a platform, in a tray, or

loose. Processors may be sealed in packaging or exposed to free air. Under these
conditions, processor landings should not be connected to any supply voltages, have
Storage Conditions any I/Os biased, or receive any clocks. Upon exposure to “free air” (that is, unsealed
packaging or a device removed from packaging material), the processor must be
handled in accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
SVID Serial Voltage Identification
TAC Thermal Averaging Constant
TAP Test Access Point
The case temperature of the processor, measured at the geometric center of the top-
TCASE
side of the TTV IHS.
TCC Thermal Control Circuit
TCONTROL is a static value that is below the TCC activation temperature and used as a
TCONTROL trigger point for fan speed control. When DTS > TCONTROL, the processor must comply
to the TTV thermal profile.
Thermal Design Power: Thermal solution should be designed to dissipate this target
TDP
power level. TDP is not the maximum power that the processor can dissipate.
TLB Translation Look-aside Buffer
Thermal Test Vehicle. A mechanically equivalent package that contains a resistive

TTV
heater in the die to evaluate thermal solutions.
Thermal Monitor. A power reduction feature designed to decrease temperature after

TM
the processor has reached its maximum operating temperature.
VCC Processor core power supply
VDDQ DDR3/DDR3L power supply.
VF Vertex Fetch
VID Voltage Identification
VS Vertex Shader
VLD Variable Length Decoding
VMM Virtual Machine Monitor
VR Voltage Regulator
VSS Processor ground
x1 Refers to a Link or Port with one Physical Lane

continued...

16 Order No.: 332376-001v1
Term Description
x2 Refers to a Link or Port with two Physical Lanes
x4 Refers to a Link or Port with four Physical Lanes
x8 Refers to a Link or Port with eight Physical Lanes
x16 Refers to a Link or Port with sixteen Physical Lanes
1.8 Related Documents

Table 2. Related Documents
Document Document
Number /
Location
Desktop 5th Generation Intel® Core™ Processor Family Datasheet, Volume 2 of 2 332377
Mobile 5th Generation Intel® Core™ Processor Family Datasheet, Volume 2 of 2 332379
Mobile/Desktop 5th Generation Intel® Core™ Processor Family Specification Update 332381
Intel® 9 Series Chipset Family Platform Controller Hub (PCH) 330550
http://
Advanced Configuration and Power Interface 3.0
www.acpi.info/
http://
PCI Local Bus Specification 3.0 www.pcisig.com/
specifications
http://
PCI Express Base Specification, Revision 2.0
www.pcisig.com
http://
DDR3 SDRAM Specification
www.jedec.org
http://
DisplayPort* Specification
www.vesa.org
http://
www.intel.com/
Intel® 64 and IA-32 Architectures Software Developer's Manuals
products/processor/
manuals/index.htm

Order No.: 332376-001v1 17
Processor—Interfaces
2.0 Interfaces
2.1 System Memory Interface

• Two channels of DDR3/DDR3L Unbuffered Dual In-Line Memory Modules (UDIMM)
or DDR3/DDR3L Unbuffered Small Outline Dual In-Line Memory Modules (SO-
DIMM) with a maximum of two DIMMs per channel.
• Single-channel and dual-channel memory organization modes
• Data burst length of eight for all memory organization modes
• Memory data transfer rates of 1333 MT/s, 1600 MT/s, and 1866 MT/s
• 64-bit wide channels
• DDR3/DDR3L I/O Voltage of 1.5 V for Desktop
• The type of the DIMM modules supported by the processor is dependent on the
PCH SKU in the target platform:
— Desktop PCH platforms support non-ECC UDIMMs only
— All In One platforms (AIO) support SO-DIMMs
• Theoretical maximum memory bandwidth of:
— 21.3 GB/s in dual-channel mode assuming 1333 MT/s
• 1Gb, 2Gb, and 4Gb DDR3/DDR3L DRAM device technologies are supported
— Using 4Gb DRAM device technologies, the largest system memory capacity
possible is 32 GB, assuming Dual Channel Mode with four x8 dual ranked
DIMM memory configuration
• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank
devices)
• Processor on-die VREF generation for DDR DQ Read and Write as well as
CMD/ADD
• Command launch modes of 1n/2n
• On-Die Termination (ODT)
• Asynchronous ODT
• Intel Fast Memory Access (Intel FMA):
— Just-in-Time Command Scheduling
— Command Overlap
— Out-of-Order Scheduling

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Interfaces—Processor
2.1.1 System Memory Technology Supported

The Integrated Memory Controller (IMC) supports DDR3/DDR3L protocols with two
independent, 64-bit wide channels, each accessing one or two DIMMs. The type of
memory supported by the processor is dependent on the PCH SKU in the target
platform.
Note: The IMC supports a maximum of two DDR3/DDR3L DIMMs per channel; thus, allowing
up to four device ranks per channel.
Note: The support of DDR3/DDR3L frequencies and number of DIMMs per channel is SKU
dependent.
DDR3/DDR3L Data Transfer Rates:

• 1333 MT/s (PC3-10600)
• 1600 MT/s (PC3-12800)
• 1866 MT/s (PC3-14900)
AIO platform DDR3/DDR3L SO-DIMM Modules:

• Raw Card B – Single Ranked x8 unbuffered non-ECC
• Raw Card F – Dual Ranked x8 (planar) unbuffered non-ECC
Desktop platform UDIMM Modules:

• Raw Card A – Single Ranked x8 unbuffered non-ECC
• Raw Card B – Dual Ranked x8 unbuffered non-ECC
• Standard 1Gb, 2Gb, and 4Gb technologies and addressing are supported for x8
devices. There is no support for memory modules with different technologies or
capacities on opposite sides of the same memory module. If one side of a memory
module is populated, the other side is either identical or empty.
Table 3. Supported UDIMM Module Configurations

Raw DIMM DRAM DRAM # of # of # of # of Page Size
Card Capacity Device Organization DRAM Physical Row / Col Banks
Version Technology Devices Devices Address Inside
Ranks Bits DRAM
Desktop Platforms
Unbuffered / Non-ECC Supported DIMM Module Configurations
A 1 GB 1 Gb 128 M X 8 8 1 14/10 8 8K
2 GB 1 Gb 128 M X 8 16 2 14/10 8 8K
4 GB 2 Gb 256 M X 8 16 2 15/10 8 8K
B
4 GB 4 Gb 512 M X 8 8 1 15/10 8 8K
8 GB 4 Gb 512 M X 8 16 2 16/10 8 8K
Note: DIMM module support is based on availability and is subject to change.

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Table 4. Supported SO-DIMM Module Configurations (AIO Only)

Raw Card DIMM DRAM # of DRAM # of Row/Col # of Banks Page Size
Version Capacity Organization Devices Address Bits Inside DRAM
1 GB 128 M x 8 8 14/10 8 8K
B 2 GB 256 M x 8 8 15/10 8 8K
4 GB 512 M x 8 8 16/10 8 8K
2 GB 128 M x 8 16 14/10 8 8K
F 4 GB 256 M x 8 16 15/10 8 8K
8 GB 512 M x 8 16 16/10 8 8K
Note: System memory configurations are based on availability and are subject to change.
2.1.2 System Memory Timing Support

The IMC supports the following DDR3/DDR3L Speed Bin, CAS Write Latency (CWL),
and command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1N indicates a new command may be issued every
clock and 2N indicates a new command may be issued every 2 clocks. Command
launch mode programming depends on the transfer rate and memory
configuration.
Table 5. DDR3 / DDR3L System Memory Timing Support

Segment Transfer Rate tCL (tCK) tRCD tRP CWL DPC CMD
(MT/s) (tCK) (tCK) (tCK) Mode
1 1N/2N
1333 8/9 8/9 8/9 7
2 2N
LGA1150 and
BGA1364
1 1N/2N
1600 10/11 10/11 10/11 8
2 2N
1 1N/2N
BGA1364 Only 1866 13 12/13 12/13 9
2 2N
Note: System memory timing support is based on availability and is subject to change.
2.1.3 System Memory Organization Modes

The Integrated Memory Controller (IMC) supports two memory organization modes –
single-channel and dual-channel. Depending upon how the DIMM Modules are
populated in each memory channel, a number of different configurations can exist.

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Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated in any
order, but not both.
Dual-Channel Mode – Intel® Flex Memory Technology Mode
The IMC supports Intel Flex Memory Technology Mode. Memory is divided into
symmetric and asymmetric zones. The symmetric zone starts at the lowest address in
each channel and is contiguous until the asymmetric zone begins or until the top
address of the channel with the smaller capacity is reached. In this mode, the system
runs with one zone of dual-channel mode and one zone of single-channel mode,
simultaneously, across the whole memory array.
Note: Channels A and B can be mapped for physical channel 0 and 1 respectively or vice
versa; however, channel A size must be greater or equal to channel B size.
Figure 2. Intel® Flex Memory Technology Operations
TOM
C Non interleaved
access
B
C
Dual channel
interleaved access
B B
B
CH A CH B
CH A and CH B can be configured to be physical channels 0 or 1

B – The largest physical memory amount of the smaller size memory module
C – The remaining physical memory amount of the larger size memory module
Dual-Channel Symmetric Mode
Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum

performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request
can be sent before data from the first request has returned. If two consecutive cache
lines are requested, both may be retrieved simultaneously, since they are ensured to
be on opposite channels. Use Dual-Channel Symmetric mode when both Channel A
and Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, the
IMC operates completely in Dual-Channel Symmetric mode.

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Note: The DRAM device technology and width may vary from one channel to the other.
2.1.4 System Memory Frequency

In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports one or two DIMM
connectors per channel. The usage of DIMM modules with different latencies is
allowed, but in that case, the worst latency (among two channels) will be used. For
dual-channel modes, both channels must have a DIMM connector populated and for
single-channel mode only a single channel may have one or both DIMM connectors
populated.
Note: In a two-DIMM Per Channel (2DPC) layout memory configuration, the furthest DIMM
from the processor of any given channel must always be populated first.
2.1.5 Intel® Fast Memory Access (Intel® FMA) Technology

Enhancements
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel FMA technology enhancements.
Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, the requests can be started
without interfering with the current request allowing for concurrent issuing of
requests. This allows for optimized bandwidth and reduced latency while maintaining
appropriate command spacing to meet system memory protocol.
Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Pre-charge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,

the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back-to-back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the
IMC to further reduce latency and increase bandwidth efficiency.
2.1.6 Data Scrambling

The memory controller incorporates a DDR3/DDR3L Data Scrambling feature to
minimize the impact of excessive di/dt on the platform DDR3/DDR3L VRs due to
successive 1s and 0s on the data bus. Past experience has demonstrated that traffic

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on the data bus is not random and can have energy concentrated at specific spectral
harmonics creating high di/dt which is generally limited by data patterns that excite
resonance between the package inductance and on die capacitances. As a result the
memory controller uses a data scrambling feature to create pseudo-random patterns
on the DDR3/DDR3L data bus to reduce the impact of any excessive di/dt.
2.2 PCI Express* Interface

This section describes the PCI Express* interface capabilities of the processor. See the
PCI Express Base Specification 3.0 for details on PCI Express*.
2.2.1 PCI Express* Support

The PCI Express* lanes (PEG[15:0] TX and RX) are fully-compliant to the PCI Express
Base Specification, Revision 3.0.
The processor with the PCH support the configurations shown in the following table
(may vary depending on PCH SKUs).
Table 6. PCI Express* Supported Configurations in Desktop Products

Configuration Desktop
1x8, 2x4 GFX, I/O
2x8 GFX, I/O
1x16 GFX, I/O
• The port may negotiate down to narrower widths.

— Support for x16/x8/x4/x2/x1 widths for a single PCI Express* mode.
• 2.5 GT/s, 5.0 GT/s and 8 GT/s PCI Express* bit rates are supported.
• Gen 1 Raw bit-rate on the data pins of 2.5 GT/s, resulting in a real bandwidth per
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
Maximum theoretical bandwidth on the interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1.
• Gen 2 Raw bit-rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per
pair of 500 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
Maximum theoretical bandwidth on the interface of 8 GB/s in each direction
simultaneously, for an aggregate of 16 GB/s when x16 Gen 2.
• Gen 3 raw bit-rate on the data pins of 8.0 GT/s, resulting in a real bandwidth per
pair of 984 MB/s using 128b/130b encoding to transmit data across this interface.
This also does not account for packet overhead and link maintenance. Maximum
theoretical bandwidth on the interface of 16 GB/s in each direction simultaneously,
for an aggregate of 32 GB/s when x16 Gen 3.
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.

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• PCI Express* Enhanced Access Mechanism. Accessing the device configuration

space in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X* Relaxed
ordering).
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0: DMI -> PCI Express* Port 0
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status.
• PCI Express* reference clock is 100-MHz differential clock.
• Power Management Event (PME) functions.
• Dynamic width capability.
• Message Signaled Interrupt (MSI and MSI-X) messages.
• Polarity inversion
Note: The processor does not support PCI Express* Hot-Plug.
2.2.2 PCI Express* Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-
and-Play specification. The processor PCI Express* ports support Gen 3. At 8 GT/s,
Gen 3 operation results in twice as much bandwidth per lane as compared to Gen 2
operation. The 16 lanes PEG can operate at 2.5 GT/s, 5 GT/s, or 8 GT/s.
Gen 3 PCI Express* uses a 128b/130b encoding that is about 23% more efficient than
the 8b/10b encoding used in Gen 1 and Gen 2.
The PCI Express* architecture is specified in three layers – Transaction Layer, Data
Link Layer, and Physical Layer. See the PCI Express Base Specification 3.0 for details
of PCI Express* architecture.
2.2.3 PCI Express* Configuration Mechanism

The PCI Express* (external graphics) link is mapped through a PCI-to-PCI bridge
structure.

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Figure 3. PCI Express* Related Register Structures in the Processor
PCI-PCI
Bridge PCI
PCI representing Compatible
PEG0
Express* root PCI Host Bridge
Device Express ports Device
(Device 1 and (Device 0)
Device 6)
DMI
PCI Express* extends the configuration space to 4096 bytes per-device/function, as

compared to 256 bytes allowed by the conventional PCI specification. PCI Express*
configuration space is divided into a PCI-compatible region (that consists of the first
256 bytes of a logical device's configuration space) and an extended PCI Express*
region (that consists of the remaining configuration space). The PCI-compatible region
can be accessed using either the mechanisms defined in the PCI specification or using
the enhanced PCI Express* configuration access mechanism described in the PCI
Express* Enhanced Configuration Mechanism section.
The PCI Express* Host Bridge is required to translate the memory-mapped PCI
Express* configuration space accesses from the host processor to PCI Express*
configuration cycles. To maintain compatibility with PCI configuration addressing
mechanisms, it is recommended that system software access the enhanced
configuration space using 32-bit operations (32-bit aligned) only. See the PCI Express
Base Specification for details of both the PCI-compatible and PCI Express* Enhanced
configuration mechanisms and transaction rules.
PCI Express* Port
The PCI Express* interface on the processor is a single, 16-lane (x16) port that can
also be configured at narrower widths. The PCI Express* port is being designed to be
compliant with the PCI Express Base Specification, Revision 3.0.
PCI Express* Lanes Connection
The following figure demonstrates the PCIe* lane mapping.

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Figure 4. PCI Express* Typical Operation 16 Lanes Mapping
Lane 0
0 0
Lane 1
1 1
Lane 2
2 2
Lane 3
3 3
Lane 4
4 4
Lane 5
5 5
Lane 6
6 6
1 X 16 Controller
Lane 7
7 7
Lane 8
0 8 8
Lane 9
1 9 9
Lane 10
2 10 10
1 X 8 Controller
Lane 11
3 11 11
Lane 12
0 4 12 12
1 X 4 Controller
Lane 13
1 5 13 13
Lane 14
2 6 14 14
Lane 15
3 7 15 15
2.3 Direct Media Interface (DMI)

Direct Media Interface (DMI) connects the processor and the PCH. Next generation
DMI2 is supported.
Note: Only DMI x4 configuration is supported.
• DMI 2.0 support.

• Compliant to Direct Media Interface Second Generation (DMI2).
• Four lanes in each direction.

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• 5 GT/s point-to-point DMI interface to PCH is supported.

• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 2 GB/s in each direction
simultaneously, for an aggregate of 4 GB/s when DMI x4.
• Shares 100-MHz PCI Express* reference clock.
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Supports the following traffic types to or from the PCH:
— DMI -> DRAM
— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs
only)
— Processor core -> DMI
• APIC and MSI interrupt messaging support:
— Message Signaled Interrupt (MSI and MSI-X) messages
• Downstream SMI, SCI and SERR error indication.
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters.
• DC coupling – no capacitors between the processor and the PCH.
• Polarity inversion.
• PCH end-to-end lane reversal across the link.
• Supports Half Swing “low-power/low-voltage”.
DMI Error Flow
DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI related SERR activity is associated with Device 0.
DMI Link Down
The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to
data link down, after the link was up, then the DMI link hangs the system by not
allowing the link to retrain to prevent data corruption. This link behavior is controlled
by the PCH.
Downstream transactions that had been successfully transmitted across the link prior
to the link going down may be processed as normal. No completions from
downstream, non-posted transactions are returned upstream over the DMI link after a
link down event.

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2.4 Processor Graphics

The processor graphics contains a generation 8 graphics core architecture. This
enables substantial gains in performance and lower power consumption over previous
generations.
• Next Generation Intel Clear Video Technology HD Support is a collection of video
playback and enhancement features that improve the end user’s viewing
experience
— Encode / transcode HD content
— Playback of high definition content including Blu-ray Disc*
— Superior image quality with sharper, more colorful images
— Playback of Blu-ray* disc S3D content using HDMI (1.4a specification
compliant with 3D)
• DirectX* Video Acceleration (DXVA) support for accelerating video processing
— Full AVC/VC1/MPEG2 HW Decode
• Advanced Scheduler 2.0, 1.0, XPDM support
• Windows* 8, Windows* 7, OSX, Linux* operating system support
• DirectX* 11.1, DirectX* 11, DirectX* 10.1, DirectX* 10, DirectX* 9 support.
• OpenGL* 4.0, support
• Switchable Graphics support on AIO platforms with MxM solutions only
2.5 Processor Graphics Controller (GT)

The Graphics Engine Architecture includes 3D compute elements, Multi-format HW
assisted decode/encode pipeline, and Mid-Level Cache (MLC) for superior high
definition playback, video quality, and improved 3D performance and media.
The Display Engine handles delivering the pixels to the screen. GSA (Graphics in
System Agent) is the primary channel interface for display memory accesses and
“PCI-like” traffic in and out.

28 Order No.: 332376-001v1
Figure 5. Processor Graphics Controller Unit Block Diagram
2.5.1 3D and Video Engines for Graphics Processing

The 3D engine provides the following performance and power-management
enhancements.
3D Pipeline
The 3D graphics pipeline architecture simultaneously operates on different primitives

or on different portions of the same primitive. All the cores are fully programmable,
increasing the versatility of the 3D Engine.
3D Engine Execution Units

• The EUs perform 128-bit wide execution per clock.
• Support SIMD8 instructions for vertex processing and SIMD16 instructions for
pixel processing.
Vertex Fetch (VF) Stage
The VF stage executes 3DPRIMITIVE commands. Some enhancements have been

included to better support legacy D3D APIs as well as SGI OpenGL*.

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Vertex Shader (VS) Stage
The VS stage performs shading of vertices output by the VF function. The VS unit
produces an output vertex reference for every input vertex reference received from
the VF unit, in the order received.
Geometry Shader (GS) Stage
The GS stage receives inputs from the VS stage. Compiled application-provided GS

programs, specifying an algorithm to convert the vertices of an input object into some
output primitives. For example, a GS shader may convert lines of a line strip into
polygons representing a corresponding segment of a blade of grass centered on the
line. Or it could use adjacency information to detect silhouette edges of triangles and
output polygons extruding out from the edges.
Clip Stage
The Clip stage performs general processing on incoming 3D objects. However, it also
includes specialized logic to perform a Clip Test function on incoming objects. The Clip
Test optimizes generalized 3D Clipping. The Clip unit examines the position of
incoming vertices, and accepts/rejects 3D objects based on its Clip algorithm.
Strips and Fans (SF) Stage
The SF stage performs setup operations required to rasterize 3D objects. The outputs
from the SF stage to the Windower stage contain implementation-specific information
required for the rasterization of objects and also supports clipping of primitives to
some extent.
Windower / IZ (WIZ) Stage
The WIZ unit performs an early depth test, which removes failing pixels and
eliminates unnecessary processing overhead.
The Windower uses the parameters provided by the SF unit in the object-specific
rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of
pixels. The Windower is also capable of performing dithering, whereby the illusion of a
higher resolution when using low-bpp channels in color buffers is possible. Color
dithering diffuses the sharp color bands seen on smooth-shaded objects.
Video Engine
The Video Engine handles the non-3D (media/video) applications. It includes support
for VLD and MPEG2 decode in hardware.
2D Engine
The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set
of 2D instructions. To take advantage of the 3D during engine’s functionality, some
BLT functions make use of the 3D renderer.
Processor Graphics VGA Registers
The 2D registers consists of original VGA registers and others to support graphics
modes that have color depths, resolutions, and hardware acceleration features that go
beyond the original VGA standard.

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Logical 128-Bit Fixed BLT and 256 Fill Engine
This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The
128-bit BLT engine provides hardware acceleration of block transfers of pixel data for
many common Windows operations. The BLT engine can be used for the following:
• Move rectangular blocks of data between memory locations
• Data alignment
• To perform logical operations (raster ops)
The rectangular block of data does not change, as it is transferred between memory
locations. The allowable memory transfers are between: cacheable system memory
and frame buffer memory, frame buffer memory and frame buffer memory, and within
system memory. Data to be transferred can consist of regions of memory, patterns, or
solid color fills. A pattern is always 8 x 8 pixels wide and may be 8, 16, or 32 bits per
pixel.
The BLT engine expands monochrome data into a color depth of 8, 16, or 32 bits.
BLTs can be either opaque or transparent. Opaque transfers move the data specified
to the destination. Transparent transfers compare destination color to source color and
write according to the mode of transparency selected.
Data is horizontally and vertically aligned at the destination. If the destination for the
BLT overlaps with the source memory location, the BLT engine specifies which area in
memory to begin the BLT transfer. Hardware is included for all 256 raster operations
(source, pattern, and destination) defined by Microsoft*, including transparent BLT.
The BLT engine has instructions to invoke BLT and stretch BLT operations, permitting
software to set up instruction buffers and use batch processing. The BLT engine can
perform hardware clipping during BLTs.
2.5.2 Multi Graphics Controllers Multi-Monitor Support

The processor supports simultaneous use of the Processor Graphics Controller (GT)
and a x16 PCI Express* Graphics (PEG) device. The processor supports a maximum of
2 displays connected to the PEG card in parallel with up to 2 displays connected to the
processor and PCH.
Note: When supporting Multi Graphics Multi Monitors, "drag and drop" between monitors and
the 2x8PEG is not supported.
2.6 Digital Display Interface (DDI)

• The processor supports:
— Three Digital Display (x4 DDI) interfaces that can be configured as
DisplayPort*, HDMI*, or DVI. DisplayPort* can be configured to use 1, 2, or 4
lanes depending on the bandwidth requirements and link data rate of RBR
(1.62 GT/s), HBR (2.7 GT/s) and HBR2 (5.4 GT/s). When configured as
HDMI*, DDIx4 port can support 2.97 GT/s. In addition, Digital Port D ( x4
DDI) interface can also be configured to carry embedded DisplayPort*
(eDPx4). Built-in displays are only supported on Digital Port D.
— One dedicated Intel FDI Port for legacy VGA support on the PCH.

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• The HDMI* interface supports HDMI with 3D, 4K, Deep Color, and x.v.Color. The
DisplayPort* interface supports the VESA DisplayPort* Standard Version 1,
Revision 2.
• The processor supports High-bandwidth Digital Content Protection (HDCP) for
high-definition content playback over digital interfaces.
• The processor also integrates dedicated a Mini HD audio controller to drive audio
on integrated digital display interfaces, such as HDMI* and DisplayPort*. The HD
audio controller on the PCH would continue to support down CODECs, and so on.
The processor Mini HD audio controller supports two High-Definition Audio streams
simultaneously on any of the three digital ports.
• The processor supports streaming any 3 independent and simultaneous display
combination of DisplayPort*/HDMI*/DVI/eDP*/VGA monitors with the exception of
3 simultaneous display support of HDMI*/DVI . In the case of 3 simultaneous
displays, two High Definition Audio streams over the digital display interfaces are
supported.
• Each digital port is capable of driving resolutions up to 3840x2160 at 60 Hz
through DisplayPort* and 4096x2304 at 24 Hz/2560x1600 at 60 Hz using HDMI*.
• DisplayPort* Aux CH, DDC channel, Panel power sequencing, and HPD are
supported through the PCH.
Figure 6. Processor Display Architecture
DP
Transcoder eDP* Aux
DP encoder
eDP* Mux
Timing, VDIP
DPT, SRID
Display Transcoder A FDI

Pipe A DP / HDMI FDI
RX
Timing, VDIP
Memory \ Config Interface
Panel Fitting
DP /
Port Mux
B HDMI /
DDI Ports B, C, and D
Transcoder B
PCH Display
Display
DP / HDMI DVI
Pipe B
Timing, VDIP DP /
C
HDMI /
DVI
Transcoder C D DP /
Display
DP / HDMI HDMI /
Pipe C
Timing, VDIP DVI / eDP
HD Audio Audio
Controller Codec
Display is the presentation stage of graphics. This involves:

• Pulling rendered data from memory
• Converting raw data into pixels
• Blending surfaces into a frame

32 Order No.: 332376-001v1
• Organizing pixels into frames

• Optionally scaling the image to the desired size
• Re-timing data for the intended target
• Formatting data according to the port output standard
DisplayPort*
DisplayPort* is a digital communication interface that uses differential signaling to

achieve a high-bandwidth bus interface designed to support connections between PCs
and monitors, projectors, and TV displays. DisplayPort* is also suitable for display
connections between consumer electronics devices, such as high-definition optical disc
players, set top boxes, and TV displays.
A DisplayPort* consists of a Main Link, Auxiliary channel, and a Hot-Plug Detect signal.
The Main Link is a unidirectional, high-bandwidth, and low latency channel used for
transport of isochronous data streams such as uncompressed video and audio. The
Auxiliary Channel (AUX CH) is a half-duplex bidirectional channel used for link
management and device control. The Hot-Plug Detect (HPD) signal serves as an
interrupt request for the sink device.
The processor is designed in accordance with the VESA DisplayPort* Standard Version
1.2a. The processor supports VESA DisplayPort* PHY Compliance Test Specification
1.2a and VESA DisplayPort* Link Layer Compliance Test Specification 1.2a.
Figure 7. DisplayPort* Overview
Source Device Main Link Sink Device

(Isochronous Streams)
DisplayPort Tx DisplayPort Rx
AUX CH
(Link/Device Managemet)
Hot-Plug Detect
(Interrupt Request)
High-Definition Multimedia Interface (HDMI*)
The High-Definition Multimedia Interface* (HDMI*) is provided for transmitting

uncompressed digital audio and video signals from DVD players, set-top boxes, and
other audiovisual sources to television sets, projectors, and other video displays. It
can carry high quality multi-channel audio data and all standard and high-definition
consumer electronics video formats. The HDMI display interface connecting the
processor and display devices uses transition minimized differential signaling (TMDS)
to carry audiovisual information through the same HDMI cable.
HDMI includes three separate communications channels — TMDS, DDC, and the
optional CEC (consumer electronics control). CEC is not supported on the processor.
As shown in the following figure, the HDMI cable carries four differential pairs that

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make up the TMDS data and clock channels. These channels are used to carry video,
audio, and auxiliary data. In addition, HDMI carries a VESA DDC. The DDC is used by
an HDMI Source to determine the capabilities and characteristics of the Sink.
Audio, video, and auxiliary (control/status) data is transmitted across the three TMDS
data channels. The video pixel clock is transmitted on the TMDS clock channel and is
used by the receiver for data recovery on the three data channels. The digital display
data signals driven natively through the PCH are AC coupled and needs level shifting
to convert the AC coupled signals to the HDMI compliant digital signals.
The processor HDMI interface is designed in accordance with the High-Definition

Multimedia Interface with 3D, 4K, Deep Color, and x.v.Color.
Figure 8. HDMI* Overview
HDMI Source HDMI Sink

HDMI Tx HDMI Rx
TMDS Data Channel 0
TMDS Data Channel 1
TMDS Data Channel 2
TMDS Clock Channel
Hot-Plug Detect
Display Data Channel (DDC)
CEC Line (optional)
Digital Video Interface
The processor Digital Ports can be configured to drive DVI-D. DVI uses TMDS for
transmitting data from the transmitter to the receiver, which is similar to the HDMI
protocol except for the audio and CEC. Refer to the HDMI section for more information
on the signals and data transmission. To drive DVI-I through the back panel the VGA
DDC signals are connected along with the digital data and clock signals from one of
the Digital Ports. When a system has support for a DVI-I port, then either VGA or the
DVI-D through a single DVI-I connector can be driven, but not both simultaneously.
The digital display data signals driven natively through the processor are AC coupled
and need level shifting to convert the AC coupled signals to the HDMI compliant digital
signals.

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embedded DisplayPort*
embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort standard

oriented towards applications such as notebook and All-In-One PCs. Digital Port D can
be configured as eDP. Like DisplayPort, embedded DisplayPort also consists of a Main
Link, Auxiliary channel, and an optional Hot-Plug Detect signal.
The eDP on the processor can be configured for 2 or 4 lanes.
The processor supports embedded DisplayPort* (eDP*) Standard Version 1.2 and
VESA embedded DisplayPort* Standard Version 1.2.
Integrated Audio
• HDMI and display port interfaces carry audio along with video.
• Processor supports two DMA controllers to output two High Definition audio
streams on two digital ports simultaneously.
• Supports only the internal HDMI and DP CODECs.
Table 7. Processor Supported Audio Formats over HDMI*and DisplayPort*

Audio Formats HDMI* DisplayPort*
AC-3 Dolby* Digital Yes Yes
Dolby Digital Plus Yes Yes
DTS-HD* Yes Yes
LPCM, 192 kHz/24 bit, 8 Channel Yes Yes
Dolby TrueHD, DTS-HD Master Audio*

Yes Yes
(Lossless Blu-Ray Disc* Audio Format)
The processor will continue to support Silent stream. Silent stream is an integrated
audio feature that enables short audio streams, such as system events to be heard
over the HDMI and DisplayPort monitors. The processor supports silent streams over
the HDMI and DisplayPort interfaces at 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz sampling rates.
Multiple Display Configurations
The following multiple display configuration modes are supported (with appropriate
driver software):
• Single Display is a mode with one display port activated to display the output to
one display device.
• Intel Display Clone is a mode with up to three display ports activated to drive the
display content of same color depth setting but potentially different refresh rate
and resolution settings to all the active display devices connected.
• Extended Desktop is a mode with up to three display ports activated to drive the
content with potentially different color depth, refresh rate, and resolution settings
on each of the active display devices connected.
The digital ports on the processor can be configured to support DisplayPort*/HDMI/

DVI. For Desktop designs, digital port D can be configured as eDPx4 in addition to
dedicated x2 port for Intel FDI for VGA. The following table shows examples of valid
three display configurations through the processor.

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Table 8. Valid Three Display Configurations through the Processor

Display 1 Display 2 Display 3 Maximum Maximum Maximum
Resolution Display Resolution Display Resolution
1 2 Display 3
4096x2304 @ 24 Hz 3840x2160 @
HDMI HDMI DP
2560x1600 @ 60 Hz 60 Hz
3840x2160 @
DVI DVI DP 1920x1200 @ 60 Hz
60 Hz
DP DP DP 3840x2160 @ 60 Hz
4096x2304 @
24 Hz
VGA DP HDMI 1920x1200 @ 60 Hz 3840x2160 @ 60 Hz
2560x1600 @
60 Hz
4096x2304 @
24 Hz
eDP DP HDMI 3840x2160 @ 60 Hz 3840x2160 @ 60 Hz
2560x1600 @
60 Hz
eDP DP DP 3840x2160 @ 60 Hz 3840x2160 @ 60 Hz
4096x2304 @ 24 Hz
eDP HDMI HDMI 3840x2160 @ 60 Hz
2560x1600 @ 60 Hz
Notes: 1. Requires support of 2 channel DDR3/DDR3L 1600 MT/s configuration for driving 3 simultaneous
3840x2160 @ 60 Hz display resolutions
2. DP and eDP resolutions in the above table are supported for 4 lanes with link data rate HBR2.
The following table shows the DP/eDP resolutions supported for 1, 2, or 4 lanes
depending on link data rate of RBR, HBR, and HBR2.
Table 9. DisplayPort and embedded DisplayPort* Resolutions for 1, 2, 4 Lanes – Link

Data Rate of RBR, HBR, and HBR2
Link Data Rate Lane Count
1 2 4
RBR 1064x600 1400x1050 2240x1400
HBR 1280x960 1920x1200 2880x1800
HBR2 1920x1200 2880x1800 3840x2160
Any 3 displays can be supported simultaneously using the following rules:

• Maximum of 2 HDMIs
• Maximum of 2 DVIs
• Maximum of 1 HDMI and 1 DVI
• Any 3 DisplayPort
• One VGA
• One eDP

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High-bandwidth Digital Content Protection (HDCP)
HDCP is the technology for protecting high-definition content against unauthorized

copy or unreceptive between a source (computer, digital set top boxes, and so on)
and the sink (panels, monitor, and TVs). The processor supports HDCP 1.4 for content
protection over wired displays (HDMI*, DVI, and DisplayPort*).
The HDCP 1.4 keys are integrated into the processor and customers are not required
to physically configure or handle the keys.
2.7 Intel® Flexible Display Interface (Intel® FDI)

• The Intel Flexible Display Interface (Intel FDI) passes display data from the
processor (source) to the PCH (sink) for display through a display interface on the
PCH.
• Intel FDI supports 2 lanes at 2.7 GT/s fixed frequency. This can be configured to 1
or 2 lanes depending on the bandwidth requirements.
• Intel FDI supports 8 bits per color only.
• Side band sync pin (FDI_CSYNC).
• Side band interrupt pin (DISP_INT). This carries combined interrupt for HPDs of all
the ports, AUX and I2C completion events, and so on.
• Intel FDI is not encrypted as it drives only VGA and content protection is not
supported on VGA.
2.8 Platform Environmental Control Interface (PECI)

PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and external components, like Super I/O (SIO) and Embedded
Controllers (EC), to provide processor temperature, Turbo, TDP, and memory
throttling control mechanisms and many other services. PECI is used for platform
thermal management and real time control and configuration of processor features
and performance.
2.8.1 PECI Bus Architecture

The PECI architecture is based on a wired-OR bus that the clients (as processor PECI)
can pull up high (with strong drive).
The idle state on the bus is near zero.
The following figure demonstrates PECI design and connectivity. While the host/
originator can be a third party PECI host, one of the PECI clients is a processor PECI
device.

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Figure 9. PECI Host-Clients Connection Example
VTT
VTT
Q3
nX
Q1
nX
PECI
Q2
1X
CPECI
<10pF/Node
Host / Originator PECI Client
Additional
PECI Clients

38 Order No.: 332376-001v1
Technologies—Processor
3.0 Technologies
This chapter provides a high-level description of Intel technologies implemented in the

processor.
The implementation of the features may vary between the processor SKUs.
Details on the different technologies of Intel processors and other relevant external
notes are located at the Intel technology web site: http://www.intel.com/technology/
3.1 Intel® Virtualization Technology (Intel® VT)

Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple
independent systems to software. This allows multiple, independent operating systems
to run simultaneously on a single system. Intel VT comprises technology components
to support virtualization of platforms based on Intel architecture microprocessors and
chipsets.
Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel®
Architecture (Intel® VT-x) added hardware support in the processor to improve the
virtualization performance and robustness. Intel® Virtualization Technology for
Directed I/O (Intel VT-d) extends Intel® VT-x by adding hardware assisted support to
improve I/O device virtualization performance.
Intel® VT-x specifications and functional descriptions are included in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3B and is available at:
http://www.intel.com/products/processor/manuals/index.htm
The Intel VT-d specification and other Intel VT documents can be referenced at:
http://www.intel.com/technology/virtualization/index.htm
https://sharedspaces.intel.com/sites/PCDC/SitePages/Ingredients/ingredient.aspx?
ing=VT
Intel® VT-x Objectives
Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual

Machine Monitor (VMM) can use Intel VT-x features to provide an improved reliable
virtualized platform. By using Intel VT-x, a VMM is:
• Robust: VMMs no longer need to use paravirtualization or binary translation. This
means that off-the-shelf operating systems and applications can be run without
any special steps.
• Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA
x86 processors.

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Processor—Technologies
• More reliable: Due to the hardware support, VMMs can now be smaller, less
complex, and more efficient. This improves reliability and availability and reduces
the potential for software conflicts.
• More secure: The use of hardware transitions in the VMM strengthens the
isolation of VMs and further prevents corruption of one VM from affecting others
on the same system.
Intel® VT-x Features
The processor supports the following Intel VT-x features:

• Extended Page Table (EPT) Accessed and Dirty Bits
— EPT A/D bits enabled VMMs to efficiently implement memory management and
page classification algorithms to optimize VM memory operations, such as de-
fragmentation, paging, live migration, and check-pointing. Without hardware
support for EPT A/D bits, VMMs may need to emulate A/D bits by marking EPT
paging-structures as not-present or read-only, and incur the overhead of EPT
page-fault VM exits and associated software processing.
• Extended Page Table Pointer (EPTP) switching
— EPTP switching is a specific VM function. EPTP switching allows guest software
(in VMX non-root operation, supported by EPT) to request a different EPT
paging-structure hierarchy. This is a feature by which software in VMX non-
root operation can request a change of EPTP without a VM exit. Software can
choose among a set of potential EPTP values determined in advance by
software in VMX root operation.
• Pause loop exiting
— Support VMM schedulers seeking to determine when a virtual processor of a
multiprocessor virtual machine is not performing useful work. This situation
may occur when not all virtual processors of the virtual machine are currently
scheduled and when the virtual processor in question is in a loop involving the
PAUSE instruction. The new feature allows detection of such loops and is thus
called PAUSE-loop exiting.
The processor core supports the following Intel VT-x features:

• Extended Page Tables (EPT)
— EPT is hardware assisted page table virtualization.
— It eliminates VM exits from the guest operating system to the VMM for shadow
page-table maintenance.
• Virtual Processor IDs (VPID)
— Ability to assign a VM ID to tag processor core hardware structures (such as
TLBs).
— This avoids flushes on VM transitions to give a lower-cost VM transition time
and an overall reduction in virtualization overhead.
• Guest Preemption Timer
— Mechanism for a VMM to preempt the execution of a guest operating system
after an amount of time specified by the VMM. The VMM sets a timer value
before entering a guest.
— The feature aids VMM developers in flexibility and Quality of Service (QoS)
guarantees.

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• Descriptor-Table Exiting
— Descriptor-table exiting allows a VMM to protect a guest operating system
from an internal (malicious software based) attack by preventing relocation of
key system data structures like IDT (interrupt descriptor table), GDT (global
descriptor table), LDT (local descriptor table), and TSS (task segment
selector).
— A VMM using this feature can intercept (by a VM exit) attempts to relocate
these data structures and prevent them from being tampered by malicious
software.
Intel® VT-d Objectives
The key Intel VT-d objectives are domain-based isolation and hardware-based
virtualization. A domain can be abstractly defined as an isolated environment in a
platform to which a subset of host physical memory is allocated. Intel VT-d provides
accelerated I/O performance for a virtualized platform and provides software with the
following capabilities:
• I/O device assignment and security: for flexibly assigning I/O devices to VMs and
extending the protection and isolation properties of VMs for I/O operations.
• DMA remapping: for supporting independent address translations for Direct
Memory Accesses (DMA) from devices.
• Interrupt remapping: for supporting isolation and routing of interrupts from
devices and external interrupt controllers to appropriate VMs.
• Reliability: for recording and reporting to system software DMA and interrupt
errors that may otherwise corrupt memory or impact VM isolation.
Intel VT-d accomplishes address translation by associating a transaction from a given

I/O device to a translation table associated with the Guest to which the device is
assigned. It does this by means of the data structure in the following illustration. This
table creates an association between the device's PCI Express* Bus/Device/Function
(B/D/F) number and the base address of a translation table. This data structure is
populated by a VMM to map devices to translation tables in accordance with the device
assignment restrictions above, and to include a multi-level translation table (VT-d
Table) that contains Guest specific address translations.

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Figure 10. Device to Domain Mapping Structures
(Dev 31, Func 7) Context entry 255
(Dev 0, Func 1)
(Dev 0, Func 0) Context entry 0
Context entry Table Address Translation

(Bus 255) Root entry 255 For bus N Structures for Domain A
(Bus N) Root entry N
(Bus 0) Root entry 0
Root entry table
Context entry 255
Context entry 0
Address Translation
Context entry Table Structures for Domain B
For bus 0
Intel VT-d functionality, often referred to as an Intel VT-d Engine, has typically been
implemented at or near a PCI Express host bridge component of a computer system.
This might be in a chipset component or in the PCI Express functionality of a processor
with integrated I/O. When one such Intel VT-d engine receives a PCI Express
transaction from a PCI Express bus, it uses the B/D/F number associated with the
transaction to search for an Intel VT-d translation table. In doing so, it uses the B/D/F
number to traverse the data structure shown in the above figure. If it finds a valid
Intel VT-d table in this data structure, it uses that table to translate the address
provided on the PCI Express bus. If it does not find a valid translation table for a given
translation, this results in an Intel VT-d fault. If Intel VT-d translation is required, the
Intel VT-d engine performs an N-level table walk.
For more information, refer to Intel® Virtualization Technology for Directed I/O
Architecture Specification http://download.intel.com/technology/computing/vptech/
Intel(r)_VT_for_Direct_IO.pdf
Intel® VT-d Features
The processor supports the following Intel VT-d features:

42 Order No.: 332376-001v1
• Memory controller and processor graphics comply with the Intel VT-d 1.2
Specification
• Two Intel VT-d DMA remap engines
— iGFX DMA remap engine
— Default DMA remap engine (covers all devices except iGFX)
• Support for root entry, context entry, and default context
• 39-bit guest physical address and host physical address widths
• Support for 4 KB page sizes
• Support for register-based fault recording only (for single entry only) and support
for MSI interrupts for faults
• Support for both leaf and non-leaf caching
• Support for boot protection of default page table
• Support for non-caching of invalid page table entries
• Support for hardware-based flushing of translated but pending writes and pending
reads, on IOTLB invalidation
• Support for Global, Domain specific, and Page specific IOTLB invalidation
• MSI cycles (MemWr to address FEEx_xxxxh) not translated
— Translation faults result in cycle forwarding to VBIOS region (byte enables
masked for writes). Returned data may be bogus for internal agents; PEG/DMI
interfaces return unsupported request status
• Interrupt remapping is supported
• Queued invalidation is supported
• Intel VT-d translation bypass address range is supported (Pass Through)
The processor supports the following added new Intel VT-d features:
• 4-level Intel VT-d Page walk: Both default Intel VT-d engine, as well as the IGD
Intel VT-d engine, are upgraded to support 4-level Intel VT-d tables (adjusted
guest address width 48 bits)
• Intel VT-d superpage: support of Intel VT-d superpage (2 MB, 1 GB) for the
default Intel VT-d engine (that covers all devices except IGD)
IGD Intel VT-d engine does not support superpage and BIOS should disable
superpage in default Intel VT-d engine when iGFX is enabled.
Note: Intel VT-d Technology may not be available on all SKUs.
3.2 Intel® Trusted Execution Technology (Intel® TXT)

Intel Trusted Execution Technology (Intel TXT) defines platform-level enhancements
that provide the building blocks for creating trusted platforms.
The Intel TXT platform helps to provide the authenticity of the controlling environment
such that those wishing to rely on the platform can make an appropriate trust
decision. The Intel TXT platform determines the identity of the controlling environment
by accurately measuring and verifying the controlling software.

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Another aspect of the trust decision is the ability of the platform to resist attempts to
change the controlling environment. The Intel TXT platform will resist attempts by
software processes to change the controlling environment or bypass the bounds set by
the controlling environment.
Intel TXT is a set of extensions designed to provide a measured and controlled launch
of system software that will then establish a protected environment for itself and any
additional software that it may execute.
These extensions enhance two areas:

• The launching of the Measured Launched Environment (MLE).
• The protection of the MLE from potential corruption.
The enhanced platform provides these launch and control interfaces using Safer Mode
Extensions (SMX).
The SMX interface includes the following functions:

• Measured/Verified launch of the MLE.
• Mechanisms to ensure the above measurement is protected and stored in a secure
location.
• Protection mechanisms that allow the MLE to control attempts to modify itself.
The processor also offers additional enhancements to System Management Mode

(SMM) architecture for enhanced security and performance. The processor provides
new MSRs to:
• Enable a second SMM range
• Enable SMM code execution range checking
• Select whether SMM Save State is to be written to legacy SMRAM or to MSRs
• Determine if a thread is going to be delayed entering SMM
• Determine if a thread is blocked from entering SMM
• Targeted SMI, enable/disable threads from responding to SMIs both VLWs and IPI
For the above features, BIOS must test the associated capability bit before attempting
to access any of the above registers.
For more information, refer to the Intel® Trusted Execution Technology Measured
Launched Environment Programming Guide.
3.3 Intel® Hyper-Threading Technology (Intel® HT

Technology)
The processor supports Intel Hyper-Threading Technology (Intel HT Technology) that
allows an execution core to function as two logical processors. While some execution
resources, such as caches, execution units, and buses are shared, each logical
processor has its own architectural state with its own set of general-purpose registers
and control registers. This feature must be enabled using the BIOS and requires
operating system support.

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Intel recommends enabling Intel HT Technology with Microsoft Windows* 8 and

Microsoft Windows* 7 and disabling Intel HT Technology using the BIOS for all
previous versions of Windows* operating systems. For more information on Intel HT
Technology, see http://www.intel.com/technology/platform-technology/hyper-
threading/.
3.4 Intel® Turbo Boost Technology 2.0

The Intel Turbo Boost Technology 2.0 allows the processor core to opportunistically
and automatically run faster than its rated operating frequency/render clock, if it is
operating below power, temperature, and current limits. The Intel Turbo Boost
Technology 2.0 feature is designed to increase performance of both multi-threaded
and single-threaded workloads.
Maximum frequency is dependant on the SKU and number of active cores. No special
hardware support is necessary for Intel Turbo Boost Technology 2.0. BIOS and the
operating system can enable or disable Intel Turbo Boost Technology 2.0.
Compared with previous generation products, Intel Turbo Boost Technology 2.0 will
increase the ratio of application power to TDP. Thus, thermal solutions and platform
cooling that are designed to less than thermal design guidance might experience
thermal and performance issues since more applications will tend to run at the
maximum power limit for significant periods of time.
Note: Intel Turbo Boost Technology 2.0 may not be available on all SKUs.
Intel® Turbo Boost Technology 2.0 Frequency
The processor rated frequency assumes that all execution cores are running an
application at the thermal design power (TDP). However, under typical operation, not
all cores are active. Therefore, most applications are consuming less than the TDP at
the rated frequency. To take advantage of the available thermal headroom, the active
cores can increase their operating frequency.
To determine the highest performance frequency amongst active cores, the processor
takes the following into consideration:
• The number of cores operating in the C0 state.

• The estimated core current consumption.
• The estimated package prior and present power consumption.
• The package temperature.
Any of these factors can affect the maximum frequency for a given workload. If the
power, current, or thermal limit is reached, the processor will automatically reduce the
frequency to stay within its TDP limit. Turbo processor frequencies are only active if
the operating system is requesting the P0 state. For more information on P-states and
C-states, see Power Management on page 49.
3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)

Intel Advanced Vector Extensions 2.0 (Intel AVX2) is the latest expansion of the Intel
instruction set. Intel AVX2 extends the Intel Advanced Vector Extensions (Intel AVX)
with 256-bit integer instructions, floating-point fused multiply add (FMA) instructions,
and gather operations. The 256-bit integer vectors benefit math, codec, image, and

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digital signal processing software. FMA improves performance in face detection,

professional imaging, and high performance computing. Gather operations increase
vectorization opportunities for many applications. In addition to the vector extensions,
this generation of Intel processors adds new bit manipulation instructions useful in
compression, encryption, and general purpose software.
For more information on Intel AVX, see http://www.intel.com/software/avx
3.6 Intel® Advanced Encryption Standard New Instructions

(Intel® AES-NI)
The processor supports Intel Advanced Encryption Standard New Instructions (Intel
AES-NI) that are a set of Single Instruction Multiple Data (SIMD) instructions that
enable fast and secure data encryption and decryption based on the Advanced
Encryption Standard (AES). Intel AES-NI are valuable for a wide range of
cryptographic applications, such as applications that perform bulk encryption/
decryption, authentication, random number generation, and authenticated encryption.
AES is broadly accepted as the standard for both government and industry
applications, and is widely deployed in various protocols.
Intel AES-NI consists of six Intel SSE instructions. Four instructions, AESENC,
AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption
and decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key
expansion procedure. Together, these instructions provide a full hardware for
supporting AES; offering security, high performance, and a great deal of flexibility.
PCLMULQDQ Instruction
The processor supports the carry-less multiplication instruction, PCLMULQDQ.

PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the
128-bit carry-less multiplication of two, 64-bit operands without generating and
propagating carries. Carry-less multiplication is an essential processing component of
several cryptographic systems and standards. Hence, accelerating carry-less
multiplication can significantly contribute to achieving high speed secure computing
and communication.
Intel® Secure Key
The processor supports Intel® Secure Key (formerly known as Digital Random Number
Generator (DRNG)), a software visible random number generation mechanism
supported by a high quality entropy source. This capability is available to
programmers through the RDRAND instruction. The resultant random number
generation capability is designed to comply with existing industry standards in this
regard (ANSI X9.82 and NIST SP 800-90).
Some possible usages of the RDRAND instruction include cryptographic key generation
as used in a variety of applications, including communication, digital signatures,
secure storage, and so on.
3.7 Intel® Transactional Synchronization Extensions - New

Instructions (Intel® TSX-NI)
Intel Transactional Synchronization Extensions - New Instructions (Intel TSX-NI). Intel
TSX-NI provides a set of instruction extensions that allow programmers to specify
regions of code for transactional synchronization. Programmers can use these

46 Order No.: 332376-001v1
extensions to achieve the performance of fine-grain locking while actually

programming using coarse-grain locks. Details on Intel TSX-NI are in the Intel®
Architecture Instruction Set Extensions Programming Reference.
3.8 Intel® 64 Architecture x2APIC

The x2APIC architecture extends the xAPIC architecture that provides key
mechanisms for interrupt delivery. This extension is primarily intended to increase
processor addressability.
Specifically, x2APIC:
• Retains all key elements of compatibility to the xAPIC architecture:
— Delivery modes
— Interrupt and processor priorities
— Interrupt sources
— Interrupt destination types
• Provides extensions to scale processor addressability for both the logical and
physical destination modes
• Adds new features to enhance performance of interrupt delivery
• Reduces complexity of logical destination mode interrupt delivery on link based
architectures
The key enhancements provided by the x2APIC architecture over xAPIC are the
following:
• Support for two modes of operation to provide backward compatibility and
extensibility for future platform innovations:
— In xAPIC compatibility mode, APIC registers are accessed through memory
mapped interface to a 4K-Byte page, identical to the xAPIC architecture.
— In x2APIC mode, APIC registers are accessed through Model Specific Register
(MSR) interfaces. In this mode, the x2APIC architecture provides significantly
increased processor addressability and some enhancements on interrupt
delivery.
• Increased range of processor addressability in x2APIC mode:
— Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt
processor addressability up to 4G–1 processors in physical destination mode.
A processor implementation of x2APIC architecture can support fewer than 32-
bits in a software transparent fashion.
— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical
x2APIC ID is partitioned into two sub-fields – a 16-bit cluster ID and a 16-bit
logical ID within the cluster. Consequently, ((2^20) – 16) processors can be
addressed in logical destination mode. Processor implementations can support
fewer than 16 bits in the cluster ID sub-field and logical ID sub-field in a
software agnostic fashion.
• More efficient MSR interface to access APIC registers:
— To enhance inter-processor and self-directed interrupt delivery as well as the
ability to virtualize the local APIC, the APIC register set can be accessed only
through MSR-based interfaces in x2APIC mode. The Memory Mapped IO
(MMIO) interface used by xAPIC is not supported in x2APIC mode.

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• The semantics for accessing APIC registers have been revised to simplify the
programming of frequently-used APIC registers by system software. Specifically,
the software semantics for using the Interrupt Command Register (ICR) and End
Of Interrupt (EOI) registers have been modified to allow for more efficient delivery
and dispatching of interrupts.
• The x2APIC extensions are made available to system software by enabling the
local x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a
new operating system and a new BIOS are both needed, with special support for
x2APIC mode.
• The x2APIC architecture provides backward compatibility to the xAPIC architecture
and forward extendible for future Intel platform innovations.
Note: Intel x2APIC Technology may not be available on all SKUs.
For more information, see the Intel® 64 Architecture x2APIC Specification at http://
www.intel.com/products/processor/manuals/.
3.9 Power Aware Interrupt Routing (PAIR)

The processor includes enhanced power-performance technology that routes
interrupts to threads or cores based on their sleep states. As an example, for energy
savings, it routes the interrupt to the active cores without waking the deep idle cores.
For performance, it routes the interrupt to the idle (C1) cores without interrupting the
already heavily loaded cores. This enhancement is mostly beneficial for high-interrupt
scenarios like Gigabit LAN, WLAN peripherals, and so on.
3.10 Execute Disable Bit

The Execute Disable Bit allows memory to be marked as executable when combined
with a supporting operating system. If code attempts to run in non-executable
memory, the processor raises an error to the operating system. This feature can
prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities
and can thus help improve the overall security of the system. See the Intel® 64 and
IA-32 Architectures Software Developer's Manuals for more detailed information.
3.11 Supervisor Mode Execution Protection (SMEP)

Supervisor Mode Execution Protection provides the next level of system protection by
blocking malicious software attacks from user mode code when the system is running
in the highest privilege level. This technology helps to protect from virus attacks and
unwanted code from harming the system. For more information, refer to Intel® 64
and IA-32 Architectures Software Developer's Manual, Volume 3A at: http://
www.intel.com/Assets/PDF/manual/253668.pdf

48 Order No.: 332376-001v1
Power Management—Processor
4.0 Power Management

This chapter provides information on the following power management topics:
• Advanced Configuration and Power Interface (ACPI) States
• Processor Core
• Integrated Memory Controller (IMC)
• PCI Express*
• Direct Media Interface (DMI)
• Processor Graphics Controller
Figure 11. Processor Power States
G0 - Working
S0 – Processor Fully powered on (full on mode / connected standy mode
C0 – Active mode
P0
Pn
C1 – Auto Halt
C1E – Auto Halt, Low freq, low voltage
C3 – L1/L2 caches flush, clocks off
C6 – Save core states before shutdown
G1 - Sleeping
S3 Cold – Sleep – Suspend to RAM (STR)
S4 – Hibernate – Suspend to Disk (STD), Wakeup on PCH
S5 – Soft Off – no power, Wakeup on PCH
G3 – Mechanical OFF
Note: Power states availability may vary between the different SKUs

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Processor—Power Management
4.1 Advanced Configuration and Power Interface (ACPI)

States Supported
This section describes the ACPI states supported by the processor.
Table 10. System States

State Description
G0/S0 Full On Mode, Display On.
G0/S0 Connected Standby Mode, Display Off.
Suspend-to-RAM (STR). Context saved to memory (S3-Hot state is not supported by the
G1/S3-Cold
processor).
G1/S4 Suspend-to-Disk (STD). All power lost (except wakeup on PCH).
G2/S5 Soft off. All power lost (except wakeup on PCH). Total reboot.
G3 Mechanical off. All power removed from system.
Table 11. Processor Core / Package State Support

State Description
C0 Active mode, processor executing code.
C1 AutoHALT state.
C1E AutoHALT state with lowest frequency and voltage operating point.
Execution cores in C3 state flush their L1 instruction cache, L1 data cache, and L2 cache
C3
to the L3 shared cache. Clocks are shut off to each core.
C6 Execution cores in this state save their architectural state before removing core voltage.
Table 12. Integrated Memory Controller States

State Description
Power up CKE asserted. Active mode.
Pre-charge CKE de-asserted (not self-refresh) with all banks closed.

Power-down
Active Power- CKE de-asserted (not self-refresh) with minimum one bank active.
down
Self-Refresh CKE de-asserted using device self-refresh.
Table 13. PCI Express* Link States

State Description
L0 Full on – Active transfer state.
L0s First Active Power Management low-power state – Low exit latency.
L1 Lowest Active Power Management – Longer exit latency.
L3 Lowest power state (power-off) – Longest exit latency.

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Table 14. Direct Media Interface (DMI) States

State Description
L0 Full on – Active transfer state.
L0s First Active Power Management low-power state – Low exit latency.
L1 Lowest Active Power Management – Longer exit latency.
L3 Lowest power state (power-off) – Longest exit latency.
Table 15. G, S, and C Interface State Combinations

Global Sleep (S) Processor Processor System Clocks Description
(G) State Package (C) State
State State
G0 S0 C0 Full On On Full On
G0 S0 C1/C1E Auto-Halt On Auto-Halt
G0 S0 C3 Deep Sleep On Deep Sleep
Deep Power-
G0 S0 C6 On Deep Power-down
down
G1 S3 Power off Off, except RTC Suspend to RAM
G1 S4 Power off Off, except RTC Suspend to Disk
G2 S5 Power off Off, except RTC Soft Off
G3 NA Power off Power off Hard off
Table 16. D, S, and C Interface State Combination

Graphics Sleep (S) Package (C) Description
Adapter (D) State State
State
D0 S0 C0 Full On, Displaying.
D0 S0 C1/C1E Auto-Halt, Displaying.
D0 S0 C3 Deep sleep, Displaying.
D0 S0 C6 Deep Power-down, Displaying.
D3 S0 Any Not displaying.
D3 S3 N/A Not displaying, Graphics Core is powered off.
D3 S4 N/A Not displaying, suspend to disk.
4.2 Processor Core Power Management

®
While executing code, Enhanced Intel SpeedStep Technology optimizes the
processor’s frequency and core voltage based on workload. Each frequency and
voltage operating point is defined by ACPI as a P-state. When the processor is not
executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In
general, deeper power C-states have longer entry and exit latencies.
4.2.1 Enhanced Intel SpeedStep® Technology Key Features

The following are the key features of Enhanced Intel SpeedStep Technology:

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• Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
• Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on the selected frequency and the number of active
processor cores.
— Once the voltage is established, the PLL locks on to the target frequency.
— All active processor cores share the same frequency and voltage. In a multi-
core processor, the highest frequency P-state requested among all active
cores is selected.
— Software-requested transitions are accepted at any time. If a previous
transition is in progress, the new transition is deferred until the previous
transition is completed.
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Because there is low transition latency between P-states, a significant number of
transitions per-second are possible.
4.2.2 Low-Power Idle States

When the processor is idle, low-power idle states (C-states) are used to save power.
More power savings actions are taken for numerically higher C-states. However,
higher C-states have longer exit and entry latencies. Resolution of C-states occur at
the thread, processor core, and processor package level. Thread-level C-states are
available if Intel Hyper-Threading Technology is enabled.
Caution: Long term reliability cannot be assured unless all the Low-Power Idle States are
enabled.
Figure 12. Idle Power Management Breakdown of the Processor Cores
Thread 0 Thread 1 Thread 0 Thread 1
Core 0 State Core N State
Processor Package State
Entry and exit of the C-states at the thread and core level are shown in the following
figure.

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Figure 13. Thread and Core C-State Entry and Exit
C0
MWAIT(C1), HLT
MWAIT(C6),
MWAIT(C1), HLT P_LVL3 I/O Read
(C1E Enabled) MWAIT(C3),
P_LVL2 I/O Read
C1 C1E C3 C6
While individual threads can request low-power C-states, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolved
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C-state.
Table 17. Coordination of Thread Power States at the Core Level

Processor Core C-State Thread 1
C0 C1 C3 C6
C0 C0 C0 C0 C0
C1 C0 C11 C11 C11

Thread 0
C3 C0 C11 C3 C3
C6 C0 C11 C3 C6
Note: 1. If enabled, the core C-state will be C1E if all cores have resolved a core C1 state or higher.
4.2.3 Requesting Low-Power Idle States

The primary software interfaces for requesting low-power idle states are through the
MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).
However, software may make C-state requests using the legacy method of I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
method of requesting C-states provides legacy support for operating systems that
initiate C-state transitions using I/O reads.
For legacy operating systems, P_LVLx I/O reads are converted within the processor to
the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result
in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be
enabled in the BIOS.
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict
the range of I/O addresses that are trapped and emulate MWAIT like functionality.
Any P_LVLx reads outside of this range do not cause an I/O redirection to MWAIT(Cx)
like request. The reads fall through like a normal I/O instruction.

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Note: When P_LVLx I/O instructions are used, MWAIT sub-states cannot be defined. The
MWAIT sub-state is always zero if I/O MWAIT redirection is used. By default, P_LVLx
I/O redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a
wakeup on an interrupt, even if interrupts are masked by EFLAGS.IF.
4.2.4 Core C-State Rules

The following are general rules for all core C-states, unless specified otherwise:
• A core C-state is determined by the lowest numerical thread state (such as Thread
0 requests C1E state while Thread 1 requests C3 state, resulting in a core C1E
state). See the G, S, and C Interface State Combinations table.
• A core transitions to C0 state when:
— An interrupt occurs
— There is an access to the monitored address if the state was entered using an
MWAIT/Timed MWAIT instruction
— The deadline corresponding to the Timed MWAIT instruction expires
• An interrupt directed toward a single thread wakes only that thread.
• If any thread in a core is in active (in C0 state), the core's C-state will resolve to
C0 state.
• Any interrupt coming into the processor package may wake any core.
• A system reset re-initializes all processor cores.
Core C0 State
The normal operating state of a core where code is being executed.
Core C1/C1E State
C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1/C1E) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal

state or the C1/C1E state. See the Intel® 64 and IA-32 Architectures Software
Developer’s Manual for more information.
While a core is in C1/C1E state, it processes bus snoops and snoops from other
threads. For more information on C1E state, see Package C-States on page 55.
Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while
maintaining its architectural state. All core clocks are stopped at this point. Because
the core’s caches are flushed, the processor does not wake any core that is in the C3
state when either a snoop is detected or when another core accesses cacheable
memory.

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Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or
an MWAIT(C6) instruction. Before entering core C6 state, the core will save its
architectural state to a dedicated SRAM. Once complete, a core will have its voltage
reduced to zero volts. During exit, the core is powered on and its architectural state is
restored.
C-State Auto-Demotion
In general, deeper C-states, such as C6 state, have long latencies and have higher
energy entry/exit costs. The resulting performance and energy penalties become
significant when the entry/exit frequency of a deeper C-state is high. Therefore,
incorrect or inefficient usage of deeper C-states have a negative impact on idle power.
To increase residency and improve idle power in deeper C-states, the processor
supports C-state auto-demotion.
There are two C-state auto-demotion options:

• C6 to C3 state
• C6/C3 To C1 state
The decision to demote a core from C6 to C3 or C3/C6 to C1 state is based on each

core’s immediate residency history and interrupt rate . If the interrupt rate
experienced on a core is high and the residence in a deep C-state between such
interrupts is low, the core can be demoted to a C3 or C1 state. A higher interrupt
pattern is required to demote a core to C1 state as compared to C3 state.
This feature is disabled by default. BIOS must enable it in the

PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
4.2.5 Package C-States

The processor supports C0, C1/C1E, C3, and C6 power states.The following is a
summary of the general rules for package C-state entry. These apply to all package C-
states, unless specified otherwise:
• A package C-state request is determined by the lowest numerical core C-state
amongst all cores.
• A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
— Each core can be at a lower idle power state than the package if the platform
does not grant the processor permission to enter a requested package C-state.
— The platform may allow additional power savings to be realized in the
processor.
— For package C-states, the processor is not required to enter C0 state before
entering any other C-state.
— Entry into a package C-state may be subject to auto-demotion – that is, the
processor may keep the package in a deeper package C-state than requested
by the operating system if the processor determines, using heuristics, that the
deeper C-state results in better power/performance.
The processor exits a package C-state when a break event is detected. Depending on
the type of break event, the processor does the following:

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• If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.
— If the break event is not masked, the target core enters the core C0 state and
the processor enters package C0 state.
— If the break event is masked, the processor attempts to re-enter its previous
package state.
• If the break event was due to a memory access or snoop request,
— But the platform did not request to keep the processor in a higher package C-
state, the package returns to its previous C-state.
— And the platform requests a higher power C-state, the memory access or
snoop request is serviced and the package remains in the higher power C-
state.
The following table shows package C-state resolution for a dual-core processor. The
following figure summarizes package C-state transitions.
Table 18. Coordination of Core Power States at the Package Level

Package C-State Core 1
C0 C1 C3 C6
C0 C0 C0 C0 C0
C1 C0 C11 C11 C11

Core 0
C3 C0 C11 C3 C3
C6 C0 C11 C3 C6
Note: 1. If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher.

56 Order No.: 332376-001v1
Figure 14. Package C-State Entry and Exit
C0
C3 C6
C1
Package C0 State
This is the normal operating state for the processor. The processor remains in the
normal state when at least one of its cores is in the C0 or C1 state or when the
platform has not granted permission to the processor to go into a low-power state.
Individual cores may be in lower power idle states while the package is in C0 state.
Package C1/C1E State
No additional power reduction actions are taken in the package C1 state. However, if
the C1E sub-state is enabled, the processor automatically transitions to the lowest
supported core clock frequency, followed by a reduction in voltage.
The package enters the C1 low-power state when:

• At least one core is in the C1 state.
• The other cores are in a C1 or deeper power state.
The package enters the C1E state when:

• All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint.
• All cores are in a power state deeper than C1/C1E state; however, the package
low-power state is limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR.
• All cores have requested C1 state using HLT or MWAIT(C1) and C1E auto-
promotion is enabled in IA32_MISC_ENABLES.

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No notification to the system occurs upon entry to C1/C1E state.
Package C2 State
Package C2 state is an internal processor state that cannot be explicitly requested by

software. A processor enters Package C2 state when:
• All cores and graphics have requested a C3 or deeper power state; however,
constraints (LTR, programmed timer events in the near future, and so on) prevent
entry to any state deeper than C 2 state. Or,
• All cores and graphics are in the C3 or deeper power states, and a memory access
request is received. Upon completion of all outstanding memory requests, the
processor transitions back into a deeper package C-state.
Package C3 State
A processor enters the package C3 low-power state when:

• The other cores are in a C3 state or deeper power state and the processor has
been granted permission by the platform.
• The platform has not granted a request to a package C6 or deeper state, however,
has allowed a package C6 state.
In package C3 state, the L3 shared cache is valid.
Package C6 State
A processor enters the package C6 low-power state when:

• The other cores are in a C6 or deeper power state and the processor has been
granted permission by the platform.
• If the cores are requesting C7 state, but the platform is limiting to a package C6
state, the last level cache in this case can be flushed.
In package C6 state all cores have saved their architectural state and have had their
core voltages reduced to zero volts. It is possible the L3 shared cache is flushed and
turned off in package C6 state. If at least one core is requesting C6 state, the L3
cache will not be flushed.
4.2.6 Package C-States and Display Resolutions

The integrated graphics engine has the frame buffer located in system memory. When
the display is updated, the graphics engine fetches display data from system memory.
Different screen resolutions and refresh rates have different memory latency
requirements. These requirements may limit the deepest Package C-state the
processor can enter. Other elements that may affect the deepest Package C-state
available are the following:
• Display is on or off
• Single or multiple displays
• Native or non-native resolution
• Panel Self Refresh (PSR) technology

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Note: Display resolution is not the only factor influencing the deepest Package C-state the
processor can get into. Device latencies, interrupt response latencies, and core C-
states are among other factors that influence the final package C-state the processor
can enter.
The following table lists display resolutions and deepest available package C-State.
The display resolutions are examples using common values for blanking and pixel
rate. Actual results will vary. The table shows the deepest possible Package C-state.
System workload, system idle, and AC or DC power also affect the deepest possible
Package C-state.
Table 19. Deepest Package C-State Available

Number of Displays 1 Native Resolution Deepest Available Package C-
State
Single 800x600 60 Hz PC6
Multiple 800x600 60 Hz PC6

continued...

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Number of Displays 1 Native Resolution Deepest Available Package C-

State
Notes: 1. For multiple display cases, the resolution listed is the highest native resolution of all enabled
displays, and PSR is internally disabled; that is, dual display with one 800x600 60 Hz display and
one 2560x1600 60 Hz display will result in a deepest available package C-state of PC2.
2. Microcode Update rev 00000010 or newer must be used.
4.3 Integrated Memory Controller (IMC) Power Management

The main memory is power managed during normal operation and in low-power ACPI
Cx states.
4.3.1 Disabling Unused System Memory Outputs

Any system memory (SM) interface signal that goes to a memory module connector in
which it is not connected to any actual memory devices (such as SO-DIMM connector
is unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM
signals are:
• Reduced power consumption.
• Reduced possible overshoot/undershoot signal quality issues seen by the
processor I/O buffer receivers caused by reflections from potentially un-
terminated transmission lines.
When a given rank is not populated, the corresponding chip select and CKE signals are
not driven.
At reset, all rows must be assumed to be populated, until it can be determined that
the rows are not populated. This is due to the fact that when CKE is tri-stated with an
SO-DIMM present, the SO-DIMM is not ensured to maintain data integrity.
CKE tri-state should be enabled by BIOS where appropriate, since at reset all rows
must be assumed to be populated.
4.3.2 DRAM Power Management and Initialization

The processor implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals, which the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
The CKE is one of the power save means. When CKE is off, the internal DDR clock is
disabled and the DDR power is reduced. The power saving differs according to the
selected mode and the DDR type used. For more information, refer to the IDD table in
the DDR specification.

60 Order No.: 332376-001v1
The processor supports three different types of power-down modes in package C0.
The different power-down modes can be enabled through configuring
"PM_PDWN_config_0_0_0_MCHBAR". The type of CKE power-down can be configured
through PDWN_mode (bits 15:12) and the idle timer can be configured through
PDWN_idle_counter (bits 11:0). The different power-down modes supported are:
• No power-down (CKE disable)
• Active power-down (APD): This mode is entered if there are open pages when
de-asserting CKE. In this mode the open pages are retained. Power-saving in this
mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this
mode is defined by tXP – small number of cycles. For this mode, DRAM DLL must
be on.
• PPD/DLL-off: In this mode the data-in DLLs on DDR are off. Power-saving in this
mode is the best among all power modes. Power consumption is defined by
IDD2P1. Exiting this mode is defined by tXP, but also tXPDLL (10–20 according to
DDR type) cycles until first data transfer is allowed. For this mode, DRAM DLL
must be off.
The CKE is determined per rank, whenever it is inactive. Each rank has an idle-
counter. The idle-counter starts counting as soon as the rank has no accesses, and if
it expires, the rank may enter power-down while no new transactions to the rank
arrives to queues. The idle-counter begins counting at the last incoming transaction
arrival.
It is important to understand that since the power-down decision is per rank, the IMC
can find many opportunities to power down ranks, even while running memory
intensive applications; the savings are significant (may be few Watts, according to the
DDR specification). This is significant when each channel is populated with more
ranks.
Selection of power modes should be according to power-performance or thermal

trade-offs of a given system:
• When trying to achieve maximum performance and power or thermal
consideration is not an issue – use no power-down
• In a system which tries to minimize power-consumption, try using the deepest
power-down mode possible – PPD/DLL-off with a low idle timer value.
• In high-performance systems with dense packaging (that is, tricky thermal
design) the power-down mode should be considered in order to reduce the heating
and avoid DDR throttling caused by the heating.
The default value that BIOS configures in "PM_PDWN_config_0_0_0_MCHBAR" is

6080h; that is, PPD/DLL-off mode with idle timer of 80h, or 128 DCLKs. This is a
balanced setting with deep power-down mode and moderate idle timer value.
The idle timer expiration count defines the number of DCKLs that a rank is idle that
causes entry to the selected power mode. As this timer is set to a shorter time, the
IMC will have more opportunities to put DDR in power-down. There is no BIOS hook to
set this register. Customers choosing to change the value of this register can do it by
changing it in the BIOS. For experiments, this register can be modified in real time if
BIOS does not lock the IMC registers.

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4.3.2.1 Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that has its level recognized
(other than the DDR3/DDR3L reset pin) once power is applied. It must be driven LOW
by the DDR controller to make sure the SDRAM components float DQ and DQS during
power-up. CKE signals remain LOW (while any reset is active) until the BIOS writes to
a configuration register. Using this method, CKE is ensured to remain inactive for
much longer than the specified 200 micro-seconds after power and clocks to SDRAM
devices are stable.
4.3.2.2 Conditional Self-Refresh
During S0 idle state, system memory may be conditionally placed into self-refresh
state when the processor is in package C3 or deeper power state. Refer to Intel®
Rapid Memory Power Management (Intel® RMPM) for more details on conditional self-
refresh with Intel HD Graphics enabled.
When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh,

the processor core flushes pending cycles and then enters SDRAM ranks that are not
used by Intel graphics memory into self-refresh. The CKE signals remain LOW so the
SDRAM devices perform self-refresh.
The target behavior is to enter self-refresh for package C3 or deeper power states as
long as there are no memory requests to service.
4.3.2.3 Dynamic Power-Down
Dynamic power-down of memory is employed during normal operation. Based on idle

conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power-down state.
The processor core controller can be configured to put the devices in active power-
down (CKE de-assertion with open pages) or pre-charge power-down (CKE de-
assertion with all pages closed). Pre-charge power-down provides greater power
savings, but has a bigger performance impact since all pages will first be closed before
putting the devices in power-down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
4.3.2.4 DRAM I/O Power Management
Unused signals should be disabled to save power and reduce electromagnetic

interference. This includes all signals associated with an unused memory channel.
Clocks, CKE, ODE, and CS signals are controlled per DIMM rank and will be powered
down for unused ranks.
The I/O buffer for an unused signal should be tri-stated (output driver disabled), the
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals should be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).

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4.3.3 DRAM Running Average Power Limitation (RAPL)

RAPL is a power and time constant pair. DRAM RAPL defines an average power
constraint for the DRAM domain. Constraint is controlled by the PCU. Platform entities
(PECI or in-band power driver) can specify a power limit for the DRAM domain. PCU
continuously monitors the extant of DRAM throttling due to the power limit and
rebudgets the limit between DIMMs.
4.3.4 DDR Electrical Power Gating (EPG)

The DDR I/O of the processor supports Electrical Power Gating (DDR-EPG) while the
processor is at C3 or deeper power state.
In C3 or deeper power state, the processor internally gates VDDQ for the majority of
the logic to reduce idle power while keeping all critical DDR pins such as
SM_DRAMRST#, CKE and VREF in the appropriate state.
In S3 or C-state transitions, the DDR does not go through training mode and will
restore the previous training information.
4.4 PCI Express* Power Management

• Active power management is supported using L0s, and L1 states.
• All inputs and outputs disabled in L2/L3 Ready state.
4.5 Direct Media Interface (DMI) Power Management

Active power management is supported using L0s/L1 state.
4.6 Graphics Power Management
4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)

Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory
into self-refresh when the processor is in package C3 or deeper power state to allow
the system to remain in the lower power states longer for memory not reserved for
graphics memory. Intel RMPM functionality depends on graphics/display state
(relevant only when processor graphics is being used), as well as memory traffic
patterns generated by other connected I/O devices.
4.6.2 Graphics Render C-State

Render C-state (RC6) is a technique designed to optimize the average power to the
graphics render engine during times of idleness. RC6 is entered when the graphics
render engine, blitter engine, and the video engine have no workload being currently
worked on and no outstanding graphics memory transactions. When the idleness
condition is met, the processor graphics will program the graphics render engine
internal power rail into a low voltage state.

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4.6.3 Intel® Graphics Dynamic Frequency

Intel Graphics Dynamic Frequency Technology is the ability of the processor and
graphics cores to opportunistically increase frequency and/or voltage above the
guaranteed processor and graphics frequency for the given part. Intel Graphics
Dynamic Frequency Technology is a performance feature that makes use of unused
package power and thermals to increase application performance. The increase in
frequency is determined by how much power and thermal budget is available in the
package, and the application demand for additional processor or graphics
performance. The processor core control is maintained by an embedded controller.
The graphics driver dynamically adjusts between P-States to maintain optimal
performance, power, and thermals. The graphics driver will always try to place the
graphics engine in the most energy efficient P-state.

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Thermal Management—Processor
5.0 Thermal Management

This chapter provides both component-level and system-level thermal management.
Topics covered include processor thermal specifications, thermal profiles, thermal
metrology, fan speed control, adaptive thermal monitor, THERMTRIP# signal, Digital
Thermal Sensor (DTS), Intel Turbo Boost Technology, package power control, power
plane control, and turbo time parameter.
The processor requires a thermal solution to maintain temperatures within its

operating limits. Any attempt to operate the processor outside these operating limits
may result in permanent damage to the processor and potentially other components
within the system. Maintaining the proper thermal environment is key to reliable,
long-term system operation.
A complete solution includes both component and system level thermal management
features. Component level thermal solutions can include active or passive heatsinks
attached to the processor integrated heat spreader (IHS).
To allow the optimal operation and long-term reliability of Intel processor-based

systems, the processor must remain within the minimum and maximum case
temperature (TCASE) specifications as defined by the applicable thermal profile.
Thermal solutions not designed to provide this level of thermal capability may affect
the long-term reliability of the processor and system.
The processors implement a methodology for managing processor temperatures that

is intended to support acoustic noise reduction through fan speed control and to
assure processor reliability. Selection of the appropriate fan speed is based on the
relative temperature data reported by the processor’s Digital Temperature Sensor
(DTS). The DTS can be read using the Platform Environment Control Interface (PECI)
as described in Processor Temperature on page 72. Alternatively, when PECI is
monitored by the PCH, the processor temperature can be read from the PCH using the
SMBus protocol defined in Embedded Controller Support Provided by the PCH. The
temperature reported over PECI is always a negative value and represents a delta
below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT#
(see Processor Temperature on page 72). Systems that implement fan speed control
must be designed to use this data. Systems that do not alter the fan speed only need
to ensure the case temperature meets the thermal profile specifications.
Analysis indicates that real applications are unlikely to cause the processor to
consume maximum power dissipation for sustained time periods. Intel recommends
that complete thermal solution designs target the Thermal Design Power (TDP),
instead of the maximum processor power consumption. The Adaptive Thermal Monitor
feature is intended to help protect the processor in the event that an application
exceeds the TDP recommendation for a sustained time period. For more details on this
feature, see Adaptive Thermal Monitor on page 72. To ensure maximum flexibility
for future processors, systems should be designed to the Thermal Solution Capability
guidelines, even if a processor with lower power dissipation is currently planned.

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Processor—Thermal Management
Table 20. Desktop Processor Thermal Specifications

Product Max Max Min Power Max Min Power TTV Min TCASE Max TTV
Power Power Package C3 Power Package C6 Thermal (°C) TCASE (°C)
Package Package (W)9 Package (W)9 Design
C1E (W) C3 (W) 1, C6 (W) 1, Power
1, 2, 5, 9 3, 5, 9 4, 5, 9 (W) 6, 7, 10
See
Quad Core
Processor
Processor
23 17 1.0 3.5 0 65 5 Thermal
with
Profile
Graphics
section
Notes: 1. The package C-state power is the worst case power in the system configured as follows:
a. Memory configured for DDR3 1333 and populated with two DIMMs per channel.
b. DMI and PCIe links are at L1.
2. Specification at DTS = 50 °C and minimum voltage loadline.
5. These DTS values in Notes 2 – 4 are based on the TCC Activation MSR having a value of 100, see Processor
Temperature on page 72.
6. These values are specified at VCC_MAX and VNOM for all other voltage rails for all processor frequencies. Systems
must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCCP
exceeds VCCP_MAX at specified ICCP. See the loadline specifications.
7. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the
maximum power that the processor can dissipate. TDP is measured at DTS = -1. TDP is achieved with the Memory
configured for DDR3 1333 and 2 DIMMs per channel.
8. N/A
9. Not 100% tested. Specified by design characterization.
5.1 Desktop Processor Thermal Profiles

This section provides thermal profiles for the Desktop processor families.

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5.1.1 Processor Thermal Profile

Figure 15. Thermal Test Vehicle Thermal Profile for Processor
See the following table for discrete points that constitute the thermal profile.
Table 21. Thermal Test Vehicle Thermal Profile for Processor

Power (W) Tcase_max Power (W) Tcase_max Power (W) Tcase_max
(°C) (°C) (°C)
Y = 0.41*Power + 44.6 30 56.9 62 70.02
0 44.6 32 57.72 64 70.84
2 45.42 34 58.54 65 71.25
4 46.24 36 59.36
6 47.06 38 60.18
8 47.88 40 61
10 48.7 42 61.82
12 49.52 44 62.64
14 50.34 46 63.46
16 51.16 48 64.28
18 51.98 50 65.1
20 52.8 52 65.92
22 53.62 54 66.74
24 54.44 56 67.56
26 55.26 58 68.38
28 56.08 60 69.2
continued... continued...

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5.2 Thermal Metrology

The maximum Thermal Test Vehicle (TTV) case temperatures (TCASE-MAX) can be
derived from the data in the appropriate TTV thermal profile earlier in this chapter.
The TTV TCASE is measured at the geometric top center of the TTV integrated heat
spreader (IHS). The following figure illustrates the location where TCASE temperature
measurements should be made.
Figure 16. Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location
Measure TCASE at
the geometric
center of the
package
37.5
37.5
Note: THERM-X OF CALIFORNIA can machine the groove and attach a thermocouple to the
IHS. The supplier is subject to change without notice. THERM-X OF CALIFORNIA, 1837
Whipple Road, Hayward, Ca 94544. Ernesto B Valencia +1-510-441-7566 Ext. 242
[email protected]. The vendor part number is XTMS1565.
5.3 Fan Speed Control Scheme with Digital Thermal Sensor

(DTS) 1.1
To correctly use DTS 1.1, the designer must first select a worst case scenario TAMBIENT,
and ensure that the Fan Speed Control (FSC) can provide a ΨCA that is equivalent or
greater than the ΨCA specification.
The DTS 1.1 implementation consists of two points: a ΨCA at TCONTROL and a ΨCA at
DTS = -1.

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The ΨCA point at DTS = -1 defines the minimum ΨCA required at TDP considering the
worst case system design TAMBIENT design point:
ΨCA = (TCASE-MAX – TAMBIENT-TARGET) / TDP
For example, for a 95 W TDP part, the Tcase maximum is 72.6 °C and at a worst case
design point of 40 °C local ambient this will result in:
ΨCA = (72.6 – 40) / 95 = 0.34 °C/W
Similarly for a system with a design target of 45 °C ambient, the ΨCA at DTS = -1
needed will be 0.29 °C/W.
The second point defines the thermal solution performance (ΨCA) at TCONTROL. The
following table lists the required ΨCA for the various TDP processors.
These two points define the operational limits for the processor for DTS 1.1
implementation. At TCONTROL the fan speed must be programmed such that the
resulting ΨCA is better than or equivalent to the required ΨCA listed in the following
table. Similarly, the fan speed should be set at DTS = -1 such that the thermal
solution performance is better than or equivalent to the ΨCA requirements at TAMBIENT-
MAX. The fan speed controller must linearly ramp the fan speed from processor DTS =
TCONTROL to processor DTS = -1.
Figure 17. Digital Thermal Sensor (DTS) 1.1 Definition Points

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Table 22. Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above
TCONTROL
Processor ΨCA at DTS = ΨCA at DTS = -1 ΨCA at DTS = -1 ΨCA at DTS = -1
TDP TCONTROL1, 2 At System At System At System TAMBIENT-
At System TAMBIENT- TAMBIENT-MAX TAMBIENT-MAX MAX = 50 °C
MAX = 30 °C = 40 °C = 45 °C
65 W 0.684 0.481 0.404 0.327
Notes: 1. ΨCA at "DTS = TCONTROL" is applicable to systems that have an internal TRISE (TROOM temperature
to Processor cooling fan inlet) of less than 10 °C. In case the expected TRISE is greater than 10
°C, a correction factor should be used as explained below. For each 1 °C TRISE above 10 °C, the
correction factor (CF) is defined as CF = 1.7 / (processor TDP)
2. Example: A chassis TRISE assumption is 12 °C for a 95 W TDP processor:
CF = 1.7 / 95 W = 0.018 /W
For TRISE > 10 °C
ΨCA at TCONTROL = (Value provide in Column 2) – (TRISE – 10) * CF
ΨCA = 0.627 – (12 – 10) * 0.018 = 0.591 °C/W
In this case, the fan speed should be set slightly higher, equivalent to ΨCA = 0.591 °C/W
5.4 Fan Speed Control Scheme with Digital Thermal Sensor

(DTS) 2.0
To simplify processor thermal specification compliance, the processor calculates the
DTS Thermal Profile from TCONTROL Offset, TCC Activation Temperature, TDP, and the
Thermal Margin Slope provided in the following table.
Note: TCC Activation Offset is 0 for the processors.
Using the DTS Thermal Profile, the processor can calculate and report the Thermal
Margin, where a value less than 0 indicates that the processor needs additional
cooling, and a value greater than 0 indicates that the processor is sufficiently cooled.
Refer to the processor Thermal Mechanical Design Guidelines (TMDG) for additional
information (see Related Documents).

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Figure 18. Digital Thermal Sensor (DTS) Thermal Profile Definition
Table 23. Thermal Margin Slope

Die Configuration TDP (W) TCC Activation Temperature Thermal
(Native) Temperature (°C) Control Offset Margin
Core + GT MSR 1A2h 23:16 MSR 1A2h 15:8 Slope (°C /
W)
4+3e (4+3e) 65 96 10 0.791
5.5 Thermal Specifications

This section provides thermal specifications (Thermal Profile) and design guidelines for
enabled thermal solutions to cool the processor.
Performance Targets
The following table provides boundary conditions and performance targets as guidance
for thermal solution design. Thermal solutions must be able to comply with the
Maximum TCASE Thermal Profile.

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Table 24. Boundary Conditions, Performance Targets, and TCASE Specifications

TLA, Maximum
TCASE-MAX @
Processor Package TDP Platform TDP Heatsink3 Airflow, RPM, TCASE Thermal
Platform TDP6
ѰCA4 Profile5
40 °C y = 0.41 * 71.3 °C
Active Al Core Power + 44.6
4C/GT3 65W 65W 65W 3100 RPM
(DHA-B)
0.460 °C/W
Notes: 1. TDP shown here, 95W for example, represents the maximum expected platform TDP in the next generation
platform for this type of SKU. This placeholder value is provided as a guideline for hardware design for the next
generation platform.
2. N/A
3. .N/A
4. These boundary conditions and performance targets are used to generate processor thermal specifications and to
provide guidance for heatsink design. Values are for the heatsink shown in the adjacent column are calculated at
sea level, and are expected to meet the Thermal Profile at TDP. TLA is the local ambient temperature of the
heatsink inlet air. Airflow is through the heatsink fins with zero bypass for a passive heatsink. RPM is fan
revolutions per minute for an active heatsink. ѰCA is the maximum target (mean + 3 sigma) for the thermal
characterization parameter. For more information on the thermal characterization parameter, refer to the processor
Thermal Mechanical Design Guidelines (see Related Documents section).
5. Maximum TCASE Thermal Profile is the specification that must be complied to. Any Attempt to operate the processor
outside these operating limits may result in permanent damage to the processor and potentially other system
components.
6. TCASE-MAX at Platform TDP is calculated using the maximum TCASE Thermal Profile and the platform TDP.
7. ATCA Reference Heatsink supports Socket B and is not tooled for Socket H.
5.6 Processor Temperature

A software readable field in the TEMPERATURE_TARGET register contains the
minimum temperature at which the TCC will be activated and PROCHOT# will be
asserted. The TCC activation temperature is calibrated on a part-by-part basis and
normal factory variation may result in the actual TCC activation temperature being
higher than the value listed in the register. TCC activation temperatures may change
based on processor stepping, frequency or manufacturing efficiencies.
5.7 Adaptive Thermal Monitor

The Adaptive Thermal Monitor feature provides an enhanced method for controlling
the processor temperature when the processor silicon exceeds the Thermal Control
Circuit (TCC) activation temperature. Adaptive Thermal Monitor uses TCC activation to
reduce processor power using a combination of methods. The first method (Frequency
control, similar to Thermal Monitor 2 (TM2) in previous generation processors)
involves the processor reducing its operating frequency (using the core ratio
multiplier) and internal core voltage. This combination of lower frequency and core
voltage results in a reduction of the processor power consumption. The second
method (clock modulation, known as Thermal Monitor 1 or TM1 in previous generation
processors) reduces power consumption by modulating (starting and stopping) the
internal processor core clocks. The processor intelligently selects the appropriate TCC
method to use on a dynamic basis. BIOS is not required to select a specific method
(as with previous-generation processors supporting TM1 or TM2). The temperature at
which Adaptive Thermal Monitor activates the Thermal Control Circuit is factory
calibrated and is not user configurable. Snooping and interrupt processing are
performed in the normal manner while the TCC is active.

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When the TCC activation temperature is reached, the processor will initiate TM2 in
attempt to reduce its temperature. If TM2 is unable to reduce the processor
temperature, TM1 will be also be activated. TM1 and TM2 will work together (clocks
will be modulated at the lowest frequency ratio) to reduce power dissipation and
temperature.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC will only be activated for very short periods of time when running the most power
intensive applications. The processor performance impact due to these brief periods of
TCC activation is expected to be so minor that it would be immeasurable. An under-
designed thermal solution that is not able to prevent excessive activation of the TCC in
the anticipated ambient environment may cause a noticeable performance loss, and in
some cases may result in a TCASE that exceeds the specified maximum temperature
and may affect the long-term reliability of the processor. In addition, a thermal
solution that is significantly under designed may not be capable of cooling the
processor even when the TCC is active continuously. See the appropriate processor
Thermal Mechanical Design Guidelines for information on designing a compliant
thermal solution.
The Thermal Monitor does not require any additional hardware, software drivers, or
interrupt handling routines. The following sections provide more details on the
different TCC mechanisms used by the processor.
Frequency Control
When the Digital Temperature Sensor (DTS) reaches a value of 0 (DTS temperatures
reported using PECI may not equal zero when PROCHOT# is activated), the TCC will
be activated and the PROCHOT# signal will be asserted if configured as bi-directional.
This indicates the processor temperature has met or exceeded the factory calibrated
trip temperature and it will take action to reduce the temperature.
Upon activation of the TCC, the processor will stop the core clocks, reduce the core
ratio multiplier by 1 ratio and restart the clocks. All processor activity stops during this
frequency transition that occurs within 2 us. Once the clocks have been restarted at
the new lower frequency, processor activity resumes while the core voltage is reduced
by the internal voltage regulator. Running the processor at the lower frequency and
voltage will reduce power consumption and should allow the processor to cool off. If
after 1 ms the processor is still too hot (the temperature has not dropped below the
TCC activation point, DTS still = 0 and PROCHOT is still active), then a second
frequency and voltage transition will take place. This sequence of temperature
checking and frequency and voltage reduction will continue until either the minimum
frequency has been reached or the processor temperature has dropped below the TCC
activation point.
If the processor temperature remains above the TCC activation point even after the
minimum frequency has been reached, then clock modulation (described below) at
that minimum frequency will be initiated.
There is no end user software or hardware mechanism to initiate this automated TCC
activation behavior.
A small amount of hysteresis has been included to prevent rapid active/inactive

transitions of the TCC when the processor temperature is near the TCC activation
temperature. Once the temperature has dropped below the trip temperature and the
hysteresis timer has expired, the operating frequency and voltage transition back to

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the normal system operating point using the intermediate VID/frequency points.
Transition of the VID code will occur first, to insure proper operation as the frequency
is increased.
Clock Modulation
Clock modulation is a second method of thermal control available to the processor.

Clock modulation is performed by rapidly turning the clocks off and on at a duty cycle
that should reduce power dissipation by about 50% (typically a 30–50% duty cycle).
Clocks often will not be off for more than 32 microseconds when the TCC is active.
Cycle times are independent of processor frequency. The duty cycle for the TCC, when
activated by the Thermal Monitor, is factory configured and cannot be modified.
It is possible for software to initiate clock modulation with configurable duty cycles.
A small amount of hysteresis has been included to prevent rapid active/inactive

transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature and the hysteresis timer has expired, the TCC goes inactive and clock
modulation ceases.
Immediate Transition to Combined TM1 and TM2
When the TCC is activated, the processor will sequentially step down the ratio
multipliers and VIDs in an attempt to reduce the silicon temperature. If the
temperature continues to increase and exceeds the TCC activation temperature by
approximately 5 °C before the lowest ratio/VID combination has been reached, the
processor will immediately transition to the combined TM1/TM2 condition. The
processor remains in this state until the temperature has dropped below the TCC
activation point. Once below the TCC activation temperature, TM1 will be discontinued
and TM2 will be exited by stepping up to the appropriate ratio/VID state.
Critical Temperature Flag
If TM2 is unable to reduce the processor temperature, then TM1 will be also be
activated. TM1 and TM2 will then work together to reduce power dissipation and
temperature. It is expected that only a catastrophic thermal solution failure would
create a situation where both TM1 and TM2 are active.
If TM1 and TM2 have both been active for greater than 20 ms and the processor
temperature has not dropped below the TCC activation point, the Critical Temperature
Flag in the IA32_THERM_STATUS MSR will be set. This flag is an indicator of a
catastrophic thermal solution failure and that the processor cannot reduce its
temperature. Unless immediate action is taken to resolve the failure, the processor
will probably reach the Thermtrip temperature (see Testability Signals on page 84)
within a short time. To prevent possible permanent silicon damage, Intel recommends
removing power from the processor within ½ second of the Critical Temperature Flag
being set.
PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core
temperature has exceeded its specification. If Adaptive Thermal Monitor is enabled (it
must be enabled for the processor to be operating within specification), the TCC will
be active when PROCHOT# is asserted.

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The processor can be configured to generate an interrupt upon the assertion or de-
assertion of PROCHOT#.
By default, the PROCHOT# signal is set to bi-directional. However, it is recommended

to configure the signal as an input only. When configured as an input or bi-directional
signal, PROCHOT# can be used for thermally protecting other platform components
should they overheat as well. When PROCHOT# is driven by an external device:
• The package will immediately transition to the minimum operation points (voltage
and frequency) supported by the processor and graphics cores. This is contrary to
the internally-generated Adaptive Thermal Monitor response.
• Clock modulation is not activated.
The TCC will remain active until the system de-asserts PROCHOT#. The processor can
be configured to generate an interrupt upon assertion and de-assertion of the
PROCHOT# signal. Refer to the appropriate Platform Thermal Mechanical Design
Guidelines (see Related Doucments section) for details on implementing the bi-
directional PROCHOT# feature.
Note: Toggling PROCHOT# more than once in 1.5 ms period will result in constant Pn state
of the processor.
Note: A corner case exists for PROCHOT# configured as a bi-directional signal that can
cause several milliseconds of delay to a system assertion of PROCHOT# when the
output function is asserted.
As an output, PROCHOT# (Processor Hot) will go active when the processor

temperature monitoring sensor detects that one or more cores has reached its
maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system will activate the TCC for all cores. TCC activation when
PROCHOT# is asserted by the system will result in the processor immediately
transitioning to the minimum frequency and corresponding voltage (using Frequency
control). Clock modulation is not activated in this case. The TCC will remain active
until the system de-asserts PROCHOT#.
Use of PROCHOT# in input or bi-directional mode can allow VR thermal designs to

target maximum sustained current instead of maximum current. Systems should still
provide proper cooling for the Voltage Regulator (VR), and rely on PROCHOT# only as
a backup in case of system cooling failure. The system thermal design should allow
the power delivery circuitry to operate within its temperature specification even while
the processor is operating at its Thermal Design Power.
5.8 THERMTRIP# Signal

Regardless of whether or not Adaptive Thermal Monitor is enabled, in the event of a
catastrophic cooling failure, the processor will automatically shut down when the
silicon has reached an elevated temperature (refer to the THERMTRIP# definition in
Error and Thermal Protection Signals on page 85). THERMTRIP# activation is
independent of processor activity. The temperature at which THERMTRIP# asserts is
not user configurable and is not software visible.

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5.9 Digital Thermal Sensor

Each processor execution core has an on-die Digital Thermal Sensor (DTS) that
detects the core's instantaneous temperature. The DTS is the preferred method of
monitoring processor die temperature because:
• It is located near the hottest portions of the die.
• It can accurately track the die temperature and ensure that the Adaptive Thermal
Monitor is not excessively activated.
Temperature values from the DTS can be retrieved through:

• A software interface using processor Model Specific Register (MSR).
• A processor hardware interface as described in Platform Environmental Control
Interface (PECI) on page 37.
When temperature is retrieved by the processor MSR, it is the instantaneous

temperature of the given core. When temperature is retrieved using PECI, it is the
average of the highest DTS temperature in the package over a 256 ms time window.
Intel recommends using the PECI reported temperature for platform thermal control
that benefits from averaging, such as fan speed control. The average DTS
temperature may not be a good indicator of package Adaptive Thermal Monitor
activation or rapid increases in temperature that triggers the Out of Specification
status bit within the PACKAGE_THERM_STATUS MSR 1B1h and IA32_THERM_STATUS
MSR 19Ch.
Code execution is halted in C1 or deeper C-states. Package temperature can still be

monitored through PECI in lower C-states.
Unlike traditional thermal devices, the DTS outputs a temperature relative to the
maximum supported operating temperature of the processor (TjMAX), regardless of
TCC activation offset. It is the responsibility of software to convert the relative
temperature to an absolute temperature. The absolute reference temperature is
readable in the TEMPERATURE_TARGET MSR 1A2h. The temperature returned by the
DTS is an implied negative integer indicating the relative offset from TjMAX. The DTS
does not report temperatures greater than TjMAX. The DTS-relative temperature
readout directly impacts the Adaptive Thermal Monitor trigger point. When a package
DTS indicates that it has reached the TCC activation (a reading of 0h, except when the
TCC activation offset is changed), the TCC will activate and indicate an Adaptive
Thermal Monitor event. A TCC activation will lower both IA core and graphics core
frequency, voltage, or both. Changes to the temperature can be detected using two
programmable thresholds located in the processor thermal MSRs. These thresholds
have the capability of generating interrupts using the core's local APIC. Refer to the
Intel® 64 and IA-32 Architectures Software Developer’s Manual for specific register
and programming details.
5.9.1 Digital Thermal Sensor Accuracy (Taccuracy)

The error associated with DTS measurements will not exceed ±5 °C within the entire
operating range.

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5.10 Intel® Turbo Boost Technology Thermal Considerations

Intel Turbo Boost Technology allows processor cores and integrated graphics cores to
run faster than the baseline frequency. During a turbo event, the processor can
exceed its TDP power for brief periods. Turbo is invoked opportunistically and
automatically as long as the processor is conforming to its temperature, power
delivery, and current specification limits. Thus, thermal solutions and platform cooling
that are designed to less than thermal design guidance may experience thermal and
performance issues since more applications will tend to run at or near the maximum
power limit for significant periods of time.
5.10.1 Intel® Turbo Boost Technology Power Control and Reporting

Package processor core and internal graphics core powers are self monitored and
correspondingly reported out.
• With the processor turbo disabled, rolling average power over 5 seconds will not
exceed the TDP rating of the part for typical applications.
• With turbo enabled (see the Package Power Control section)
— For the PL1: Package rolling average of the power set in POWER_LIMIT_1
(TURBO_POWER_LIMIT MSR 0610h bits [14:0]) over time window set in
POWER_LIMIT_1_TIME (TURBO_POWER_LIMIT MSR 0610h bits [23:17]) must
be less than or equal to the TDP package power as read from the
PACKAGE_POWER_SKU MSR 0614h for typical applications. Power control is
valid only when the processor is operating in turbo. PL1 lower than the
package TDP is not guaranteed.
— For the PL2: Package power will be controlled to a value set in
POWER_LIMIT_2 (TURBO_POWER_LIMIT MSR 0610h bits [46:32]). Occasional
brief power excursions may occur for periods of less than 10 ms over PL2.
The processor monitors its own power consumption to control turbo behavior,
assuming the following:
• The power monitor is not 100% tested across all processors.
• The Power Limit 2 (PL2) control is only valid for power levels set at or above TDP
and under workloads with similar activity ratios as the product TDP workload. This
also assumes the processor is working within other product specifications.
• Setting power limits (PL1 or PL2) below TDP are not ensured to be followed, and
are not characterized for accuracy.
• Under unknown work loads and unforeseen applications the average processor
power may exceed Power Limit 1 (PL1).
• Uncharacterized workloads may exist that could result in higher turbo frequencies
and power. If that were to happen, the processor Thermal Control Circuitry (TCC)
would protect the processor. The TCC protection must be enabled by the platform
for the product to be within specification.
An illustration of Intel Turbo Boost Technology power control is shown in the following
sections and figures. Multiple controls operate simultaneously allowing for
customization for multiple system thermal and power limitations. These controls
provide turbo optimizations within system constraints.

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5.10.2 Package Power Control

The package power control settings of PL1, PL2, and PL3 Tau allow the designer to
configure Intel Turbo Boost Technology 2.0 to match the platform power delivery and
package thermal solution limitations.
• Power Limit 1 (PL1): A threshold for average power that will not exceed;
recommend to set equal to TDP power. PL1 should not be set higher than thermal
solution cooling limits.
• Power Limit 2 (PL2): A threshold that if exceeded, the PL2 rapid power limiting
algorithms will attempt to limit the spike above PL2.
• Power Limit 3 (PL3): A threshold that if exceeded, the PL3 rapid power limiting
algorithms will attempt to limit the duty cycle of spikes above PL3 by reactively
limiting frequency. This is an optional setting.
• Turbo Time Parameter (Tau): An averaging constant used for PL1 exponential
weighted moving average (EWMA) power calculation.
Notes: 1. Implementation of Intel Turbo Boost Technology 2.0 only requires configuring PL1,
PL1 Tau, and PL2.
2. PL3 is disabled by default.
Figure 19. Package Power Control

78 Order No.: 332376-001v1
Signal Description—Processor
6.0 Signal Description

This chapter describes the processor signals. The signals are arranged in functional
groups according to the associated interface or category. The following notations are
used to describe the signal type.
Notation Signal Type
I Input pin
O Output pin
I/O Bi-directional Input/Output pin
The signal description also includes the type of buffer used for the particular signal
(see the following table).
Table 25. Signal Description Buffer Types

Signal Description
PCI Express* interface signals. These signals are compatible with PCI Express 3.0
PCI Express* Signaling Environment AC Specifications and are AC coupled. The buffers are not 3.3 V-
tolerant. See the PCI Express Base Specification 3.0.
Direct Media Interface signals. These signals are compatible with PCI Express 2.0
DMI Signaling Environment AC Specifications, but are DC coupled. The buffers are not 3.3 V-
tolerant.
CMOS CMOS buffers. 1.05V- tolerant
DDR3/DDR3L DDR3/DDR3L buffers: 1.5 V- tolerant
Analog reference or output. May be used as a threshold voltage or for buffer

A
compensation
GTL Gunning Transceiver Logic signaling technology
Ref Voltage reference signal
Asynchronous 1 Signal has no timing relationship with any reference clock.
1. Qualifier for a buffer type.
6.1 System Memory Interface Signals

Table 26. Memory Channel A Signals
Signal Name Description Direction / Buffer
Type
Bank Select: These signals define which banks are selected O

SA_BS[2:0] within each SDRAM rank. DDR3/DDR3L
Write Enable Control Signal: This signal is used with O

SA_WE# SA_RAS# and SA_CAS# (along with SA_CS#) to define the
SDRAM Commands. DDR3/DDR3L
continued...

Order No.: 332376-001v1 79
Processor—Signal Description

Type
RAS Control Signal: This signal is used with SA_CAS# and O

SA_RAS# SA_WE# (along with SA_CS#) to define the SRAM Commands. DDR3/DDR3L
CAS Control Signal: This signal is used with SA_RAS# and O

SA_CAS# SA_WE# (along with SA_CS#) to define the SRAM Commands. DDR3/DDR3L
Data Strobes: SA_DQS[8:0] and its complement signal group

SA_DQS[8:0] make up a differential strobe pair. The data is captured at the I/O
SA_DQSN[8:0] crossing point of SA_DQS[8:0] and SA_DQS#[8:0] during read DDR3/DDR3L
and write transactions.
Data Bus: Channel A data signal interface to the SDRAM data I/O
SA_DQ[63:0] bus. DDR3/DDR3L
Memory Address: These signals are used to provide the O

SA_MA[15:0] multiplexed row and column address to the SDRAM. DDR3/DDR3L
SDRAM Differential Clock: These signals are Channel A

SDRAM Differential clock signal pairs. The crossing of the O
SA_CK[3:0] positive edge of SA_CK and the negative edge of its complement
SA_CK# are used to sample the command and control signals on DDR3/DDR3L
the SDRAM.
Clock Enable: (1 per rank). These signals are used to:

• Initialize the SDRAMs during power-up O
SA_CKE[3:0]
• Power-down SDRAM ranks DDR3/DDR3L
• Place all SDRAM ranks into and out of self-refresh during STR
Chip Select: (1 per rank). These signals are used to select O

SA_CS#[3:0] particular SDRAM components during the active state. There is
one Chip Select for each SDRAM rank. DDR3/DDR3L
On Die Termination: Active Termination Control. O

SA_ODT[3:0]
DDR3/DDR3L
Table 27. Memory Channel B Signals

Type
Bank Select: These signals define which banks are selected O

SB_BS[2:0] within each SDRAM rank. DDR3/DDR3L
Write Enable Control Signal: This signal is used with O

SB_WE# SB_RAS# and SB_CAS# (along with SB_CS#) to define the
SDRAM Commands. DDR3/DDR3L
RAS Control Signal: This signal is used with SB_CAS# and O

SB_RAS# SB_WE# (along with SB_CS#) to define the SRAM Commands. DDR3/DDR3L
CAS Control Signal: This signal is used with SB_RAS# and O

SB_CAS# SB_WE# (along with SB_CS#) to define the SRAM Commands. DDR3/DDR3L
Data Strobes: SB_DQS[8:0] and its complement signal group

SB_DQS[8:0] make up a differential strobe pair. The data is captured at the I/O
SB_DQSN[8:0] crossing point of SB_DQS[8:0] and its SB_DQS#[8:0] during DDR3/DDR3L
read and write transactions.
Data Bus: Channel B data signal interface to the SDRAM data I/O
SB_DQ[63:0] bus. DDR3/DDR3L
Memory Address: These signals are used to provide the O

SB_MA[15:0] multiplexed row and column address to the SDRAM. DDR3/DDR3L
continued...

80 Order No.: 332376-001v1

Type
SDRAM Differential Clock: Channel B SDRAM Differential

clock signal pair. The crossing of the positive edge of SB_CK O
SB_CK[3:0]
and the negative edge of its complement SB_CK# are used to DDR3/DDR3L
sample the command and control signals on the SDRAM.
Clock Enable: (1 per rank). These signals are used to:

• Initialize the SDRAMs during power-up.
O
SB_CKE[3:0] • Power-down SDRAM ranks.
DDR3/DDR3L
• Place all SDRAM ranks into and out of self-refresh during
STR.
Chip Select: (1 per rank). These signals are used to select O

SB_CS#[3:0] particular SDRAM components during the active state. There is
one Chip Select for each SDRAM rank. DDR3/DDR3L
On Die Termination: Active Termination Control. O

SB_ODT[3:0]
DDR3/DDR3L
6.2 Memory Reference and Compensation Signals

Table 28. Memory Reference and Compensation Signals
Signal Name Description Direction /
Buffer Type
System Memory Impedance Compensation: I

SM_RCOMP[2:0]
A
DDR3/DDR3L Reference Voltage: This signal is used as O

SM_VREF a reference voltage to the DDR3/DDR3L controller and is
defined as VDDQ/2 DDR3/DDR3L
Memory Channel A/B DIMM DQ Voltage Reference: O

SA_DIMM_VREFDQ
The output pins are connected to the DIMMs, and holds
SB_DIMM_VREFDQ DDR3/DDR3L
VDDQ/2 as reference voltage.

Order No.: 332376-001v1 81
6.3 Reset and Miscellaneous Signals

Table 29. Reset and Miscellaneous Signals
Buffer Type
Configuration Signals: The CFG signals have a default value of

'1' if not terminated on the board.
• CFG[1:0]: Reserved configuration lane. A test point may be
placed on the board for these lanes.
• CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
— 1 = Normal operation
— 0 = Lane numbers reversed.
• CFG[3]: MSR Privacy Bit Feature
— 1 = Debug capability is determined by
IA32_Debug_Interface_MSR (C80h) bit[0] setting
I/O
CFG[19:0] — 0 = IA32_Debug_Interface_MSR (C80h) bit[0] default
setting overridden GTL
• CFG[4]: Reserved configuration lane. A test point may be
placed on the board for this lane.
• CFG[6:5]: PCI Express* Bifurcation: 1
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
• CFG[19:7]: Reserved configuration lanes. A test point may
be placed on the board for these lands.
Configuration resistance compensation. Use a 49.9 Ω ±1%

CFG_RCOMP —
resistor to ground.
FC (Future Compatibility) signals are signals that are available for

FC_x compatibility with other processors. A test point may be placed —
on the board for these lands.
Power Management Sync: A sideband signal to communicate I

PM_SYNC power management status from the platform to the processor. CMOS
Signal is for debug. I

PWR_DEBUG# Asynchronous
CMOS
Signal is for IFDIM testing only. I

IST_TRIGGER
CMOS
Signal is for debug. If both THERMTRIP# and this signal are

simultaneously asserted, the processor has encountered an O
IVR_ERROR
unrecoverable power delivery fault and has engaged automatic CMOS
shutdown as a result.
Platform Reset pin driven by the PCH. I

RESET#
CMOS
RESERVED: All signals that are RSVD and RSVD_NCTF must be No Connect
RSVD
left unconnected on the board. Intel recommends that all Test Point
RSVD_TP RSVD_TP signals have via test points.
Non-Critical to
RSVD_NCTF
Function
DRAM Reset: Reset signal from processor to DRAM devices. One O

SM_DRAMRST# signal common to all channels. CMOS
TESTLO should be individually connected to VSS through a

TESTLO_x —
resistor.
Note: 1. PCIe bifurcation support varies with the processor and PCH SKUs used.

82 Order No.: 332376-001v1
6.4 PCI Express* Interface Signals

Table 30. PCI Express* Graphics Interface Signals
Signal Name Description Direction / Buffer Type
PCI Express Resistance Compensation I

PEG_RCOMP
A
PEG_RXP[15:0] PCI Express Receive Differential Pair I

PEG_RXN[15:0] PCI Express
PEG_TXP[15:0] PCI Express Transmit Differential Pair O

PEG_TXN[15:0] PCI Express
6.5 Display Interface Signals

Table 31. Display Interface Signals
Type
FDI_TXP[1:0] Intel Flexible Display Interface Transmit Differential Pair O

FDI_TXN[1:0] FDI
DDIB_TXP[3:0] Digital Display Interface Transmit Differential Pair O

DDIB_TXN[3:0] FDI
DDIC_TXP[3:0] Digital Display Interface Transmit Differential Pair O

DDIC_TXN[3:0] FDI
DDID_TXP[3:0] Digital Display Interface Transmit Differential Pair O

DDID_TXN[3:0] FDI
Intel Flexible Display Interface Sync I

FDI_CSYNC
CMOS
Intel Flexible Display Interface Hot-Plug Interrupt I

DISP_INT Asynchronous
CMOS
6.6 Direct Media Interface (DMI)

Table 32. Direct Media Interface (DMI) – Processor to PCH Serial Interface
Type
DMI_RXP[3:0] DMI Input from PCH: Direct Media Interface receive I

DMI_RXN[3:0] differential pair. DMI
DMI_TXP[3:0] DMI Output to PCH: Direct Media Interface transmit O

DMI_TXN[3:0] differential pair. DMI

Order No.: 332376-001v1 83
6.7 Phase Locked Loop (PLL) Signals

Table 33. Phase Locked Loop (PLL) Signals
Type
BCLKP Differential bus clock input to the processor I

BCLKN Diff Clk
DPLL_REF_CLKP Embedded Display Port PLL Differential Clock In: I

DPLL_REF_CLKN 135 MHz Diff Clk
SSC_DPLL_REF_CLKP Spread Spectrum Embedded DisplayPort PLL I

SSC_ DPLL_REF_CLKN Differential Clock In: 135 MHz Diff Clk
6.8 Testability Signals

Table 34. Testability Signals
Type
Breakpoint and Performance Monitor Signals:

Outputs from the processor that indicate the status of I/O
BPM#[7:0]
breakpoints and programmable counters used for GTL
monitoring processor performance.
Debug Reset: This signal is used only in systems where

no debug port is implemented on the system board.
DBR# O
DBR# is used by a debug port interposer so that an in-
target probe can drive system reset.
Processor Ready: This signal is a processor output O

PRDY# used by debug tools to determine processor debug
readiness. GTL
Processor Request: This signal is used by debug tools I

PREQ# to request debug operation of the processor. GTL
Test Clock: This signal provides the clock input for the
processor Test Bus (also known as the Test Access I
TCK
Port). This signal must be driven low or allowed to float GTL
during power on Reset.
Test Data In: This signal transfers serial test data into I
TDI the processor. This signal provides the serial input
needed for JTAG specification support. GTL
Test Data Out: This signal transfers serial test data out O
TDO of the processor. This signal provides the serial output
needed for JTAG specification support. Open Drain
Test Mode Select: This is a JTAG specification I

TMS supported signal used by debug tools. GTL
Test Reset: This signal resets the Test Access Port I

TRST# (TAP) logic. This signal must be driven low during power
on Reset. GTL

84 Order No.: 332376-001v1
6.9 Error and Thermal Protection Signals

Table 35. Error and Thermal Protection Signals
Type
Catastrophic Error: This signal indicates that the system has

experienced a catastrophic error and cannot continue to
operate. The processor will set this for non-recoverable O
CATERR# machine check errors or other unrecoverable internal errors.
CATERR# is used for signaling the following types of errors: GTL
Legacy MCERRs, CATERR# is asserted for 16 BCLKs. Legacy
IERRs, CATERR# remains asserted until warm or cold reset.
Platform Environment Control Interface: A serial I/O

PECI sideband interface to the processor, it is used primarily for
thermal, power, and error management. Asynchronous
Processor Hot: PROCHOT# goes active when the processor

temperature monitoring sensor(s) detects that the processor
has reached its maximum safe operating temperature. This GTL Input
PROCHOT#
indicates that the processor Thermal Control Circuit (TCC) has Open-Drain Output
been activated, if enabled. This signal can also be driven to
the processor to activate the TCC.
Thermal Trip: The processor protects itself from catastrophic

overheating by use of an internal thermal sensor. This sensor
is set well above the normal operating temperature to ensure O
THERMTRIP# that there are no false trips. The processor will stop all Asynchronous OD
execution when the junction temperature exceeds Asynchronous CMOS
approximately 130 °C. This is signaled to the system by the
THERMTRIP# pin.
6.10 Power Sequencing Signals

Table 36. Power Sequencing Signals
Type
SM_DRAMPWROK Processor Input: This signal I

SM_DRAMPWROK connects to the PCH DRAMPWROK. Asynchronous CMOS
The processor requires this input signal to be a clean

indication that the VCC and VDDQ power supplies are
stable and within specifications. This requirement
applies regardless of the S-state of the processor. I
PWRGOOD 'Clean' implies that the signal will remain low (capable
of sinking leakage current), without glitches, from the Asynchronous CMOS
time that the power supplies are turned on until the
supplies come within specification. The signal must
then transition monotonically to a high state.
SKTOCC# (Socket Occupied) / PROC_DETECT#:

Processor Detect: This signal is pulled down directly
(0 Ohms) on the processor package to ground. There
SKTOCC# —
is no connection to the processor silicon for this signal.
System board designers may use this signal to
determine if the processor is present.

Order No.: 332376-001v1 85
6.11 Processor Power Signals

Table 37. Processor Power Signals
Type
VCC Processor core power rail. Ref
VCCIO_OUT Processor power reference for I/O. Ref
VDDQ Processor I/O supply voltage for DDR3. Ref
VCCST Sustain voltage for the processor in standby modes Ref
VCOMP_OUT Processor power reference for PEG/Display RCOMP. Ref
The processor requires this input signal to be a clean

indication that the VCCST and VDDQ power supplies
are stable and within specifications. This signal must
have a valid level during both S0 and S3 power I
VCCST_PWRGD states. 'Clean' implies that the signal will remain low
(capable of sinking leakage current), without glitches, Asynchronous CMOS
from the time that the power supplies are turned on
until the supplies come within specification. The signal
must then transition monotonically to a high state.
VIDALERT#, VIDSCLK, and VIDSCLK comprise a three Input GTL/ Output Open
VIDSOUT
signal serial synchronous interface used to transfer Drain
VIDSCLK power management information between the Output Open Drain
VIDALERT# processor and the voltage regulator controllers.
Input CMOS
6.12 Sense Signals

Table 38. Sense Signals
Buffer Type
VCC_SENSE and VSS_SENSE provide an isolated, low-

VCC_SENSE impedance connection to the processor input VCC voltage O
VSS_SENSE and ground. The signals can be used to sense or measure A
voltage near the silicon.
6.13 Ground and Non-Critical to Function (NCTF) Signals

Table 39. Ground and Non-Critical to Function (NCTF) Signals
Buffer Type
VSS Processor ground node GND
Non-Critical to Function: These pins are for package

VSS_NCTF —
mechanical reliability.

86 Order No.: 332376-001v1
6.14 Processor Internal Pull-Up / Pull-Down Terminations

Table 40. Processor Internal Pull-Up / Pull-Down Terminations
Signal Name Pull Up / Pull Down Rail Value
BPM[7:0] Pull Up VCCIO_TERM 40–60 Ω
PREQ# Pull Up VCCIO_TERM 40–60 Ω
TDI Pull Up VCCIO_TERM 30–70 Ω
TMS Pull Up VCCIO_TERM 30–70 Ω
CFG[17:0] Pull Up VCCIO_OUT 5–8 kΩ
CATERR# Pull Up VCCIO_TERM 30–70 Ω

Order No.: 332376-001v1 87
Processor—Electrical Specifications
7.0 Electrical Specifications

This chapter provides the processor electrical specifications including integrated
voltage regulator (VR), VCC Voltage Identification (VID), reserved and unused signals,
signal groups, Test Access Points (TAP), and DC specifications.
7.1 Integrated Voltage Regulator

A feature to the processor is the integration of platform voltage regulators into the
processor. Due to this integration, the processor has one main voltage rail (VCC) and a
voltage rail for the memory interface (VDDQ) , compared to six voltage rails on
previous processors. The VCC voltage rail will supply the integrated voltage regulators
which in turn will regulate to the appropriate voltages for the cores, cache, system
agent, and graphics. This integration allows the processor to better control on-die
voltages to optimize between performance and power savings. The processor VCC rail
will remain a VID-based voltage with a loadline similar to the core voltage rail (also
called VCC) in previous processors.
7.2 Power and Ground Lands

The processor has VCC, VDDQ, and VSS (ground) lands for on-chip power distribution.
All power lands must be connected to their respective processor power planes; all VSS
lands must be connected to the system ground plane. Use of multiple power and
ground planes is recommended to reduce I*R drop. The VCC lands must be supplied
with the voltage determined by the processor Serial Voltage IDentification (SVID)
interface. Table 41 on page 89 specifies the voltage level for the various VIDs.
7.3 VCC Voltage Identification (VID)

The processor uses three signals for the serial voltage identification interface to
support automatic selection of voltages. The following table specifies the voltage level
corresponding to the 8-bit VID value transmitted over serial VID. A ‘1’ in this table
refers to a high voltage level and a ‘0’ refers to a low voltage level. If the voltage
regulation circuit cannot supply the voltage that is requested, the voltage regulator
must disable itself. VID signals are CMOS push/pull drivers. See the Voltage and
Current Specifications section for the DC specifications for these signals. The VID
codes will change due to temperature and/or current load changes to minimize the
power of the part. A voltage range is provided in the Voltage and Current
Specifications section. The specifications are set so that one voltage regulator can
operate with all supported frequencies.
Individual processor VID values may be set during manufacturing so that two devices
at the same core frequency may have different default VID settings. This is shown in
the VID range values in the Voltage and Current Specifications section. The processor
provides the ability to operate while transitioning to an adjacent VID and its
associated voltage. This will represent a DC shift in the loadline.

88 Order No.: 332376-001v1
Electrical Specifications—Processor
Table 41. Voltage Regulator (VR) 12.5 Voltage Identification

B B B B B B B B Hex VCC B B B B B B B B Hex VCC
i i i i i i i i i i i i i i i i
t t t t t t t t t t t t t t t t
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 00h 0.0000 0 0 1 0 0 0 0 1 21h 0.8200
0 0 0 0 0 0 0 1 01h 0.5000 0 0 1 0 0 0 1 0 22h 0.8300
0 0 0 0 0 0 1 0 02h 0.5100 0 0 1 0 0 0 1 1 23h 0.8400
0 0 0 0 0 0 1 1 03h 0.5200 0 0 1 0 0 1 0 0 24h 0.8500
0 0 0 0 0 1 0 0 04h 0.5300 0 0 1 0 0 1 0 1 25h 0.8600
0 0 0 0 0 1 0 1 05h 0.5400 0 0 1 0 0 1 1 0 26h 0.8700
0 0 0 0 0 1 1 0 06h 0.5500 0 0 1 0 0 1 1 1 27h 0.8800
0 0 0 0 0 1 1 1 07h 0.5600 0 0 1 0 1 0 0 0 28h 0.8900
0 0 0 0 1 0 0 0 08h 0.5700 0 0 1 0 1 0 0 1 29h 0.9000
0 0 0 0 1 0 0 1 09h 0.5800 0 0 1 0 1 0 1 0 2Ah 0.9100
0 0 0 0 1 0 1 0 0Ah 0.5900 0 0 1 0 1 0 1 1 2Bh 0.9200
0 0 0 0 1 0 1 1 0Bh 0.6000 0 0 1 0 1 1 0 0 2Ch 0.9300
0 0 0 0 1 1 0 0 0Ch 0.6100 0 0 1 0 1 1 0 1 2Dh 0.9400
0 0 0 0 1 1 0 1 0Dh 0.6200 0 0 1 0 1 1 1 0 2Eh 0.9500
0 0 0 0 1 1 1 0 0Eh 0.6300 0 0 1 0 1 1 1 1 2Fh 0.9600
0 0 0 0 1 1 1 1 0Fh 0.6400 0 0 1 1 0 0 0 0 30h 0.9700
0 0 0 1 0 0 0 0 10h 0.6500 0 0 1 1 0 0 0 1 31h 0.9800
0 0 0 1 0 0 0 1 11h 0.6600 0 0 1 1 0 0 1 0 32h 0.9900
0 0 0 1 0 0 1 0 12h 0.6700 0 0 1 1 0 0 1 1 33h 1.0000
0 0 0 1 0 0 1 1 13h 0.6800 0 0 1 1 0 1 0 0 34h 1.0100
0 0 0 1 0 1 0 0 14h 0.6900 0 0 1 1 0 1 0 1 35h 1.0200
0 0 0 1 0 1 0 1 15h 0.7000 0 0 1 1 0 1 1 0 36h 1.0300
0 0 0 1 0 1 1 0 16h 0.7100 0 0 1 1 0 1 1 1 37h 1.0400
0 0 0 1 0 1 1 1 17h 0.7200 0 0 1 1 1 0 0 0 38h 1.0500
0 0 0 1 1 0 0 0 18h 0.7300 0 0 1 1 1 0 0 1 39h 1.0600
0 0 0 1 1 0 0 1 19h 0.7400 0 0 1 1 1 0 1 0 3Ah 1.0700
0 0 0 1 1 0 1 0 1Ah 0.7500 0 0 1 1 1 0 1 1 3Bh 1.0800
0 0 0 1 1 0 1 1 1Bh 0.7600 0 0 1 1 1 1 0 0 3Ch 1.0900
0 0 0 1 1 1 0 0 1Ch 0.7700 0 0 1 1 1 1 0 1 3Dh 1.1000
0 0 0 1 1 1 0 1 1Dh 0.7800 0 0 1 1 1 1 1 0 3Eh 1.1100
0 0 0 1 1 1 1 0 1Eh 0.7900 0 0 1 1 1 1 1 1 3Fh 1.1200
0 0 0 1 1 1 1 1 1Fh 0.8000 0 1 0 0 0 0 0 0 40h 1.1300
0 0 1 0 0 0 0 0 20h 0.8100 0 1 0 0 0 0 0 1 41h 1.1400


Order No.: 332376-001v1 89

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 1 0 0 0 0 1 0 42h 1.1500 0 1 1 0 0 1 0 0 64h 1.4900
0 1 0 0 0 0 1 1 43h 1.1600 0 1 1 0 0 1 0 1 65h 1.5000
0 1 0 0 0 1 0 0 44h 1.1700 0 1 1 0 0 1 1 0 66h 1.5100
0 1 0 0 0 1 0 1 45h 1.1800 0 1 1 0 0 1 1 1 67h 1.5200
0 1 0 0 0 1 1 0 46h 1.1900 0 1 1 0 1 0 0 0 68h 1.5300
0 1 0 0 0 1 1 1 47h 1.2000 0 1 1 0 1 0 0 1 69h 1.5400
0 1 0 0 1 0 0 0 48h 1.2100 0 1 1 0 1 0 1 0 6Ah 1.5500
0 1 0 0 1 0 0 1 49h 1.2200 0 1 1 0 1 0 1 1 6Bh 1.5600
0 1 0 0 1 0 1 0 4Ah 1.2300 0 1 1 0 1 1 0 0 6Ch 1.5700
0 1 0 0 1 0 1 1 4Bh 1.2400 0 1 1 0 1 1 0 1 6Dh 1.5800
0 1 0 0 1 1 0 0 4Ch 1.2500 0 1 1 0 1 1 1 0 6Eh 1.5900
0 1 0 0 1 1 0 1 4Dh 1.2600 0 1 1 0 1 1 1 1 6Fh 1.6000
0 1 0 0 1 1 1 0 4Eh 1.2700 0 1 1 1 0 0 0 0 70h 1.6100
0 1 0 0 1 1 1 1 4Fh 1.2800 0 1 1 1 0 0 0 1 71h 1.6200
0 1 0 1 0 0 0 0 50h 1.2900 0 1 1 1 0 0 1 0 72h 1.6300
0 1 0 1 0 0 0 1 51h 1.3000 0 1 1 1 0 0 1 1 73h 1.6400
0 1 0 1 0 0 1 0 52h 1.3100 0 1 1 1 0 1 0 0 74h 1.6500
0 1 0 1 0 0 1 1 53h 1.3200 0 1 1 1 0 1 0 1 75h 1.6600
0 1 0 1 0 1 0 0 54h 1.3300 0 1 1 1 0 1 1 0 76h 1.6700
0 1 0 1 0 1 0 1 55h 1.3400 0 1 1 1 0 1 1 1 77h 1.6800
0 1 0 1 0 1 1 0 56h 1.3500 0 1 1 1 1 0 0 0 78h 1.6900
0 1 0 1 0 1 1 1 57h 1.3600 0 1 1 1 1 0 0 1 79h 1.7000
0 1 0 1 1 0 0 0 58h 1.3700 0 1 1 1 1 0 1 0 7Ah 1.7100
0 1 0 1 1 0 0 1 59h 1.3800 0 1 1 1 1 0 1 1 7Bh 1.7200
0 1 0 1 1 0 1 0 5Ah 1.3900 0 1 1 1 1 1 0 0 7Ch 1.7300
0 1 0 1 1 0 1 1 5Bh 1.4000 0 1 1 1 1 1 0 1 7Dh 1.7400
0 1 0 1 1 1 0 0 5Ch 1.4100 0 1 1 1 1 1 1 0 7Eh 1.7500
0 1 0 1 1 1 0 1 5Dh 1.4200 0 1 1 1 1 1 1 1 7Fh 1.7600
0 1 0 1 1 1 1 0 5Eh 1.4300 1 0 0 0 0 0 0 0 80h 1.7700
0 1 0 1 1 1 1 1 5Fh 1.4400 1 0 0 0 0 0 0 1 81h 1.7800
0 1 1 0 0 0 0 0 60h 1.4500 1 0 0 0 0 0 1 0 82h 1.7900
0 1 1 0 0 0 0 1 61h 1.4600 1 0 0 0 0 0 1 1 83h 1.8000
0 1 1 0 0 0 1 0 62h 1.4700 1 0 0 0 0 1 0 0 84h 1.8100
0 1 1 0 0 0 1 1 63h 1.4800 1 0 0 0 0 1 0 1 85h 1.8200


90 Order No.: 332376-001v1

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1 0 0 0 0 1 1 0 86h 1.8300 1 0 1 0 1 0 0 0 A8h 2.1700
1 0 0 0 0 1 1 1 87h 1.8400 1 0 1 0 1 0 0 1 A9h 2.1800
1 0 0 0 1 0 0 0 88h 1.8500 1 0 1 0 1 0 1 0 AAh 2.1900
1 0 0 0 1 0 0 1 89h 1.8600 1 0 1 0 1 0 1 1 ABh 2.2000
1 0 0 0 1 0 1 0 8Ah 1.8700 1 0 1 0 1 1 0 0 ACh 2.2100
1 0 0 0 1 0 1 1 8Bh 1.8800 1 0 1 0 1 1 0 1 ADh 2.2200
1 0 0 0 1 1 0 0 8Ch 1.8900 1 0 1 0 1 1 1 0 AEh 2.2300
1 0 0 0 1 1 0 1 8Dh 1.9000 1 0 1 0 1 1 1 1 AFh 2.2400
1 0 0 0 1 1 1 0 8Eh 1.9100 1 0 1 1 0 0 0 0 B0h 2.2500
1 0 0 0 1 1 1 1 8Fh 1.9200 1 0 1 1 0 0 0 1 B1h 2.2600
1 0 0 1 0 0 0 0 90h 1.9300 1 0 1 1 0 0 1 0 B2h 2.2700
1 0 0 1 0 0 0 1 91h 1.9400 1 0 1 1 0 0 1 1 B3h 2.2800
1 0 0 1 0 0 1 0 92h 1.9500 1 0 1 1 0 1 0 0 B4h 2.2900
1 0 0 1 0 0 1 1 93h 1.9600 1 0 1 1 0 1 0 1 B5h 2.3000
1 0 0 1 0 1 0 0 94h 1.9700 1 0 1 1 0 1 1 0 B6h 2.3100
1 0 0 1 0 1 0 1 95h 1.9800 1 0 1 1 0 1 1 1 B7h 2.3200
1 0 0 1 0 1 1 0 96h 1.9900 1 0 1 1 1 0 0 0 B8h 2.3300
1 0 0 1 0 1 1 1 97h 2.0000 1 0 1 1 1 0 0 1 B9h 2.3400
1 0 0 1 1 0 0 0 98h 2.0100 1 0 1 1 1 0 1 0 BAh 2.3500
1 0 0 1 1 0 0 1 99h 2.0200 1 0 1 1 1 0 1 1 BBh 2.3600
1 0 0 1 1 0 1 0 9Ah 2.0300 1 0 1 1 1 1 0 0 BCh 2.3700
1 0 0 1 1 0 1 1 9Bh 2.0400 1 0 1 1 1 1 0 1 BDh 2.3800
1 0 0 1 1 1 0 0 9Ch 2.0500 1 0 1 1 1 1 1 0 BEh 2.3900
1 0 0 1 1 1 0 1 9Dh 2.0600 1 0 1 1 1 1 1 1 BFh 2.4000
1 0 0 1 1 1 1 0 9Eh 2.0700 1 1 0 0 0 0 0 0 C0h 2.4100
1 0 0 1 1 1 1 1 9Fh 2.0800 1 1 0 0 0 0 0 1 C1h 2.4200
1 0 1 0 0 0 0 0 A0h 2.0900 1 1 0 0 0 0 1 0 C2h 2.4300
1 0 1 0 0 0 0 1 A1h 2.1000 1 1 0 0 0 0 1 1 C3h 2.4400
1 0 1 0 0 0 1 0 A2h 2.1100 1 1 0 0 0 1 0 0 C4h 2.4500
1 0 1 0 0 0 1 1 A3h 2.1200 1 1 0 0 0 1 0 1 C5h 2.4600
1 0 1 0 0 1 0 0 A4h 2.1300 1 1 0 0 0 1 1 0 C6h 2.4700
1 0 1 0 0 1 0 1 A5h 2.1400 1 1 0 0 0 1 1 1 C7h 2.4800
1 0 1 0 0 1 1 0 A6h 2.1500 1 1 0 0 1 0 0 0 C8h 2.4900
1 0 1 0 0 1 1 1 A7h 2.1600 1 1 0 0 1 0 0 1 C9h 2.5000


Order No.: 332376-001v1 91

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1 1 0 0 1 0 1 0 CAh 2.5100 1 1 1 0 1 1 0 0 ECh 2.8500
1 1 0 0 1 0 1 1 CBh 2.5200 1 1 1 0 1 1 0 1 EDh 2.8600
1 1 0 0 1 1 0 0 CCh 2.5300 1 1 1 0 1 1 1 0 EEh 2.8700
1 1 0 0 1 1 0 1 CDh 2.5400 1 1 1 0 1 1 1 1 EFh 2.8800
1 1 0 0 1 1 1 0 CEh 2.5500 1 1 1 1 0 0 0 0 F0h 2.8900
1 1 0 0 1 1 1 1 CFh 2.5600 1 1 1 1 0 0 0 1 F1h 2.9000
1 1 0 1 0 0 0 0 D0h 2.5700 1 1 1 1 0 0 1 0 F2h 2.9100
1 1 0 1 0 0 0 1 D1h 2.5800 1 1 1 1 0 0 1 1 F3h 2.9200
1 1 0 1 0 0 1 0 D2h 2.5900 1 1 1 1 0 1 0 0 F4h 2.9300
1 1 0 1 0 0 1 1 D3h 2.6000 1 1 1 1 0 1 0 1 F5h 2.9400
1 1 0 1 0 1 0 0 D4h 2.6100 1 1 1 1 0 1 1 0 F6h 2.9500
1 1 0 1 0 1 0 1 D5h 2.6200 1 1 1 1 0 1 1 1 F7h 2.9600
1 1 0 1 0 1 1 0 D6h 2.6300 1 1 1 1 1 0 0 0 F8h 2.9700
1 1 0 1 0 1 1 1 D7h 2.6400 1 1 1 1 1 0 0 1 F9h 2.9800
1 1 0 1 1 0 0 0 D8h 2.6500 1 1 1 1 1 0 1 0 FAh 2.9900
1 1 0 1 1 0 0 1 D9h 2.6600 1 1 1 1 1 0 1 1 FBh 3.0000
1 1 0 1 1 0 1 0 DAh 2.6700 1 1 1 1 1 1 0 0 FCh 3.0100
1 1 0 1 1 0 1 1 DBh 2.6800 1 1 1 1 1 1 0 1 FDh 3.0200
1 1 0 1 1 1 0 0 DCh 2.6900 1 1 1 1 1 1 1 0 FEh 3.0300
1 1 0 1 1 1 0 1 DDh 2.7000 1 1 1 1 1 1 1 1 FFh 3.0400
1 1 0 1 1 1 1 0 DEh 2.7100
1 1 0 1 1 1 1 1 DFh 2.7200
1 1 1 0 0 0 0 0 E0h 2.7300
1 1 1 0 0 0 0 1 E1h 2.7400
1 1 1 0 0 0 1 0 E2h 2.7500
1 1 1 0 0 0 1 1 E3h 2.7600
1 1 1 0 0 1 0 0 E4h 2.7700
1 1 1 0 0 1 0 1 E5h 2.7800
1 1 1 0 0 1 1 0 E6h 2.7900
1 1 1 0 0 1 1 1 E7h 2.8000
1 1 1 0 1 0 0 0 E8h 2.8100
1 1 1 0 1 0 0 1 E9h 2.8200
1 1 1 0 1 0 1 0 EAh 2.8300
1 1 1 0 1 0 1 1 EBh 2.8400
continued...

92 Order No.: 332376-001v1
7.4 Reserved or Unused Signals

The following are the general types of reserved (RSVD) signals and connection
guidelines:
• RSVD – these signals should not be connected
• RSVD_TP – these signals should be routed to a test point
• RSVD_NCTF – these signals are non-critical to function and may be left un-
connected
Arbitrary connection of these signals to VCC, VDDQ, VSS, or to any other signal
(including each other) may result in component malfunction or incompatibility with
future processors. See Signal Description on page 79 for a pin listing of the processor
and the location of all reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an

appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (VSS). Unused outputs maybe left unconnected; however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability.
7.5 Signal Groups

Signals are grouped by buffer type and similar characteristics as listed in the following
table. The buffer type indicates which signaling technology and specifications apply to
the signals. All the differential signals and selected DDR3L and Control Sideband
signals have On-Die Termination (ODT) resistors. Some signals do not have ODT and
need to be terminated on the board.
Note: All Control Sideband Asynchronous signals are required to be asserted/de-asserted for
at least 10 BCLKs with maximum Trise/Tfall of 6 ns for the processor to recognize the
proper signal state. See the DC Specifications section and AC Specifications section.
Table 42. Signal Groups

Signal Group Type Signals
System Reference Clock
Differential CMOS Input BCLKP, BCLKN, DPLL_REF_CLKP, DPLL_REF_CLKN,

SSC_DPLL_REF_CLKP, SSC_DPLL_REF_CLKN
DDR3 / DDR3L Reference Clocks 2
Differential DDR3/DDR3L SA_CKP[3:0], SA_CKN[3:0], SB_CKP[3:0], SB_CKN[3:0]

Output
DDR3 / DDR3L Command Signals 2
Single ended DDR3/DDR3L SA_BS[2:0], SB_BS[2:0], SA_WE#, SB_WE#, SA_RAS#,

Output SB_RAS#, SA_CAS#, SB_CAS#, SA_MA[15:0], SB_MA[15:0]
DDR3 / DDR3L Control Signals 2
Single ended DDR3/DDR3L SA_CKE[3:0], SB_CKE[3:0], SA_CS#[3:0], SB_CS#[3:0],

Output SA_ODT[3:0], SB_ODT[3:0]
Single ended CMOS Output SM_DRAMRST#

continued...

Order No.: 332376-001v1 93
DDR3 / DDR3L Data Signals 2
Single ended DDR3/DDR3L Bi- SA_DQ[63:0], SB_DQ[63:0]

directional
Differential DDR3/DDR3L Bi- SA_DQSP[7:0], SA_DQSN[7:0], SB_DQSP[7:0], SB_DQSN[7:0]

directional
DDR3 / DDR3L Compensation
Analog Input SM_RCOMP[2:0]
DDR3 / DDR3L Reference Voltage Signals
DDR3/DDR3L SM_VREF, SA_DIMM_VREFDQ, SB_DIMM_VREFDQ

Output
Testability (ITP/XDP)
Single ended CMOS Input TCK, TDI, TMS, TRST#
Single ended GTL TDO
Single ended Output DBR#
Single ended GTL BPM#[7:0]
Single ended GTL PREQ#
Single ended GTL PRDY#
Control Sideband
Single ended GTL Input/Open PROCHOT#

Drain Output
Single ended Asynchronous THERMTRIP#, IVR_ERROR

CMOS Output
Single ended GTL CATERR#
Single ended Asynchronous PM_SYNC,RESET#, PWRGOOD, PWR_DEBUG#

CMOS Input
Single ended Asynchronous Bi- PECI

directional
Single ended GTL Bi-directional CFG[19:0]
Single ended Analog Input SM_RCOMP[2:0]
Voltage Regulator
Single ended CMOS Input VR_READY
Single ended CMOS Input VIDALERT#
Single ended Open Drain Output VIDSCLK
Single ended GTL Input/Open VIDSOUT

Drain Output
Differential Analog Output VCC_SENSE, VSS_SENSE
Power / Ground / Other
Single ended Power VCC, VDDQ, VCCST
Ground VSS, VSS_NCTF 3
No Connect RSVD, RSVD_NCTF

continued...

94 Order No.: 332376-001v1
Test Point RSVD_TP
Other SKTOCC#,
PCI Express* Graphics
Differential PCI Express Input PEG_RXP[15:0], PEG_RXN[15:0]
Differential PCI Express Output PEG_TXP[15:0], PEG_TXN[15:0]
Single ended Analog Input PEG_RCOMP
Digital Media Interface (DMI)
Differential DMI Input DMI_RXP[3:0], DMI_RXN[3:0]
Differential DMI Output DMI_TXP[3:0], DMI_TXN[3:0]
Digital Display Interface
Differential DDI Output DDIB_TXP[3:0], DDIB_TXN[3:0], DDIC_TXP[3:0],

DDIC_TXN[3:0], DDID_TXP[3:0], DDID_TXN[3:0]
Intel® FDI
Single ended CMOS Input FDI_CSYNC
Single ended Asynchronous DISP_INT

CMOS Input
Differential FDI Output FDI_TXP[1:0], FDI_TXN[1:0]
Notes: 1. See Signal Description on page 79 for signal description details.

2. SA and SB refer to DDR3/DDR3L Channel A and DDR3/DDR3L Channel B.
7.6 Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port
(TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any
other components within the system. A translation buffer should be used to connect to
the rest of the chain unless one of the other components is capable of accepting an
input of the appropriate voltage. Two copies of each signal may be required with each
driving a different voltage level.
The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE
1149.6-2003 standards. A few of the I/O pins may support only one of those
standards.
7.7 DC Specifications
The processor DC specifications in this section are defined at the processor pins,
unless noted otherwise. See Signal Description on page 79 for the processor pin
listings and signal definitions.
• The DC specifications for the DDR3L signals are listed in the Voltage and Current
Specifications section.
• The Voltage and Current Specifications section lists the DC specifications for the
processor and are valid only while meeting specifications for junction temperature,
clock frequency, and input voltages. Read all notes associated with each
parameter.

Order No.: 332376-001v1 95
• AC tolerances for all DC rails include dynamic load currents at switching

frequencies up to 1 MHz.
7.8 Voltage and Current Specifications

Table 43. Processor Core Active and Idle Mode DC Voltage and Current Specifications
Symbol Parameter Min Typ Max Unit Note1
Operational
VID Range 1.65 1.75 1.86 V 2
VID
Idle VID
VID Range 1.5 1.6 1.65 V 2
(package C6)
Loadline
slope within
the VR
R_DC_LL -1.5 mΩ 3, 5, 6, 8
regulation
loop
capability
Loadline
slope in
response to
R_AC_LL -2.4 mΩ —
dynamic load
increase
events
Loadline
slope in
response to
R_AC_LL_OS -3.0 mΩ —
dynamic load
release
events
Overshoot
T_OVS 500 uS —
time
V_OVS Overshoot 50 mV —
VCC
VCC TOB Tolerance ± 20 (PS0, PS1, PS2, PS3) mV 3, 5, 6, 7, 8
Band
Ripple ± 10 (PS0)
± 15 (PS1)
VCC Ripple mV 3, 5, 6, 7, 8
+50/-15 (PS2)
+60/-15 (PS3)
Default VCC
voltage for
VCC,BOOT — 1.70 — V —
initial power
up
continued...

96 Order No.: 332376-001v1
Symbol Parameter Min Typ Max Unit Note1
ICC ICC — — 95 A 4, 8
PMAX — — 153 W 9
Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or
empirical data.
2. Each processor is programmed with a maximum valid voltage identification value (VID) that is
set at manufacturing and cannot be altered. Individual maximum VID values are calibrated
during manufacturing such that two processors at the same frequency may have different
settings within the VID range. This differs from the VID employed by the processor during a
power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or
Low-Power States).
3. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands
at the socket with a 20-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-
MΩ minimum impedance. The maximum length of ground wire on the probe should be less than
5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
4. ICC_MAX specification is based on the VCC loadline at worst case (highest) tolerance and ripple.
5. The VCC specifications represent static and transient limits.
6. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE
lands. Voltage regulation feedback for voltage regulator circuits must also be taken from
processor VCC_SENSE and VSS_SENSE lands.
7. PSx refers to the voltage regulator power state as set by the SVID protocol.
8. PCG is Platform Compatibility Guide (previously known as FMB). These guidelines are for
estimation purposes only.
9. PMAX is the maximum power the processor will dissipate as measured at VCC_SENSE and
VSS_SENSE lands. The processor may draw this power for up to 10 ms before it regulates to
PL2.
Table 44. Memory Controller (VDDQ) Supply DC Voltage and Current Specifications
Symbol Parameter Min Typ Max Unit Note
Processor I/O supply

VDDQ (DC+AC)
voltage for DDR3/DDR3L Typ-5% 1.5 Typ+5% V 2, 3, 5
DDR3/DDR3L
(DC + AC specification)
Processor I/O supply

VDDQ (DC+AC)
voltage for DDR3L (DC + Typ-5% 1.35 Typ+5% V 2, 3
DDR3/DDR3L
AC specification)
IccMAX_VDDQ (DDR3/ Max Current for VDDQ Rail

— — 2.5 A 1
DDR3L)
Average Current for VDDQ

ICCAVG_VDDQ (Standby) — 12 20 mA 4
Rail during Standby
Notes: 1. The current supplied to the SO-DIMM modules is not included in this specification.
2. Includes AC and DC error, where the AC noise is bandwidth limited to under 20 MHz.
3. No requirement on the breakdown of AC versus DC noise.
4. Measured at 50 °C
5. This specification applies to desktop processors.
Table 45. VCCIO_OUT, VCOMP_OUT, and VCCIO_TERM

Symbol Parameter Typ Max Units Notes
Termination
VCCIO_OUT 1.0 — V
Voltage
Maximum
ICCIO_OUT — 300 mA
External Load
continued...

Order No.: 332376-001v1 97
Symbol Parameter Typ Max Units Notes
Termination
VCOMP_OUT 1.0 — V 1
Voltage
Termination
VCCIO_TERM 1.0 — V 2
Voltage
Notes: 1. VCOMP_OUT may only be used to connect to PEG_RCOMP and DP_RCOMP.

2. Internal processor power for signal termination.
Table 46. DDR3 / DDR3L Signal Group DC Specifications

Symbol Parameter Min Typ Max Units Notes1
VIL Input Low Voltage — VDDQ/2 0.43*VDDQ V 2, 4, 11
VIH Input High Voltage 0.57*VDDQ VDDQ/2 — V 3, 11
Input Low Voltage

VIL — — 0.15*VDDQ V —
(SM_DRAMPWROK)
Input High Voltage

VIH 0.45*VDDQ — 1.0 V 10, 12
(SM_DRAMPWROK)
DDR3/DDR3L Data
RON_UP(DQ) Buffer pull-up 20 26 32 Ω 5, 11
Resistance
DDR3/DDR3L Data
RON_DN(DQ) Buffer pull-down 20 26 32 Ω 5, 11
Resistance
DDR3/DDR3L On-die
termination equivalent
RODT(DQ) 38 50 62 Ω 11
resistance for data
signals
DDR3/DDR3L On-die
termination DC working
VODT(DC) 0.45*VDDQ 0.5*VDDQ 0.55*VDDQ V 11
point (driver set to
receive mode)
DDR3/DDR3L Clock
5, 11,
RON_UP(CK) Buffer pull-up 20 26 32 Ω
13
Resistance
DDR3/DDR3L Clock
5, 11,
RON_DN(CK) Buffer pull-down 20 26 32 Ω
13
Resistance
DDR3/DDR3L Command
5, 11,
RON_UP(CMD) Buffer pull-up 15 20 25 Ω
13
Resistance
DDR3/DDR3L Command
5, 11,
RON_DN(CMD) Buffer pull-down 15 20 25 Ω
13
Resistance
DDR3/DDR3L Control
5, 11,
RON_UP(CTL) Buffer pull-up 19 25 31 Ω
13
Resistance
DDR3/DDR3L Control
5, 11,
RON_DN(CTL) Buffer pull-down 19 25 31 Ω
13
Resistance
DDR3/DDR3L Reset
RON_UP(RST) Buffer pull-up 40 80 130 Ω —
Resistance
continued...

98 Order No.: 332376-001v1
DDR3/DDR3L Reset
RON_DN(RST) Buffer pull-up 40 80 130 Ω —
Resistance
Input Leakage Current

(DQ, CK)
ILI 0V — — 0.7 mA —
0.2*VDDQ
0.8*VDDQ
Input Leakage Current

(CMD, CTL)
ILI 0V — — 1.0 mA —
0.2*VDDQ
0.8*VDDQ
Command COMP
SM_RCOMP0 99 100 101 Ω 8
Resistance
SM_RCOMP1 Data COMP Resistance 74.25 75 75.75 Ω 8
SM_RCOMP2 ODT COMP Resistance 99 100 101 Ω 8
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a
logical low value.
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a
logical high value.
4. VIH and VOH may experience excursions above VDDQ. However, input signal drivers must comply
with the signal quality specifications.
5. This is the pull up/down driver resistance.
6. RTERM is the termination on the DIMM and in not controlled by the processor.
7. The minimum and maximum values for these signals are programmable by BIOS to one of the
two sets.
8. SM_RCOMPx resistance must be provided on the system board with 1% resistors. SM_RCOMPx
resistors are to VSS.
9. SM_DRAMPWROK rise and fall time must be < 50 ns measured between VDDQ *0.15 and VDDQ
*0.47.
10.SM_VREF is defined as VDDQ/2.
11.Maximum-minimum range is correct; however, center point is subject to change during MRC
boot training.
12.Processor may be damaged if VIH exceeds the maximum voltage for extended periods.
13.The MRC during boot training might optimize RON outside the range specified.
Table 47. Digital Display Interface Group DC Specifications

Symbol Parameter Min Typ Max Units
VIL HPD Input Low Voltage — — 0.8 V
VIH HPD Input High Voltage 2.25 — 3.6 V
Aux peak-to-peak voltage at transmitting

Vaux(Tx) 0.39 — 1.38 V
device
Aux peak-to-peak voltage at receiving

Vaux(Rx) 0.32 — 1.36 V
device

Order No.: 332376-001v1 99
Table 48. embedded DisplayPort* (eDP*) Group DC Specifications

Symbol Parameter Min Typ Max Units
VIL HPD Input Low Voltage 0.02 — 0.21 V
VIH HPD Input High Voltage 0.84 — 1.05 V
VOL eDP_DISP_UTIL Output Low Voltage 0.1*VCC — — V
VOH eDP_DISP_UTIL Output High Voltage 0.9*VCC — — V
RUP eDP_DISP_UTIL Internal pull-up 100 — — Ω
RDOWN eDP_DISP_UTIL Internal pull-down 100 — — Ω
Aux peak-to-peak voltage at

Vaux(Tx) 0.39 — 1.38 V
transmitting device
Aux peak-to-peak voltage at receiving

Vaux(Rx) 0.32 — 1.36 V
device
eDP_RCOMP
COMP Resistance 24.75 25 25.25 Ω
DP_RCOMP
Note: 1. COMP resistance is to VCOMP_OUT.
Table 49. CMOS Signal Group DC Specifications

Symbol Parameter Min Max Units Notes1
VIL Input Low Voltage — VCCIO_OUT* 0.3 V 2
VIH Input High Voltage VCCIO_OUT* 0.7 — V 2, 4
VOL Output Low Voltage — VCCIO_OUT * 0.1 V 2
VOH Output High Voltage VCCIO_OUT * 0.9 — V 2, 4
RON Buffer on Resistance 23 73 Ω —
Input Leakage
ILI — ±150 μA 3
Current
2. The VCCIO_OUT referred to in these specifications refers to instantaneous VCCIO_OUT.
3. For VIN between “0” V and VCCIO_OUT. Measured when the driver is tri-stated.
4. VIH and VOH may experience excursions above VCCIO_OUT. However, input signal drivers must
comply with the signal quality specifications.
Table 50. GTL Signal Group and Open Drain Signal Group DC Specifications
Input Low Voltage (TAP, except

VIL — VCCIO_TERM * 0.6 V 2
TCK)
Input High Voltage (TAP, except

VIH VCCIO_TERM * 0.72 — V 2, 4
TCK)
VIL Input Low Voltage (TCK) — VCCIO_TERM * 0.4 V 2
VIH Input High Voltage (TCK) VCCIO_TERM * 0.8 — V 2, 4
VHYSTERESIS Hysteresis Voltage VCCIO_TERM * 0.2 — V —
RON Buffer on Resistance (TDO) 12 28 Ω —
VIL Input Low Voltage (other GTL) — VCCIO_TERM * 0.6 V 2

continued...

100 Order No.: 332376-001v1
VIH Input High Voltage (other GTL) VCCIO_TERM * 0.72 — V 2, 4
RON Buffer on Resistance (CFG/BPM) 16 24 Ω —
RON Buffer on Resistance (other GTL) 12 28 Ω —
ILI Input Leakage Current — ±150 μA 3
2. The VCCIO_OUT referred to in these specifications refers to instantaneous VCCIO_OUT.
3. For VIN between 0 V and VCCIO_TERM. Measured when the driver is tri-stated.
4. VIH and VOH may experience excursions above VCCIO_TERM. However, input signal drivers must
comply with the signal quality specifications.
Table 51. PCI Express* DC Specifications

DC Differential Tx Impedance (Gen 1

ZTX-DIFF-DC 80 — 120 Ω 1, 6
Only)
DC Differential Tx Impedance (Gen 2 and

ZTX-DIFF-DC — — 120 Ω 1, 6
Gen 3)
ZRX-DC DC Common Mode Rx Impedance 40 — 60 Ω 1, 4, 5
DC Differential Rx Impedance (Gen1

ZRX-DIFF-DC 80 — 120 Ω 1
Only)
PEG_RCOMP Comp Resistance 24.75 25 25.25 Ω 2, 3
Notes: 1. See the PCI Express Base Specification for more details.
2. PEG_RCOMP should be connected to VCOMP_OUT through a 25 Ω ±1% resistor.
3. Intel allows using 24.9 Ω ±1% resistors.
4. DC impedance limits are needed to ensure Receiver detect.
5. The Rx DC Common Mode Impedance must be present when the Receiver terminations are first
enabled to ensure that the Receiver Detect occurs properly. Compensation of this impedance can
start immediately and the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50 Ω
±20%) must be within the specified range by the time Detect is entered.
6. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.

Order No.: 332376-001v1 101
Processor—Package Specifications
8.0 Package Specifications

The processor is available in a LGA package (LGA1150 socket type ) and BGA package
(BGA1364).
8.1 LGA Package Specifications

The Flip-Chip Land Grid Array package interfaces with the motherboard using the
LGA1150 socket. The package consists of a processor mounted on a substrate land-
carrier. An integrated heat spreader (IHS) is attached to the package substrate and
core and serves as the mating surface for processor thermal solutions, such as a
heatsink. The following figure shows a sketch of the processor package components
and how they are assembled together.
The package components shown in the following figure include the following:
1. Integrated Heat Spreader (IHS)
2. Thermal Interface Material (TIM)
3. Processor core (die)
4. Package substrate
5. Capacitors
Figure 20. Processor Package Assembly Sketch
8.1.1 Package Mechanical Drawing
®
The Package Mechanical Drawings are available on CDI in the 4th Generation Intel
Core™ Processors - Package Mechanical Drawings document.
8.1.2 Processor Component Keep-Out Zone

The processor may contain components on the substrate that define component keep-
out zone requirements. A thermal and mechanical solution design must not intrude
into the required keep-out zones. Decoupling capacitors are typically mounted to the

102 Order No.: 332376-001v1
Package Specifications—Processor
land-side of the package substrate. Refer to the LGA1150 Socket Application Guide for
keep-out zones. The location and quantity of package capacitors may change due to
manufacturing efficiencies but will remain within the component keep-in. This keep-in
zone includes solder paste and is a post reflow maximum height for the components.
8.1.3 Package Loading Specifications

The following table provides dynamic and static load specifications for the processor
package. These mechanical maximum load limits should not be exceeded during
heatsink assembly, shipping conditions, or standard use condition. Also, any
mechanical system or component testing should not exceed the maximum limits. The
processor package substrate should not be used as a mechanical reference or load-
bearing surface for thermal and mechanical solution.
Table 52. Processor Loading Specifications

Parameter Minimum Maximum Notes
Static Compressive Load — 600 N [135 lbf] 1, 2, 3
Dynamic Compressive — 712 N [160 lbf] 1, 3, 4

Load
Notes: 1. These specifications apply to uniform compressive loading in a direction normal to the processor,
IHS.
2. This is the maximum static force that can be applied by the heatsink and retention solution to
maintain the heatsink and processor interface.
3. These specifications are based on limited testing for design characterization. Loading limits are
for the package only and do not include the limits of the processor socket.
4. Dynamic loading is defined as an 50g shock load, 2X Dynamic Acceleration Factor with a 500g
maximum thermal solution.
8.1.4 Package Handling Guidelines

The following table includes a list of guidelines on package handling in terms of
recommended maximum loading on the processor IHS relative to a fixed substrate.
These package handling loads may be experienced during heatsink removal.
Table 53. Package Handling Guidelines

Parameter Maximum Recommended Notes
Shear 311 N [70 lbf] 1, 4
Tensile 111 N [25 lbf] 2, 4
Torque 3.95 N-m [35 lbf-in] 3, 4
Notes: 1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
2. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS
surface.
3. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the
IHS top surface.
4. These guidelines are based on limited testing for design characterization.
8.1.5 Package Insertion Specifications

The processor can be inserted into and removed from an LGA1150 socket 15 times.
The socket should meet the LGA1150 socket requirements detailed in the LGA1150
Socket Application Guide.

Order No.: 332376-001v1 103
8.1.6 Processor Mass Specification

The typical mass of the processor is 27.0 g (0.95 oz). This mass [weight] includes all
the components that are included in the package.
8.1.7 Processor Materials

The following table lists some of the package components and associated materials.
Table 54. Processor Materials

Component Material
Integrated Heat Spreader (IHS) Nickel Plated Copper
Substrate Fiber Reinforced Resin
Substrate Lands Gold Plated Copper
8.1.8 Processor Markings

The following figure shows the top-side markings on the processor. This diagram aids
in the identification of the processor.
Figure 21. Processor Top-Side Markings
8.1.9 Processor Land Coordinates

The following figures show the bottom view of the processor package.

104 Order No.: 332376-001v1
Figure 22. Processor Package Land Coordinates

Order No.: 332376-001v1 105
Figure 23. 2014 Processor Package Land/Pin Side Components
8.1.10 Processor Storage Specifications

The following table includes a list of the specifications for device storage in terms of
maximum and minimum temperatures and relative humidity. These conditions should
not be exceeded in storage or transportation.
Table 55. Processor Storage Specifications

Parameter Description Minimum Maximum Notes
The non-operating device storage

temperature. Damage (latent or
Tabsolute storage -55 °C 125 °C 1, 2, 3
otherwise) may occur when subjected to
for any length of time.
The ambient storage temperature limit

Tsustained storage (in shipping media) for a sustained -5 °C 40 °C 4, 5
period of time.
continued...

106 Order No.: 332376-001v1
Parameter Description Minimum Maximum Notes
The maximum device storage relative

RHsustained storage 60% @ 24 °C 5, 6
humidity for a sustained period of time.
A prolonged or extended period of time;

TIMEsustained storage typically associated with customer shelf 0 Months 6 Months 6
life.
Notes: 1. Refers to a component device that is not assembled in a board or socket that is not to be
electrically connected to a voltage reference or I/O signals.
2. Specified temperatures are based on data collected. Exceptions for surface mount reflow are
specified in by applicable JEDEC standard. Non-adherence may affect processor reliability.
3. TABSOLUTE storage applies to the unassembled component only and does not apply to the shipping
media, moisture barrier bags, or desiccant.
4. Intel branded board products are certified to meet the following temperature and humidity limits
that are given as an example only (Non-Operating Temperature Limit: -40 °C to 70 °C,
Humidity: 50% to 90%, non-condensing with a maximum wet bulb of 28 °C). Post board attach
storage temperature limits are not specified for non-Intel branded boards.
5. The JEDEC, J-JSTD-020 moisture level rating and associated handling practices apply to all
moisture sensitive devices removed from the moisture barrier bag.
6. Nominal temperature and humidity conditions and durations are given and tested within the
constraints imposed by Tsustained storage and customer shelf life in applicable Intel box and bags.
8.2 BGA Package Specifications
8.2.1 Package Mechanical Specifications

The processor is a Flip Chip technology package available in Ball Grid Array (BGA).
The following table provides an overview of the mechanical attributes of the package.
Table 56. Package Mechanical Attributes

Type Parameter H-Processor Line
Package Type Flip Chip Ball Grid Array
Interconnect Ball Grid Array (BGA)

Package Technology
Lead Free Yes
Halogenated Flame Retardant

Yes
Free
Solder Ball Composition SAC405
Ball/Pin Count 1364
Grid Array Pattern Balls Anywhere

Package Configuration
Land Side Capacitors Yes
Die Side Capacitors Yes
Die Configuration Multi-chip/2 dies
Nominal Package Size 37.5 x 32.0 mm

Package Dimensions
Min Ball/Pin pitch 0.7 mm

Order No.: 332376-001v1 107
8.2.2 Package Loading Specifications

Table 57. Package Loading Specifications
Maximum Static Normal Load Limit Notes
111 N (25 lbf) 1, 2, 3, 4, 5

BGA1364
67 N (15 lbf) 1, 2, 3, 4
Notes: 1. The thermal solution attach mechanism must not induce continuous stress to the package. It
may only apply a uniform load to the die to maintain a thermal interface.
2. This specification applies to the uniform compressive load in the direction perpendicular to the
die top surface. It is the nominal + tolerance maximum load.
3. This specification is based on limited testing for design characterization.
4. Assumes a motherboard thickness of 1.0 mm or greater.
5. Assumes the use of a backing plate.
8.2.3 Package Storage Specifications

Table 58. BGA Package Storage Conditions
Parameter Description Min Max Notes
The non-operating device storage

temperature. Damage (latent or otherwise)
TABSOLUTE STORAGE -25 °C 125 °C 1, 2, 3
may occur when subjected to for any length
of time.
The ambient storage temperature limit (in

TSUSTAINED STORAGE shipping media) for a sustained period of -5 °C 40 °C 4, 5
time.
RHSUSTAINED The maximum device storage relative

60% @ 24 °C 5, 6
STORAGE humidity for a sustained period of time.
TIMESUSTAINED A prolonged or extended period of time;

0 months 6 months 6
STORAGE typically associated with customer shelf life.
Notes: 1. Refers to a component device that is not assembled in a board or socket that is not to be
electrically connected to a voltage reference or I/O signals.
2. Specified temperatures are based on data collected. Exceptions for surface mount reflow are
specified in by applicable JEDEC standard . Non-adherence may affect processor reliability.
3. TABSOLUTE STORAGE applies to the unassembled component only and does not apply to the shipping
media, moisture barrier bags or desiccant.
4. Intel-branded board products are certified to meet the following temperature and humidity limits
that are given as an example only (Non-Operating Temperature Limit: -40 °C to 70 °C,
Humidity: 50% to 90%, non-condensing with a maximum wet bulb of 28°C). Post board attach
storage temperature limits are not specified for non-Intel branded boards.
5. The JEDEC, J-JSTD-020 moisture level rating and associated handling practices apply to all
moisture sensitive devices removed from the moisture barrier bag.
6. Nominal temperature and humidity conditions and durations are given and tested within the
constraints imposed by TSUSTAINED STORAGE and customer shelf life in applicable Intel box and
bags.

108 Order No.: 332376-001v1
Processor Ball and Signal Information—Processor
9.0 Processor Ball and Signal Information

This chapter provides processor ball information. The following table provides the ball
list by signal name.
Note: References to SA_ECC_CB[7:0] and SB_ECC_CB[7:0] are for processor SKUs that
support ECC. These signals are reserved on the 5th Generation Intel® Core™ processor
based on Desktop H-Processor Line.
Table 59. Processor LGA1150 Ball List by Signal Name

Signal Name LGA Ball # Signal Name LGA Ball # Signal Name LGA Ball #
BCLKN V4 CFG3 W38 DDID_TXDN1 B16
BCLKP V5 CFG4 V39 DDID_TXDN2 C17
BPM#0 G39 CFG5 U39 DDID_TXDN3 B18
BPM#1 J39 CFG6 U40 DDID_TXDP0 B15
BPM#2 G38 CFG7 V38 DDID_TXDP1 A16
BPM#3 H37 CFG8 T40 DDID_TXDP2 B17
BPM#4 H38 CFG9 Y35 DDID_TXDP3 A18
BPM#5 J38 DBR# G40 DISP_INT D18
BPM#6 K39 DDIB_TXBN0 F17 DMI_RXN0 T3
BPM#7 K37 DDIB_TXBN1 G18 DMI_RXN1 V1
CATERR# M36 DDIB_TXBN2 H19 DMI_RXN2 V2
CFG_RCOMP H40 DDIB_TXBN3 G20 DMI_RXN3 W3
CFG0 AA37 DDIB_TXBP0 E17 DMI_RXP0 U3
CFG1 Y38 DDIB_TXBP1 F18 DMI_RXP1 U1
CFG10 AA34 DDIB_TXBP2 G19 DMI_RXP2 W2
CFG11 V37 DDIB_TXBP3 F20 DMI_RXP3 Y3
CFG12 Y34 DDIC_TXCN0 E19 DMI_TXN0 AA5
CFG13 U38 DDIC_TXCN1 D20 DMI_TXN1 AB4
CFG14 W34 DDIC_TXCN2 E21 DMI_TXN2 AC4
CFG15 V35 DDIC_TXCN3 D22 DMI_TXN3 AC2
CFG16 Y37 DDIC_TXCP0 D19 DMI_TXP0 AA4
CFG17 Y36 DDIC_TXCP1 C20 DMI_TXP1 AB3
CFG18 W36 DDIC_TXCP2 D21 DMI_TXP2 AC5
CFG19 V36 DDIC_TXCP3 C22 DMI_TXP3 AC1
CFG2 AA36 DDID_TXDN0 C15 DP_RCOMP R4

continued... continued... continued...

Order No.: 332376-001v1 109
Processor—Processor Ball and Signal Information
DPLL_REF_CLKN W6 PEG_RXP14 K5 PEG_TXP4 C8
DPLL_REF_CLKP W5 PEG_RXP15 L4 PEG_TXP5 B7
EDP_DISP_UTIL E16 PEG_RXP2 E13 PEG_TXP6 A6
VCCST K9 PEG_RXP3 D12 PEG_TXP7 B5
VCCST_PWRGD Y7 PEG_RXP4 E11 PEG_TXP8 E1
FDI_CSYNC D16 PEG_RXP5 F10 PEG_TXP9 F2
FDI0_TX0N0 B14 PEG_RXP6 E9 PM_SYNC P36
FDI0_TX0N1 C13 PEG_RXP7 F8 PRDY# L39
FDI0_TX0P0 A14 PEG_RXP8 D3 PREQ# L37
FDI0_TX0P1 B13 PEG_RXP9 E4 PROCHOT# K38
IST_TRIGGER C39 PEG_TXN0 B12 PWR_DEBUG N40
IVR_ERROR R36 PEG_TXN1 C11 PWRGOOD AB35
PECI N37 PEG_TXN10 G2 RESET# M39
PEG_RCOMP P3 PEG_TXN11 H3 RSVD AB33
PEG_RXN0 F15 PEG_TXN12 J2 RSVD AB36
PEG_RXN1 E14 PEG_TXN13 K3 RSVD AB8
PEG_RXN10 F6 PEG_TXN14 M3 RSVD AC8
PEG_RXN11 G5 PEG_TXN15 L2 RSVD AK20
PEG_RXN12 H6 PEG_TXN2 D10 RSVD AL20
PEG_RXN13 J5 PEG_TXN3 C9 RSVD AT40
PEG_RXN14 K6 PEG_TXN4 D8 RSVD AU1
PEG_RXN15 L5 PEG_TXN5 C7 RSVD AU27
PEG_RXN2 F13 PEG_TXN6 B6 RSVD AU39
PEG_RXN3 E12 PEG_TXN7 C5 RSVD AV2
PEG_RXN4 F11 PEG_TXN8 E2 RSVD AV20
PEG_RXN5 G10 PEG_TXN9 F3 RSVD AV24
PEG_RXN6 F9 PEG_TXP0 A12 RSVD AV29
PEG_RXN7 G8 PEG_TXP1 B11 RSVD AW12
PEG_RXN8 D4 PEG_TXP10 G1 RSVD AW23
PEG_RXN9 E5 PEG_TXP11 H2 RSVD AW24
PEG_RXP0 E15 PEG_TXP12 J1 RSVD AW27
PEG_RXP1 D14 PEG_TXP13 K2 RSVD AY18
PEG_RXP10 F5 PEG_TXP14 M2 RSVD H12
PEG_RXP11 G4 PEG_TXP15 L1 RSVD H14
PEG_RXP12 H5 PEG_TXP2 C10 RSVD H15
PEG_RXP13 J4 PEG_TXP3 B9 RSVD J15


110 Order No.: 332376-001v1
RSVD J17 RSVD_TP P37 SA_DQ20 AM37
RSVD J40 SA_BS0 AV12 SA_DQ21 AM38
RSVD J9 SA_BS1 AY11 SA_DQ22 AP37
RSVD L10 SA_BS2 AT21 SA_DQ23 AP40
RSVD L12 SA_CAS# AU9 SA_DQ24 AV37
RSVD M10 SA_CK0 AY15 SA_DQ25 AW37
RSVD M11 SA_CK1 AW15 SA_DQ26 AU35
RSVD M38 SA_CK2 AV14 SA_DQ27 AV35
RSVD N35 SA_CK3 AW13 SA_DQ28 AT37
RSVD P33 SA_CKE0 AV22 SA_DQ29 AU37
RSVD R33 SA_CKE1 AT23 SA_DQ3 AF39
RSVD R34 SA_CKE2 AU22 SA_DQ30 AT35
RSVD T34 SA_CKE3 AU23 SA_DQ31 AW35
RSVD T35 SA_CKN0 AY16 SA_DQ32 AY6
RSVD T8 SA_CKN1 AV15 SA_DQ33 AU6
RSVD U8 SA_CKN2 AW14 SA_DQ34 AV4
RSVD W8 SA_CKN3 AY13 SA_DQ35 AU4
RSVD Y8 SA_CS#0 AU14 SA_DQ36 AW6
RSVD_TP A4 SA_CS#1 AV9 SA_DQ37 AV6
RSVD_TP AV1 SA_CS#2 AU10 SA_DQ38 AW4
RSVD_TP AW2 SA_CS#3 AW8 SA_DQ39 AY4
RSVD_TP B3 SA_DIMM_VREF AB39 SA_DQ4 AD37

DQ
RSVD_TP C2 SA_DQ40 AR1
SA_DQ0 AD38
RSVD_TP D1 SA_DQ41 AR4
SA_DQ1 AD39
RSVD_TP H16 SA_DQ42 AN3
SA_DQ10 AK38
RSVD_TP J10 SA_DQ43 AN4
SA_DQ11 AK39
RSVD_TP J12 SA_DQ44 AR2
SA_DQ12 AH37
RSVD_TP J13 SA_DQ45 AR3
SA_DQ13 AH38
SA_DQ14 AK37
SA_DQ15 AK40
RSVD_TP K11 SA_DQ48 AL1
SA_DQ16 AM40
RSVD_TP K12 SA_DQ49 AL4
SA_DQ17 AM39
RSVD_TP K13 SA_DQ5 AD40
SA_DQ18 AP38
RSVD_TP K8 SA_DQ50 AJ3
SA_DQ19 AP39
RSVD_TP N36 SA_DQ51 AJ4
SA_DQ2 AF38
RSVD_TP N38 SA_DQ52 AL2
continued...

Order No.: 332376-001v1 111
SA_DQ53 AL3 SA_ECC_CB3 AV31 SB_CKE1 AY29
SA_DQ54 AJ2 SA_ECC_CB4 AT33 SB_CKE2 AU28
SA_DQ55 AJ1 SA_ECC_CB5 AU33 SB_CKE3 AU29
SA_DQ56 AG1 SA_ECC_CB6 AT31 SB_CKN0 AM21
SA_DQ57 AG4 SA_ECC_CB7 AW31 SB_CKN1 AP21
SA_DQ58 AE3 SA_MA0 AU13 SB_CKN2 AN21
SA_DQ59 AE4 SA_MA1 AV16 SB_CKN3 AP20
SA_DQ6 AF37 SA_MA10 AW11 SB_CS#0 AP17
SA_DQ60 AG2 SA_MA11 AV19 SB_CS#1 AN15
SA_DQ61 AG3 SA_MA12 AU19 SB_CS#2 AN17
SA_DQ62 AE2 SA_MA13 AY10 SB_CS#3 AL15
SA_DQ63 AE1 SA_MA14 AT20 SB_DIMM_VREF AB40

DQ
SA_DQ7 AF40 SA_MA15 AU21
SB_DQ0 AE34
SA_DQ8 AH40 SA_MA2 AU16
SB_DQ1 AE35
SA_DQ9 AH39 SA_MA3 AW17
SB_DQ10 AK31
SA_DQSN0 AE38 SA_MA4 AU17
SB_DQ11 AL31
SA_DQSN1 AJ38 SA_MA5 AW18
SB_DQ12 AK34
SA_DQSN2 AN38 SA_MA6 AV17
SB_DQ13 AK35
SA_DQSN3 AU36 SA_MA7 AT18
SB_DQ14 AK32
SA_DQSN4 AW5 SA_MA8 AU18
SB_DQ15 AL32
SA_DQSN5 AP2 SA_MA9 AT19
SB_DQ16 AN34
SA_DQSN6 AK2 SA_ODT0 AW10
SB_DQ17 AP34
SA_DQSN7 AF2 SA_ODT1 AY8
SB_DQ18 AN31
SA_DQSN8 AU32 SA_ODT2 AW9
SB_DQ19 AP31
SA_DQSP0 AE39 SA_ODT3 AU8
SB_DQ2 AG35
SA_DQSP1 AJ39 SA_RAS# AU12
SB_DQ20 AN35
SA_DQSP2 AN39 SA_WE# AU11
SB_DQ21 AP35
SA_DQSP3 AV36 SB_BS0 AK17
SB_DQ22 AN32
SA_DQSP4 AV5 SB_BS1 AL18
SB_DQ23 AP32
SA_DQSP5 AP3 SB_BS2 AW28
SB_DQ24 AM29
SA_DQSP6 AK3 SB_CAS# AP16
SB_DQ25 AM28
SA_DQSP7 AF3 SB_CK0 AM20
SB_DQ26 AR29
SA_DQSP8 AV32 SB_CK1 AP22
SB_DQ27 AR28
SA_ECC_CB0 AW33 SB_CK2 AN20
SB_DQ28 AL29
SA_ECC_CB1 AV33 SB_CK3 AP19
SB_DQ29 AL28
SA_ECC_CB2 AU31 SB_CKE0 AW29
continued...

112 Order No.: 332376-001v1
SB_DQ3 AH35 SB_DQ62 AF6 SB_MA13 AR15
SB_DQ30 AP29 SB_DQ63 AF7 SB_MA14 AV27
SB_DQ31 AP28 SB_DQ7 AH34 SB_MA15 AY28
SB_DQ32 AR12 SB_DQ8 AL34 SB_MA2 AM22
SB_DQ33 AP12 SB_DQ9 AL35 SB_MA3 AM23
SB_DQ34 AL13 SB_DQS0 AF35 SB_MA4 AP23
SB_DQ35 AL12 SB_DQS1 AL33 SB_MA5 AL23
SB_DQ36 AR13 SB_DQS2 AP33 SB_MA6 AY24
SB_DQ37 AP13 SB_DQS3 AN28 SB_MA7 AV25
SB_DQ38 AM13 SB_DQS4 AN12 SB_MA8 AU26
SB_DQ39 AM12 SB_DQS5 AP8 SB_MA9 AW25
SB_DQ4 AD34 SB_DQS6 AL8 SB_ODT0 AM17
SB_DQ40 AR9 SB_DQS7 AG7 SB_ODT1 AL16
SB_DQ41 AP9 SB_DQS8 AN25 SB_ODT2 AM16
SB_DQ42 AR6 SB_DQSN0 AF34 SB_ODT3 AK15
SB_DQ43 AP6 SB_DQSN1 AK33 SB_RAS# AM18
SB_DQ44 AR10 SB_DQSN2 AN33 SB_WE# AK16
SB_DQ45 AP10 SB_DQSN3 AN29 SKTOCC# D38
SB_DQ46 AR7 SB_DQSN4 AN13 SM_DRAMPWRO AK21

K
SB_DQ47 AP7 SB_DQSN5 AR8
SM_DRAMRST# AK22
SB_DQ48 AM9 SB_DQSN6 AM8
SM_RCOMP0 R1
SB_DQ49 AL9 SB_DQSN7 AG6
SM_RCOMP1 P1
SB_DQ5 AD35 SB_DQSN8 AN26
SM_RCOMP2 R2
SB_DQ50 AL6 SB_ECC_CB0 AM26
SM_VREF AB38
SB_DQ51 AL7 SB_ECC_CB1 AM25
SSC_DPLL_REF_ U5
SB_DQ52 AM10 SB_ECC_CB2 AP25 CLKN
SB_DQ53 AL10 SB_ECC_CB3 AP26 SSC_DPLL_REF_ U6

CLKP
SB_DQ54 AM6 SB_ECC_CB4 AL26
TCK D39
SB_DQ55 AM7 SB_ECC_CB5 AL25
TDI F38
SB_DQ56 AH6 SB_ECC_CB6 AR26
TDO F39
SB_DQ57 AH7 SB_ECC_CB7 AR25
TESTLO_N5 N5
SB_DQ58 AE6 SB_MA0 AL19
TESTLO_P6 P6
SB_DQ59 AE7 SB_MA1 AK23
THERMTRIP# F37
SB_DQ6 AG34 SB_MA10 AP18
TMS E39
SB_DQ60 AJ6 SB_MA11 AY25
TRST# E37
SB_DQ61 AJ7 SB_MA12 AV26
continued...

Order No.: 332376-001v1 113
VCC A24 VCC E29 VCC J22
VCC B25 VCC F23 VCC J29
VCC C24 VCC F35 VCC J35
VCC C25 VCC G22 VCC K19
VCC C34 VCC G31 VCC L15
VCC C35 VCC G32 VCC L16
VCC D25 VCC G33 VCC L17
VCC D31 VCC H23 VCC L20
VCC E24 VCC H29 VCC L23
VCC E28 VCC J21 VCC L27


114 Order No.: 332376-001v1
VCC L28 VDDQ AU20 VSS AC34
VCC L29 VDDQ AU24 VSS AC35
VCC L30 VDDQ AV10 VSS AC36
VCC M13 VDDQ AV8 VSS AC6
VCC M15 VDDQ AW16 VSS AC7
VCC M17 VDDQ AY12 VSS AD1
VCC M23 VIDALERT# B37 VSS AD33
VCC M25 VIDSCLK C38 VSS AD36
VCC M27 VIDSOUT C37 VSS AD4
VCC M29 VSS A11 VSS AD5
VCC P8 VSS A17 VSS AD8
VCC_SENSE E40 VSS A23 VSS AE33
VCCIO_OUT L40 VSS A5 VSS AE36
VCOMP_OUT P4 VSS A7 VSS AE37
VDDQ AJ12 VSS AA3 VSS AE40
VDDQ AJ17 VSS AA38 VSS AF1
VDDQ AJ25 VSS AB34 VSS AF5
VDDQ AJ28 VSS AB37 VSS AF8
VDDQ AJ29 VSS AB5 VSS AG33
VDDQ AJ9 VSS AB6 VSS AG36
VDDQ AT17 VSS AB7 VSS AG37
VDDQ AT22 VSS AC3 VSS AG38
VDDQ AU15 VSS AC33 VSS AG39


Order No.: 332376-001v1 115
VSS AG40 VSS AK14 VSS AM2
VSS AH1 VSS AK24 VSS AM3
VSS AJ11 VSS AK4 VSS AM4
VSS AJ14 VSS AK5 VSS AM5
VSS AJ16 VSS AK6 VSS AN10
VSS AJ23 VSS AL11 VSS AN18
VSS AK1 VSS AM1 VSS AN9
VSS AK10 VSS AM11 VSS AP1


116 Order No.: 332376-001v1
VSS AP24 VSS AT15 VSS AV7
VSS AP27 VSS AT16 VSS AW26
VSS AR11 VSS AT27 VSS AW36
VSS AR14 VSS AT28 VSS AW7
VSS AR16 VSS AT29 VSS AY17
VSS AR23 VSS AT39 VSS B10
VSS AR34 VSS AU2 VSS B34
VSS AR38 VSS AU34 VSS C12
VSS AT1 VSS AV21 VSS C19


Order No.: 332376-001v1 117
VSS C6 VSS F22 VSS H30
VSS D11 VSS F24 VSS H32
VSS D28 VSS F7 VSS J11
VSS D30 VSS G11 VSS J14
VSS E10 VSS G36 VSS K1
VSS E3 VSS H1 VSS K17
VSS F1 VSS H20 VSS K28


118 Order No.: 332376-001v1
VSS K40 VSS N3 VSS T7
VSS K7 VSS N33 VSS U2
VSS L11 VSS N34 VSS U33
VSS L38 VSS P2 VSS U7
VSS L6 VSS P34 VSS V3
VSS M1 VSS P40 VSS V6
VSS M16 VSS R3 VSS W1
VSS M28 VSS R5 VSS Y33
VSS M35 VSS T1 VSS_NCTF AU40
VSS M37 VSS T2 VSS_NCTF AV39
VSS M4 VSS T33 VSS_NCTF AW38
VSS M40 VSS T36 VSS_NCTF AY3
VSS M5 VSS T37 VSS_NCTF B38
VSS M6 VSS T38 VSS_NCTF B39
VSS M7 VSS T39 VSS_NCTF C40
VSS M9 VSS T4 VSS_NCTF D40
VSS N1 VSS T5 VSS_SENSE F40
VSS N2 VSS T6

Order No.: 332376-001v1 119
Table 60. BGA1364 Processor Ball List by Signal Name

Signal Name BGA Ball # Signal Name BGA Ball # Signal Name BGA Ball #
BCLKN AB6 DAISY_CHAIN_ A51 DAISY_CHAIN_ BF53

NCTF_A51 NCTF_BF53
BCLKP AA6
DAISY_CHAIN_ A52 DAISY_CHAIN_ C1
BPM#0 R51 NCTF_A52 NCTF_C1
BPM#1 R50 DAISY_CHAIN_ A53 DAISY_CHAIN_ C2

NCTF_A53 NCTF_C2
BPM#2 P49
DAISY_CHAIN_ B2 DAISY_CHAIN_ C3
BPM#3 N50 NCTF_B2 NCTF_C3
BPM#4 R49 DAISY_CHAIN_ B3 DAISY_CHAIN_ C54

NCTF_B3 NCTF_C54
BPM#5 P53
DAISY_CHAIN_ B52 DAISY_CHAIN_ D1
BPM#6 U51 NCTF_B52 NCTF_D1
BPM#7 P51 DAISY_CHAIN_ B53 DAISY_CHAIN_ D54
NCTF_B53 NCTF_D54
CATERR# G50
DAISY_CHAIN_ B54 DBR# F53
CFG_RCOMP R54
NCTF_B54
DDIB_TXN0 C25
CFG0 AG49
DAISY_CHAIN_ BC1
NCTF_BC1 DDIB_TXN1 A25
CFG1 AD49
DAISY_CHAIN_ BC54 DDIB_TXN2 C24
CFG10 Y53
NCTF_BC54
DDIB_TXN3 A24
CFG11 W53
DAISY_CHAIN_ BD1
NCTF_BD1 DDIB_TXP0 D25
CFG12 U53
DAISY_CHAIN_ BD54 DDIB_TXP1 B25
CFG13 V54
NCTF_BD54
DDIB_TXP2 D24
CFG14 R53
DAISY_CHAIN_ BE1
NCTF_BE1 DDIB_TXP3 B24
CFG15 R52
DAISY_CHAIN_ BE2 DDIC_TXN0 C21
CFG16 Y52
NCTF_BE2
DDIC_TXN1 A21
CFG17 Y51
DAISY_CHAIN_ BE3
DDIC_TXN2 C20
CFG18 V53 NCTF_BE3
DDIC_TXN3 A20
CFG19 V52 DAISY_CHAIN_ BE52
NCTF_BE52
DDIC_TXP0 D21
CFG2 AC49
DAISY_CHAIN_ BE53
DDIC_TXP1 B21
CFG3 AE49 NCTF_BE53
DDIC_TXP2 D20
CFG4 Y50 DAISY_CHAIN_ BE54
NCTF_BE54 DDIC_TXP3 B20
CFG5 AB49
DAISY_CHAIN_ BF2 DDID_TXN0 C17
CFG6 V51 NCTF_BF2
DDID_TXN1 A17
CFG7 W51 DAISY_CHAIN_ BF3
NCTF_BF3 DDID_TXN2 C16
CFG8 Y49
DAISY_CHAIN_ BF4 DDID_TXN3 A16
CFG9 Y54 NCTF_BF4
DDID_TXP0 D17
DAISY_CHAIN_ A3 DAISY_CHAIN_ BF51
NCTF_A3 NCTF_BF51 DDID_TXP1 B17
DAISY_CHAIN_ A4 DAISY_CHAIN_ BF52 DDID_TXP2 D16
NCTF_A4 NCTF_BF52
continued...

120 Order No.: 332376-001v1
DDID_TXP3 B16 FDI_TXP1 B14 PEG_RXP9 L3
DISP_INT F12 IST_TRIGGER W49 PEG_TXN0 B6
DMI_RXN0 AB2 IVR_ERROR AM49 PEG_TXN1 C5
DMI_RXN1 AB3 PECI G51 PEG_TXN10 T6
DMI_RXN2 AC3 PEG_RCOMP AH6 PEG_TXN11 R6
DMI_RXN3 AC1 PEG_RXN0 E10 PEG_TXN12 R2
DMI_RXP0 AB1 PEG_RXN1 C10 PEG_TXN13 R4
DMI_RXP1 AB4 PEG_RXN10 M2 PEG_TXN14 T4
DMI_RXP2 AC4 PEG_RXN11 V5 PEG_TXN15 T1
DMI_RXP3 AC2 PEG_RXN12 V4 PEG_TXN2 E6
DMI_TXN0 AF2 PEG_RXN13 V1 PEG_TXN3 D4
DMI_TXN1 AF4 PEG_RXN14 Y3 PEG_TXN4 G4
DMI_TXN2 AG4 PEG_RXN15 Y2 PEG_TXN5 E3
DMI_TXN3 AG2 PEG_RXN2 B10 PEG_TXN6 J5
DMI_TXP0 AF1 PEG_RXN3 E9 PEG_TXN7 G3
DMI_TXP1 AF3 PEG_RXN4 D9 PEG_TXN8 J3
DMI_TXP2 AG3 PEG_RXN5 B9 PEG_TXN9 J2
DMI_TXP3 AG1 PEG_RXN6 L5 PEG_TXP0 C6
DPLL_REF_CLKN AC6 PEG_RXN7 L2 PEG_TXP1 B5
DPLL_REF_CLKP AE6 PEG_RXN8 M4 PEG_TXP10 T5
EDP_AUXN F15 PEG_RXN9 L4 PEG_TXP11 R5
EDP_AUXP F14 PEG_RXP0 F10 PEG_TXP12 R1
EDP_DISP_UTIL E12 PEG_RXP1 D10 PEG_TXP13 R3
eDP_HPD E14 PEG_RXP10 M1 PEG_TXP14 T3
EDP_RCOMP AG6 PEG_RXP11 Y5 PEG_TXP15 T2
eDP_TXN0 C14 PEG_RXP12 V3 PEG_TXP2 D6
eDP_TXN1 A12 PEG_RXP13 V2 PEG_TXP3 E4
eDP_TXP0 D14 PEG_RXP14 Y4 PEG_TXP4 G5
eDP_TXP1 B12 PEG_RXP15 Y1 PEG_TXP5 E2
VCCST_PWRGD D3 PEG_RXP2 A10 PEG_TXP6 J6
VCCST D5 PEG_RXP3 F9 PEG_TXP7 G2
FC_F17 F17 PEG_RXP4 C9 PEG_TXP8 J4
FDI_CSYNC F11 PEG_RXP5 A9 PEG_TXP9 J1
FDI_TXN0 C12 PEG_RXP6 M5 PLTRSTIN# L54
FDI_TXN1 A14 PEG_RXP7 L1 PM_SYNC D52
FDI_TXP0 D12 PEG_RXP8 M3 PRDY# N53


Order No.: 332376-001v1 121
PREQ# N52 RSVD BC4 RSVD_TP F6
PROC_DETECT# C51 RSVD BC53 RSVD_TP G10
PROCHOT# E50 RSVD BD31 RSVD_TP G12
PWR_DEBUG# F19 RSVD BD37 RSVD_TP G21
PWRGOOD F50 RSVD BD38 RSVD_TP G24
RSVD AD45 RSVD BD39 RSVD_TP G6
RSVD AE9 RSVD BD4 RSVD_TP L51
RSVD AF9 RSVD BE37 RSVD_TP L52
RSVD AG45 RSVD BE38 RSVD_TP L53
RSVD AH49 RSVD BE39 RSVD_TP U49
RSVD AH9 RSVD BF37 RSVD_TP V49
RSVD AL6 RSVD BF39 SA_BS0 BC20
RSVD AM48 RSVD E5 SA_BS1 BD21
RSVD AN18 RSVD F16 SA_BS2 BD32
RSVD AN22 RSVD F8 SA_CAS# BE21
RSVD AN31 RSVD G14 SA_CKE0 BE34
RSVD AN33 RSVD G17 SA_CKE1 BF34
RSVD AN35 RSVD G53 SA_CKE2 BC34
RSVD AN37 RSVD H50 SA_CKE3 BD34
RSVD AR49 RSVD J12 SA_CKN0 BE25
RSVD AU26 RSVD J17 SA_CKN1 BD25
RSVD AU27 RSVD J21 SA_CKN2 BE23
RSVD AU39 RSVD J26 SA_CKN3 BD23
RSVD AU40 RSVD J31 SA_CKP0 BF25
RSVD AV39 RSVD L49 SA_CKP1 BC25
RSVD AV40 RSVD L50 SA_CKP2 BF23
RSVD AW39 RSVD N51 SA_CKP3 BC23
RSVD AW40 RSVD W9 SA_CS#0 BE16
RSVD AY36 RSVD_TP A5 SA_CS#1 BC17
RSVD AY39 RSVD_TP A6 SA_CS#2 BE17
RSVD AY40 RSVD_TP BD3 SA_CS#3 BD16
RSVD B50 RSVD_TP BE4 SA_DIMM_VREF AR6

DQ
RSVD BA39 RSVD_TP E1
SA_DQ0 AH54
RSVD BA40 RSVD_TP F1
SA_DQ1 AH52
RSVD BC37 RSVD_TP F24
SA_DQ10 AR51
RSVD BC39 RSVD_TP F25
continued...

122 Order No.: 332376-001v1
SA_DQ11 AR53 SA_DQ44 BD9 SA_DQSN3 AY46
SA_DQ12 AN53 SA_DQ45 BF9 SA_DQSN4 BD12
SA_DQ13 AN51 SA_DQ46 BE5 SA_DQSN5 BE7
SA_DQ14 AR52 SA_DQ47 BD6 SA_DQSN6 BA3
SA_DQ15 AR54 SA_DQ48 BB4 SA_DQSN7 AT2
SA_DQ16 AV52 SA_DQ49 BC2 SA_MA0 BD28
SA_DQ17 AV53 SA_DQ5 AH51 SA_MA1 BD27
SA_DQ18 AY52 SA_DQ50 AW3 SA_MA10 BD20
SA_DQ19 AY51 SA_DQ51 AW2 SA_MA11 BF31
SA_DQ2 AK51 SA_DQ52 BB3 SA_MA12 BC31
SA_DQ20 AV51 SA_DQ53 BB2 SA_MA13 BE20
SA_DQ21 AV54 SA_DQ54 AW4 SA_MA14 BE32
SA_DQ22 AY54 SA_DQ55 AW1 SA_MA15 BE31
SA_DQ23 AY53 SA_DQ56 AU3 SA_MA2 BF28
SA_DQ24 AY47 SA_DQ57 AU1 SA_MA3 BE28
SA_DQ25 AY49 SA_DQ58 AR1 SA_MA4 BF32
SA_DQ26 BA47 SA_DQ59 AR4 SA_MA5 BC27
SA_DQ27 BA45 SA_DQ6 AK52 SA_MA6 BF27
SA_DQ28 AY45 SA_DQ60 AU2 SA_MA7 BC28
SA_DQ29 AY43 SA_DQ61 AU4 SA_MA8 BE27
SA_DQ3 AK54 SA_DQ62 AR2 SA_MA9 BC32
SA_DQ30 BA49 SA_DQ63 AR3 SA_ODT0 BC16
SA_DQ31 BA43 SA_DQ7 AK53 SA_ODT1 BF16
SA_DQ32 BF14 SA_DQ8 AN54 SA_ODT2 BF17
SA_DQ33 BC14 SA_DQ9 AN52 SA_ODT3 BD17
SA_DQ34 BC11 SA_DQS0 AJ53 SA_RAS# BF20
SA_DQ35 BF11 SA_DQS1 AP52 SA_WE# BF21
SA_DQ36 BE14 SA_DQS2 AW53 SB_BS0 AY23
SA_DQ37 BD14 SA_DQS3 BA46 SB_BS1 BA23
SA_DQ38 BD11 SA_DQS4 BE12 SB_BS2 BA36
SA_DQ39 BE11 SA_DQS5 BD7 SB_CAS# AV20
SA_DQ4 AH53 SA_DQS6 BA2 SB_CKE0 AU36
SA_DQ40 BC9 SA_DQS7 AT3 SB_CKE1 AU35
SA_DQ41 BE9 SA_DQSN0 AJ52 SB_CKE2 AV35
SA_DQ42 BE6 SA_DQSN1 AP53 SB_CKE3 AV36
SA_DQ43 BC6 SA_DQSN2 AW52 SB_CKN0 AW27


Order No.: 332376-001v1 123
SB_CKN1 AW26 SB_DQ3 AE54 SB_DQ62 AK2
SB_CKN2 BA26 SB_DQ30 BD42 SB_DQ63 AK3
SB_CKN3 BA27 SB_DQ31 BE42 SB_DQ7 AE53
SB_CKP0 AV27 SB_DQ32 BA16 SB_DQ8 AU47
SB_CKP1 AV26 SB_DQ33 AU16 SB_DQ9 AU49
SB_CKP2 AY26 SB_DQ34 BA15 SB_DQS0 AD53
SB_CKP3 AY27 SB_DQ35 AV15 SB_DQS1 AV46
SB_CS#0 BA20 SB_DQ36 AY16 SB_DQS2 BE48
SB_CS#1 AY19 SB_DQ37 AV16 SB_DQS3 BE43
SB_CS#2 AU19 SB_DQ38 AY15 SB_DQS4 AW15
SB_CS#3 AW20 SB_DQ39 AU15 SB_DQS5 AW12
SB_DIMM_VREF AN6 SB_DQ4 AC53 SB_DQS6 AW6

DQ
SB_DQ40 AU12 SB_DQS7 AL3
SB_DQ0 AC54
SB_DQ41 AY12 SB_DQSN0 AD52
SB_DQ1 AC52
SB_DQ42 BA10 SB_DQSN1 AU46
SB_DQ10 AV43
SB_DQ43 AU10 SB_DQSN2 BD48
SB_DQ11 AV45
SB_DQ44 AV12 SB_DQSN3 BD43
SB_DQ12 AU43
SB_DQ45 BA12 SB_DQSN4 AW16
SB_DQ13 AU45
SB_DQ46 AY10 SB_DQSN5 AW10
SB_DQ14 AV47
SB_DQ47 AV10 SB_DQSN6 AW8
SB_DQ15 AV49
SB_DQ48 AU8 SB_DQSN7 AL2
SB_DQ16 BC49
SB_DQ49 BA8 SB_MA0 BA30
SB_DQ17 BE49
SB_DQ5 AC51 SB_MA1 AW30
SB_DQ18 BD47
SB_DQ50 AV6 SB_MA10 AU23
SB_DQ19 BC47
SB_DQ51 BA6 SB_MA11 AY35
SB_DQ2 AE51
SB_DQ52 AV8 SB_MA12 AW35
SB_DQ20 BD49
SB_DQ53 AY8 SB_MA13 AU20
SB_DQ21 BD50
SB_DQ54 AU6 SB_MA14 AW36
SB_DQ22 BE47
SB_DQ55 AY6 SB_MA15 BA35
SB_DQ23 BF47
SB_DQ56 AM2 SB_MA2 AY30
SB_DQ24 BE44
SB_DQ57 AM3 SB_MA3 AV30
SB_DQ25 BD44
SB_DQ58 AK1 SB_MA4 AW32
SB_DQ26 BC42
SB_DQ59 AK4 SB_MA5 AY32
SB_DQ27 BF42
SB_DQ6 AE52 SB_MA6 AT30
SB_DQ28 BF44
SB_DQ60 AM1 SB_MA7 AV32
SB_DQ29 BC44
SB_DQ61 AM4 SB_MA8 BA32
continued...

124 Order No.: 332376-001v1
SB_MA9 AU32 VCC A46 VCC AM9
SB_ODT0 AY20 VCC A48 VCC AN10
SB_ODT1 BA19 VCC AA46 VCC AN12
SB_ODT2 AV19 VCC AA47 VCC AN13
SB_ODT3 AW19 VCC AA8 VCC AN14
SB_RAS# AV23 VCC AA9 VCC AN15
SB_WE# AW23 VCC AB45 VCC AN16
SM_DRAMPWRO AP48 VCC AB46 VCC AN17

K
VCC AB8 VCC AN19
SM_DRAMRST# BE51
VCC AC46 VCC AN20
SM_RCOMP0 BB51
VCC AC47 VCC AN21
SM_RCOMP1 BB53
VCC AC8 VCC AN23
SM_RCOMP2 BB52
VCC AC9 VCC AN24
SM_VREF AM6
VCC AD46 VCC AN25
SSC_DPLL_REF_ V6
CLKN VCC AD8 VCC AN26
SSC_DPLL_REF_ Y6 VCC AE46 VCC AN27

CLKP
VCC AE47 VCC AN29
TCK N54
VCC AE8 VCC AN30
TDI N49
VCC AF8 VCC AN32
TDO M49
VCC AG46 VCC AN34
TESTLO_F20 F20
VCC AG8 VCC AN36
TESTLO_F21 F21
VCC AH46 VCC AN38
THERMTRIP# D53
VCC AH47 VCC AN39
TMS M51
VCC AH8 VCC AN40
TRST# M53
VCC AJ45 VCC AN41
VCC A27
VCC AJ46 VCC AN42
VCC A28
VCC AK46 VCC AN43
VCC A31
VCC AK47 VCC AN44
VCC A32
VCC AK8 VCC AN45
VCC A34
VCC AL45 VCC AN46
VCC A36
VCC AL46 VCC AN8
VCC A38
VCC AL8 VCC AN9
VCC A39
VCC AL9 VCC AP10
VCC A42
VCC AM46 VCC AP12
VCC A43
VCC AM47 VCC AP13
VCC A45
VCC AM8 VCC AP14
continued...

Order No.: 332376-001v1 125
VCC AP15 VCC AR41 VCC D38
VCC AP19 VCC B27 VCC D45
VCC AP22 VCC B32 VCC E27
VCC AP33 VCC C27 VCC E45
VCC AP36 VCC C32 VCC F22
VCC AP47 VCC D27 VCC F43
VCC AR35 VCC D32 VCC F48
VCC AR37 VCC D34 VCC G27
VCC AR39 VCC D36 VCC G29


126 Order No.: 332376-001v1
VCC G31 VCC H40 VCC L38
VCC G45 VCC J10 VCC L6
VCC G46 VCC J14 VCC L8
VCC G48 VCC J19 VCC M37
VCC H11 VCC J24 VCC M38
VCC H24 VCC J46 VCC N37
VCC H29 VCC K38 VCC N42
VCC H37 VCC K8 VCC P45
VCC H38 VCC K9 VCC P46
VCC H39 VCC L37 VCC P8


Order No.: 332376-001v1 127
VCC R46 VDDQ AY18 VSS AA5
VCC R47 VDDQ BB21 VSS AA7
VCC R8 VDDQ BB22 VSS AB48
VCC R9 VDDQ BB26 VSS AB5
VCC T45 VDDQ BB27 VSS AB50
VCC T46 VDDQ BB30 VSS AB51
VCC U46 VDDQ BB31 VSS AB52
VCC U9 VDDQ BD22 VSS AB7
VCC V45 VDDQ BD26 VSS AB9
VCC V46 VDDQ BD30 VSS AC48
VCC V8 VDDQ BD33 VSS AC5
VCC W46 VDDQ BE18 VSS AC50
VCC W47 VDDQ BE22 VSS AC7
VCC W8 VDDQ BE26 VSS AD48
VCC Y45 VDDQ BE30 VSS AD50
VCC Y46 VDDQ BE33 VSS AD51
VCC Y8 VIDALERT# J53 VSS AD54
VCC_SENSE C50 VIDSCLK J52 VSS AD7
VCCIO_OUT D51 VIDSOUT J50 VSS AD9
VCOMP_OUT AK6 VSS A11 VSS AE1
VDDQ AR29 VSS A15 VSS AE2
VDDQ AT13 VSS A26 VSS AE48
VDDQ AT32 VSS A40 VSS AF5
VDDQ AT36 VSS A44 VSS AF6
VDDQ AV37 VSS AA1 VSS AF7
VDDQ AW22 VSS AA2 VSS AG48


128 Order No.: 332376-001v1
VSS AG52 VSS AN1 VSS AT25
VSS AH1 VSS AN49 VSS AT37
VSS AH48 VSS AP49 VSS AT42
VSS AJ48 VSS AP7 VSS AT47
VSS AJ49 VSS AR12 VSS AT49
VSS AK48 VSS AR20 VSS AT52
VSS AL1 VSS AR50 VSS AU13
VSS AL7 VSS AT1 VSS AU29
VSS AM5 VSS AT10 VSS AU30
VSS AM7 VSS AT22 VSS AV1


Order No.: 332376-001v1 129
VSS AV13 VSS B11 VSS BB20
VSS AW13 VSS BA13 VSS BB46
VSS AW49 VSS BA42 VSS BC10
VSS AY13 VSS BA9 VSS BC26
VSS AY22 VSS BB10 VSS BC3


130 Order No.: 332376-001v1
VSS BC48 VSS C22 VSS E37
VSS BD10 VSS C4 VSS E52
VSS BD36 VSS C49 VSS F2
VSS BD5 VSS D11 VSS F30
VSS BD51 VSS D15 VSS F33
VSS BE10 VSS D19 VSS F37
VSS BF10 VSS D37 VSS F5
VSS BF18 VSS D49 VSS G11
VSS BF22 VSS D8 VSS G13
VSS BF26 VSS E11 VSS G16
VSS C11 VSS E26 VSS G40


Order No.: 332376-001v1 131
VSS G52 VSS P3 VSS_NCTF A49
VSS G8 VSS P5 VSS_NCTF B4
VSS G9 VSS P50 VSS_NCTF BA1
VSS H44 VSS P52 VSS_NCTF BA54
VSS H49 VSS P54 VSS_NCTF BB1
VSS H51 VSS P6 VSS_NCTF BB54
VSS H52 VSS P7 VSS_NCTF BD2
VSS H53 VSS P9 VSS_NCTF BD53
VSS H54 VSS R48 VSS_NCTF BF49
VSS H7 VSS R7 VSS_NCTF BF5
VSS J44 VSS T48 VSS_NCTF BF50
VSS J49 VSS U1 VSS_NCTF BF6
VSS J51 VSS U2 VSS_NCTF C53
VSS J54 VSS U3 VSS_NCTF D2
VSS J7 VSS U4 VSS_NCTF E54
VSS K1 VSS U48 VSS_NCTF F54
VSS K2 VSS U5 VSS_NCTF G1
VSS K3 VSS U50 VSS_SENSE D50
VSS K4 VSS U52
VSS K5 VSS U54
VSS K6 VSS U6
VSS K7 VSS U7
VSS L48 VSS V48
VSS L7 VSS V50
VSS L9 VSS V7
VSS M48 VSS V9
VSS M50 VSS W48
VSS M52 VSS W50
VSS M54 VSS W52
VSS M7 VSS W54
VSS N48 VSS W7
VSS N7 VSS Y48
VSS P1 VSS Y7
VSS P2 VSS Y9

132 Order No.: 332376-001v1

Desktop 5th Gen Core Family Datasheet Vol 1

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Desktop 5th Gen Core Family Datasheet Vol 1

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Desktop 5th Generation Intel® Core™

Supporting 5th Generation Intel® Core™ Processor based on

Order No.: 332376-001v1

No computer system can be absolutely secure.

Copyright © 2015, Intel Corporation. All rights reserved.

Desktop 5th Generation Intel® Core™ Processor Family

Desktop 5th Generation Intel® Core™ Processor Family

4.0 Power Management.................................................................................................... 49

Desktop 5th Generation Intel® Core™ Processor Family

6.14 Processor Internal Pull-Up / Pull-Down Terminations................................................ 87

Desktop 5th Generation Intel® Core™ Processor Family

Desktop 5th Generation Intel® Core™ Processor Family

Desktop 5th Generation Intel® Core™ Processor Family

54 Processor Materials................................................................................................ 104

Desktop 5th Generation Intel® Core™ Processor Family

001 • Initial Release June 2015

Desktop 5th Generation Intel® Core™ Processor Family

Desktop 5th Generation Intel® Core™ Processor Family

Figure 1. Platform Block Diagram

PCI Express* 3.0 2 DIMMs / CH

Intel® Flexible Display

USB 3.0 Analog Display

SPI Intel® High

1.1 Supported Technologies

Desktop 5th Generation Intel® Core™ Processor Family

• Execute Disable Bit

1.3 Power Management Support

Desktop 5th Generation Intel® Core™ Processor Family

Processor Graphics Controller

1.4 Thermal Management Support

1.5 Package Support

1.6 Processor Testability

APD Active Power-down

BGA Ball Grid Array

BLC Backlight Compensation

BLT Block Level Transfer

Desktop 5th Generation Intel® Core™ Processor Family

BPP Bits per pixel

CKE Clock Enable

CLTM Closed Loop Thermal Management

DDI Digital Display Interface

DDR3 Third-generation Double Data Rate SDRAM memory technology

DLL Delay-Locked Loop

DMA Direct Memory Access

DMI Direct Media Interface

DTS Digital Thermal Sensor

ECC Error Correction Code

eDP* embedded DisplayPort*

EPG Electrical Power Gating

FMA Floating-point fused Multiply Add instructions

FSC Fan Speed Control

HDCP High-bandwidth Digital Content Protection

HDMI* High Definition Multimedia Interface

HFM High Frequency Mode

iDCT Inverse Discrete Cosine Transform

IHS Integrated Heat Spreader

GSA Graphics in System Agent

GUI Graphical User Interface

IMC Integrated Memory Controller

Intel®64 64-bit memory extensions to the IA-32 architecture