Desktop 6th Gen Core Family Spec Update
Desktop 6th Gen Core Family Spec Update
Desktop 6th Gen Core Family Spec Update
Family
Specification Update
Supporting 6th Generation Intel Core Processor Families
based on the H-Processor, S-Processor and Intel Pentium
Processors
Supporting 6th Generation Intel Core Processor Families
based on Y-Processor Line, U-Processor Line and Intel
Pentium Processors
January 2016
Version 1.0
Revision History
You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning
Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter
drafted which includes subject matter disclosed herein.
No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.
Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service
activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with
your system manufacturer or retailer or learn more at intel.com.
Intel technologies may require enabled hardware, specific software, or services activation. Check with your system manufacturer
or retailer.
The products described may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness
for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or
usage in trade.
All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel
product specifications and roadmaps
Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-5484725 or visit www.intel.com/design/literature.htm.
Intel Hyper-Threading Technology (Intel HT Technology) is available on select Intel Core processors. It requires an Intel
HT Technology enabled system. Consult your PC manufacturer. Performance will vary depending on the specific hardware and
software used. Not available on Intel Core i5-750. For more information including details on which processors support Intel
HT Technology, visit http://www.intel.com/info/hyperthreading.
Intel 64 architecture requires a system with a 64-bit enabled processor, chipset, BIOS and software. Performance will vary
depending on the specific hardware and software you use. Consult your PC manufacturer for more information. For more
information, visit http://www.intel.com/content/www/us/en/architecture-and-technology/microarchitecture/intel-64-architecturegeneral.html.
Intel Virtualization Technology (Intel VT) requires a computer system with an enabled Intel processor, BIOS, and virtual
machine monitor (VMM).Functionality, performance or other benefits will vary depending on hardware and software
configurations. Software applications may not be compatible with all operating systems. Consult your PC manufacturer. For more
information, visit http://www.intel.com/go/virtualization.
The original equipment manufacturer must provide TPM functionality, which requires a TPM-supported BIOS. TPM functionality
must be initialized and may not be available in all countries.
For Enhanced Intel SpeedStep Technology, see the Processor Spec Finder at http://ark.intel.com/ or contact your Intel
representative for more information.
Intel AES-NI requires a computer system with an AES-NI enabled processor, as well as non-Intel software to execute the
instructions in the correct sequence. AES-NI is available on select Intel processors. For availability, consult your reseller or
system manufacturer. For more information, see http://software.intel.com/en-us/articles/intel-advanced-encryption-standardinstructions-aes-ni/.
No computer system can provide absolute security under all conditions. Intel Trusted Execution Technology (Intel TXT)
requires a computer with Intel Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code
Modules and an Intel TXT-compatible measured launched environment (MLE). Intel TXT also requires the system to contain a TPM
v1.s. For more information, visit http://www.intel.com/technology/security.
Requires a system with Intel Turbo Boost Technology. Intel Turbo Boost Technology and Intel Turbo Boost Technology 2.0 are
only available on select Intel processors. Consult your PC manufacturer. Performance varies depending on hardware, software,
and system configuration. For more information, visit https://www-ssl.intel.com/content/www/us/en/architecture-andtechnology/turbo-boost/turbo-boost-technology.html.
Intel Advanced Vector Extensions (Intel AVX) are designed to achieve higher throughput to certain integer and floating point
operations. Due to varying processor power characteristics, utilizing AVX instructions may cause a) some parts to operate at less
than the rated frequency and b) some parts with Intel Turbo Boost Technology 2.0 to not achieve any or maximum turbo
frequencies. Performance varies depending on hardware, software, and system configuration and you should consult your system
manufacturer for more information. Intel Advanced Vector Extensions refers to Intel AVX, Intel AVX2 or Intel AVX-512.
For more information on Intel Turbo Boost Technology 2.0, visit https://www-ssl.intel.com/content/www/us/en/architectureand-technology/turbo-boost/turbo-boost-technology.html
Intel, 6th Generation Intel Core processor, Intel Xeon processor, Intel Pentium processor, Intel Celeron processor,
Intel Processor Trace (Intel PT), Intel Virtualization Technology (Intel VT), Intel Virtualization Technology (Intel VT)
for IA-32, Intel 64 and Intel Architecture (Intel VT-x), Intel Virtualization Technology (Intel VT) for Directed I/O (Intel
VT-d), Intel Trusted Execution Technology (Intel TXT), Intel Advanced Encryption Standard New Instructions (Intel AESNI), Intel Secure Key, Boot Guard, Intel Memory Protection Extensions (Intel MPX), Intel Software Guard Extensions
(Intel SGX), Intel Hyper-Threading Technology (Intel HT Technology), Intel Turbo Boost Technology, Intel Advanced
Vector Extensions 2 (Intel AVX2), and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.
*Other names and brands may be claimed as the property of others.
Copyright 20152016, Intel Corporation. All rights reserved.
Specification Update
Revision History
Contents
Revision History ...................................................................................................................4
Preface ...............................................................................................................................5
Summary Tables of Changes ..................................................................................................7
Identification Information .................................................................................................... 13
Errata ............................................................................................................................... 23
Specification Changes ......................................................................................................... 47
Specification Clarifications.................................................................................................... 49
Documentation Changes ...................................................................................................... 50
Specification Update
Revision History
Revision History
Revision
Version
Description
Date
001
N/A
Initial release
002
1.0
August 2015
003
1.0
January 2016
July 2015
SKL055,
SKL060,
SKL065,
SKL070,
SKL075,
SKL080,
SKL085,
SKL090,
SKL096,
SKL056,
SKL061,
SKL066,
SKL071,
SKL076,
SKL081,
SKL086,
SKL091,
SKL097
SKL057,
SKL062,
SKL067,
SKL072,
SKL077,
SKL082,
SKL087,
SKL093,
SKL058,
SKL063,
SKL068,
SKL073,
SKL078,
SKL083,
SKL088,
SKL094,
Specification Update
Preface
Preface
This document is an update to the specifications contained in the documents listed in
the following Affected Documents/Related Documents table. It is a compilation of
device and document errata and specification clarifications and changes, and is
intended for hardware system manufacturers and for software developers of
applications, operating system, and tools.
Information types defined in the Nomenclature section of this document are
consolidated into this update document and are no longer published in other
documents. This document may also contain information that has not been previously
published.
Affected Documents
Document Title
6th Generation Intel Processor Datasheet for S-Platforms, Volume 1 of 2
Document
Number/Location
332687
th
332688
th
332986
th
332987
332990
332991
Related Documents
Document Title
Document
Number/Location
http://www.intel.co
m/design/processor
/applnots/241618.h
tm
http://www.intel.co
m/products/process
or/manuals/index.h
tm
Specification Update
Preface
Document Title
Document
Number/Location
http://www.intel.co
m/content/www/us/
en/processors/archi
tec-tures-softwaredevelopermanuals.html
D51397-001
www.acpi.info
Nomenclature
Errata are design defects or errors. Errata may cause the processors behavior to
deviate from published specifications. Hardware and software designed to be used
with any given stepping must assume that all errata documented for that stepping are
present on all devices.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further
highlight a specifications impact to a complex design situation. These clarifications will
be incorporated in the next release of the specifications.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These changes will be incorporated in the next release of the
specifications.
Note: Errata remain in the specification update throughout the products lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon
request. Specification changes, specification clarifications and documentation changes
are removed from the specification update when the appropriate changes are made to
the appropriate product specification or user documentation (datasheets, manuals,
etc.).
Specification Update
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification
change does not apply to listed stepping.
Status
Doc:
Plan Fix:
Fixed:
No Fix:
Shaded:
Row
Specification Update
Stepping
D-0
SKL001
SKL002
SKL003
SKL004
SKL005
SKL006
SKL007
SKL008
SKL009
SKL010
SKL011
SKL012
SKL013
SKL014
SKL015
SKL016
SKL017
SKL018
SKL019
SKL020
SKL021
K-0
Status
Title
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
WRMSR May Not Clear The Sticky Count Overflow Bit in The
IA32_MCi_STATUS MSRs Corrected Error Count Field
No Fix
No Fix
No Fix
No Fix
R-0
Specification Update
Number
Stepping
D-0
SKL022
SKL023
SKL024
SKL027
SKL028
SKL029
SKL030
SKL031
SKL032
SKL033
SKL034
SKL035
SKL036
SKL037
SKL038
SKL039
SKL040
SKL041
SKL042
SKL043
SKL044
Specification Update
Title
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
PCIe* and DMI Links With Lane Polarity Inversion May Result in
Link Failure
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
R-0
SKL025
SKL026
K-0
Status
X
X
Number
Stepping
D-0
SKL045
SKL046
SKL047
SKL048
SKL049
SKL050
SKL051
SKL052
SKL053
SKL054
SKL055
SKL056
SKL057
SKL058
SKL059
SKL060
SKL061
SKL062
SKL063
SKL064
SKL065
SKL066
10
K-0
Status
Title
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
R-0
Specification Update
Number
Stepping
D-0
SKL067
K-0
SKL069
SKL070
SKL071
SKL072
SKL073
SKL074
SKL075
SKL076
SKL077
SKL078
SKL079
SKL080
X
X
SKL081
SKL082
SKL083
SKL084
SKL085
SKL086
SKL087
SKL088
SKL089
SKL090
Specification Update
X
X
X
Title
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
Display Flicker May Occur When Both VT-d And FBC Are
Enabled
No Fix
System May Hang When Using Intel TXT And Memory That
Supports Address Mirroring
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
x87 FPU Data Pointer Updated Only for Instructions That Incur
Unmasked Exceptions
No Fix
No Fix
No Fix
R-0
SKL068
Status
X
X
11
Number
Stepping
D-0
K-0
Status
Title
R-0
Interrupts
SKL091
No Fix
SKL092
SKL093
SKL094
SKL095
SKL096
SKL097
X
X
No Fix
No Fix
No Fix
No Fix
No Fix
#GP After RSM May Push Incorrect RFLAGS Value When Intel
PT is Enabled
Notes:
1.
2.
3.
Affects 6th
Affects 6th
G4xxx and
Affects 6th
Generation Intel Pentium processor family and Intel Celeron processor family.
Generation Intel Core i3 U/H/S, Intel Pentium, Intel Celeron, Intel Pentium
Intel Celeron G3xxx Processors.
Generation Intel Core i7 & i5 Desktop and Intel Xeon E3-1200 v5 Family Processors.
12
Specification Update
Identification Information
Identification Information
Component Identification via Programming Interface
The processor stepping can be identified by the following register contents:
Table 2. Y/U-Processor Lines Component Identification
Reserved
Extended
Family
Extended
Model
Reserved
Processor
Type
Family
Code
Model
Number
Stepping
ID
31:28
27:20
19:16
15:14
13:12
11:8
7:4
3:0
0000000b
0100b
00b
0110b
1110b
xxxxb
Extended
Family
Extended
Model
Reserved
Processor
Type
Family
Code
Model
Number
Stepping
ID
31:28
27:20
19:16
15:14
13:12
11:8
7:4
3:0
0000000b
0101b
00b
0110b
1110b
xxxxb
Notes:
1.
2.
3.
4.
5.
6.
The Extended Family, Bits [27:20] are used in conjunction with the Family
Code, specified in Bits[11:8], to indicate whether the processor belongs to the
Intel386, Intel486, Pentium, Pentium 4, or Intel Core processor
family.
The Extended Model, Bits [19:16] in conjunction with the Model Number,
specified in Bits [7:4], are used to identify the model of the processor within
the processors family.
The Family Code corresponds to Bits [11:8] of the EDX register after RESET,
Bits [11:8] of the EAX register after the CPUID instruction is executed with a 1
in the EAX register, and the generation field of the Device ID register
accessible through Boundary Scan.
The Model Number corresponds to Bits [7:4] of the EDX register after RESET,
Bits [7:4] of the EAX register after the CPUID instruction is executed with a 1
in the EAX register, and the model field of the Device ID register accessible
through Boundary Scan.
The Stepping ID in Bits [3:0] indicates the revision number of that model. See
Table 1 for the processor stepping ID number in the CPUID information.
When EAX is initialized to a value of 1, the CPUID instruction returns the
Extended Family, Extended Model, Processor Type, Family Code, Model
Number and Stepping ID value in the EAX register. Note that the EDX
processor signature value after reset is equivalent to the processor signature
output value in the EAX register.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX, and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register.
Specification Update
13
Identification Information
Production (SSPEC):
GRP1LINE1:
GRP2LINE1 (G2L1):
GRP3LINE1 (G3L1):
14
FPOxxxxxSSPEC
Intel logo
{eX}
Specification Update
Identification Information
S-Spec
#
Cache
Size
(MB)
Functional
Core
Process
or
Graphic
s Cores
Process
or
Graphic
s Freq.
(MHz)
Process
or
Graphic
s Turbo
Freq.
(GHz)
Turbo
1 Core
Freq.
Rate
(GHz)
Therm
al
Design
Power
(W)
1500
1500
BGA1515
1866
900
2200
4.5
BGA1515
1600
1866
1100
2700
4.5
BGA1515
1000
1600
1866
1200
3100
4.5
BGA1515
900
1600
1866
1100
2800
4.5
BGA1515
DDR3L
Mem.
(MHz)
LPDDR
3
Mem.
(MHz)
Processor
Number
Stepping
SR2ER
Pentium
4405Y
D-1
300
800
1600
1866
SR2EN
m3-6Y30
D-1
300
850
1600
SR2EM
m5-6Y54
D-1
300
900
SR2EH
m7-6Y75
D-1
300
SR2EG
m5-6Y57
D-1
300
Specification Update
Core
Freq.
(GHz)
15
Slot /
Socket
Type
Identification Information
Figure 2.
Package Size: 42 mm x 24 mm
Sample (SSPEC):
GRP1LINE1:
GRP2LINE1 (G2L1):
GRP3LINE1 (G3L1):
16
FPOxxxxxQxxx
{eX}
Intel logo
Specification Update
Identification Information
Func
tional
Core
Processor
Graphics
Cores
Process
or
Graphics
Freq.
(MHz)
Process
or
Graphics
Turbo
Freq.
(GHz)
DDR3L
Mem.
(MHz)
DDR4
Mem.
(MHz)
LPDDR
3 Mem.
(MHz)
Core
Freq.
(GHz)
Turbo
1 Core
Freq.
Rate
(GHz)
Therm
al
Design
Power
(W)
Slot /
Socket
Type
S-Spec #
Processor
Number
Stepping
Cache
Size
(MB)
SR2F0
i5-6300U
D-1
300
1000
1600
2133
1866
2400
3000
15
BGA1356
SR2F1
i7-6600U
D-1
300
1050
1600
2133
1866
2600
3400
15
BGA1356
SR2EY
i5-6200U
D-1
300
1000
1600
2133
1866
2300
2800
15
BGA1356
SR2EZ
i7-6500U
D-1
300
1050
1600
2133
1866
2500
3100
15
BGA1356
SR2EX
Pentium
4405U
D-1
300
950
1600
2133
1866
2100
2100
15
BGA1356
SR2EV
Celeron
3855U
D-1
300
900
1600
2133
1866
1600
1600
15
BGA1356
SR2EW
Celeron
3955U
D-1
300
900
1600
2133
1866
2000
2000
15
BGA1356
SR2EU
i3-6100U
D-1
300
1000
1600
2133
1866
2300
2300
15
BGA1356
D-1
300
1050
1600
2133
1866
2600
3200
15
BGA1356
D-1
300
1000
1600
2133
1866
2500
3100
15
BGA1356
D-1
300
1000
1600
2133
1866
2400
2900
15
BGA1356
D-1
300
1000
1600
2133
1866
2400
2400
15
BGA1356
SR2F4
SR2F3
SR2F5
SR2F9
I7-6510U
I5-6310U
I5-6210U
I3-6110U
SR2F6
Pentium
4415U
D-1
300
950
1600
2133
1866
2200
2200
15
BGA1356
SR2F7
Celeron
3865U
D-1
300
900
1600
2133
1866
2100
2100
15
BGA1356
SR2F8
Celeron
3965U
D-1
300
900
1600
2133
1866
1700
1700
15
BGA1356
R2JB
I7-6560U
K-1
300
1050
1600
2133
1866
2200
3200
15
R2JC
I5-6260U
K-1
300
950
1600
2133
1866
1800
2900
15
R2JF
I3-6167U
K-1
300
1000
1600
2133
1866
2700
2700
28
300
1100
1600
2133
1866
3300
3600
28
300
1100
1600
2133
1866
3100
3500
28
300
1050
1600
2133
1866
2900
3300
28
300
1000
1600
2133
1866
2000
3100
15
300
1050
1600
2133
1866
2200
3400
15
R2JH
I7-6567U
R2JJ
I5-6287U
R2JK
I5-6267U
R2JM
I5-6360U
R2KA
I7-6650U
K-1
K-1
K-1
K-1
K-1
Specification Update
17
BGA1356
BGA1356
BGA1356
BGA1356
BGA1356
BGA1356
BGA1356
BGA1356
Identification Information
Figure 3.
Sample (SSPEC):
GRP1LINE1:
GRP1LINE2:
GRP1LINE3:
GRP1LINE4:
GRP1LINE5:
18
Intel logo
BRAND
PROC#
SSPEC SPEED
{FPO} {eX}
Specification Update
Identification Information
S-Spec
#
SR2BR
Processor
Number
Cache
Size
(MB)
Stepping
Functional
Core
Process
or
Graphic
s Cores
Process
or
Graphic
s Freq.
(MHz)
Process
or
Graphic
s Turbo
Freq.
(GHz)
DDR4
Mem.
(MHz)
DDR3L
Mem.
(MHz)
Core
Freq.
(GHz)
Turbo
1 Core
Freq.
Rate
(GHz)
Therm
al
Design
Power
(W)
Slot /
Socket
Type
i7-6700K
R-0
350
1.15
2133
1600
4.2
91
LGA1151
i5-6400T
R-0
350
0.95
2133
1600
2.2
2.8
35
LGA1151
i7-6700
R-0
350
1.15
2133
1600
3.4
65
LGA1151
i7-6700T
R-0
350
1.1
2133
1600
2.8
3.6
35
LGA1151
i5-6600K
R-0
350
1.15
2133
1600
3.5
3.9
91
LGA1151
i5-6600
R-0
350
1.15
2133
1600
3.3
3.9
65
LGA1151
i5-6500
R-0
350
1.05
2133
1600
3.2
3.6
65
LGA1151
i5-6400
R-0
350
0.95
2133
1600
2.7
3.3
65
LGA1151
i5-6500T
R-0
350
1.1
2133
1600
2.5
3.1
35
LGA1151
SR2C0
i5-6600T
R-0
350
1.1
2133
1600
2.7
3.5
35
LGA1151
SR2L0
I7-6700K
R-0
350
1.15
2133
1600
4.1
95
LGA1151
SR2L1
I5-6400T
R-0
350
0.95
2133
1600
2.2
2.8
35
LGA1151
SR2L2
I7-6700
R-0
350
1.15
2133
1600
3.4
65
LGA1151
SR2L3
I7-6700T
R-0
350
1.1
2133
1600
2.8
3.6
35
SR2L4
I5-6600K
R-0
350
1.15
2133
1600
3.5
3.9
95
LGA1151
SR2L5
I5-6600
R-0
350
1.15
2133
1600
3.3
3.9
65
LGA1151
SR2L6
I5-6500
R-0
350
1.05
2133
1600
3.2
3.6
65
LGA1151
SR2L7
I5-6400
R-0
350
0.95
2133
1600
2.7
3.3
65
LGA1151
SR2L8
I5-6500T
R-0
350
1.1
2133
1600
2.5
3.1
35
SR2L9
I5-6600T
R-0
350
1.1
2133
1600
2.7
3.5
35
LGA1151
SR2H9
i3-6320
S-0
350
1.15
2133
1600
3.9
N/A
51
LGA1151
SR2HA
i3-6300
S-0
350
1.15
2133
1600
3.8
N/A
51
LGA1151
SR2HG
i3-6100
S-0
350
1.05
2133
1600
3.7
N/A
51
LGA1151
SR2HM
G4520
S-0
350
1.05
2133
1600
3.6
N/A
51
LGA1151
SR2HJ
G4500
S-0
350
1.05
2133
1600
3.5
N/A
51
LGA1151
SR2DC
Pentium
G4400
R-0
350
1.0
2133
1600
3.3
N/A
65
LGA1151
SR2HD
i3-6300T
S-0
350
0.95
2133
1600
3.3
N/A
35
LGA1151
SR2HE
i3-6100T
S-0
350
0.95
2133
1600
3.2
N/A
35
LGA1151
SR2HS
G4500T
S-0
350
0.95
2133
1600
N/A
35
LGA1151
SR2BS
SR2BT
SR2BU
SR2BV
SR2BW
SR2BX
SR2BY
SR2BZ
Specification Update
19
LGA1151
LGA1151
Identification Information
S-Spec
#
Processor
Number
Cache
Size
(MB)
Stepping
Functional
Core
Process
or
Graphic
s Cores
Process
or
Graphic
s Freq.
(MHz)
Process
or
Graphic
s Turbo
Freq.
(GHz)
DDR4
Mem.
(MHz)
DDR3L
Mem.
(MHz)
Core
Freq.
(GHz)
Turbo
1 Core
Freq.
Rate
(GHz)
Therm
al
Design
Power
(W)
Slot /
Socket
Type
SR2HR
Pentium
G4520T
S-0
350
0.95
2133
1600
3.1
N/A
35
LGA1151
SR2HC
I3-6320T
S-0
350
0.95
2133
1600
3.4
N/A
35
LGA1151
SR2HH
I3-6120
S-0
350
1.05
2133
1600
3.8
N/A
65
LGA1151
SR2HF
I3-6120T
S-0
350
0.95
2133
1600
3.3
N/A
35
LGA1151
SR2HN
Pentium
G4540
S-0
350
0.95
2133
1600
3.7
N/A
65
LGA1151
SR2HQ
G4400T
S-0
350
0.95
2133
1600
2.9
N/A
35
LGA1151
SR2HL
Pentium
G4420
S-0
350
1.0
2133
1600
3.4
N/A
65
LGA1151
SR2HK
Pentium
G4400
S-0
350
1.0
2133
1600
3.3
N/A
65
LGA1151
SR2HT
Celeron
G3900T
S-0
350
0.95
2133
1600
2.6
N/A
35
LGA1151
SR2HU
Celeron
G3920T
S-0
350
0.95
2133
1600
2.7
N/A
35
LGA1151
SR2HP
Pentium
G4420T
S-0
350
0.95
2133
1600
N/A
35
LGA1151
SR2HV
Celeron
G3900
S-0
350
0.95
2133
1600
2.8
N/A
65
LGA1151
SR2HX
Celeron
G3920
S-0
350
0.95
2133
1600
2.9
N/A
65
LGA1151
SR2HW
Celeron
G3940
S-0
350
0.95
2133
1600
N/A
65
LGA1151
Notes:
1. The following S-Spec is affected by erratum SKL067 which is being addressed by Product Change Notification (PCN)
#114074.
2. Intel is initiating new S-Spec and MM numbers for 6th Generation Intel Core i7 & i5 desktop and the Intel
Xeon E3-1200 v5 family processors for a minor manufacturing configuration change to allow customers to enable
Intel Software Guard Extensions (Intel SGX) when using these processors.
The stepping will not change for these processors; it remains R-0.
The CPUID Processor Signature will not change for these processors; it remains 0x506E3.
Die size and package will not change for these processors.
Link to SKL-S 4+2 PCN #114074 (Product Change Notification) for new S-Specs:
http://qdms.intel.com/dm/i.aspx/5A160770-FC47-47A0-BF8A-062540456F0A/PCN114074-00.pdf
20
Specification Update
Identification Information
Figure 4.
Package Size: 42 mm x 28 mm
Production (SSPEC):
GRP1LINE1 (G1L1):
GRP2LINE1:
GRP3LINE1 (G3L1):
Specification Update
{eX}
FPOxxxxxSSPEC
Intel logo
21
Identification Information
Proces
sor
Graphi
cs
Freq.
(MHz)
Proces
sor
Graphi
cs
Turbo
Freq.
(GHz)
DDR3L
Mem.
(MHz)
DDR4
Mem.
(MHz)
LPDD
R3
Mem.
(MHz)
Core
Freq.
(GHz)
Turbo
1
Core
Freq.
Rate
(GHz)
Ther
mal
Desig
n
Powe
r (W)
S-Spec
#
Process
or
Number
SR2FM
E31535MV5
R-0
350
1.05
1600
2133
1866
2.9
3.8
45
BGA1440
SR2FT
i76920HQ
R-0
350
1.05
1600
2133
1866
2.9
3.8
45
BGA1440
SR2FN
E31505MV5
R-0
350
1.05
1600
2133
1866
2.8
3.7
45
BGA1440
SR2FU
i76820HQ
R-0
350
1.05
1600
2133
1866
2.7
3.6
45
BGA1440
SR2FL
i76820HK
R-0
350
1.05
1600
2133
1866
2.7
3.6
45
BGA1440
SR2FQ
i76700HQ
R-0
350
1.05
1600
2133
1866
2.6
3.5
45
BGA1440
SR2FS
i56440HQ
R-0
350
0.95
1600
2133
1866
2.6
3.5
45
BGA1440
SR2FP
i56300HQ
R-0
350
0.95
1600
2133
1866
2.3
3.2
45
BGA1440
SR2FR
i3-6100H
R-0
350
0.9
1600
2133
1866
2.7
2.7
35
BGA1440
SR2QT
E31515MV5
R-0
350
1600
2133
1866
2.8
3.7
45
BGA1440
SR2QU
E31545MV5
R-0
350
1.05
1600
2133
1866
2.9
3.8
45
BGA1440
SR2QV
E31575MV5
R-0
350
1.1
1600
2133
1866
3.9
45
BGA1440
SR2QW
i76970HQ
R-0
350
1.05
1600
2133
1866
2.8
3.7
45
BGA1440
SR2QX
i76870HQ
R-0
350
1600
2133
1866
2.7
3.6
45
BGA1440
SR2QY
i76770HQ
R-0
350
0.95
1600
2133
1866
2.6
3.5
45
BGA1440
SR2QZ
I56350HQ
R-0
350
0.9
1600
2133
1866
2.3
3.2
45
BGA1440
Stepping
Cache
Size
(MB)
Func
tiona
l
Core
22
Specification Update
Slot /
Socket
Type
Errata
Errata
SKL001
Reported Memory Type May Not Be Used to Access the VMCS and
Referenced Data Structures
Problem
Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the processor
uses to access the VMCS and data structures referenced by pointers in the VMCS.
Due to this erratum, a VMX access to the VMCS or referenced data structures will
instead use the memory type that the MTRRs (memory-type range registers) specify
for the physical address of the access.
Implication
Bits 53:50 of the IA32_VMX_BASIC MSR report that the WB (write-back) memory
type will be used but the processor may use a different memory type.
Workaround
Software should ensure that the VMCS and referenced data structures are located at
physical addresses that are mapped to WB memory type by the MTRRs.
Status
SKL002
Instruction Fetch May Cause Machine Check if Page Size and Memory Type
Was Changed Without Invalidation
Problem
Implication
Due to this erratum an unexpected machine check with error code 0150H may occur,
possibly resulting in a shutdown. Intel has not observed this erratum with any
commercially available software.
Workaround
Software should not write to a paging-structure entry in a way that would change, for
any linear address, both the page size and the memory type. It can instead use the
following algorithm: first clear the P flag in the relevant paging-structure entry (e.g.,
PDE); then invalidate any translations for the affected linear addresses; and then
modify the relevant paging-structure entry to set the P flag and establish the new
page size and memory type.
Status
SKL003
Problem
The VAESIMC and VAESKEYGENASSIST instructions should produce a #UD (InvalidOpcode) exception if the value of the vvvv field in the VEX prefix is not 1111b. Due to
this erratum, if CR0.TS is 1, the processor may instead produce a #NM (DeviceNot-Available) exception.
Implication
Due to this erratum, some undefined instruction encodings may produce a #NM
instead of a #UD exception.
Specification Update
23
Errata
Workaround
Software should always set the vvvv field of the VEX prefix to 1111b for instances of
the VAESIMC and VAESKEYGENASSIST instructions.
Status
SKL004
Problem
Implication
The Corrected Error Count Overflow indication will be lost if the overflow occurs after
an uncorrectable error has been logged.
Workaround
None identified
Status
SKL005
Problem
Implication
Software in VMX root operation may execute with the execute disable feature
enabled despite the fact that the feature should be disabled by the
IA32_MISC_ENABLE MSR. Intel has not observed this erratum with any commercially
available software.
Workaround
Status
SKL006
SMRAM State-Save Area Above the 4GB Boundary May Cause Unpredictable
System Behavior
Problem
If BIOS uses the RSM instruction to load the SMBASE register with a value that would
cause any part of the SMRAM state-save area to have an address above 4-GBytes,
subsequent transitions into and out of SMM (system-management mode) might save
and restore processor state from incorrect addresses.
Implication
This erratum may cause unpredictable system behavior. Intel has not observed this
erratum with any commercially available system.
Workaround
Ensure that the SMRAM state-save area is located entirely below the 4GB address
boundary.
Status
24
Specification Update
Errata
SKL007
Problem
x87 instructions that trigger #MF normally service interrupts before the #MF. Due to
this erratum, if an instruction that triggers #MF is executing when an Enhanced Intel
SpeedStep Technology transitions, an Intel Turbo Boost Technology transitions,
or a Thermal Monitor events occurs, the #MF may be taken before pending interrupts
are serviced.
Implication
Software may observe #MF being signaled before pending interrupts are serviced.
Workaround
None identified.
Status
SKL008
Incorrect FROM_IP Value For an RTM Abort in BTM or BTS May be Observed
Problem
Implication
Due to this erratum, the From_IP pointer may be the same as that of the
immediately preceding taken branch.
Workaround
None identified.
Status
SKL009
Problem
Implication
When the instruction at the fallback instruction address causes a debug exception,
DR6 may report a breakpoint that was not triggered by that instruction, or it may fail
to report a breakpoint that was triggered by the instruction.
Workaround
Status
SKL010
Problem
Implication
Software that expects REP prefix before a BSF instruction to be ignored may not
operate correctly since there are cases in which BSF and TZCNT differ with regard to
the flags that are set and how the destination operand is established.
Workaround
Specification Update
25
Errata
Status
SKL011
Problem
If the processor is directed to enter PCIe Polling.Compliance at 5.0 GT/s or 8.0 GT/s
transfer rates, it should use the Link Control 2 Compliance Preset/De-emphasis field
(bits [15:12]) to determine the correct de-emphasis level. Due to this erratum, when
the processor is directed to enter Polling.Compliance from 2.5 GT/s transfer rate, it
retains 2.5 GT/s de-emphasis values.
Implication
Workaround
None identified.
Status
SKL012
Problem
The SMSW instruction is illegal within an SGX (Software Guard Extensions) enclave,
and an attempt to execute it within an enclave should result in a #UD (invalid-opcode
exception). Due to this erratum, the instruction executes normally within an enclave
and does not cause a #UD.
Implication
The SMSW instruction provides access to CR0 bits 15:0 and will provide that
information inside an enclave. These bits include NE, ET, TS, EM, MP and PE.
Workaround
Status
SKL013
Problem
Implication
The Eventing EIP field of the generated PEBS record may be incorrect. Intel has not
observed this erratum with any commercially available software.
Workaround
Status
SKL014
Problem
When Intel PT (Intel Processor Trace) is enabled and a direct unconditional branch
clears IA32_RTIT_STATUS.FilterEn (MSR 571H, bit 0), due to this erratum, the
resulting TIP.PGD (Target IP Packet, Packet Generation Disable) may not have an IP
payload with the target IP.
Implication
It may not be possible to tell which instruction in the flow caused the TIP.PGD using
only the information in trace packets when this erratum occurs.
Workaround
The Intel PT trace decoder can compare direct unconditional branch targets in the
26
Specification Update
Errata
source with the FilterEn address range(s) to determine which branch cleared FilterEn.
Status
SKL015
Problem
Implication
A MOVBE instruction with both REX.W=1 and a 66H prefix will unexpectedly cause an
#UD (invalid-opcode exception). Intel has not observed this erratum with any
commercially available software.
Workaround
Do not use a 66H instruction prefix with a 64-bit operand MOVBE instruction.
Status
SKL016
Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM
Exception
Problem
Attempt to use FXSAVE or FXRSTOR with a VEX prefix should produce a #UD
(Invalid-Opcode) exception. If either the TS or EM flag bits in CR0 are set, a #NM
(device-not-available) exception will be raised instead of #UD exception.
Implication
Due to this erratum a #NM exception may be signaled instead of a #UD exception on
an FXSAVE or an FXRSTOR with a VEX prefix.
Workaround
Software should not use FXSAVE or FXRSTOR with the VEX prefix.
Status
SKL017
WRMSR May Not Clear The Sticky Count Overflow Bit in The
IA32_MCi_STATUS MSRs Corrected Error Count Field
Problem
The sticky count overflow bit is the most significant bit (bit 52) of the Corrected Error
Count Field (bits[52:38]) in IA32_MCi_STATUS MSRs. Once set, the sticky count
overflow bit may not be cleared by a WRMSR instruction. When this occurs, that bit
can only be cleared by power-on reset.
Implication
Software that uses the Corrected Error Count field and expects to be able to clear the
sticky count overflow bit may misinterpret the number of corrected errors when the
sticky count overflow bit is set. This erratum does not affect threshold-based CMCI
(Corrected Machine Check Error Interrupt) signaling.
Workaround
None identified.
Status
SKL018
Problem
Implication
Performance monitoring software using PEBS may incorrectly attribute PEBS events
that occur on a Jcc to the preceding instruction.
Specification Update
27
Errata
Workaround
None identified.
Status
SKL019
Problem
Implication
Debugging software may fail to operate properly if a debug exception is lost or does
not report complete information.
Workaround
Software should avoid using WRMSR instruction immediately after executing MOV SS
or POP SS
Status
SKL020
Problem
A PCIe link should retrain when Retrain Link (bit 5) in the Link Control register (Bus
0; Device 1; Functions 0,1,2; Offset 0xB0) is set. Due to this erratum, if the link is in
the L1 state, it may ignore the retrain request.
Implication
Workaround
Status
SKL021
Problem
Some Intel Processor Trace packets should be issued only between TIP.PGE (Target
IP Packet.Packet Generation Enable) and TIP.PGD (Target IP Packet.Packet
Generation Disable) packets. Due to this erratum, when a TIP.PGE packet is
generated it may be preceded by a PSB+ (Packet Stream Boundary) that incorrectly
includes FUP (Flow Update Packet) and MODE.Exec packets.
Implication
Workaround
Decoders should ignore FUP and MODE.Exec packets that are not between TIP.PGE
and TIP.PGD packets.
Status
SKL022
Problem
Due to this erratum, an APIC timer interrupt coincident with the core entering C6
state may be lost rather than held for servicing later.
Implication
A lost APIC timer interrupt may lead to missed deadlines or a system hang.
Workaround
Status
28
Specification Update
Errata
SKL023
Problem
Implication
Workaround
None identified. Intel PT ToPA should reside in WB memory and should not be written
within a Transactional Region.
Status
SKL024
Problem
Implication
When this erratum occurs, an unexpected FUP may be generated that creates the
appearance of an asynchronous event taking place immediately before or during the
VM entry.
Workaround
The Intel PT trace decoder may opt to ignore any FUP whose IP matches that of a VM
entry instruction.
Status
SKL026
Problem
Implication
Workaround
None identified.
Status
SKL027
Machine Check or Shutdown May Occur When Using The PECI RdIAMSR
Command
Problem
Under certain circumstances, reading a core Machine Check register using the PECI
(Platform Environmental Control Interface) RdIAMSR command may result in a
Machine Check or Shutdown.
Implication
Workaround
Status
Specification Update
29
Errata
SKL028
Problem
Implication
ENCLU[EGETKEY] will return the same key in response to two requests that differ
only in the value of KEYREQUEST.MISCMASK. Intel has not observed this erratum
with any commercially available software.
Workaround
When executing the ENCLU[EGETKEY] instruction, software should ensure the bits set
in KEYREQUEST.MISCMASK are a subset of the bits set in the current SECSs
MISCSELECT field.
Status
SKL029
Problem
Implication
Software using the POPCNT instruction may experience lower performance than
expected.
Workaround
None identified
Status
SKL030
Problem
Implication
Workaround
When executing the ENCLU[EREPORT] instruction, software should ensure the bits set
in TARGETINFO.MISCSELECT are a subset of the bits set in the current SECSs
MISCSELECT field.
Status
SKL031
Problem
Implication
Workaround
Status
30
Specification Update
Errata
SKL032
Transitions Out of 64-bit Mode May Lead to an Incorrect FDP And FIP
Problem
A transition from 64-bit mode to compatibility or legacy modes may result in cause a
subsequent x87 FPU state save to zeroing bits [63:32] of the FDP (x87 FPU Data
Pointer Offset) and the FIP (x87 FPU Instruction Pointer Offset).
Implication
Leaving 64-bit mode may result in incorrect FDP and FIP values when x87 FPU state
is saved.
Workaround
None identified. 64-bit software should save x87 FPU state before leaving 64-bit
mode if it needs to access the FDP and/or FIP values.
Status
SKL033
Problem
Some Intel PT (Intel Processor Trace) OVF (Overflow) packets may not be followed by
a FUP (Flow Update Packet) or TIP.PGE (Target IP Packet, Packet Generation Enable).
Implication
Workaround
When it encounters an OVF without a following FUP or TIP.PGE, the Intel PT trace
decoder should scan for the next TIP, TIP.PGE, or PSB+ to resume operation.
Status
SKL034
Problem
Implication
Workaround
System software should always specify a canonical address as the base address of
the 64-bit mode enclave.
Status
SKL035
Problem
A REP MOVS instruction that causes an exception or a VM exit may not detect a data
breakpoint that occurred on an earlier memory access of that REP MOVS instruction.
Implication
Workaround
Status
SKL036
Problem
The IOMMU unit for Processor Graphics pre-fetches context (or extended-context)
entries to improve performance. Due to the erratum, the IOMMU unit may report
Specification Update
31
Errata
spurious DMA remapping faults if prefetching encounters a context (or extendedcontext) entry which is not marked present.
Implication
Software may observe spurious DMA remapping faults when the present bit for the
context (or extended-context) entry corresponding to the Processor Graphics device
(Bus: 0; Device: 2; Function: 0) is cleared. These faults may be reported when the
Processor Graphics device is quiescent.
Workaround
None identified. Instead of marking a context not present, software should mark the
context (or extended-context) entry present while using the page table to indicate all
the memory pages referenced by the context entry is not present.
Status
SKL037
PCIe* and DMI Links With Lane Polarity Inversion May Result in Link Failure
Problem
The processors PCIe and DMI links may fail after exiting Package C7 or deeper if the
platform requires the link to utilize lane polarity inversion.
Implication
Due to this erratum, the processor cannot support lane polarity inversion on the PCIe
or DMI links when Package C7 or deeper is enabled.
Workaround
None identified.
Status
SKL038
Problem
After PCIe 8.0 GT/s Link Equalization on a root port (Bus 0; Device 1; Function 0, 1,
2) has completed, the Expansion ROM Base Address Register (Offset 38H) may be
incorrect.
Implication
Software that uses this BAR may behave unexpectedly. Intel has not observed this
erratum with any commercially available software.
Workaround
It is possible for the BIOS to contain a partial workaround for this erratum. Software
should wait at least 5ms following link equalization before accessing these Expansion
ROM Base Address Register.
Status
SKL039
Problem
Due to this erratum, when a processor PCIe port operating at 8.0 GT/s is directed to
redo equalization, either via software or from the link partner, incorrect coefficients
may be conveyed during Equalization Phase 3.
Implication
If the link partner accepts the incorrect coefficients, the link may become unstable.
Note this affects 8.0 GT/s only.
Workaround
Status
SKL040
Two DIMMs Per Channel 2133 MHz DDR4 SODIMM Daisy-Chain Systems
With Different Vendors May Hang
Problem
When, on a single memory channel with 2133 MHz DDR4 SODIMMs, mixing different
vendors or mixing single rank and dual rank DIMMs, may lead to a higher rate of
32
Specification Update
Errata
Due to this erratum, reported correctable error counts may increase or system may
hang.
Workaround
Use a single vendor for and do not mix single rank and dual rank 2133 MHz DDR4
SODIMM.
Status
SKL041
Problem
When using Intel SGX (Software Guard Extensions), the ENCLS[EINIT] instruction
will incorrectly cause a #GP (general protection fault) if the MISCSELECT field of the
SIGSTRUCT structure is not zero.
Implication
This erratum may cause an unexpected #GP, but only if software has set bits in the
MISCSELECT field in SIGSTRUCT structure that do not correspond to extended
features that can be written to the MISC region of the SSA (State Save Area). Intel
has not observed this erratum with any commercially available software.
Workaround
When executing the ENCLS[EINIT] instruction, software should only set bits in the
MISCSELECT field in the SIGSTRUCT structure that are enumerated as 1 by
CPUID.(EAX=12H,ECX=0):EBX (the bit vector of extended features that can be
written to the MISC region of the SSA).
Status
SKL042
Problem
Implication
The trace decoder will not see the OVF packet, nor any subsequent packets (e.g.,
TraceStop) that were lost due to overflow.
Workaround
None identified.
Status
SKL043
Problem
Implication
A system hang may occur when Intel PT and Intel TSX are used together.
Workaround
Status
SKL044
Problem
Specification Update
33
Errata
(79H) on multiple logical processors in parallel, a logical processor may, due to this
erratum, count the WRMSR instruction as multiple instruction-retired events.
Implication
Workaround
None identified.
Status
SKL045
Problem
The x87 FPU should update the x87 FIP (FPU instruction pointer) for every noncontrol x87 instruction executed. Due to this erratum, the FIP is valid only if the last
non-control FP instruction had an unmasked exception.
Implication
When this erratum occurs, an instruction that saves FIP (e.g., FSTENV) may save an
incorrect value. Software that depends on the FIP value for x87 non-control
instructions without unmasked exceptions may not operate as expected.
Workaround
Status
SKL046
Problem
Implication
A branch instruction that has executed both in user mode and in supervisor mode
(from the same linear address) may cause a #BR (bound range fault) when it should
not have or may not cause a #BR when it should have.
Workaround
An operating system can avoid this erratum by setting CR4.SMEP[bit 20] to enable
supervisor-mode execution prevention (SMEP). When SMEP is enabled, no code can
be executed both with CPL = 3 and with CPL < 3.
Status
SKL047
Writing a Non-Canonical Value to an LBR MSR Does Not Signal a #GP When
Intel PT is Enabled
If Intel PT (Intel Processor Trace) is enabled, WRMSR will not cause a generalprotection exception (#GP) on an attempt to write a non-canonical value to any of
the following MSRs:
MSR_LASTBRANCH_{0 - 31}_FROM_IP (680H 69FH)
Problem
34
Specification Update
Errata
value had been written. Specifically, the WRMSR will be dropped and the MSR value
will not be changed.
Implication
Workaround
None identified.
Status
SKL048
Processor May Run Intel AVX Code Much Slower Than Expected
Problem
After a C6 state exit, the execution rate of AVX instructions may be reduced.
Implication
Workaround
Status
SKL049
Problem
Implication
When this erratum occurs, the splicing of the CYC and OVF packets may prevent the
Intel PT decoder from recognizing the overflow. The Intel PT decoder may then
encounter subsequent packets that are not consistent with expected behavior.
Workaround
None Identified. The decoder may be able to recognize that this erratum has
occurred when a two-byte CYC packet is followed by a single byte CYC, where the
latter 2 bytes are 0xf302, and where the CYC packets are followed by a FUP (Flow
Update Packet) and a PSB+ (Packet Stream Boundary+). It should then treat the
two CYC packets as indicating an overflow.
Status
SKL050
Problem
An Intel PT (Processor Trace) PSB+ (Packet Stream Boundary+) set of packets may
not be generated as expected when IA32_RTIT_STATUS.PacketByteCnt[48:32] (MSR
0x571) reaches the PSB threshold and a logical processor C6 entry occurs within the
following one KByte of trace output.
Implication
After a logical processor enters C6, Intel PT output may be missing PSB+ sets of
packets.
Workaround
Status
SKL051
Problem
Implication
Specification Update
35
Errata
Workaround
Status
SKL052
Problem
Executing CPUID with EAX = 7 and ECX = 0 may return EBX with bits [3] and [8] set,
incorrectly indicating the presence of BMI1 and BMI2 instruction set extensions.
Implication
Attempting to use instructions from the BMI1 or BMI2 instruction set extensions will
result in a #UD exception.
Workaround
Status
SKL053
Problem
These processors may incorrectly report support for Intel Turbo Boost Technology
via CPUID.06H.EAX bit 1.
Implication
The CPUID instruction may report Turbo Boost Technology as supported even though
the processor does not permit operation above the Base Frequency.
Workaround
None identified.
Status
SKL054
Problem
Implication
Workaround
Status
SKL055
Problem
Implication
Software that relies on loads executing in program order may not operate correctly.
Workaround
Status
SKL056
Problem
Implication
Instructions may be executed beyond the CS limit. Intel has not observed this
36
Specification Update
Errata
Status
SKL057
Problem
Implication
Workaround
Status
SKL058
#GP Occurs Rather Than #DB on Code Page Split Inside an Intel SGX
Enclave
Problem
When executing within an Intel SGX (Software Guard Extensions) enclave, a #GP
(general-protection exception) may be delivered instead of a #DB (debug exception)
when an instruction breakpoint is detected. This occurs when the instruction to be
executed spans two pages, the second of which has an entry in the EPCM (enclave
page cache map) that is not valid.
Implication
Workaround
Software should ensure that all pages containing enclave instructions have valid
EPCM entries.
Status
SKL059
Problem
Implication
As a result of this erratum, an operating system may restore AVX and other state
unnecessarily.
Workaround
None identified.
Status
SKL060
Intel SGX Enclave Accesses to the APIC-Access Page May Cause APICAccess VM Exits
Problem
In VMX non-root operation, Intel SGX (Software Guard Extensions) enclave accesses
to the APIC-access page may cause APIC-access VM exits instead of page faults.
Implication
A VMM (virtual-machine monitor) may receive a VM exit due to an access that should
Specification Update
37
Errata
have caused a page fault, which would be handled by the guest OS (operating
system).
Workaround
A VMM avoids this erratum if it does not map any part of the EPC (Enclave Page
Cache) to the guests APIC-access address; an operating system avoids this erratum
if it does not attempt indirect enclave accesses to the APIC.
Status
SKL061
Problem
In PAE paging mode, the CR3[11:5] are used to locate the page-directory-pointer
table. Due to this erratum, those bits of CR3 are not compared to
IA32_RTIT_CR3_MATCH (MSR 572H) when IA32_RTIT_CTL.CR3Filter (MSR 570H, bit
7) is set.
Implication
Workaround
None identified.
Status
SKL062
Intel PT PacketEn Change on C-state Wake May Not Generate a TIP Packet
Problem
A TIP.PGE (Target IP, Packet Generation Enabled) or TIP.PGD (Target IP, Packet
Generation Disabled) packet may not be generated if Intel PT (Processor Trace)
PacketEn changes after IA32_RTIT_STATUS.FilterEn (MSR 571H, bit 0) is reevaluated on wakeup from C6 or deeper sleep state.
Implication
When code enters or exits an IP filter region without a taken branch, tracing may
begin or cease without proper indication in the trace output. This may affect trace
decoder behavior.
Workaround
Status
SKL063
Problem
Implication
When this erratum occurs, a graphics driver restart may lead to system instability.
Such a restart may occur when upgrading the graphics driver.
Workaround
Status
SKL064
Problem
38
Specification Update
Errata
unmasked exception.
Implication
Workaround
None identified. Software should use the FDP value saved by the listed instructions
only when the most recent non-control x87 instruction incurred an unmasked
exception.
Status
SKL065
Problem
Implication
Platforms attempting to run PECI above 1 MHz may not behave as expected.
Workaround
Status
SKL066
Processor Graphics IOMMU Unit May Not Mask DMA Remapping Faults
Problem
Intel Virtualization Technology for Directed I/O specification specifies setting the
FPD (Fault Processing Disable) field in the context (or extended-context) entry of
IOMMU to mask recording of qualified DMA remapping faults for DMA requests
processed through that context entry. Due to this erratum, the IOMMU unit for
Processor Graphics device may record DMA remapping faults from Processor Graphics
device (Bus: 0; Device: 2; Function: 0) even when the FPD field is set to 1.
Implication
Software may continue to observe DMA remapping faults recorded in the IOMMU
Fault Recording Register even after setting the FPD field.
Workaround
None identified. Software may mask the fault reporting event by setting the IM
(Interrupt Mask) field in the IOMMU Fault Event Control register (Offset 038H in
GFXVTBAR).
Status
SKL067
Processor With Intel SGX Support May Hang During S3 Wake or Power-On
Reset
Problem
Processors that support Intel SGX (Intel Software Guard Extensions) may experience
hangs when waking from S3 (Standby) system sleep state or during a power-on
reset. This erratum may occur even if the Intel SGX feature is not enabled.
Implication
Due to this erratum, the system may not wake after entering standby sleep state or
may not start up after a power-on reset
Workaround
It is possible for the BIOS to contain a workaround for this erratum. For systems that
do not power gate Vcc Sustain, if the workaround detects this erratum, support for
Intel SGX will be removed until platform power is disconnected and reapplied.
Status
Specification Update
39
Errata
SKL068
Problem
After a reset or S3/S4 exit the processor may operate at a lower than expected
frequency.
Implication
When this erratum occurs, the processor may be unable to adequately support audio
playback resulting in several seconds of audio glitches.
Workaround
Status
SKL069
Problem
Intel PT (Intel Processor Trace) CYC (Cycle Count) threshold is configured through
CYCThresh field in bits [22:19] of IA32_RTIT_CTL MSR (570H). A value of 13 is
advertised as supported by CPUID (leaf 14H, sub-lead 1H). Due to this erratum, if
CYCThresh is set to 13 then the CYC threshold will be 0 cycles instead of 4096 (2131) cycles.
Implication
CYC packets may be issued in higher rate than expected if threshold value of 13 is
used.
Workaround
None identified. Software should not use value of 13 for CYC threshold.
Status
SKL070
Exx. Intel PT May Drop Some Timing Packets After Entering Thread
Problem
Intel PT (Intel Processor Trace) may temporarily stop sending MTC (Mini Time
Counter) and CYC (Cycle) packets after entering thread C3 state. MTC and CYC
packets may be missing in up to 1KB of trace output after entering thread C3.
Implication
Some Intel PT timing packets may temporarily not be sent after thread C3 is entered.
Workaround
Status
SKL071
Problem
Implication
VDPPS with YMM registers may not produce the expected result.
Workaround
Status
SKL072
Problem
40
Specification Update
Errata
Implication
Workaround
Status
SKL073
Problem
HDC (Hardware Duty Cycling) will not put the physical package into the forced idle
state while any logical processor is in VMX non-root operation and the activate VMXpreemption timer VM-execution control is 1.
Implication
HDC will not provide the desired power reduction when the VMX-preemption timer is
active in VMX non-root operation.
Workaround
None identified.
Status
SKL074
Problem
Certain processors should be configured with a TDP (Thermal Design Power) limit of
54 or 51 watts. Due to this erratum, these processors may be incorrectly configured
at 65 W TDP. The following processors are affected by this erratum: Intel Core i3
Processor Series, Celeron and Pentium (Dual-Core With GT1/GT2). A processor
that reports a value of 0x208 in TDP_POWER_OF_SKU field in MSR
PACKAGE_POWER_SKU (MSR 614H [14:0]) are affected by this erratum.
Implication
Processors affected by this erratum may spend more time in turbo and thus may
experience unexpected thermal throttling events.
Workaround
Status
SKL075
Display Flicker May Occur When Both VT-d And FBC Are Enabled
Problem
Display flickering may occur when both FBC (Frame Buffer Compression) and VT-d
(Intel Virtualization Technology for Directed I/O) are enabled and in use by the
display controller.
Implication
Workaround
It is possible for the graphics driver to contain a workaround for this erratum. This
workaround will disable FBC.
Status
SKL076
System May Hang When Using Intel TXT And Memory That Supports
Address Mirroring
Problem
Within platforms that utilize memory that supports address mirroring, processors that
utilize Intel TXT (Intel Trusted Execution Technology) measured launch environment
may fail to boot and hang.
Implication
Workaround
A BIOS code change has been identified and may be implemented as a workaround
for this erratum.
Specification Update
41
Errata
Status
SKL077
Problem
Implication
Display artifacts may be seen or the system may log a machine check error and reset
or hang when resuming from C9.
Workaround
It is possible for the BIOS and Intel Graphics Driver 15.40.11.4308 or later to
contain a workaround for this erratum.
Status
SKL078
Problem
Integrated Audio Codec may lose power when LPSP (Low-Power Single Pipe) mode is
enabled for an eDP* (embedded DisplayPort) or HDMI ports. Platforms with Intel
SST (Intel Smart Sound Technology) enabled are not affected.
Implication
The Audio Bus driver may attempt to do enumeration of Codecs when eDP or HDMI
port enters LPSP mode, due to this erratum, the Integrated Audio Codec will not be
detected and audio maybe be lost.
Workaround
Intel Graphics Driver 15.40.11.4312 or later will prevent the Integrated Audio
Codec from losing power when LPSP mode is enabled.
Status
SKL079
Problem
Implication
Workaround
Status
SKL080
Problem
When the APIC timer is configured to TSC Deadline Mode, a timer interrupt may
occur before the expected deadline if any of IA32_TSC_DEADLINE MSR (6E0H) bits
[63:56] are set.
Implication
Workaround
42
Specification Update
Errata
Status
SKL081
Problem
During platform initialization, the processors eDRAM interface may fail to complete
its training and configuration sequence.
Implication
When this erratum occurs, a processor that supports eDRAM may not initialize
properly.
Workaround
Status
SKL082
Problem
Implication
When this issue occurs, the system may cause unpredictable system behavior
Workaround
Status
SKL083
Problem
When the processor exits Package C6 or deeper, it may hang, generate a machine
check exception with an Internal Unclassified error reported in IA32_MCi_STATUS
with MCACOD (bits[15:0]) equal to 0x402 and MSCOD (31:16)] equal to 0x94yy
(where y can be any value), or exhibit unpredictable system behavior.
Implication
Workaround
Status
SKL084
Problem
The U-processor with GT3 and TDP of 28W may report an incorrect value of 1926H in
DID2 (Processor Graphics Device ID) (Bus 0, Device 2, Function 0; offset 2h; bits
[15:0]) register. This value should be 1927H.
Implication
Workaround
Status
SKL085
Problem
When entering S3/S4/S5 state, it may hang and generate a machine check with an
Internal Unclassified error reported in IA32_MCi_STATUS with MCACOD (bits[15:0])
equal to 0x402 and MSCOD (31:16)] equal to 0x77yy (where y can be any value).
Implication
Specification Update
43
Errata
Workaround
Status
SKL086
Problem
Implication
Workaround
Intel Graphics Driver version 15.40.12.4326 or later contains a workaround for this
erratum.
Status
SKL087
x87 FPU Data Pointer Updated Only for Instructions That Incur Unmasked
Exceptions
Problem
The x87 FPU data pointer is the pointer to data (operand) for the last x87 non-control
instruction executed. Due to this erratum, it contains the pointer to data (operand)
for the last x87 non-control instruction that incurred an unmasked x87 exception.
This behavior should hold only if CPUID.(EAX=07H,EXC=0H):EBX.
FDP_EXCPTN_ONLY [bit 6] is enumerated as 1, which is not the case.
Implication
If the most recent x87 non-control instruction did not incur an unmasked x87
exception, software that then examines the x87 FPU data pointer will see an incorrect
value.
Workaround
It is possible for the BIOS to contain a workaround for this erratum. This workaround
will cause CPUID.(EAX=07H,EXC=0H):EBX. FDP_EXCPTN_ONLY [bit 6] to be
enumerated as 1. Software should examine the x87 FPU data pointer only when the
most recent x87 non-control instruction incurred an unmasked x87 exception.
Status
SKL088
Problem
BTS (Branch Trace Store) and BTM (Branch Trace Message) send branch records to
the Debug Store management area and system bus respectively. The Branch
Predicted bit (bit 4 of eighth byte in BTS/BTM records) should report whether the
most recent branch was predicted correctly. Due to this erratum, the Branch
Predicted bit may be incorrect.
Implication
BTS and BTM cannot be used to determine the accuracy of branch prediction.
Workaround
None identified.
Status
SKL089
Problem
Implication
44
Specification Update
Errata
undercount.
Workaround
None identified.
Status
SKL090
Problem
Implication
Workaround
None identified.
Status
SKL091
Problem
Implication
Workaround
None identified.
Status
SKL092
Problem
Implication
Workaround
Status
SKL093
Problem
Execution of REP MOVS may incorrectly change [R/E]CX, [R/E]SI, and/or [R/E]DI
register values during instruction execution. This erratum occurs only if the
execution would set an accessed or dirty flag in a paging structure to which EPT does
not allow writes.
Implication
Incorrect changes to RCX, RSI, and/or RDI may lead to a block-copy operation with
Specification Update
45
Errata
Status
SKL094
Ring Frequency Changes May Cause a Machine Check And System Hang
Problem
Ring frequency changes may lead to a system hang with the processor logging a
machine check in IA32_MCi_STATUS where the MCACOD (bits[15:0]) value is 0x0402
and the MSCOD (bits[31:16]) value is 0x77yy (yy is any 8-bit value).
Implication
When this erratum occurs, the system will log a machine check and hang. Power
management activity, including system power state changes, can result in ring
frequency changes that may trigger this erratum.
Workaround
Status
SKL095
Problem
Implication
Workaround
None identified. Software may use the following model-specific events that provide
related performance monitoring data: OFFCORE_REQUESTS (all sub-events),
L2_TRANS.L2_WB and L2_RQSTS.PF_MISS.
Status
SKL096
Problem
Using the BIOS hardware core disable facility may cause the processor to hang when
it attempts to enter or exit Package C6.
Implication
When this erratum occurs, attempting to enter or exit Package C6 state will hang the
system.
Workaround
Status
SKL097
Instructions Fetch #GP After RSM During Inter PT May Push Incorrect
RFLAGS Value on Stack
Problem
Implication
Software that relies on RFLAGS value pushed on the stack under the conditions
described may not work properly.
46
Specification Update
Errata
Workaround
None identified.
Status
Specification Update
47
Specification Changes
Specification Changes
There are no Specification Changes in this Specification Update revision.
48
Specification Update
Specification Clarifications
Specification Clarifications
There are no specification clarifications in this Specification Update revision.
Specification Update
49
Documentation Changes
Documentation Changes
There are no documentation changes in this Specification Update revision.
50
Specification Update