Ovonic Unified Memory

OVONIC INOFIED MEMORY (OUM)
A Seminar Report
On
OVONIC UNIFIED
MEMORY (OUM)
Submitted by
Mr. Nishant K Patel (09EC082)
Internal Guide:
Asst. Prof. Jignesh Patoliya
V.T.Patel Department of
Electronics & Communication Engineering
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CHAROTAR UNIVERSITY OF SCIENCE & TECHNOLOGY
CERTIFICATE
This is to certify that the Seminar entitled “OVONIC UNIFIED MEMORY

(OUM)” is a bonafied report of the work carried out by Mr. Nishant Patel
(09EC082) under the guidance and supervision for the submission of 2nd semester to
Charotar Institute of Technology -Changa. , Gujarat.
To the best of my knowledge and belief, this work embodies the work of candidate
themselves, has duly been completed, fulfills the requirement of the ordinance
relating to the Bachelor degree of the university and is up to the standard in respect of
content, presentation and language for being referred to the examiner.
Guided By: Head of Dept.

Asst. Prof. Jignesh Patoliya Prof. Jaymin Bhalani
ELECTRONICS AND
COMMUNICATION
ENGINEERING
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ACKNOWLEDGEMENT
At this stage of my seminar, I take this opportunity to express my heartiest

gratitude and thanks to my guide Asst. Prof. Jignesh Patoliya, for his valuable
guidance and encouragement during each stage of my work. I would especially thank
him, as they have helped me lot to present my seminar related work in a much better
way. He always listens to problems patiently and suggests the best possible solution
and especially thanks for his extensive comments on thesis write up.
Starting off, I am indebted to our Head of Department Prof. Jaymin Bhalani
who also helped me to present my seminar related work in a much better way, and
also as a Head of Department who gave me an opportunity to elect an appropriate
subject for my seminar. I would especially thank him, as he helps me while facing
problems and suggests the best possible solutions. He is very supportive and heartily
acknowledged for providing laboratory support.
Last but not the least; I would like to thank my seniors, friends, and
especially my parents for their support and acknowledgement.
Mr. Nishant Patel

(09EC082)
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ABSTRACT
Nowadays, digital memories are used in each and every fields of

day-to-day life. Semiconductors form the fundamental building blocks of the
modern electronic world providing the brains and the memory of products all
around us from washing machines to super computers. But now we are entering an
era of material limited scaling. Continuous scaling has required the introduction of
new materials.
Current memory technologies have a lot of limitations. The new

memory technologies have got all the good attributes for an ideal memory. Among
them Ovonic Unified Memory (OUM) is the most promising one. OUM is a type
of nonvolatile memory, which uses chalcogenide materials for storage of binary
data. The term “chalcogen” refers to the Group VI elements of the periodic table.
“Chalcogenide” refers to alloys containing at least one of these elements such as
the alloy of germanium, antimony, and tellurium, which is used as the storage
element in OUM. Electrical energy (heat) is used to convert the material between
crystalline (conductive) and amorphous (resistive) phases and the resistive
property of these phases is used to represent 0s and 1s.
To write data into the cell, the chalcogenide is heated past its melting
point and then rapidly cooled to make it amorphous. To make it crystalline, it is
heated to just below its melting point and held there for approximately 50ns,
giving the atoms time to position themselves in their crystal locations. Once
programmed, the memory state of the cell is determined by reading its resistance.
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INDEX
CHAPTER 1 INTRODUCTION…………………………………………………. 1
CHAPTER 2
2.1 REVIEW OF MEMORY BASICS…………………………... 2
2.2 MEMEORY DEVICE CHARACTERISTICS
2.2.1 COST………………………………………………… 3
2.2.2 ACCESS TIME AND ACCESS RATE…………….. 3
2.2.3 ACCESSS MODE RANDOM AND SERIAL……… 4
2.2.4 ALTERABILITY-ROM……………………………... 5
2.2.5 PERMANANCE OF STORAGE…………………… 6
2.2.6 CYCLE TIME AND DATA TRANSFER RATE…… 7
CHAPTER 3
3.1 EMERGING MEMORY TECHNOLOGY…………………… 8
3.2 FUNDAMENTALS IDEAS OF EMERGING MEMORIES… 8
CHAPTER 4
4.1 OVONIC UNIFIED MEMORY …………………………… 10
4.2 OUM ATTRIBUTES………………………………………….. 13
4.3 OUM ARCHITECTURE ……………………………………... 14
CHAPTER 5
5.1 BASIC DEVICE OPERATION...…………………………..... 15
5.2 TECHNOLOGY AND PERFORMANCE…………………… 16
5.3 I-V CHARACTERISTICS…….............................................. 16
5.4 R-I CHARACTERISTICS……….............................................. 17
CHAPTER 6
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6.1 INTEGRATION WITH CMOS………...................................... 19

6.2 CIRCUIT DEMONSTRATION………………………………. 23
CHAPTER 7 ADVANTAGES ………………....................................................... 28
CHAPTER 8
8.1 ABOUT CHALCOGENIDE ALLOY………………………….29
8.2 COMPARISION OF AMORPHOUS AND CRYSTALLINE
STATE......................................................................................... 30
CONCLUSION…………………………………………………………………… 31
REFERENCE…………………………………………………………………….. 32
CHAPTER 1
INTRODUCTION
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We are now living in a world driven by various electronic equipments.

Semiconductors form the fundamental building blocks of the modern electronic
world providing the brains and the memory of products all around us from
washing machines to super computers. Semi conductors consist of array of
transistors with each transistor being a simple switch between electrical 0 and 1.
Now often bundled together in there 10’s of millions they form highly complex,
intelligent, reliable semiconductor chips, which are small and cheap enough for
proliferation into products all around us.
Identification of new materials has been, and still is, the primary means
in the development of next generation semiconductors. For the past 30 years,
relentless scaling of CMOS IC technology to smaller dimensions has enabled the
continual introduction of complex microelectronics system functions. However,
this trend is not likely to continue indefinitely beyond the semiconductor
technology roadmap. As silicon technology approaches its material limit, and as
we reach the end of the roadmap, an understanding of emerging research devices
will be of foremost importance in the identification of new materials to address the
corresponding technological requirements.
If scaling is to continue to and below the 65nm node, alternatives to

CMOS designs will be needed to provide a path to device scaling beyond the end
of the roadmap. However, these emerging research technologies will be faced with
an uphill technology challenge. For digital applications, these challenges include
exponentially increasing the leakage current (gate, channel, and source/drain
junctions), short channel effects, etc. while for analogue or RF applications,
among the challenges are sustained linearity, low noise figure, power added
efficiency and transistor matching. One of the fundamental approaches to manage
this challenge is using new materials to build the next generation transistors.
CHAPTER 2
2.1 REVIEW OF MEMORY BASICS
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Every computer system contains a variety of devices to store the instructions

and data required for its operation. These storage devices plus the algorithms needed
to control or manage the stored information constitute the memory system of the
computer. In general, it is desirable that processors should have immediate and
interrupted access to memory, so the time required to transfer information between
the processor and memory should be such that the processor can operate at, close to,
its maximum speed. Unfortunately, memories that operate at speeds comparable to
processors speed are very costly. It is not feasible to employ a single memory using
just one type of technology. Instead the stored information is distributed in complex
fashion over a variety of different memory units with very different physical
characteristics.
The memory components of a computer can be subdivided into three main
groups:
1) Internal processor memory: this usually comprises of a small set of high speed
registers used as working registers for temporary storage of instructions and
data.
2) Main memory: this is a relatively large fast memory used for program and
data storage during computer operation. It is characterized by the fact that
location in the main memory can be directly accessed by the CPU instruction
set. The principal technologies used for main memory are semiconductor
integrated circuits and ferrite cores.
3) Secondary memory: this is generally much larger in capacity but also

much slower than main memory. It is used for storing system programs and
large data files and the likes which are not continually required by the CPU; it
also serves as an overflow memory when the capacity of the main memory
when the capacity of the main memory is exceeded. Information in secondary
storage is usually accessed directly via special programs that first
transfer the required information to main memory. Representative
technologies used for secondary memory are magnetic disks and tapes.
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The major objective in designing any memory is to provide adequate storage

capacity with an acceptable level of performance at a reasonable cost.
2.2 MEMORY DEVICE CHARACRERISTICS
The computer architect is faced with a bewildering variety of memory

devices to use. However; all memories are based on a relatively small number of
physical phenomena and employ relatively few organizational principles. The
characteristics and the underlying physical principles of some specific representative
technologies are also discussed.
2.2.1 Cost:
The cost of a memory unit is almost meaningfully measured by the purchase

or lease price to the user of the complete unit. The price should include not only the
cost of the information storage cells themselves but also the cost of the peripheral
equipment or access circuitry essential to the operation of the memory.
2.2.2 Access time and access rate:
The performance of a memory device is primarily determined by the rate at

which information can be read from or written into the memory. A convenient
performance measure is the average time required to read a fixed amount of
information from the memory. This is termed read access time. The write access time
is defined similarly; it is typically but not always equal to the read access time.
Access time depends on the physical characteristics of the storage medium, and also
on the type of access mechanism used. It is usually calculated from the time a read
request is received by the memory and to the time at which all the requested
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information has been made available at the memory output terminals. The access rate
of the memory is defined is the inverse of the access time.
Clearly low cost and high access rate are desirable memory characteristics;
unfortunately they appear to be largely compatible. Memory units with high access
rates are generally expensive, while low cost memory are relatively slow.
2.2.3 Access mode-random and serial:
An important property of a memory device is the order or sequence in which

information can be accessed. If locations may be accessed in any order and the access
time is independent of the location being accessed, the memory is termed as a random
access memory.
Ferrite core memory and semiconductor memory are usually of this type.
Memories where storage locations can be accessed only in a certain predetermined
sequence are called serial access memories. Magnetic tape units and magnetic bubble
memories employ serial access methods.
In a random access memory each storage location can be accessed

independently of the other locations. There is, in effect, a separate access mechanism,
or read-write, for every location. In serial memories, on the other hand, the access
mechanism is shared among different locations. It must be assigned to different
locations at different times. This is accomplished by moving the stored information;
he read write head or both. Many serial access memories operate by continually
moving the storage locations around a closed path or track. A particular location can
be accessed only when it passes the fixed read write head; thus the time required to
access a particular location depends on the relative location of the read/write head
when the access request is received.
Since every location has its own addressing mechanism, random access
memory tends to be more costly than the serial type. In serial type memory, however
the time required to bring the desired location into correspondence with a read/write
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head increases the effective access time, so access tends to be slower than the random
access. Thus the access mode employed contributes significantly to the inverse
relation between cost and access time.
Some memory devices such as magnetic disks and d rums contain large
number of independently rotating tracks. If each track has its own read-write head, the
track may be accessed randomly, although access within track in serial.
In such cases the access mode is sometimes called semi random or direct access. It
should be noted that the access
is a function of the memory technology used.
2.2.4 Alterability-ROMS:
The method used to write information into a memory may be irreversible, in

that once the information has been written, it cannot be altered while the memory is in
use,i.e.,online. Punching holes in cards in cards and printing on paper are examples of
essentially permanent storage techniques. Memories whose contents cannot be altered
online are called read only memories. A Rom is therefore a non alterable storage
device. ROMs are widely used for storing control programs such as micro programs.
ROMs whose contents can be changed are called programmable read only memories
(PROMs).
Memories in which reading or writing can be done with impunity online are
sometimes called read-write memories (RWMs) to contrast them with ROMs. All
memories used for temporary storage are RWMs.
2.2.5 Permanence of storage:
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The physical processes involved in storage are sometimes inherently

unstable, so that the stored information may be lost over a period of time unless
appropriate action is taken. There are important memory characteristics that can
destroy information:
1. Destructive read out
2. Dynamic volatility
3. Volatility
Ferrite core memories have the property that the method of reading the memory
alters, i.e., destroys, the stored information; this phenomenon is called destructive
read out (DRO). Memories in which reading does not affect the stored data are said to
have nondestructive readout (NRDO). In DRO memories, each read operation must
be followed by a write operation followed by a write operation that restores the
original state of the memory. This restoration is usually carried out by automatically
using a buffer register.
Certain memory devices have the property that a stored 1 tends to become a 0,
or vice versa, due to some physical decay processes. Over a period of time, a stored
charge tends to leak away, causing a loss of information unless the stored charge is
restored. This process of restoring is called refreshing. Memories which require
periodic refreshing are called dynamic memories, as opposed to static memories,
which require no refreshing. Most memories that using magnetic storage techniques
are static. Refreshing in dynamic memories can be carried out in the same way data is
restored in a DRO memory. The contents of every location are transferred
systematically to a buffer register and then returned, in suitably amplified form, to
their original locations.
Another physical process that can destroy the contents of a memory is the
failure of power supply. A memory is said to be volatile if the stored information can
be destroyed by a power failure. Most semiconductor memories are volatile, while
most magnetic memories are non volatile.
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2.2.6 Cycle time and data transfer rate:
The access time of a memory is defined as the time between the receipt of a
read request and the delivery of the requested information to its external output
terminals. In DRO and dynamic memories, it may not be possible to initiate another
memory access until a restore or refresh operation has been carried out. This means
that the minimum time that must elapse between the initiations of two different
accesses by the memory can be greater than the access time: this rather loosely
defined time is called the cycle time of the memory.
It is generally convenient to assume the cycle time as the time needed to

complete any read or write operation in the memory. Hence the maximum amount of
information that can be transferred to or from the memory every second is the
reciprocal of cycle time. This quantity is called the data transfer rate or band width.
CHAPTER 3
3.1 EMERGING MEMORY TECHNOLOGIES
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Many new memory technologies were introduced when it is understood that

semiconductor memory technology has to be replaced, or updated by its successor
since scaling with semiconductor memory reached its material limit. These
memory technologies are referred as ‘Next Generation Memories”. Next
Generation Memories satisfy all of the good attributes of memory. The most
important one among them is their ability to support expansion in three-
dimensional spaces. Intel, the biggest maker of computer processors, is also the
largest maker of flash-memory chips is trying to combine the processing features
and space requirements feature and several next generation memories are being
studied in this perspective. They include MRAM, FeRAM, Polymer Memory
Ovonic Unified Memory, ETOX-4BPC, NRAM etc. One or two of them will
become the mainstream.
3.2 FUNDAMENTAL IDEAS OF EMERGING

MEMORIES
The fundamental idea of all these technologies is the bistable nature possible for
of the selected material. FeRAM works on the basis of the bistable nature of the
centre atom of selected crystalline material. A voltage is applied upon the crystal,
which in turn polarizes the internal dipoles up or down. I.e. actually the difference
between these states is the difference in conductivity. Non –Linear FeRAM read
capacitor, i.e., the crystal unit placed in between two electrodes will remain in the
direction polarized (state) by the applied electric field until another field capable
of polarizing the crystal’s central atom to another state is applied.
In the case of Polymer memory data stored by changing the polarization

of the polymer between metal lines (electrodes). To activate this cell structure, a
voltage is applied between the top and bottom electrodes, modifying the organic
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material. Different voltage polarities are used to write and read the cells.
Application of an electric field to a cell lowers the polymer’s resistance, thus
increasing its ability to conduct current; the polymer maintains its state until a
field of opposite polarity is applied to raise its resistance back to its original level.
The different conductivity States represent bits of information.
In the case of NROM memory ONO stacks are used to store charges at
specific locations. This requires a charge pump for producing the charges required
for writing into the memory cell. Here charge is stored at the ON junctions.
Phase change memory also called Ovonic unified memory (OUM),
is based on rapid reversible phase change effect in materials under the influence of
electric current pulses. The OUM uses the reversible structural phase-change in
thin-film material (e.g., chalcogenide) as the data storage mechanism. The small
volume of active media acts as a programmable resistor between a high and low
resistance with > 40X dynamic range. Ones and zeros are represented by
crystalline versus amorphous phase states of active material. Phase states are
programmed by the application of a current pulse through a
MOSFET, which drives the memory cell into a high or low resistance state,
depending on current magnitude. Measuring resistance changes in the cell
performs the function of reading data. OUM cells can be programmed to
intermediate resistance values; e.g., for multistate data storage.
MRAMs are based on the magnetoresistive effects in magnetic materials

and structures that exhibit a resistance change when an external magnetic field is
applied. In the MRAM, data are stored by applying magnetic fields that cause
magnetic materials to be magnetized into one of two possible magnetic states.
Measuring resistance changes in the cell compared to a reference performs reading
data. Passing currents nearby or through the magnetic structure creates the
magnetic fields applied to each cell.
CHAPTER 4
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4.1 OVONIC UNIFIED MEMORY
Among the above-mentioned non-volatile Memories, Ovonic Unified

Memory is the most promising one. “Ovonic Unified Memory” is the registered
name for the non-volatile memory based on the material called chalcogenide.
The term “chalcogen” refers to the Group VI elements of the periodic

table. “Chalcogenide” refers to alloys containing at least one of these elements
such as the alloy of germanium, antimony, and tellurium discussed here. Energy
Conversion Devices, Inc. has used this particular alloy to develop a phase-change
memory technology used in commercially available rewriteable CD and DVD
disks. This phase change technology uses a thermally activated, rapid, reversible
change in the structure of the alloy to store data. Since the binary information is
represented by two different phases of the material it is inherently non-volatile,
requiring no energy to keep the material in either of its two stable structural states.
The two structural states of the chalcogenide alloy, as shown in Figure 1,

are an amorphous state and a polycrystalline state. Relative to the amorphous
state, the polycrystalline state shows a dramatic increase in free electron density,
similar to a metal. This difference in free electron density gives rise to a difference
in reflectivity and resistivity. In the case of the re-writeable CD and DVD disk
technology, a laser is used to heat the material to change states. Directing a low-
power laser at the material and detecting the difference in reflectivity between the
two phases read the state of the memory.
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FIGURE 1
Ovonyx, Inc., under license from Energy Conversion Devices, Inc., is

working with several commercial partners to develop a solid-state nonvolatile
memory technology using the chalcogenide phase change material. To implement
a memory the device is incorporated as a two terminal resistor element with
standard CMOS processing. Resistive heating is used to change the phase of the
chalcogenide material. Depending upon the temperature profile applied, the
material is either melted by taking it above the melting temperature (Tm) to form
the amorphous state, or crystallized by holding it at a lower temperature (Tx) for a
slightly longer period of time, as shown in Figure 2. The time needed to program
either state is = 400ns. Multiple resistance states between these two extremes have
been demonstrated, enabling multi-bit storage per memory cell. However, current
development activities are focused on single-bit applications. Once programmed,
the memory state of the cell is determined by reading its resistance.
Since the data in a chalcogenide memory element is stored as a structural
phase rather than an electrical charge or state, it is expected to be impervious to
ionizing radiation effects. This inherent radiation tolerance of the chalcogenide
material and demonstrated write speeds more than 1000 times faster than
commercially available nonvolatile memories make it attractive for space based
applications.
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FIGURE 2
A radiation hardened semiconductor technology incorporating

chalcogenide based memory elements will address both critical and enabling
space system needs, including standalone memory modules and embedded cores
for microprocessors and ASICs. Previously, BAE SYSTEMS and Ovonyx have
reported on the results of discrete memory elements fabricated in BAE
SYSTEMS’ Manassas, Virginia facility. These devices were manufactured using
standard semiconductor process equipment to sputter and etch the chalcogenide
material. While built in the same line used to fabricate radiation-hardened CMOS
products, these memory elements were not yet integrated with transistors. They
were discrete two-terminal programmable resistors, requiring approximately 0.6
mA to set the device into a low resistance state, and 1.3 mA to reset it to the high
resistance state. One billion (1E9) write cycles between these two states were
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demonstrated. Reading the state of the device is non-destructive and has no impact
on device wear out (unlimited read cycles).
4.2 OUM ATTRIBUTES
• Non volatile in nature

• High density ensures large storage of data within a small area
• Non destructive read:-ensures that the data is not corrupted during a read
cycle.
• Uses very low voltage and power from a single source.
• Write/erase cycles of 10e12 are demonstrated
• Poly crystalline
• This technology offers the potential of easy addition of non volatile memory to
a standard CMOS process.
• This is a highly scalable memory
• Low cost implementation is expected.
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4.3 OUM ARCHITECTURE
FIGURE 3 OUM ARCHITECTURE
A memory cell consists of a top electrode, a layer of the chalcogenide,

and a resistive heating element. The base of the heater is connected to a diode. As
with MRAM, reading the micrometer-sized cell is done by measuring its
resistance. But unlike MRAM the resistance change is very large-more than a
factor of 100. Thermal insulators are also attached to the memory structure in
order to avoid data lose due to destruction of material at high temperatures.
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To write data into the cell, the chalcogenide is heated past its melting point
and then rapidly cooled to make it amorphous. To make it crystalline, it is heated
to just below its melting point and held there for approximately 50ns, giving the
atoms time to position themselves in their crystal locations.
CHAPTER 5
5.1 BASIC DEVICE OPERATION
FIGURE 4 TEMPERATURE VS. TIME PLOT
The basic device operation can be explained from the temperature versus
time graph. During the amorphizing reset pulse, the temperature of the programmed
volume of phase change material exceeds the melting point which eliminates the poly
crystalline order in the material. When the reset pulse is terminated the device
quenches to freeze in the disordered structural state. The quench time is determined
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by the thermal environment of the device and the fall time of the pulse. The
crystallizing set pulse is of lower amplitude and of sufficient duration to maintain the
device temperature in the rapid crystallization range for a time sufficient for crystal
growth.
5.2 TECHNOLOGY AND PERFORMANCE
The figure below shows device resistance versus write pulse width. The reset
resistance saturates when the pulse width is long enough to achieve melting of the
phase change material. The set pulse adequately crystallizes the bit in 50 ns with a
RESET/SET resistance ratio of greater than 100.
FIGURE 5 RESISTANCE VS PULSE WIDTH PLOT
5.3 I-V CHARACTERISTICS
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FIGURE 6 I-V CHARECTERISTICS
The figure above shows I-V characteristics of the OUM device. At low voltages, the
device exhibits either a low resistance (~1k) or high resistance (>100k), depending on
its programmed state. This is the read region of operation. To program the device, a
pulse of sufficient voltage is applied to drive the device into a high conduction
“dynamic on state”. For a reset device, this requires a voltage greater than Vth.
Vth is the device design parameter and for current memory application is
chosen to be in the range of 0.5 to 0.9 V. to avoid read disturb, the device read region
as shown in the figure, is well below Vth and also below the reset regime.
The device is programmed while it is in the dynamic on state. The final programmed
state of the device is determined by the current amplitude and the pulse duration in
the dynamic on state. The reciprocal slope of the I-V curve in the dynamic on state is
the series device resistance.
5.4 R-I CHARACTERISTICS
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FIGURE 7 R-I CHARACTERISTICS
The above figure shows the device read resistance resulting from
application of the programming current pulse amplitude. Starting in the set condition,
moving from left to right, the device continues to remain in SET state as the
amplitude is increased. Further increase in the pulse amplitude begins to reset the
device with still further increase resetting the device to a standard amorphous
resistance. Beginning again with a device initially in the RESET state, low amplitude
pulses at voltages less than Vth do not set the device. Once Vth is surpassed, the
device switches to the dynamic on state and programmed resistance is dramatically
reduced as crystallization of the material is achieved. Further increase in
programming current further crystallizes the material, which drops the resistance to a
minimum value. As the programming pulse amplitude is increased further, resetting
again is exhibited as in the case above. Devices can be safely reset above the
saturation point for margin. Importantly, the right side of the curve exhibits direct
overwrite capability, where a particular resistance value can be obtained from a
programming pulse, irrespective of the prior state of the material. The slope of the
right side of the curve is the device design parameter and can be adjusted to enable a
multistate memory cell.
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CHAPTER 6
6.1 INTEGRATION WITH CMOS
Under contract to the Space Vehicles Directorate of the Air Force Research
Laboratory (AFRL), BAE SYSTEMS and Ovonyx began the current program in
August of 2001 to integrate the chalcogenide-based memory element into a
radiation-hardened CMOS process. The initial goal of this effort was to develop the
processes necessary to connect the memory element to CMOS transistors and metal
wiring, without degrading the operation of either the memory elements or the
transistors. It also was desired to maximize the potential memory density of the
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technology by placing the memory element directly above the transistors and below
the first level of metal as shown in a simplified diagram in Figure.
FIGURE 8 INTEGRATION WITH CMOS
To accomplish this process integration task, it was necessary to design a

test chip with appropriate structures. This vehicle was called the Access Device
Test Chip (ADTC) since each memory cell requires an access device (transistor)
in addition to the chalcogenide memory element. Such a memory cell, comprised
of one access transistor and one chalcogenide resistor, is herein referred to as a
1T1R cell. The ADTC included 272 macros, each with 2 columns of 10 probe
pads. Of these, 163 macros were borrowed from existing BAE SYSTEMS’ test
structures and used to verify normal transistor operation. There were 109 new
macros designed to address the memory element features. These included sheet
resistance and contact resistance measurement structures, discrete memory
elements of various sizes and configurations, and two 16-bit 1T1R memory arrays.
Short loop (partial flow) experiments were processed using subsets of

the full ADTC mask set. These experiments were used to optimize the process
steps used to connect the bottom electrode of the memory element to underlying
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tungsten studs and to connect an additional tungsten stud level between Metal 1
and the top electrode of the memory element. A full flow experiment was then
processed to demonstrate integrated transistors and memory elements.
FIGURE 8 VI CHARACTERISTICS
Figure shows the I-V characteristic for a 1T1R memory cell successfully
fabricated using the ADTC vehicle. The voltage is applied to one of the two
terminals of the chalcogenide resistor, and the access transistor (biased on) is
between the other resistor terminal and ground. The high resistance amorphous
material shows very little current below a threshold voltage (VT) of 1.2V. In this
same region the low resistance polycrystalline material shows a significantly
higher current. The state of the memory cell is read using the difference in I-V
characteristics below VT. Above VT, both materials display identical I-V
characteristics, with a dynamic resistance (RDYNAMIC) of ˜1k. In itself, this
transition to a low resistance electrical state does not change the structural phase
of the material. However, it does allow for heating of the material to program it to
the low resistance state (1) or the high resistance state (0). Extrapolation of the
portion of the I-V curve that is above VT to the X-axis yields a point referred to as
a holding voltage (VH). The applied voltage must be reduced below VH to exit
the programming mode.
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FIGURE 9 RESISTANCE VS CURRENT PLOT
Figure shows the operation of a 1T1R memory, again with the access transistor
biased on. The plotted resistance values were measured below VT, while the
current used to program these resistances were measured above V T. Similar to the
previously demonstrated stand-alone memory elements, these devices require
approximately 0.6 mA to set to the low resistance state (RSET) and 1.2 mA to reset
to the high resistance state (RRESET). The circuit was verified to be electrically open
with the access transistor biased off.
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FIGURE 10 DRAIN CURRENT VS GATE VOLTAGE PLOT
Figure 6 shows the total dose (X-ray) response of N-channel transistors processed
through the chalcogenide memory flow. The small threshold voltage shift is
typical of BAE SYSTEMS’ standard radiation-hardened transistor processing. All
other measured parameters (drive current, threshold voltage, electrical channel
length, contact resistance, etc.) were also typical of product manufactured without
the memory element.
6.2 CIRCUIT DEMONSTRATION
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In order to test the behavior of chalcogenide cells as circuit elements, the

Chalcogenide Technology Characterization Vehicle (CTCV) was developed. The
CTCV contains a variety of memory arrays with different architecture, circuit, and
layout variations. Key goals in the design of the CTCV were: 1) to make the read
and write circuits robust with respect to potential variations in cell electrical
characteristics; 2) to test the effect of the memory cell layout on performance; and
3) to maximize the amount of useful data obtained that could later be used for
product design. The CTCV was sub-divided into four chiplets, each containing
variations of 1T1R cell memory arrays and various standalone sub circuits.
Standalone copies of the array sub circuits were included in each chiplet for
process monitoring and read/write current experiments.
FIGURE 11 CHIPSET
A diagram of one of the chiplets is shown in Figure 11. The arrays all
contain 64k 1T1R cells, arranged as 256 rows by 256 columns. This is large enough
to make meaningful analyses of parasitic capacitance effects, while still permitting
four variations of the array to be placed on each chiplet. The primary differences
between arrays consist of the type of sense amp (single-ended or differential) and
variations in the location and number of contacts in the memory cell.
09EC082 Page 30
The data in the single-ended arrays is formatted as 4096 16-bit words

(64k bits), and in the differential arrays as 4096 8-bit words (32k bits). The 256
columns are divided into 16 groups of 16. One sense amplifier services each group,
and the 16 columns in each group are selected one at a time based on the four most
significant address bits. In simulations, stray capacitance was predicted to cause
excessive read settling time when more than 16 columns were connected to a sense
amp. Each column has its own write current river, which also performs the column
select function for write operations.
The single-ended sense amplifier reads the current drawn by a single cell
when a voltage is applied to it. The differential amplifier measures the currents in
two selected cells that have previously been written with complementary data, and
senses the difference in current between them. This cuts the available memory size
in half, but increases noise margin and sensitivity. In both the single-ended and
differential sense amplifiers, a voltage limiting circuit prevents the chalcogenide
element voltage from exceeding VT, so that the cell is not inadvertently re-
programmed.
On one chiplet, there are two arrays designed without sense amplifiers.
Instead, the selected column outputs are routed directly to the 16 I/O pins where
the data outputs would normally be connected. This enables direct analog
measurements to be made on a selected cell. A third array on this chiplet has both
the column select switches and the sense amplifiers deleted. Eight of the 256
columns are brought out to I/O pins. This enables further analog measurements to
be made, without an intervening column select transistor.
“Conservative” and “aggressive” layout versions of the chalcogenide

cell were made. The conservative cell is larger, and has four contacts to bring
current through to the bottom and top electrodes of the memory cell. The
aggressive cell contains only two contacts per electrode, reducing its size. The
pitch of the larger cell was used to establish row and column spacing in all arrays.
The aggressive cell could thus be easily substituted for the conservative cell. Short
wires were added to the smaller cell to map its connection points to those of the
09EC082 Page 31
larger. This permitted testing both cells in one array layout without requiring
significant additional layout labor.
A final variation in the cell design involved contact spacing. The

contacts on the bottom electrode were moved to be either closer to or farther away
from the chalcogenide "pore." This allows assessment of the effect of contact
spacing on the thermal and electrical characteristics of the chalcogenide pore.
Process monitoring structures were included on each chiplet to aid in

calibration of memory array test data. These consist of a standalone replica of
each of the Write and Read (single-ended) circuits, a CMOS inverter, and a 1T1R
cell. The outputs of each of these circuits were brought out to permit measurement
of currents versus bias voltages.
Pins were provided on the CTCV for external bias voltage inputs to vary
the read and write current levels. The standalone copies of the read/write circuits
are provided with all key nodes brought out to pins. These replica circuits permit
the read and write currents to be programmed by varying the bias voltages. This
allows more in-depth characterization to be performed in advance of designing a
product. In an actual product, on-chip reference circuits would generate bias
voltages. In the write circuit, a PFET driver is connected to each column, and is
normally turned off by setting its gate bias to VDD. When a write is to occur, the
selected driver’s gate is switched to one of two external bias voltages for the
required write pulse time. The bias voltages can be calibrated to set the write drive
currents to the levels needed to reliably write a one or a zero. The data inputs
determine which bias voltage is applied to each write driver.
For the read circuit, several cell resistance-sensing schemes were

investigated during CTCV development. The adopted scheme applies a controlled
voltage to the cell to be read, and the resulting current is measured. Care is taken
not to exceed VT during a read cycle. The sense amplifier reflects the read current
into a programmable NFET load, thus generating a high (1) or low (0) output. The
gate bias of all sense amplifier loads can be varied in parallel to change the current
level at which the output voltage switches. The bias levels are calibrated via a
09EC082 Page 32
standalone copy of the read circuit that has all key nodes brought out to pins. The
NFET load's output is buffered by a string of CMOS inverters to provide full
CMOS logic voltage swing, and then routed to the correct data output I/O pad
driver.
When a read circuit supplies a current to a selected cell, the cell's

corresponding column charges up toward the steady state read voltage. The
column voltage waveform is affected by the programmed resistance and internal
capacitances of each of the cells in the column, and thus is pattern dependent. The
combined charge from all of the column's cells during this charging process may
travel into the sense amplifier input, momentarily causing it to experience a
transient, which could prevent the accessed cells’ data from being read correctly.
To minimize this effect, each column is discharged after a write, and recharged
before a read.
Transistor parametric and discrete memory element test structures were

tested on the CTCV lot at the wafer level. These tests served two purposes. The
first goal was to confirm that the extra processing steps involved in inserting the
chalcogenide flow had no effect on the base CMOS technology. No statistical
differences in transistor parametric values were noted between these wafers and
standard 0.5µm RHCMOS product.
The second goal of wafer test was to measure the set, reset and dynamic
programming resistances (RSET, RRESET and RDYNAMIC), threshold and holding
voltages (VT and VH), and required programming currents (ISET and IRESET) of
stand-alone, two terminal chalcogenide memory elements. These values were used
to set the operating points of the write driver circuits and the bias point of the
sense amp.
To allow debug of the CTCV module test setup in parallel with the wafer
test effort, one wafer was selected and diced to remove the CTCV die. Five die of
one of the four chiplets, (chip 1) were sent ahead through the packaging process.
Chip 1 has four different array configurations, two 64 kbit, single ended sense
amp arrays and two 32 kbit, differential sense amp arrays. Two of the arrays were
09EC082 Page 33
constructed with the conservative cell layout and two with the aggressive cell
layout. Functional test patterns used on these send-ahead devices included all
zeros, all ones, checkerboard and checkerboard bar. The results of this testing
showed that all circuit functional blocks (control circuits, addressing, data I/O,
write 0/1, and sense amp) performed as designed. All four of the array
configurations present on the chip showed functional memory elements, i.e.,
memory cells could be programmed to zero or one and subsequently read out. As
more packaged parts become available, more exhaustive test patterns will be
employed for full characterization.
The five send-ahead devices were also used for determining the optimum
bias points of the three externally adjustable parameters: write 0 drive current,
write 1 drive current, and the sense amp switching point. An Integrated
Measurements Systems XTS-Blazer tester was used to provide stimulus and
measure response curves. A wide range of load conditions was chosen based on
the measurements performed at wafer test.
A family of drive current vs. bias voltage curves was constructed for
both on-chip programming drive circuits across various values of RDYNAMIC. These
curves validate design simulations and demonstrate adequate operating range of
each of the circuits.
Likewise, a family of switching point curves was generated at various

RSET and RRESET values using the standalone sense amp built onto each die. These
curves were used to determine the optimal sense amp DC bias point for the test
chips and demonstrated the ability of the sense amp to distinguish the 0 and 1 state
within the range of chalcogenide resistance values measured at wafer test.
CHAPTER 7
09EC082 Page 34
ADVANTAGES
• OUM uses a reversible structural phase change.

• Small active storage medium.
• Simple manufacturing process.
• Simple planar device structure.
• Low voltage single supply.
• Reduced assembly and test costs.
• Highly scalable- performance improves with scaling.
• Multistates are demonstrated.
• High temperature resistance.
• Easy integration with CMOS.
• It makes no effect on measured CMOS transistor parametric.
• Total dose response of the base technology is not affected.
CHAPTER 8
09EC082 Page 35
8.1 ABOUT CHALCOGENIDE ALLOY
Chalcogenide or phase change alloys is a ternary system of Gallium, Antimony and

Tellurium. Chemically it is Ge2Sb2Te5.
FIGURE 12 TERNARY SYSTEM
Production Process: Powders for the phase change targets are produced by
state-of –the art alloying through melting of the raw material and subsequent milling.
This achieves the defined particle size distribution. Then powders are processed to
discs through Hot Isotactic Pressing
8.2 COMPARISON OF AMORPHOUS AND

CRYSALLINE STATE
09EC082 Page 36
Amorphous Crystalline
Short range atomic order Long range atomic order

Low free electron density High free electron density
High activation energy Low activation energy
High resistivity Low resistivity
09EC082 Page 37
CONCLUSION
Unlike conventional flash memory Ovonic unified memory can be

randomly addressed. OUM cell can be written 10 trillion times when compared
with conventional flash memory. The computers using OUM would not be
subjected to critical data loss when the system hangs up or when power is abruptly
lost as are present day computers using DRAM a/o SRAM. OUM requires fewer
steps in an IC manufacturing process resulting in reduced cycle times, fewer
defects, and greater manufacturing flexibility. These properties essentially make
OUM an ideal commercial memory. Current commercial technologies do not
satisfy the density, radiation tolerance, or endurance requirements for space
applications. OUM technology offers great potential for low power operation and
radiation tolerance, which assures its compatibility in space applications. OUM
has direct applications in all products presently using solid state memory,
including computers, cell phones, graphics-3D rendering, GPS, video
conferencing, multi-media, Internet networking and interfacing, digital TV,
telecom, PDA, digital voice recorders, modems, DVD, networking (ATM),
Ethernet, and pagers. OUM offers a way to realize full system-on-a-chip
capability through integrating unified memory, linear, and logic on the same
silicon chip.
09EC082 Page 38
REFERENCE
1. www.intel.com
2. www.ovonyx.com
3. http://en.wikipedia.org/wiki/Ovonic_Unified_Memory
4. http://ovonyx.com/technology/technical-presentation.html
5. http://www.interfacebus.com/ovonics-unified-memory-oum-
ics.html
09EC082 Page 39

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OVONIC INOFIED MEMORY (OUM)

Asst. Prof. Jignesh Patoliya

CHAROTAR UNIVERSITY OF SCIENCE & TECHNOLOGY

This is to certify that the Seminar entitled “OVONIC UNIFIED MEMORY

Guided By: Head of Dept.

At this stage of my seminar, I take this opportunity to express my heartiest

Mr. Nishant Patel

Nowadays, digital memories are used in each and every fields of

Current memory technologies have a lot of limitations. The new

6.1 INTEGRATION WITH CMOS………...................................... 19

CHAPTER 7 ADVANTAGES ………………....................................................... 28

We are now living in a world driven by various electronic equipments.

If scaling is to continue to and below the 65nm node, alternatives to

2.1 REVIEW OF MEMORY BASICS

Every computer system contains a variety of devices to store the instructions

3) Secondary memory: this is generally much larger in capacity but also

The major objective in designing any memory is to provide adequate storage

2.2 MEMORY DEVICE CHARACRERISTICS

The computer architect is faced with a bewildering variety of memory

The cost of a memory unit is almost meaningfully measured by the purchase

2.2.2 Access time and access rate:

The performance of a memory device is primarily determined by the rate at

2.2.3 Access mode-random and serial:

An important property of a memory device is the order or sequence in which

In a random access memory each storage location can be accessed

The method used to write information into a memory may be irreversible, in

2.2.5 Permanence of storage:

The physical processes involved in storage are sometimes inherently

2.2.6 Cycle time and data transfer rate:

It is generally convenient to assume the cycle time as the time needed to

3.1 EMERGING MEMORY TECHNOLOGIES

Many new memory technologies were introduced when it is understood that

3.2 FUNDAMENTAL IDEAS OF EMERGING

In the case of Polymer memory data stored by changing the polarization

MRAMs are based on the magnetoresistive effects in magnetic materials

4.1 OVONIC UNIFIED MEMORY

Among the above-mentioned non-volatile Memories, Ovonic Unified

The term “chalcogen” refers to the Group VI elements of the periodic

The two structural states of the chalcogenide alloy, as shown in Figure 1,

Ovonyx, Inc., under license from Energy Conversion Devices, Inc., is

A radiation hardened semiconductor technology incorporating

4.2 OUM ATTRIBUTES

• Non volatile in nature

4.3 OUM ARCHITECTURE

FIGURE 3 OUM ARCHITECTURE

A memory cell consists of a top electrode, a layer of the chalcogenide,

5.1 BASIC DEVICE OPERATION

FIGURE 4 TEMPERATURE VS. TIME PLOT

5.2 TECHNOLOGY AND PERFORMANCE

FIGURE 5 RESISTANCE VS PULSE WIDTH PLOT

5.3 I-V CHARACTERISTICS

FIGURE 6 I-V CHARECTERISTICS

5.4 R-I CHARACTERISTICS

FIGURE 7 R-I CHARACTERISTICS

6.1 INTEGRATION WITH CMOS

FIGURE 8 INTEGRATION WITH CMOS

To accomplish this process integration task, it was necessary to design a

Short loop (partial flow) experiments were processed using subsets of

FIGURE 9 RESISTANCE VS CURRENT PLOT

FIGURE 10 DRAIN CURRENT VS GATE VOLTAGE PLOT