ATubriaI on BuiIkln SeIkTest

Part 2: Applications

HAVING -D the BIST pat- VlSHWANl D. AGRAWAL slower than the test-perclock a p
tern generation and response analysis proach. The two approaches in-
concepts in Part 1, we now focus on AT&T Bell Laboratories volve distinct hardware structures
their implementation.First we will d e CHARLES R. KlME and trade-offs.
scribethe testing of general logic;then Figure la (next page) shows a
we will briefly discuss testing a p KEWAL K. SALUJA simple test-perclockconfiguration
proaches for sbuctured logic such as University of Wisconsin, using an LFSR as a pattern genera-
ROMs, RAMS, and PUS. We refer the tor and an MISR as a response
reader back to Table2 in Part 1, which Madison compactor. Figure 1b shows a test-
containstypicalpattern generatorand perclock configuration using an
response analyzersbuctures.Here,we LFSR, an MISR, and a shift register.
concentrate almost entirely on the Concluding an overview of b * The first configuration is suitable for
LFSR and MISR structures. For these self-test (BIST) concepts a exhaustive or pseudorandom test-
sttuctures,scan is an integml part of the
practices, Part 2 covers B
ing and the second for pseudoex-
design. Note also that ROMs and haustive or pseudorandom testing.
counters can be useful as supple hardware structures, applica Notice that the pattern generator
ments or alternatives to a number of and tools. The authors LFSR costs little more than a serial
the structures described. testing approaches for g scan register because we can ordi-
structured logic. They illustrate BtST narily implement it with only two
BlST structures for general techniques with rea additional XOR gates.’ But using
logic examples and present
the MISR on the circuit’soutputs r e
First of all, most BIST techniques quires XOR structures on every out-
for general logic involve a funda- structures and software tools put stage,plus the LFSR hardware.
mental trade-off between time and supporting BIST design. In contrast, when we examine
hardware. We can characterize this the test-perscanconfiguration in
trade-off most easily by classifying Figure 2a, we find that the LFSR and
BlST techniques into two categories: scan path or to shift the response out of the scan register SRI on the circuit’sin-
test-per-clock and test-per-scan. In test- the serial scan path (whichever is larger) puts are identical to those in Figure lb.
perclock BIST, we apply a test vector plus one or more normal mode clocks. But instead of the MISR logic on the out-
and capture a response each clock peri- For example, if a chip containing 200 puts, a scan register SRO drives a short-
od. In test-per-scan BET, we use scan edgetriggered flip-flopshas a single, full ened MISR on only a portion of the
capability to apply a test vector and c a p scan path, test-per-scan requires 201 outputs. This configuration saves the
ture a response each scan cycle. A scan clock periods to apply a test vector and MISR hardware on the remaining out-
cycle is the number of clock cycles re- simultaneously observe the response to puts, but it must shift all the outputsc a p
quired to shift the vector into a serial the previous vector-roughly 200 times tured in SRO into the output MISR

JUNE 1993 0 1993 IEEE

0740-7475/93/0600-0069$03.00 69
 B U I L T - I N S E L F - T E S T

between each normal clock. Thus, it is is of the external-XORtype (described in as compact outputs from driving logic
much slower in applying tests. For a cir- the “LFSR theory”section of Part 1) and are useful. This capability is quite natu-
cuit that uses a single serial scan path, that the serial scan paths are fed direct- ral for test-perscan using the STUMPS
one can use the configuration in Figure ly from adjacent bits of the LFSR. Then, configuration but is more difficult for
2b, with the pattern generator LFSR and the value in bit i o f a serial scan path will test-perclock. One of the earliest struc-
the response LFSR separated totally be identical to the value of bit i- 1 of the tures designed for test-perclock is
from the circuit under test (CUT). serial scan path to its right. the built-in logic block observer
STUMPS2(self-testusing an MISR and Thus, these bits are 100%correlated, (BILB0).2%P. 304 The original BILBO pro
parallel shift register sequence genera- and if they both feed the same combina- vided normal operation, reset, serial
tor) is a test-perscan approach to pseu- tional network, the patterns seen by the scan, and MISR functions. By using the
dorandom testing of circuits with network are certainly not pseudoran- feedback associated with the MISR, the
multiple serial scan paths. In this ap- dom and may yield reduced fault cover- BILBO can also provide pattern genera-
proach an LFSR used as a pseudoran- age. In general,a BIST designer must be tion as a variation of serial scan.
dom test pattern generator (PRTPG) very mindful of such correlation and Figure 3 shows a modified version of
feeds the inputs directly to a set of serial design to avoid it. In the case of the BILBO structure,its modes o f opera-
scan paths, as in Figure 2c, with the in- STUMPS, the input network in Figure 2c tion, and an application to a circuit with
put network consisting of simple con- is actually a phase shift network con- a pipeline structure. In Figure 3c,CUTS A
nections from the LFSR to the scan path. structed of XOR trees specifically de- and C can be tested simultaneously,and
The outputs from the serial scan paths signed to avoid correlation between CUT B individually, with the modes
feed MISR inputs. Suppose that the LFSR inputs to the serial scan chains and specified in Figure 3d. The BILBO
hence to the logic under test.’ The BIST modes are defined on the premise that
hardware overhead for STUMPSbeyond the outputs of an MlSR are not adequate
full scan consists of the PRTPG, the input to serve as pseudorandom test inputs.
Shift register
network, and the MISR. This approach A final test-perclock approach,called
can simultaneously test all the synchro circular self-testor circular BIST, elimi-
nous internal logic in a chip or set of nates the linear feedback circuits for

... chips, except embedded structures

such as RAMS and ROMs.
both pattern generation and response
compa~tion.~, P. 496, The circular ap-
Obviously, in a given circuit, cornbi- proach converts each flip-flop to an
MlSR
national logic typically not only drives MISR stage,and the feedback is the nat-
but is driven by storage elements. Thus, ural nonlinear feedback provided by the
ial ibl BIST structures that can generate or d e CUT itself. Figure 4 shows a full circular
Figure 1. Test-per-clockconfigurations. liver test patterns to driven logic as well BIST structure. Here, we initialize the

1 Pseudorandom test pattern generator 1

li ...
Scan register SRI LFSR Scan register SRI 1 Input network

CUT II 1
...
so+/eHuJ Scan register SRO LFSR MlSR
v

ibl fd
Figure 2. Test-per-scanconfigurations.

70 IEEE DESION & TEST OF COMPUTERS

 B1 Dn-1 Dn

B2

SI so

Clock

Q1 Q2 Qn

E] 0 0 Serial scan

I I I

fbl (cl fdl

Figure 3. A modified BllBO configuration: hardware (a),operating modes (b), application structure (c), and application modes (dl.

BIST path by scan, allow the circuit to

Qt
operate for some number of clock cy-
cles, and scan out all or part of the signa-
ture left in the path and compare it to the
correct signature. Problems can arise
with this structure because the MISRs
ScanjVCirculate

SI
0) GP

:. C gA
1
Inputs

:
I

I
outputs

.
:
i iz
I-1
[r
E

outputs, with the circuit as feedback, Corn binational +

serve as test patterns. Thus, fault simula-
tion and possibly redesign of the path or
.. - logic
.
4A

the use of multiple testing cycles are

necessary to ensure adequate coverage.
Thus far, all the methods we have
considered assume that BIST or serial
scan structures have made the CUT
combinational.But that is not essential;
1 Internal flip-flops
BIST can be successful on sequential cir-
cuits as well. Usually, however, MlSR or Figure 4. General full-circular BlST configuration.

JUNE 1993 71

. -
 B U I L T - I N S E L F - T E S T

BlST glossary
Aliasing: condition in which a faulty cir- Design for testability (DFT): any pro- method in which the subcircuits in a
cuit with erroneous response produc- cess applied to a circuit design that covering set for the circuit under test
es the same signatureas a good circuit facilitates testing the circuit are tested exhaustively
Automatic test patkm generafw Exhaustive testing: a testingtechnique Pseudorandom patterns: sequences
(ATPG):a system (typically a comput- that applies all possible input com- of patterns havingproperties similar
er prcgram)thatgeneratesasequence binations to the circuit under test to sequences of random patterns
of test patterns to test faults in a circuit Fault coverrrge: ratio, expressed as a Pseudorandom testing: a testing
Boundary scan: a method of provid- fractionor percentage, of all faults de- method that applies pseudorandom
ing serial scan access to all the in- teded by a test sequence to the toto1 patterns to the circuit under test
puts and outputs of a device modeledfaults in the circuit under test Pseudorandomtest patterngenerotor
Built-in logic block observer (BIBO): In-cimuittesfing0: a methodthat uses (PRTPG): a BlST circuit, usually
an LFSR-basedBlST circuit with four direct access to the chip pins to test based on an LFSR or a cellular au-
modes of operation: normal stor- chips or intercondons on a b a r d tomaton, that produces a pseudo-
age, reset, serial scan, and multiple- Level-sensitive scan design (LSSD): a random sequence of patterns
input signature analysis variant of the serial scan design con- Rei& ratio:percentage (or fraction) of
Cellular automaton: a circuit consist- cept defined by IBM faulty devices among all devices
ing of an array of sequential cells Linear feedback shift register (LFSR): passing a set of tests
having a repetitive local intercon- a circuit made up of flip-flops and Scan design: a DFT technique in which
nection structure (the most common XOR gates interconnected in certain all storage elements, except those in
form is a one-dimensionalcell array configurations (typically used for storage arrays, can be controlled
consisting of a single bit of storage BlST pattern generation and re- and observed without using the
dependent on its own value and the sponse analysis) functional logic (the most common
value stored in its nearest neighbor) Muk+inputsignahJre register (MISR): form is serial scan, in which storage
Circular BIST: a technique in which an LFSR-basedBlST circuit that simul- elements are electronically recon-
pattern generation and response taneously compacts multipleresponse nected to form one or more shift reg-
compaction are carried out simulta- sequences for response analysis isters for testing)
neouslyby the same set of flip-flops, Partialscan: a DFT technique in which Signature: contents of a set of storage
which form a circular chain only a subset of all circuit flip-flops elements containing the compacted
Compaction: reduction of a response is scannable or compressed responsesof a circuit
sequence into a much shorter se- Patiwn an ordered set of binaty values under test
quence with possible loss of infor- that is applied simultaneouslyto the in- Stuck fault: a fault model in which a
mation (that is, the response puts of a circuit or that appean simul- line in the circuit remains at a con-
sequence may not be recoverable taneously on the ouputs of a circuit stant logic value irrespective of the
from the shorter sequence) Programmable logic army (PIA):usu- signal value at the line
Cumpression: reduction of a response ally refers to a structured implemen- Surface mount technology (SMT): a
sequence into a much shorter se- tation of a digital function based on method of assembly in which elec-
quencew i h lossof infonxhon (that a two-level AND/OR description of tronic components are mounted on
is, the response sequence can be re- the combinationalpartof the function both sides of a printed circuit board
covered from the shorter sequence) Pseudoexhaustive testing: a testing Vector: another term for pattern

scan capabilities must be provided to at one that has no cycles between storage detect such faults,we will need a serial
least a portion of the internal storage el-' I elements or into one that roughly resem- scan path to scan in the patterns and
ements. This approach, which we call bles a pipeline? scan out the responses, a ROM to store
partially sequential BET, can be applied The fundamental BIST structures and the patterns, and associated test manag-
to the circular BIST c~nfiguration.~ Par- methods given so far may not detect all er hardware. If we attack hard-to-detect
tially sequential BIST can also employ
I faults,so we must consider how to deal faults with weighted pseudorandom
techniques that change the sequential with the remaining hard-todetect faults. tests, we will need a weighted pseudo-
circuit, for testing purposes, either into If we simplyuse deterministic patterns to random generator.6.iAnother possibility

72 IEEE DESIGN & TEST OF COMPUTERS

is the use of cellular automata8 Additional logic
Additional logic
to control
BlST for structured logic
b in AND plane
* output lines
The basic structured logic block types ~

to which BlST is applied separately from 4

general logic blocks are PLAs, ROMs, Additional

and RAMs. PLAs are almost always em-
bedded in a larger circuit, whereas
logic
to
control
i AND plane
.: OR plane
Additional
logic
in
OR
ROMs and RAMs may be embedded or product
plane
stand-alonestructures for application of lines . =
BIST. In either case,the BlST method for
embedded structures uses extra logic to
isolate these blocks from the remaining
logic. That is, BlST treats these blocks as
stand-alonestructures. Thus, if the struc-
tures are embedded, BlST integration
control
block
t t ... t ...
can take place at the architectural and 1 PLA inputs PLA outputs
chip organization levels.
Figure 5 diagrams a generic BET PLA Figure 5. A generic BlSTarchitecture of PMs.
structure. The figure shows a number of
extra logic blocks around a PLA. Not all
these blocks are necessary to self-test a that until some novel technique ap- the other hand, the fault model asumes
PLA. For example, if the PLA has only a pears, BlST will be practical only for stuck-at, coupling, and patternsensitive
small number of inputs (less than about small- to medium-size PLAs that can be faults.” RAMs require such diverse and
25), the best strategy may be exhaustive tested exhaustively or for cases where complex fault modelsbecause of theirvety
testing. In that case, all we need is a pat- multiple-fault detection is so important high density.
tern generator at the input, a response that the silicon area overhead is a sec- Both deterministic tests12 and ran-
analyzer such as an MISR at the output, ondary consideration. dom tests2,p.242 have been used for em-
and a BIST control block to isolate the ROM, embedded orstand-alone,is rel- bedded RAMs. For the application of
PLA from the rest of the logic.The control atively easy to test. The basic method is to BIST to embedded RAMs, the pattern
block initiates the self-testand at its com- read the ROM contents and compact the generator contains an address generator
pletion evaluates the compacted results outputs by means of an MISR. Both the and a data generator. The address gen-
to determine the status of the PLA. pattern generator and the response ana- erator consists of an LFSR or a counter,
A host of other methods, using either lyzer are simple structures. Aliasing is a and the data generator is often an LFSR
deterministic or random vectors for problem only if the probability of rnulti- or a finitestate machine that produces
maximum fault coverage with mini- ple bit errors in the ROM outputs is high. the data to be written into the RAM. Dur-
mum silicon area overhead due to extra Typical multiple bit errors are caused by ing reading from the RAM, the address
logic, have been proposed. The struc- the failure of an output buffer or a decod- generator and the data generator can
ture shown in Figure 5 is generic,and all er circuit. Such faults either are not generate the same sequence of address-
BISTarchitecturesfor PLAs fit into it. The masked by the MISR or can be detected es and data again, but responses are usu-
most prevalent fault model used for relatively easily by a few extra determin- ally compacted to protect against failure
PLAs is cross-point faults, as opposed to istic test vectors.Also, faults in the control of the generators. The present trend is to
conventional stuck-at faults. Research part of the ROM are often catastrophic use deterministic test patterns for em-
has shown that tests that detect cross- and hence are detected by a test that sim- bedded RAMs because fault coverage
point faults also detect most other classi- ply reads the ROM contents. for the deterministic method can be
cal and nonclassical faults in PLAS.~We In deriving tests for RAMS, engineers computed exactly for possible impacts
refer the reader to two works that de- have used different fault models for differ- on reliability.
scribe almost all these methods and ent parts of a RAM. For example, the fault Although neither deterministic nor
compare their performance impact ( d e model for decoders includes not only random testing is a high-overhead rneth-
lay), silicon area overhead, and fault stuck-at faults but also arbitrary address- od, the sharing of test logic between
c~verage.~ Our
. ’ ~general assessment is mapping faults. For the memory array, on multiple RAM blocks on the chip poten-

JUNE 1993 73
 B U I L T - I N S E L F - T E S T

tially reduces overhead even further. vided for the PLAs by LFSRs embedded
~ Boundaryscan However, such sharing raises a concern in the input storage elements and for the
about interconnection overhead. To ROM by the microprogram counter that
Boundaryscan provides a method of keep the interconnection area low, we is part of the normal logic. The largest
testing board interconnections as well can integrate internal scan or boundary structure is a PLA with 19 inputs, so the
as isdatingthe interiorof chips for BIST. scan with the BlST logic.'3 test length is 512K clock cycles. The in-
Thus, boundary scan suppotis the inte- Thus far, most practical applications formation gathered by the MISRs is con-
gration of BlST into the hierarchical of BIST to embedded RAMs have used tinuouslyshifted out to additional LFSRs
stnrdure proposed in this article. A only algorithms that test for stuck-at tied to the data path. An internal com-
number of manufacturers have &el- faults. Stand-alone RAMs have even parison at the end of the test yields an
oped their own boundary-scanand test higher integration density and therefore output of zero in an observable register
access d o d s for chips. For design- must be tested for more complex fault if it detects no error.
ers planning to use vendor parts on types. The test sequence length and
their boards, the approach used by hence the time necessary to test a RAM Circular BIST in AT&T ASICs.4
those parts is given in IEEE Std 1149.1- are proportional to the number of bits in AT&T has employed a partial sequential
1990. The standard defines a four-to- the RAM. With the continual increase in approach using circular BIST in seven
five-signal test access port, RAM size and the increasing cost of application-specific integrated circuits.
requirements for boundary scan, an in- tester-based testing, self-test of large Four of the devices contain embedded
struction register and a standard sub- RAM chips has become imperative. RAM, and for all but one device, the goal
set of instnrctions, a bypass register, Among the earliest BIST RAM architec- was complete self-test except for I/O
and an optional device identification tures were two proposed by Kinoshita buffers and portions of the multiplexer
register. It also provides for optional, and S a l ~ j a .These
'~ architectures use logic on the inputs. The implementation
user-defined, scannable registers. transition count as the compaction func- uses a cell similar to that shown in Fig-
These registers plus the instruction reg- tion; data are generated in such a way ure 3 but with the logical functions of the
ister constitute a convenient means of that no aliasing can take place even original BILBO. The signature read-out
BlST implementation and control. Sup- though the compactor consists of a 1-bit occurs only from an LFSR or MISR em-
port for boundary scan in hardware transition counter. One of the proposed bedded in the circular chain. In addi-
and CAD tools is growing rapidly. test architectures is based on random log tion, BIST is provided for the embedded
ic, the other on microcode. The over- RAMs. For the six devices with full BIST,
Bibliography head for these architectures is negligibly the gate count, including BIST logic, av-
Bleeker, H., P. van den Eiinden, and F. small (less than 1%) for very large RAMs erages 14,150,the logic overhead aver-
de h g , Boundary-scan Test:A Prac- (4 Mbits or more). Both architectures ages 20%,and the active area overhead
ticalqppnxlCh, Kluwerkademic, Bos- have been used in practice. A list describ averages 13%.The average fault cover-
ton,1993. ing the special features of BlST RAM d e age for the portion of the circuit covered
signs and implementations appears in an by BIST for four faultsimulated circuits is
/€€€Stdl149.1-~99OT&Acoess Port article by Franklin and Saluja.I5All these 92%. Much of the hardware overhead is
and&xmda?l-soanAn)r~E(ANs/ RAMs use deterministic test patterns. in the BIST cells, and a trade-off is appar-
I€€Lj,IEEE, Piscc&wy, NJ., 1990. ent between the number of storage cells
Example BlST applications to which BlST is applied and the fault
Journal of €/ectronic Testing: Theory Manufacturers are increasingly em- coverage. The company has automated
and Applications, Special Issue on ploying BIST in real products. Here we the BIST design for standard cell VLSl
Boundary Scan, Vol. 2, No. 1,1991. offer three examples of such applica- implementation or PLD-based circuit
tions, selected to illustrate the use of packs.
Maunder, C.M. and R.E. Tulloss, eds., BIST in the semiconductor, communica-
The Test Access Port and Boundary- tions, and computer industries. Pseudorandom test in the IBM
Scan Archikdure, IEEE Computer So- RISC/6000.I7 The RISC/6000 uses an
ciety Press, Los Alamitos, Calif., 1990. Exhaustive test in the Intel extensive BlST structure that covers the
80386.'6 In the 80386, BlST logic ex- entire system. Its BIST techniques in-
Parker, K., The Boundary-ScanHand- haustively tests three control PLAs clude full serial scan and pseudoran-
book, Kluwer Academic, Boston, and the control ROM. All have MISRs on dom pattern use in the form of STUMPS.
1992. their outputs. Exhaustive stimuli are pro- In addition, the system uses embedded

74 IEEE DESIGN 81TEST OF COMPUTERS

RAM self-testand performs delay testing. Table 1. CAD fools for BIST/DFT. *
~

The RISC/6000’sBIST system is hierar- , I

chically structured,with a common on- , Vendor/Tool Capabilities

chip processor (COP) on each chip. The I
COP, which occupies less than 3%of the Crosscheck TRDC: test rules design checker; Scangen: automatic
chip area, contains an LESR for pattern AlDA Testability Tools scan insertion (single/multiplechain), combinational
generation, an MlSR for response com- test generator; Fltsim: fault simulator; boundary-scan
paction, and a counter for addressing support available
during RAM testing. In addition,the COP Siemens Cerberus: design rule checker, automatic scan register
contains a control finitestate machine, Cerberus, Socrates insertion, overhead optimization; Socrates:combina-
attached by a few dozen control lines to tional test generator
the normal onchip and BIST logic. Each Racal-Redac~
Full or partial scan, testability analyzers, sequential
chip also has boundary scan. Intelligen 2 circuit test generator, CADAT fault simulator, boundary-
For delay tests, two normal clock p h s scan support available
es are applied in sequence at normal o p Synopsys Redundancyremoval from automatically synthesized
erating speed between scan-in and Test Compiler circuit, automatic scan insertion and test generation
scan-ut operations. For RAM tests, RAM AT&T Alert: design rule checker, combinational test
data inputs and outputs are attached di- Titus, Testpilot generator, fault simulators, scan overhead optimizer for
rectly to scan paths by means of DFr standard-cell design; Gentest/Pascant: partial scan and
techniques, and RAM address and read/ sequential circuit test generator; CKT: automatic circular
write controls are attached to the COP. BIST; PEST: pseudoexhaustive self-test; Maclog: BlST
macrocell generator
BlST tools ~ Cadence Design rule audit (random and serial scan), manual
Most designers of BIST circuits use , TestScan scan register implementation,combinational test
general-purpose tools such as logic and generator, fault simulator
fault simulators,but somespecialized tools Philips DFT rule checker, testability hardware insertion,
have also been developed. Table 1 pre Panther Tool Kit automatic full-scan design and scan chain routing, test
sents a list of commerciallyavailable CAD control block generator, combinationaltest pattern
tools suitable for BISTcircuit design.These generator, boundary-scaninsertion
are largely analysis tools, and some have Sunrise Partial scan and sequential circuit test generator
their origin in the DFr environment. Such TestGen/Test Syn
tools can be useful because DlT is often a
precursor to BET. Next we describe some ~ 1 *Due to rapid growth in this field, vendor offerings may have changed and new products
hardware structures and software design may be available.
systems developed specifically for BIST
implementations.
testing these blocks require special ac- supports the implementation with a stan-
BIST support of VLSI design.Mucha, cess to the I/O pins. Such access requires dard cell library. BlST implementation
Daehn, and GrossI8have designed build- extra routing area. BIST design of embed- starts from the chip definition, which in-
ing blocks to facilitate BIST. Their catalog ded memory blocks keeps the routing cludes a plan for implementing the test
of three CMOS chips supports printed cir- overhead contained and is widely used features. The system follows this plan in
cuit board design.Two of the chips imple in ASIC3 and custom chip^.'^^'^ A variety selectingappropriate macrocellsfor BIST.
ment BILBO structures, and the third of tests can be generated from the BIST AT&Ts macrocell generation tool
contains the necessaty hardware for test- circuitry-for example,tests for cellstuck Maclog provides automated design of
ing memories. They have also designed a faults and data retention faults. The over- ROMs, register files,and content-addres-
BIST multiplier chip and a BISTarithmetic head is about 5% for l&Kbit static RAM sable memories with BIST features.”
logic chip. The authors give the area over- and decreases for larger memories. The Among other tools in use at AT&T,
head and performance degradation due Cathedral-I1silicon compiler system also PEST3supports the design of pseudoex-
to BIST in their article. uses a BlST memory approach?0 haustive BIST, and CKTZ4inserts hard-
Many VU1 chips contain memory General Electric‘s design sy9 ’ ware necessary for circular BIST in
blocks. The conventional methods of ternz1partitionsa chip into macrocellsand ~ random-logic circuits.

JUNE 1993 75

.. -
 B U I L T - I N S E L F - T E S T

BIST support of synthesis.Incorpe interesting feature of thissystem is that it Reterences

rating DFT in automatic synthesis is a presents alternatives and allows the user 1. P.H. Bardell, “Design Considerations for
current trend. The Silc silicon compil- to make choices. Parallel Pseudorandom Pattern Genera-
er,25developed at GTE and supported Somewhat similar features are irnple tors,”J. Electronic Testing: Theory and
by Racal-Redac, performs rulebased mented in Bides (BIST Design Expert Applications,Vol. 1, Feb. 1990,pp. 73-87.
synthesis. The following is a partial list of System),27developed at the University 2. P.H. Bardell,W.H. McAnney, and J. Savir,
the rules Silc uses: of Virginia, and Tiger (Testability Inser- Built-In Testfor VLSI:Pseudorandom Tech-
tion Guidance Expert System),28 at niques, John Wiley & Sons, New York,
1. Use PLA-type control logic with Microelectronics and Computer Tech- 1987.
clocked feedbacks only. nology Corporation. 3. M. Abramovici, M. Breuer, and A. Fried-
2. All internal clocks must be control- man, DigitalsystemsTesting and Testable
lable from primary inputs. Design, Computer Science Press, New
3. All flipflops should be masterslave York, 1991.
D-type. 4. C.E. Stroud, “AutomatedBIST for Sequen-
4. All reset lines should be controlla- OURDISCUSSION OF BIST structures tial Logic Synthesis,”IEEE Design & Test
ble from primary inputs. and their applications in real-world de- ofComputers,Vol. 5, No. 6, Dec. 1988,pp.
5. Allow a test pin. signs demonstrates the applicability of 22-32.
BIST in today’s electronic systems. BIST 5. H.-J. Wunderlich, “The Design of Ran-
The Silc system uses a SCOAP-like offers the unique opportunity to use hi- dom-Testable Sequential Circuits,”Roc.
(Sandia Controllability Observability erarchy in the testing of complex sys- Int’l Symp. Fault-Tolerant Computing,
Analysis Program) testability measure to tems. It also provides an economical IEEE Computer Society Press, Los Alami-
identify testing problems?,p.49 Such anal- answer to the test problems of future tos, Calif., 1989,pp. ll(1117.
ysis identifies circuit areas where signals technologies in which physical accessto 6. J. Waicukauski et al., “A Method for Gen-
are difficult to control or observe.The sys- parts embedded in very large systems erating Weighted Random Test Patterns,”
tem then uses an expertsystem approach may be restricted. Although most com- IBM J. Research and Development, Vol.
to implement testability.Although the fi- mercially available CAD tools have ad- 33, No. 2, May 1989, pp. 149-161.
nal design is heavily biased toward BIST, vanced only to the level of supporting 7. H.J. Wunderlich, “Self-Test Using Un-
Silc uses other techniques when neces- DFT within captive tool environments, equiprobable Random Patterns,” F’roc.
sary. It can implement BlST PLAS and BIST tools have appeared. As these tools Int’l Symp. Fault-Tolerant Computing,
modify other structures to form pattern proliferate, the essential componentsfor IEEE CS Press, 1987,pp. 258-263.
generators and signature analyzers. broader adoption of hierarchical BIST 8. P.D. Hortensius, R.D. McLeod, and B.W.
While adding the BlST hardware, the sys- will be in place. Podaima, “CellularAutomata Circuitsfor
tem considers design parameterssuch as We have presented the principles of Built-In Self-Test,”IBM J. Research and
required fault coverage, acceptable over- pattern generation and response analy- Development,Vol. 34, No. 213, Mar./May
head, cost,test time, and the capability of sis and described the structures for their 1990, pp. 389405.
available CAD tools. implementation. In addition, we have 9. M.M. Ligthart and R.J. Stans, “A Fault
TDES (Testable Design Expert Sys- outlined real BIST applications and indi- Model for PLAs,”IEEE Trans. Computer-
a CAD system developed at the cated the state of development of CAD Aided Design, Vol. 10, No. 2, Feb. 1991,
University of Southern California, con- tools for BIST. With this foundation es- pp. 265270.
tains information about various testable tablished, we encourage readers to fur- 10. C.Y. Liu and K.K. Saluja, “Built-inSelf-Test
design methodologies (TDMs) in its ther explore the world of BIST to meet Techniques for Programmable Logic Ar-
knowledge base. The designer sets the present and future needs in the testing of rays,”in VLSlFault Modeling and Testing
design goals and constraints on area their products. Techniques,G.W.Zobrist,ed., Ablex P u b
overhead,speed degradation,fault cov- lishing, Norwood, N.J., 1993.
erage, I/O pins for test, test time, and the 11. A.J. van de Goor and C.A. Vermijt, “An
use of external test equipment. TDES Overview of Deterministic Functional
then analyzes the block-level design Acknowledgment RAM Chip Testing,”ACMComputingSur-
consisting of PLAs, registers, buses, The National Science Foundation, Divi- vqs, Vol. 22, Mar. 1990,pp. 533.
RAMS, and ROMs. Recognizing these sion of Microelectronic Information Process- 12. S. Jain and C. Stroud, “Built-InSelf-Testing
basic structures, it modifies the circuit to ing Systems, under grants MIP-9003292and of Embedded Memories,”lEEEDesign&
incorporate the appropriate TDMs. An MIP-9111886,partially supported this work. Test ofComputers,Vol. 3, No. 5, Oct. 1986,

76 IEEE DESIGN & TEST OF COMPUTERS

 pp. 52-63. matic DFT System for the Silc t the University of Wisconsin-Madison,
13. B. Nadeau-Dostie, A. Silburt, and V.K. Silicon Compiler,” IEEE Design & ihere he has developed and taught a broad
Agarwal, “Serial Interfacing for Embed- Test of Computers, Vol. 3, No. 1, inge of computer engineering courses. His
ded-MemotyTesting,”IEEEDesign & Test Feb. 1986, pp. 45-57. search interests include testing, design for
ofcomputers,Vol.7, No. 2, Apr. 1990,pp. 26. M.S. Abadir and M.A. Breuer, “A Knowl- stability, BIST,and fault-tolerantcomputing.
52-63. edge-Based System for Designing Test- le hasserved as general chair of the 1979 In-
14. K. Kinoshita and K.K. Saluja, “Built-In able VLSI Chips,” IEEE Design & Test of 3mational Symposium on Fault-Tolerant
Testing of Memory Using an OnChip Computers,Vol. 2, No. 4, Aug. 1985, pp. ‘omputing,as associate editor of IEEE Trans-
Compact Testing Scheme,” IEEE Trans. 56-68. ctions on Computersand lEEE Transactions
Computers,Vol. C-35, No. 10, Oct. 1986, 27. K. Kim, J.G. Tront, and D.S. Ha, “BIDES: n Computer-AidedDesign, and on the p r o
pp. 862-870. A BIST Design Expert System,”J.Electron- ram committees of IEEE conferences. Kime
15. M. Franklin and K.K. Saluja, “Built-InSelf- ic Testing: Theory and Applications,Vol. ; a fellow of the IEEE and a member of the
Test of Random-AccessMemories,”Com- 2, No. 2, June 1991,pp. 165-179. :EE Computer Society.
puter,Vol.23, No. 10,Oct. 1990,pp. 45-56. 28. M.S. Abadir, ‘‘TIGERTestabilityInsertion
16. P. Gelsinger, “Design and Test of the Guidance Expert System,” Roc. Int’l
80386,”IEEEDesign & Test ofComputers, Con[ Computer-Aided Design, IEEE CS
Vol.4, No. 3,June 1987, pp. 42-50. Press, 1989, pp. 562-565.
17. I.M. Ratiu and H.B. Bakoglu, “Pseudoran-
dom Built-In Self-Test Methodology and
Implementation for the IBM RlSC System/
6000 Processor,”IBMJ. Research and De-
oelopment,Vol. 34, Jan. 1990,pp. 78-84. Lewal K. Saluja a professor in the Depart-
18. J.P. Mucha, W. Daehn, and J. Gross, “Self- lent of Electrical and Computer Engineer-
Test in a Standard Cell Environment,” ig at the University of Wisconsin-Madison,
IEEEDesign & Test of computers,Vol.3, rhere he teaches logic design, computer
No. 6, Dec. 1986, pp. 3541. rchitecture, microprocessor-based sys-
19. R. Dekker, F. Beenker, and L. Thijssen, member of the technical staff at AT&T Bell ms, and VLSl design and testing. Previous-
“Realistic Built-In Self-Test for Static Laboratoriesand a visiting professor of elec- {, he worked at the University of Newcastle,

RAMS,”IEEEDesign & Test ofComputers, trical and computer engineering at Rutgers ustralia. He has also held visiting and con-
Vol. 6, No. 1, Feb. 1989,pp. 2&34. University. His interests include VLSl testing ulting positions at the University of South-
20. F. Catthoor, J. van Sas, L. Inze, and H. de and neural network algorithms. He has c e rn California, the University of Iowa, and
Man, “ATestabilityStrategy for Multipre authored three books. A former editor-in- liroshima University. His research interests
cessor Architecture,” IEEEDesign & Test chief of IEEE Design & Test o f Computers, iclude design for testability, fault-tolerant
ofComputers,Vol.6, No. 2, Apr. 1989,pp. Agrawal presently serves as editor-inchief of omputing, VLSI design, and computer ar-
B34. the Journal ofEectronic Testing: Theoryand hitecture. He is an associate editor of the
2 1. R.C. Kroeger,‘TestabilityEmphasis in the Applications. He received his PhD from the ournal ofElectronic Testing: Theoryand Ap
General Electric ANLSl Program,” IEEE University of Illinois at Urbana-Champaign. dications. Saluja received the BE from the
Design & Test of Computers,Vol. 1,No. 2, He is a fellow of the IEEE and a member of Jniversity of Roorkee, India, and the MS and
May 1984,pp. 6165. the IEEE Computer Society, the ACM, and he PhD in electrical and computer engi-
22. Y. Zorian, “A Structured Approach to the VLSl Society of India. He has served on leering from the University of Iowa. He is a
Macrocell Testing Using Built-In Self- the IEEE CS Board of Governors. nember of the IEEE Computer Society.
Test,” Roc. IEEE Custom Integrated Cir-
cuits Con[, 1990, pp. 28.3.1-28.3.4.
23. E. Wu, “PEST: A Tool for Implementing
PseudeExhaustiveSelf-Test,”AT&TTech-
nicalJ.,Vol. 70, No. 1, Jan./Feb. 1991,pp.
87-100.
24. M.M. Pradhan et al., “Circular BIST with Send correspondence about this article to
Partial Scan,” Roc. Int’l Test Cod, IEEE lishwani D. Agrawal, AT&T Bell Laboratories,
CS Press, 1988,pp. 719729. io0 Mountain Ave., Room 2C-476, Murray
25. H.S. Fung and S. Hirschhom, “An Auto ment of Electricaland Computer Engineering MI, NJ 07974; [email protected].

JUNE 1993 77