International Journal of Computer Applications (0975 – 8887)

Volume 98– No.8, July 2014

Comparative Power Analysis of LFSR Test Pattern

Generators

H. Srikanth Kamath Aakash Nath, Shobhit Kumar

Assistant Professor Srivastava, Saket Garg
ECE Department, MIT Students
Manipal University, India ECE Department, MIT
Manipal University, India

ABSTRACT concurrent techniques and off-line BIST which includes

Automatic Test Pattern Generation Automatic Test Pattern functional and structural approaches. The main purpose of
Generator is an electronic de-sign automation method used to BIST is to re-duce the complexity, and thereby decrease the
find an input sequence that, when applied to a digital circuit, cost and reduce reliance upon external (pattern-programmed)
enables automatic test equipment to distinguish between the test equipment. BIST reduces cost in two ways which are
correct circuit behavior and the faulty circuit behavior caused reducing test-cycle duration and reducing the complexity of
by defects. The designs selected for comparison use LFSR as the test/probe setup, by reducing the number of I/O signals
its core central component around which the entire algorithms that must be driven/examined under tester control. One of the
are based which contribute in construction of Automatic test methods to generate test patterns in BIST is Linear Feedback
pattern generator. The LFSR is considered as it gives Shift Register (LFSR) which acts as the seed generator which
excellent random characteristics and has a low area overhead is then fed into the Circuit under Test (CUT).
which allows it to be placed in the integrated circuit. Linear-feedback shift register (LFSR) is a shift register whose
input bit is a linear function of its previous state. The most
General Terms commonly used linear function of single bits is XOR. Thus,
Random Pattern Generators for testing. an LFSR is most often a shift register whose input bit is
driven by the exclusive-or (XOR) of some bits of the overall
Keywords shift register value. The initial value of the LFSR is called the
LFSR, random, pattern, low power, four bits, seed, and because the operation of the register is
deterministic, the stream of values produced by the register is
1. INTRODUCTION completely determined by its current (or previous) state.
If a product is designed, fabricated, tested, and it fails the test,
Likewise, because the register has a finite number of possible
then there must be a cause for the failure, either test was
states, it must eventually enter a repeating cycle. However, an
wrong or the fabrication process was faulty or the design was
LFSR with a well-chosen feedback function can produce a
in-correct, etc. The role of testing is to detect whether
sequence of bits which appears random and which has a very
something went wrong and the role of diagnosis is to deter-
long cycle.
mine exactly what went wrong, Correctness and effectiveness
of testing is most important for quality products. Quality and 3. ALGORITHMS
economy are two major benefits of testing. ATPG (
Automatic Test Pattern Generation or Automatic Test Pattern 3.1 Simple LFSR
Generator) is an electronic design automation meth- Here a four bit LFSR is taken into consideration which is
od/technology used to find an input (or test) sequence that, made by using four D flip flops connected in a serial in
when applied to a digital circuit, enables automatic test parallel out form and a XOR gate [5]. This is expected to give
equipment to distinguish between the correct circuit behavior all the sixteen patterns but it gets stuck at ‘0000’ and hence
and the faulty circuit behavior caused by defects. A defect is only fifteen patterns are generated at a particular moment.
an error caused in a device during the manufacturing process. Hence an initial seed needs to be set. The connections are
A fault model is a mathematical description of how a defect decided by the characteristic equation of the LFSR which in
alters de-sign behavior. The logic values observed at the the case of four bits is [4].
device's primary outputs, while applying a test pattern to some
device under test (DUT), are called the output of that test
pattern. The output of a test pattern, when testing a fault-free
device that works exactly as designed, is called the expected
out-put of that test pattern [2]. A fault is said to be detected by
a test pattern if the output of that test pattern, when testing a
device that has only that one fault, is different than the
expected output.

2. BIST and LFSR

Built In Self-Test which is one of the most efficient ways of
testing present. BIST is a design technique in which parts of a
circuit are used to test the circuit itself. BIST techniques are
classified as on-line BIST which includes concurrent and non- Fig 1: Simple LFSR [5]

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 International Journal of Computer Applications (0975 – 8887)
Volume 98– No.8, July 2014

3.2 Modified LFSR showed reduction of switching activity [5].

To overcome this stuck at fault a modified LFSR was
designed .In this to get all the patterns we add a couple of
logic gates and it is assumed that the addition of these logic
gates have not increased the area overhead and power
consumption by a great amount so it is justified to add them to
get all the patterns. The gates used are three input NOR gate
and two XOR gates each with two inputs rather than the
single XOR gate. The rest of the part is similar to that of
Simple LFSR which is made by four D flip flops connected in
Serial in Parallel Out form.
Fig 4: Bit Swapping LFSR [5]

4. SIMULATION AND RESULTS

To check the working and observe the various patterns the
algorithms were initially constructed using VHDL coding and
after satisfactory results the power analysis of the same was
done[6]. After this these algorithms were simulated in
Cadence Virtuoso by using schematics and their power
analysis was done. A 180 nm technology was used for the
schematics and the test conditions for the analysis were set as
Fig 2: Modified LFSR follows:

3.3 Unit Switching LFSR o Voltage: 1.8Volts

In this algorithm the main aim is to minimize the switching o Frequency: 800Mhz
power as it can be minimized using various techniques and in o Rise Time: 100ps
a well-designed circuit switching power plays a pivotal role in o Fall Time:100ps
the total power consumption. The switching power is reduced o Duty Cycle:50%
by reducing the switching activity. To achieve this a seed The power of the individual algorithms were first found and
generator is used, a n bit counter, gray code converter, XOR then their test power was found by putting the patterns in a
gates and nor gates. In this the counter will produce the test circuit (4:1 mux in this case) and he values were
sequence and nor operation will be performed with the tabulated.
previous term of the gray encoder which then will be fed to
and gate which will supply the clock for seed generator. Then 1: Observed Patterns
there will be XOR operation between the seed generator and
Simple Modified Unit Bit
the gray converter output. If the seeds are selected carefully
LFSR LFSR Switching Swapping
then we have a single change code hence reducing the
(n=3)
switching considerably which will result in reduction of the
switching power [1]. 0001 1010 - 0010
1000 1011 - 0100
1100 0110 - 1100
1110 0011 - 1110
1111 1001 - 1111
0111 0100 - 0111
1011 0010 - 1011
0101 0001 1101 0110
1010 0000 1100 1010
Fig 3: Unit Switching LFSR [1]
1101 1000 0100 1101
3.4 Bit Swapping LFSR 0110 1100 0000 0101
After the following algorithms then a new technique called
the Bit Swapping LFSR was implemented. This is a technique 0011 1110 0010 0011
in which multiplexer act as the means to reduce the switching
activity. Here the bits are swapped if the switching exceeds a 1001 1111 0011 1001
threshold value as compared to the previous pattern. In this 0100 0111 1011 1000
algorithm the reduction of switching activity is quite
significant when the pattern length is grater as compared to 0010 1011 0101 0001
that smaller length of same algorithm. It was simulated and it
Not Possible 0101 1101 0000
Total Number Of Switching per pattern
2 2 1 1.625

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 International Journal of Computer Applications (0975 – 8887)
Volume 98– No.8, July 2014

Table 2: Average Power for Pattern Generator 5. CONCLUSION

The power saving in testing is quite evident from the data
Generating Power above. The overhead generating power is compensated if the
number of bits is increased and where testing take the chunk
Algorithm Power Consumed
of the power consumed in the total setup. During test power
Simple LFSR 0.960mW
simple LFSR was not considered as it did not give all the pat-
Modified LFSR 0.978mW terns. The results are quite significant if there is great amount
of testing required and where flexibility is required for the
Bit Swapping LFSR 1.137mW number of pat-terns generated.
Unit Switching LFSR 1.250mW 6. ACKNOWLEDGMENTS
We take this opportunity to express a deep sense of gratitude
to Prof. S N Bhat, Associate Professor, MIT Manipal, for his
cordial support, valuable information and guidance, which
1.5 helped us in completing this task through various stages. The
constant inputs were life savers and were the driving force
Generation Power behind this project. We are obliged to staff members,
Power in mW

Department of Electronics and Communication, for the

1
valuable information provided by them in their respective
fields. We are grateful for their cooperation during the period
of this assignment. A very special mention is due to the HOD
0.5 Dr K. Prabhakar Nayak for his unwavering support.

7. REFERENCES
0 [1] BO YE and Tian-Wang Li,” A novel BIST scheme for low
Simple Modified Unit Bit power testing,” 2010 IEEE.
LFSR LFSR Switching Swapping
Generation Power [2] P. Girard,” survey of low-power testing of VLSI circuits,”
Algorithms IEEE design and test of computers, Vol. 19,no.3,PP 80-
90,May-June 2002.
Fig 5: Graphical representation of Generation Power [3] S. Wang and S.K. Gupta,” DS-LFSR: a BIST TPG for low
Table 3: Average power during Testing switching activity,” IEEE Trans computer-aided design
of Integrated circuits and systems, Vol. 21, No.7,pp.842-
Power Consumption 851, July 2002.
Algorithm Power Power Saving [4] Low power, Low Transition random pattern
Consumed generator.2012
Modified LFSR 0.814mW NA [5] Mark Goresky and Andrew M Klapper, “Fibonacci and
Galois Representations of Feedback with Carry Shift
Bit Swapping 0.306mW 62.20%
Registers”, IEEE, Vol.48, No.11, November 2002.
Unit Switching 0.434mW 46.60% [6] J Bhasker,”A VHDL Primer”, Prentice Hall,3rd
Edition,8120323661
[7] H Roth, Lizzy Kurian John, Digital System Design Using
VHDL 2nd Edition.
Test Power
1

0.8
Power in mW

0.6

0.4

0.2

0
Category 1 Unit Switching Bit Swapping
Algorithms

Test Power

Fig 6: Graphical Representation of Test Power

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