ACTIVE PIXEL SENSORS

SEMINAR REPORT

HARIKUMAR.K.

E7B, 16
 INTRODUCTION

CMOS Active Pixel Sensor(APS) can be utilized to convert optical images

into corresponding electronic signals, and can be utilized to convert optical
images into corresponding electronic signals and can be used as the sensing
part in digital still image camera systems. The main advantage of the CMOS APS
compared to the conventional charge coupled device (CCD) imager is that
the CMOS APS can be fabricated in standard CMOS process. Therefore the
CMOS APS imager and the other CMOS circuits can be integrated to a single
chip. Consequently the cost, power consumption and complexity of the
whole system can be greatly reduced. APS sensors have found markets in many
consumer applications, especially camera phones. They have also been used in
other fields including digital radiography, military ultra high speed image
acquisition, security cameras and optical mice. Manufacturers include Aptina
Imaging (independent spinout from Micron Technology, who purchased
Photobit in 2001), Canon, Samsung, STMicroelectronics, Toshiba, OmniVision
Technologies, Sony, and Foveon, among others.

Charge-coupled devices (CCD’s was the dominant technology for image

sensors for 3 decades. However, CCD’s cannot be easily integrated with CMOS
circuits due to additional fabrication complexity and increased cost. Also,
CCD’s are high capacitance devices so that on-chip CMOS drive electronics
would dissipate prohibitively high power levels for large area arrays (2–3 W).
Furthermore, CCD’s need many different voltage levels to ensure high charge
transfer efficiency. The readout rate is limited due to the inherent sequential
read out of CCD’s and the need to achieve nearly perfect charge transfer
efficiency to maintain signal fidelity. CCD’s also suffer from smear and
susceptibility to radiation damage.
 CCD IMAGE SENSORS

An image sensor is a device that converts an optical image to an electric

signal. It is used mostly in digital cameras and other imaging devices. The most
popular and earlier type of image sensors made use of charge coupled
devices. A charge-coupled device (CCD) is a device for the movement of
electrical charge, usually from within the device to an area where the charge
can be manipulated, for example conversion into a digital value.
In a CCD for capturing images, there is a photoactive region (an epitaxial layer
of silicon), and a transmission region made out of a shift register. The
photoactive region is exposed to the light and this results in the accumulation of
charge which is proportional to the intensity of light at that point. Once the array
has been exposed to the image, a control circuit causes each capacitor to
transfer its contents to its neighbor (operating as a shift register). The last
capacitor in the array dumps its charge into a charge amplifier, which converts
the charge into a voltage. By repeating this process, the controlling circuit
converts the entire contents of the array in the semiconductor to a sequence of
voltages.

The CCD image sensors can be implemented in several different

architectures. The most common are full-frame, frame-transfer, and interline. The
distinguishing characteristic of each of these architectures is their approach to
the problem of shuttering. In a full-frame device, all of the image area is active,
and there is no electronic shutter. A mechanical shutter must be added to this
type of sensor or the image smears as the device is clocked or read out.

With a frame-transfer CCD, half of the silicon area is covered by an

opaque mask (typically aluminum). The image can be quickly transferred from
the image area to the opaque area or storage region with acceptable smear
of a few percent. That image can then be read out slowly from the storage
region while a new image is integrating or exposing in the active area. Frame-
transfer devices typically do not require a mechanical shutter and were a
common architecture for early solid-state broadcast cameras. The downside to
the frame-transfer architecture is that it requires twice the silicon real estate of
an equivalent full-frame device; hence, it costs roughly twice as much.

The interline architecture extends this concept one step further and masks
every other column of the image sensor for storage. In this device, only one pixel
shift has to occur to transfer from image area to storage area; thus, shutter times
can be less than a microsecond and smear is essentially eliminated. The
advantage is not free, however, as the imaging area is now covered by
opaque strips dropping the fill factor to approximately 50 percent and the
effective quantum efficiency by an equivalent amount. Modern designs have
addressed this deleterious characteristic by adding microlenses on the surface
of the device to direct light away from the opaque regions and on the active
area. Microlenses can bring the fill factor back up to 90 percent or more
depending on pixel size and the overall system's optical design.

The choice of architecture comes down to one of utility. If the application

cannot tolerate an expensive, failure-prone, power-intensive mechanical
shutter, an interline device is the right choice. Consumer snap-shot cameras
have used interline devices. On the other hand, for those applications that
require the best possible light collection and issues of money, power and time
are less important, the full-frame device is the right choice. Astronomers tend to
prefer full-frame devices. The frame-transfer falls in between and was a
common choice
 ACTIVE PIXEL SENSORS

An active pixel image sensor is defined as an image sensor technology

that has one or more active transistors within the pixel unit cell. This is in contrast
to a “passive pixel” approach that uses a simple switch to connect the pixel
signal charge to the column bus capacitance . It is fabricated using CMOS
processing technology which integrates an amplifier at each pixel site.

Active pixel sensors promise lower noise readout, improved scalability to

large array formats, and higher speed readout compared to passive pixel
sensors. Each pixel unit cell contains an imaging element and three transistors for
readout, selection, and reset. The imager is read out a row at a time using a
column parallel readout architecture. The major innovation is the use of
intrapixel charge transfer to allow correlated-double-sampling (CDS) and on-
chip fixed pattern noise (FPN) suppression circuitry located in each column.
These innovations allow the CMOS image sensor to achieve low noise
performance comparable to a CCD. The presence of the reset transistor helps in
controlling the lateral blooming and reduces the lag or smear. The reset and
signal levels are read out differentially and this is termed as the correlated-
double-sampling (CDS) which helps in suppressing kTc noise, noise, and fixed
pattern noise from the pixel. Low noise and high dynamic range are achieved.

The CMOS active pixel image sensors have performance suitable for
many applications including robotics and machine vision, guidance and
navigation, automotive applications, and consumer electronics such as video
phones, computer inputs, and home surveillance devices.The solid state CMOS
image sensor technology being developed at the NASA Jet Propulsion
Laboratory(JPL) is a 2nd generation ultra low power monolithic APS that
incorporates
 On-Pixel amplification
 Noise reduction
 Improved digital control features
 Larger size
 The APS imager is produced with the same commercially available CMOS
device fabrication process used for microcontroller and memory chips. This
allows the on-chip integration of the following
 Detector Array element
 On-Pixel amplifier
 Timing and control circuit
 High speed analog signal chain circuits
 Multiplexers , ADCs, etc
Active Pixel Sensors use single +3.3V/5V power supply and features small
pixels with wide dynamic range.
 APS PIXEL DESIGN

The schematic of the pixel design and the read out circuit is shown in the
fig. The pixel unit cell is shown within the dotted outline. The imaging structure
consists of a photogate (PG) with a floating diffusion output (FD) separated by a
transfer gate(TX). The pixel unit cell also contain a reset transistor (MR), the input
transistor of the in-pixel source follower (MIN) and the row selection transistor
(MX). The readout circuit which is common to an entire column of pixels
includes the load transistor of the first source follower (MLN). It also consists of the
two sample and hold circuits for storing the signal level and the reset level.
Sampling both the reset and signal levels permits correlated double sampling
(CDS) which suppresses reset noise from the floating diffusion node of the pixel,
and noise and threshold variations from the source-follower transistor within the
pixel.
Each sample-and-hold circuit consists of a sample-and-hold switch (MSHS
or MSHR) and capacitor (CS or CR) and a column source-follower (MP1 or MP2)
and column selection transistor (MY1 or MY2) to buffer the capacitor voltages
and to drive the high capacitance horizontal bus at higher readout speeds. The
load transistors of the column source-followers (MLP1 and MLP2) are common to
the entire array of pixels. P-channel source-followers are used in the column
circuit to compensate for the level shifting of the signal due to the n-channel
source followers within the pixels.

OPERATION

The rail voltages VDD and VSS are set at 5 V and 0 V, respectively. During
the signal integration period [Fig. 2(a)], photo-generated electrons are
integrated and stored under the surface channel photogate PG, which is
biased at 5 V. The reset transistor MR is biased at 2.5 V to act as a lateral
antiblooming drain, allowing excess signal charge to flow to the reset drain. The
rowselection transistor MX is biased off at 0 V. Following signal integration, an
entire row of pixels are read out simultaneously.

The reset and signal levels are read out to separate chanells utilizing the
correlated sampling to reduce the kTc noise, 1/f and fixed pattern noise. The
sensor is read out in parallel one row at a time. The signal from the pixel is the
difference between the potential on the floating node before and after the
photo charges are transferred to it. These two potentials are stored at
thebottom capacitors sequentially by using the 2 sample and hold circuits. The
voltages on the capacitances are differentially read out to produce a voltage
proportional to the photo charge.
First, the pixels in the row to be read out are addressed by enabling row
selection switch MX. Then the floating diffusion output node of the pixel (FD) is
reset by briefly pulsing the reset gate of MR to 5 V. This resets FD to
approximately 3.5 V [Fig. 2(b)]. The output of the first source-follower is sampled
onto capacitor CR at the bottom of the column by enabling sample-and-hold
switch MSHR. Then, PG is pulsed low to 0 V, transferring the signal charge to FD
[Fig. 2(c)]. The new output voltage is sampled onto capacitor CS by enabling
sample and hold switch MSHS [Fig. 2(d)]. The stored reset and signal levels are
sequentially scanned out through the second set of source-followers by
enabling column address switches MY1 and MY2. The entire sequence of
activities are shown in the figure given below.

Operation of CMOS APS (a) signal integration, (b) reset, (c) signal charge
transfer, and (d) signal readout.
ADVANTAGES OF CMOS APS OVER CCD IMAGE
SENSORS

 Speed : an area in which CMOS arguably has the advantage over CCDs
because all camera functions can be placed on the image sensor.
 On Chip Processing and compactness: CMOS APS has on-chip integrated
circuitry which helps to realize various functions at reduced cost and size.
CCD with its specialized fabrication process is quite expensive.
 Less power Consumption : APS systems based on CMOS technology
consumes 100X less power than CCD systems. As a result such sensors are
preferred for systems like mobile phones, laptops, etc where power
consumption is a major factor. For the same pixel throughput, CCD
systems require about 2.5W of power whereas CMOS systems require only
20-50mW of power which provides longer battery life.
 Responsivity : It is the amount of signal the sensor delivers per unit of input
optical energy. CMOS imagers are marginally superior to CCDs, in
general, because gain elements are easier to place on a CMOS image
sensor. Their complementary transistors allow low-power high-gain
amplifiers, whereas CCD amplification usually comes at a significant
power penalty.
 Windowing: One unique capability of CMOS technology is the ability to
read out a portion of the image sensor. This allows elevated frame or line
rates for small regions of interest. This is an enabling capability for CMOS
imagers in some applications, such as high-temporal-precision object
tracking in a subregion of an image. CCDs generally have limited abilities
in windowing.
 Anti-blooming: the ability to gracefully drain localized overexposure
without compromising the rest of the image in the sensor. CMOS
generally has natural blooming immunity. CCDs, on the other hand,
require specific engineering to achieve this capability
 NOISE

The noise in the sensor is suppressed by the correlated double

sampling of the pixel output. The CDS technique suppresses the kTc noise
from pixel reset, suppresses the 1/f noise from the in-pixel source follower
and suppresses the Fixed Pattern Noise (FPN) originating from the pixel to
pixel variation in the source follower threshold voltage. The noise in a
CMOS APS is dominated by the white noise from pixel source follower and
reset noise on the sample and hold capacitor at the bottom of the
column. Typically the value of the S/H capacitor is around 1-4pF and
represents a trade off between the noise speed and layout. Typical
output noise in CMOS APS array is of the order 140-170µVRMS.

The power dissipation of an APS array can be very low depending

on the desired read out rate. The power associated with the read out is
primarily determined by the common pixel biased load on each column
and the analog line driver. The required bias current for a given frame rate
(Fr) is determined mainly by the slew rate requirements on the source
follower. If Ccol is the capacitance at the bottom of the column and Cload
is the capacitance of the line driver, then average analog power
dissipation from the pixel source follower and the line driver is given by

P=2CcolFrMΔVcolVdd + 4αCloadFrMΔVoutVdd
Where
α:Parameter that indicates the number of operation level

Fr: Frame Rate

M: Total number of Pixel readout

Vdd: Power supply voltage

ΔVcol : Maximum voltage change at the bottom of the column

ΔVout : Maximum voltage change at the output circuit.

 CMOS ACTIVE PIXEL SENSORS IN PARTICLE
PHYSICS

The straightforward application of a CMOS sensor in a tracking detector is

nevertheless not possible because of its poor fill factor. For visible light applications this
number is defined as the fraction of the pixel area that is sensitive to the radiation.
Because of the transistors and metal interconnections; it is usually in the range of 20-
30%, an unacceptable low value for particle tracking application; In order to overcome
this limitation a sensor is integrated in a twintub process with an n-well/p substrate
diode. This technique has already proved its effectiveness in visible light applications
reducing the blind area only to the routing metal lines, which absorb the visible light but
have no effect on the detection of minimum ionising particles. Since the proposed
device is an Active Pixel Sensors (APS) fabricated on a single substrateit is called
Monolithic APS or MAPS. In the past, other pixel technologies were proposed and
developed for tracking.

The MAPS helps in the detection of charged particles with 100% efficiency and
a few micron spatial resolution. These new devices are extremely promising for future
high precision vertex detectors as they provide solutions with a very low material
budget and with high resolution at relatively low cost due to their fabrication in a
standard submicron CMOS technology. Vertex Detectors are particle detectors
designed to provide high-precision (typically 5 to 20 micrometers) measurements of
points along the trajectories of charged particles.