100 MHz to 30 GHz,

Silicon SPDT Switch

Data Sheet ADRF5020
FEATURES FUNCTIONAL BLOCK DIAGRAM
RF2
Ultrawideband frequency range: 100 MHz to 30 GHz
Nonreflective 50 Ω design ADRF5020 VSS
Low insertion loss: 2.0 dB to 30 GHz EN
50Ω
High isolation: 60 dB to 30 GHz

DRIVER
RFC
High input linearity
CTRL
1 dB power compression (P1dB): 28 dBm typical 50Ω
VDD
Third-order intercept (IP3): 52 dBm typical

14581-001
High power handling RF1
24 dBm through path Figure 1.
24 dBm terminated path
ESD sensitivity: Class 1, 1 kV human body model (HBM)
20-terminal, 3 mm × 3 mm, land grid array package
No low frequency spurious
Radio frequency (RF) settling time (to 0.1 dB of final RF
output): 15 ns

APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, electronic counter measures (ECMs)
Broadband telecommunications systems

GENERAL DESCRIPTION
The ADRF5020 is a general-purpose, single-pole, double-throw This broadband switch requires dual supply voltages, +3.3 V
(SPDT) switch manufactured using a silicon process. It comes and −2.5 V, and provides CMOS/LVTTL logic-compatible
in a 3 mm × 3 mm, 20-terminal land grid array (LGA) package control.
and provides high isolation and low insertion loss from 100 MHz
to 30 GHz.

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADRF5020 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Interface Schematics .....................................................................6
Applications ....................................................................................... 1 Typical Performance Characterics ..................................................7
Functional Block Diagram .............................................................. 1 Insertion Loss, Return Loss, and Isolation ................................7
General Description ......................................................................... 1 Input Power Compression and Third-Order Intercept (IP3)........8
Revision History ........................................................................... 2 Theory of Operation .........................................................................9
Specifications..................................................................................... 3 Applications Information .............................................................. 10
Absolute Maximum Ratings ............................................................ 5 Evaluation Board ........................................................................ 10
Power Derating Curves ................................................................ 5 Probe Matrix Board ................................................................... 11
ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 12
Pin Configuration and Function Descriptions ............................. 6 Ordering Guide .......................................................................... 12

REVISION HISTORY
2/2017—Rev. 0 to Rev. A
Changed VEN = 3.3 V to 5 V to VEN = 0 V or 3.3 V to 5 V .......... 3

7/2016—Revision 0: Initial Version

Rev. A | Page 2 of 12
Data Sheet ADRF5020

SPECIFICATIONS
VDD = 3.3 V to 5 V, VSS = −2.5 V, VCTRL = 0 V or 3.3 V to 5 V, VEN = 0 V or 3.3 V to 5 V, TCASE = 25°C, 50 Ω system, unless otherwise noted.

Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 100 30,000 MHz
INSERTION LOSS
Between RFC and RF1/RF2 100 MHz to 10 GHz 1.2 dB
10 GHz to 20 GHz 1.5 dB
20 GHz to 30 GHz 2.0 dB
ISOLATION
Between RFC and RF1/RF2 100 MHz to 10 GHz 65 dB
10 GHz to 20 GHz 60 dB
20 GHz to 30 GHz 60 dB
Between RF1 and RF2 100 MHz to 10 GHz 70 dB
10 GHz to 20 GHz 65 dB
20 GHz to 30 GHz 65 dB
RETURN LOSS
RFC and RF1/RF2 (On) 100 MHz to 10 GHz 22 dB
10 GHz to 20 GHz 16 dB
20 GHz to 30 GHz 13 dB
RF1/RF2 (Off ) 100 MHz to 10 GHz 28 dB
10 GHz to 20 GHz 20 dB
20 GHz to 30 GHz 10 dB
SWITCHING
Rise and Fall Time tRISE, tFALL 10% to 90% of RF output 2 ns
On and Off Time tON, tOFF 50% VCTL to 90% of RF output 10 ns
RF Settling Time
0.1 dB 50% VCTL to 0.1 dB of final RF output 15 ns
0.05 dB 50% VCTL to 0.05 dB of final RF output 20 ns
INPUT LINEARITY1 600 MHz to 30 GHz
Power Compression
0.1 dB P0.1dB 26 dBm
1 dB P1dB 28 dBm
Third-Order Intercept IP3 Two-tone input power = 14 dBm each tone, 52 dBm
Δf = 1 MHz
SUPPLY CURRENT VDD, VSS pins
Positive IDD VDD = 3.3 V 80 300 µA
VDD = 5 V 100 600 µA
Negative ISS VSS = −2.5 V <1 10 µA
DIGITAL CONTROL INPUTS CTRL, EN pins
Voltage
Low VINL VDD = 3.3 V 0 0.8 V
VDD = 5 V 0.9 V
High VINH VDD = 3.3 V 1.2 3.3 V
VDD = 5 V 1.7 5.0 V
Current
Low and High IINL, IINH <1 µA

Rev. A | Page 3 of 12
ADRF5020 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
RECOMMENDED OPERATING CONDITONS
Supply Voltage
Positive VDD 3.0 5.4 V
Negative VSS −2.75 −2.25 V
Digital Control Voltage VCTL 0 VDD V
RF Input Power2 PIN f = 600 MHz to 30 GHz, TCASE = 85°C
Through Path RF signal is applied to RFC or through 24 dBm
connected RF1/RF2
Terminated Path RF signal is applied to terminated RF1/RF2 24 dBm
Hot Switching RF signal is present at RFC while switching 18 dBm
between RF1 and RF2
Case Temperature TCASE −40 +85 °C
1
For input linearity performance at frequencies less than 600 MHz, see Figure 15 to Figure 17.
2
For power derating at frequencies less than 600 MHz, see Figure 2 to Figure 4.

Rev. A | Page 4 of 12
Data Sheet ADRF5020

ABSOLUTE MAXIMUM RATINGS

For recommended operating conditions, see Table 1. 4

2
Table 2.
0
Parameter Rating

POWER DERATING (dB)

Supply Voltage –2

Positive −0.3 V to +5.5 V –4

Negative −2.75 V to +0.3 V
–6
Digital Control Input Voltage −0.3 V to VDD + 0.3 V
RF Input Power1 (f = 600 MHz to 30 GHz, –8

TCASE) = 85°C) –10

Through Path 27 dBm
–12
Terminated Path 25 dBm
Hot Switching 21 dBm –14

14581-003
10k 100k 1M 10M 100M 1G 10G
Temperature FREQUENCY (Hz)
Junction (TJ) 135°C Figure 3. Power Derating for Terminated Path vs. Frequency, TCASE = 85°C
Storage −65°C to +150°C 4
Reflow (MSL3 Rating)2 260°C
2
Junction to Case Thermal Resistance (θJC)
Through Path 420°C/W 0

POWER DERATING (dB)

Terminated Path 160°C/W –2
ESD Sensitivity
–4
HBM 1 kV (Class 1)
–6
1
For power derating at frequencies less than 600 MHz, see Figure 2 to Figure 4.
2
See the Ordering Guide section. –8

Stresses at or above those listed under Absolute Maximum –10

Ratings may cause permanent damage to the product. This is a
–12
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational –14

14581-004
10k 100k 1M 10M 100M 1G 10G
section of this specification is not implied. Operation beyond FREQUENCY (Hz)
the maximum operating conditions for extended periods may Figure 4. Power Derating for Hot Switching vs. Frequency, TCASE = 85°C
affect product reliability.
ESD CAUTION
Only one absolute maximum rating can be applied at any one
time.
POWER DERATING CURVES
4

0
POWER DERATING (dB)

–2

–4

–6

–8

–10

–12

–14
14581-002

10k 100k 1M 10M 100M 1G 10G

FREQUENCY (Hz)

Figure 2. Power Derating for Through Path vs. Frequency, TCASE = 85°C

Rev. A | Page 5 of 12
ADRF5020 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND

GND

GND

GND
RF2
20 19 18 17 16

GND 1 15 VSS

GND 2 14 EN
ADRF5020
RFC 3
TOP VIEW
13 GND
(Not to Scale)
GND 4 12 CTRL

GND 5 11 VDD

6 7 8 9 10

GND

GND
RF1
GND

GND
NOTES

14581-005
1. THE EXPOSED PAD MUST BE CONNECTED
TO THE RF/DC GROUND OF THE PRINTED
CIRCUIT BOARD (PCB).

Figure 5. Pin Configuration (Top View)

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description
1, 2, 4 to 7, 9, 10, GND Ground. These pins must be connected to the RF/dc ground of the printed circuit board (PCB).
13, 16, 17, 19, 20
3 RFC RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
necessary when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic.
8 RF1 RF1 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic.
11 VDD Positive Supply Voltage.
12 CTRL Control Input. See Figure 7 for the interface schematic.
14 EN Enable Input. See Figure 7 for the interface schematic.
15 VSS Negative Supply Voltage.
18 RF2 RF2 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic.
EPAD Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.

INTERFACE SCHEMATICS
VDD
VDD
RFC,
RF1,
14581-006

RF2
CTRL, EN
14581-007

Figure 6. RFC, RF1, and RF2 Pins Interface Schematic Figure 7. Digital Pins (CTRL and EN) Interface Schematic

Rev. A | Page 6 of 12
Data Sheet ADRF5020

TYPICAL PERFORMANCE CHARACTERICS

INSERTION LOSS, RETURN LOSS, AND ISOLATION
Insertion loss and return loss measured on the probe matrix board using the ground, signal, ground (GSG) probes close to the RF pins;
isolation measured on an evaluation board because signal coupling between the probes limits the isolation performance of the ADRF5020
on the probe matrix board (see the Applications Information section for details of evaluation and probe matrix boards).
0 0
TCASE = +85°C
–0.5 TCASE = +25°C –5
TCASE = –40°C
–1.0 –10
INSERTION LOSS (dB)

–1.5 –15

RETURN LOSS (dB)

–2.0 –20

–2.5 –25

–3.0 –30

–3.5 –35

–4.0 –40
RFC
–4.5 –45 RF1 ON
RF2 OFF
–5.0 –50
14581-008

14581-010
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 8. Insertion Loss Between RFC and RF1/RF2 vs. Figure 10. Return Loss vs. Frequency for RFC, RF1 On, and RF2 Off
Frequency over Temperature
0 0
TCASE = +85°C TCASE = +85°C
–10 TCASE = +25°C –10 TCASE = +25°C
TCASE = –40°C TCASE = –40°C
–20 –20

–30 –30
ISOLATION (dB)

ISOLATION (dB)

–40 –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90

–100 –100
14581-009

14581-011
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 9. Isolation Between RFC and RF1/RF2 vs. Figure 11. Isolation Between RF1 and RF2
Frequency over Temperature vs. Frequency over Temperature

Rev. A | Page 7 of 12
ADRF5020 Data Sheet
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT (IP3)
All large signal performance parameters were measured on the evaluation board.
32 32
TCASE = +85°C TCASE = +85°C
30 TCASE = +25°C 30 TCASE = +25°C
TCASE = –40°C TCASE = –40°C
28 28

26 26
INPUT P0.1dB (dBm)

INPUT P0.1dB (dBm)

24 24
22 22
20 20
18 18
16 16
14 14
12 12
10 14581-012
10

14581-015
0 5 10 15 20 25 30 10k 100k 1M 10M 100M 1G
FREQUENCY (GHz) FREQUENCY (Hz)

Figure 12. Input 0.1 dB Power Compression (P0.1dB) vs. Figure 15. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over
Frequency over Temperature Temperature (Low Frequency Detail)
32 32

30 30

28 28
26 26
INPUT P1dB (dBm)

INPUT P1dB (dBm)

24 24
22 22
20 20
18 18
16 16
14 14
TCASE = +85°C TCASE = +85°C
12 TCASE = +25°C 12 TCASE = +25°C
TCASE = –40°C TCASE = –40°C
10
14581-013

10

14581-016
0 5 10 15 20 25 30 10k 100k 1M 10M 100M 1G
FREQUENCY (GHz) FREQUENCY (Hz)

Figure 13. Input 1 dB Power Compression (P1dB) vs. Frequency over Figure 16. Input 1 dB Power Compression (P1dB) vs. Frequency over
Temperature Temperature (Low Frequency Detail)

60 60
TCASE = +85°C
TCASE = +25°C
55 TCASE = –40°C 55

50 50
INPUT IP3 (dBm)
INPUT IP3 (dBm)

45 45

40 40

35 35

30 30

25 25 TCASE = +85°C
TCASE = +25°C
TCASE = –40°C
20 20
14581-017
14581-014

0 5 10 15 20 25 30 10k 100k 1M 10M 100M 1G

FREQUENCY (GHz) FREQUENCY (Hz)

Figure 14. Input IP3 vs. Frequency over Temperature Figure 17. Input IP3 vs. Frequency over Temperature
(Low Frequency Detail)

Rev. A | Page 8 of 12
Data Sheet ADRF5020

THEORY OF OPERATION
The ADRF5020 requires a positive supply voltage applied to the conducts the RF signal equally well in both directions between
VDD pin and a negative supply voltage applied to the VSS pin. its throw port (for example, RF1) and common port (RFC). The
Bypassing capacitors are recommended on the supply lines to isolation path (for example, RF2 to RFC) provides high loss
minimize RF coupling. between the insertion loss path and its throw port (for example,
The ADRF5020 is internally matched to 50 Ω at the RF RF2) terminated to an internal 50 Ω resistor.
common port (RFC) and the RF throw ports (RF1 and RF2); When the EN pin is logic high, both the RF1 to RFC path and
therefore, no external matching components are required. All of the RF2 to RFC path are in an isolation state regardless of the
the RF ports are dc-coupled to 0 V, and no dc blocking is required logic state of CTRL. RF1 and RF2 ports are terminated to
at the RF ports when the RF line potential is equal to 0 V. The internal 50 Ω resistors, and RFC becomes open reflective.
design is bidirectional; the RF input signal can be applied to the The ideal power-up sequence is as follows:
RFC port while the RF throw port (RF1 or RF2) is output or
vice versa. 1. Power up GND.
2. Power up VDD and VSS. The relative order is not
The ADRF5020 incorporates a driver to perform logic functions important.
internally and to provide the user with the advantage of a simplified 3. Power up the digital control inputs. The relative order of
control interface. The driver features two digital control input the logic control inputs is not important. However,
pins, CTRL and EN. powering the digital control inputs before the VDD supply
When the EN pin is logic low, the RF1 to RFC path is in an can inadvertently forward bias and damage the internal
insertion loss state, and the RF2 to RFC path is in an isolation ESD protection structures.
state, or vice versa, depending on the logic level applied to the 4. Apply an RF input signal.
CTRL pin. The insertion loss path (for example, RF1 to RFC)
Table 4. Control Voltage Truth Table
Digital Control Input RF Paths
EN CTRL RF1 to RFC RF2 to RFC
Low Low Isolation (off ) Insertion loss (on)
Low High Insertion loss (on) Isolation (off )
High Low Isolation (off ) Isolation (off )
High High Isolation (off ) Isolation (off )

Rev. A | Page 9 of 12
ADRF5020 Data Sheet

APPLICATIONS INFORMATION
EVALUATION BOARD Figure 20 shows the actual ADRF5020 evaluation board with
Figure 18 and Figure 19 show the top and cross sectional views component placement. Two power supply ports are connected
of the evaluation board, which uses 4-layer construction with a to the VDD and VSS test points, TP5 and TP2, and the ground
copper thickness of 0.5 oz (0.7 mil) and dielectric materials reference is connected to the GND test point, TP1. On each
between each copper layer. supply trace, a 100 pF bypass capacitor is used, and unpopulated
components positions are available for applying extra bypass
EDGE PLATING 5 × 520mil
capacitors.
R 32mil

570mil
940mil

828mil

40mil
14581-018

40mil
1500mil

Figure 18. Evaluation Board Layout (Top View)

G = 5mil
W = 14mil

0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil) T = 0.7mil

14581-020
RO4003 H = 8mil

0.5oz Cu (0.7mil) Figure 20. Populated Evaluation Board

TOTAL THICKNESS

Two control ports are connected to the EN and CTRL test

~62mil

FR4 points, TP3 and TP4. On each control trace, a resistor position
is available to improve the isolation between the RF and control
0.5oz Cu (0.7mil) signals. The RF ports are connected to the RFC, RF1, and RF2
FR4 connectors (J1, J2, and J3) that are end launch 2.4 mm RF
14581-019

connectors. A through transmission line that connects

unpopulated RF connectors (J7 and J8) is also available to
0.5oz Cu (0.7mil)

Figure 19. Evaluation Board (Cross Sectional View)

measure the loss of the PCB. Figure 21 and Table 5 are the
All RF and dc traces are routed on the top copper layer whereas evaluation board schematic and bill of materials, respectively.
the inner and bottom layers are grounded planes that provide a The evaluation board shown in Figure 20 is available from
solid ground for the RF transmission lines. Top dielectric Analog Devices, Inc., upon request.
material is 8 mil Rogers RO4003, offering good high frequency
performance. The middle and bottom dielectric materials are
FR-4 type materials to achieve an overall board thickness of 62 mil.
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model with a width of 14 mil and ground
spacing of 5 mil to have a characteristic impedance of 50 Ω. For
good RF and thermal grounding, as many plated through vias
as possible are arranged around transmission lines and under
the exposed pad of the package.

Rev. A | Page 10 of 12
Data Sheet ADRF5020
THR_CAL
J7 J8
DEPOP DEPOP

RF2
J3
TP1

GND

GND

GND

GND
RF2
VSS
TP2
C4 C3 C6
20 19 18 17 16 100pF 100nF 10µF
DEPOP DEPOP
GND 15
VSS
1 R1
GND EN 0Ω EN
2 14 TP3
RFC RFC U1 GND
J1 3 13 R2
GND CTRL 0Ω CTRL
4 12 TP4
GND VDD VDD
5 11 TP5
C5 C2 C1
6 7 8 9 10
100pF 100pF 10µF
DEPOP DEPOP

RF1

GND

GND
GND

GND
RF1

14581-021
J2

Figure 21. Evaluation Board Schematic

Table 5. Bill of Materials, Evaluation Board Components PROBE MATRIX BOARD

Component Description Figure 22 and Figure 23 show the top and cross sectional views
J1, J2, J3 End launch connectors, 2.4 mm of the probe matrix board that measures the s-parameters of the
J7, J8 Unpopulated end launch connectors, 2.4 mm ADRF5020 at close proximity to the RF pins using the GSG
TP1 to TP5 Through hole mount test points probes. The actual board duplicates the same layout in matrix
C4, C5 100 pF capacitors, 0402 package form to assemble multiple devices and uses RF traces for
C2, C3 Unpopulated capacitors, 0402 package through, reflect, and line (TRL) calibration.
C1, C6 Unpopulated capacitors, 0603 package
R1, R2 0 Ω resistors, 0402 package
U1 ADRF5020 SPDT switch
PCB 600-01583-00-1 evaluation PCB
220mil

14581-022
340mil

Figure 22. Probe Board Layout (Top View)

G = 5mil
W = 14mil

0.5oz Cu 0.5oz Cu 0.5oz Cu T = 0.7mil

RO4003 H = 8mil
14581-023

0.5oz Cu

Figure 23. Probe Matrix Board (Cross Sectional View)

Rev. A | Page 11 of 12
ADRF5020 Data Sheet

OUTLINE DIMENSIONS
3.10
0.25
3.00 0.30 0.20 CHAMFERED
2.90 0.25
PIN 1 0.15 PIN 1 (0.3 × 45°)
CORNER AREA
0.20 16 20
0.70
15 1
REF

1.70
1.60 REF
SQ
EXPOSED
PAD 1.60 SQ
1.50

11 5

0.40
BSC 10 6

TOP VIEW
0.13BOTTOM VIEW
REF

0.776 FOR PROPER CONNECTION OF

0.530 REF THE EXPOSED PADS, REFER TO
0.726 SIDE VIEW THE PIN CONFIGURATION AND
0.676 FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.236
0.196

05-25-2016-B
0.156
PKG-004908

Figure 24. 20-Terminal Land Grid Array [LGA]

3 mm × 3 mm Body and 0.72 mm Package Height
(CC-20-3)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Package Description Package Option Branding3
ADRF5020BCCZN −40°C to +85°C MSL3 20-Terminal Land Grid Array [LGA] CC-20-3 020
XXXX
ADRF5020BCCZN-R7 −40°C to +85°C MSL3 20-Terminal Land Grid Array [LGA] CC-20-3 020
XXXX
ADRF5020-EVALZ Evaluation Board
1
Z = RoHS-Compliant Part.
2
See the Absolute Maximum Ratings section.
3
XXXX is the 4-digit lot number.

©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D14581-0-2/17(A)

Rev. A | Page 12 of 12