Pe 4259 Ds

Product Specification
PE4259
SPDT High Power UltraCMOS®
Product Description 10 MHz–3.0 GHz RF Switch
The PE4259 UltraCMOS® RF switch is designed to Features
cover a broad range of applications from 10 MHz  Single-pin or complementary CMOS
through 3000 MHz. This reflective switch integrates logic control inputs
on-board CMOS control logic with a low voltage
CMOS-compatible control interface, and can be  Low insertion loss:
controlled using either single-pin or complementary  0.35 dB @ 1000 MHz
control inputs. Using a nominal +3-volt power supply
voltage, a typical input 1dB compression point of  0.5 dB @ 2000 MHz
+33.5 dBm can be achieved.  Isolation of 30 dB @ 1000 MHz
The PE4259 is manufactured on Peregrine’s  High ESD tolerance of 2 kV HBM

UltraCMOS process, a patented variation of silicon-  Typical input 1 dB compression point
on-insulator (SOI) technology on a sapphire of +33.5 dBm
substrate, offering the performance of GaAs with the
economy and integration of conventional CMOS.  1.8V minimum power supply voltage
 Ultra-small SC-70 package
Figure 1. Functional Diagram Figure 2. Package Type SC-70

6‐lead SC‐70
RFC
ESD
RF1 RF2
ESD ESD
CMOS
Control
Driver
CTRL CTRL or VDD

DOC-02109
Document No. DOC-03694-3 │ www.psemi.com ©2005-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 10
PE4259
Table 1. Electrical Specifications @ +25 °C, VDD = 3V (ZS = ZL = 50Ω )
Parameter Condition Minimum Typical Maximum Unit

1
Operation frequency 10 3000 MHz
1000 MHz 0.35 0.45 dB
Insertion loss3
2000 MHz 0.50 0.60 dB
1000 MHz 29 30 dB
Isolation
2000 MHz 19 20 dB
1000 MHz 21 22 dB
Return loss3
2000 MHz 24 27 dB
‘ON’ switching time 50% CTRL to 0.1 dB of final value, 1 GHz 1.50 us
‘OFF’ switching time 50% CTRL to 25 dB isolation, 1 GHz 1.50 us

2
Video feedthrough 15 mVpp
1000 MHz @ 2.3–3.3V 31.5 33.5 dBm
1000 MHz @ 1.8–2.3V 29.5 30.5 dBm
Input 1dB compression point
2500 MHz @ 2.3–3.3V 28.5 30.5 dBm
2500 MHz @ 1.8–2.3V 28 29 dBm
Input IP3 1000 MHz, 20 dBm input power 55 dBm
Notes: 1. Device linearity will begin to degrade below 10 MHz.

2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50Ω test
set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
3. A tuning capacitor must be added to the application board to optimize the insertion loss and return loss performance. See Figure 6 for
details.
©2005-2016 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-03694-3 │ UltraCMOS® RFIC Solutions
Page 2 of 10
PE4259
Figure 3. Pin Configuration (Top View) Table 4. Absolute Maximum Ratings

Symbol Parameter/Condition Min Max Unit
VDD Power supply voltage –0.3 4.0 V
VDD+
VI Voltage on any DC input –0.3 V
0.3
Storage temperature
TST –65 150 °C
range
Operating temperature
TOP –40 85 °C
range
PIN Input power (50Ω) +34* dBm
ESD Voltage (HBM,
Table 2. Pin Descriptions ML_STD 883 Method 2000 V
VESD 3015.7)
Pin No. Pin Name Description ESD Voltage (MM,
100 V
JEDEC, JESD22-A114-B)
1 RF1* RF port 1.
Note: * To maintain optimum device performance, do not exceed Max PIN at
Ground connection. Traces should be desired operating frequency (see Figure 4).
2 GND physically short and connected to ground
plane for best performance. Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
3 RF21 RF port 2.
the limits in the Operating Ranges table. Operation
4 CTRL Switch control input, CMOS logic level. between operating range maximum and absolute
5 RFC 1
RF common.
maximum for extended periods may reduce reliability.
This pin supports two interface options:

Single-pin control mode. A nominal 3-volt Figure 4. Maximum Input Power
supply connection is required.
CTRL or
6
VDD Complementary-pin control mode. A
complementary CMOS control signal to
CTRL is supplied to this pin. Bypassing
on this pin is not required in this mode.
Note: * All RF pins must be DC blocked with an external series capacitor or

held at 0 VDC.
Table 3. Operating Ranges

Parameter Min Typ Max Unit
VDD Power supply voltage 1.8 3.0 3.3 V
IDD Power supply current

9 20 µA
(VDD = 3V, VCNTL = 3V)
Control voltage high 0.7x VDD V
Control voltage low 0.3x VDD V

Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
Moisture Sensitivity Level devices are immune to latch-up.
The Moisture Sensitivity Level rating for the PE4259 in
the SC70 package is MSL1. Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe the
Switching Frequency same precautions that you would use with other ESD-
The PE4259 has a maximum 25 kHz switching rate. sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating.
Page 3 of 10
PE4259
Table 5. Single-pin Control Logic Truth Table Control Logic Input

Control Voltages Signal Path The PE4259 is a versatile RF CMOS switch that
Pin 6 (VDD) = VDD
supports two operating control modes; single-pin
RFC to RF1 control mode and complementary-pin control
Pin 4 (CTRL) = High
mode.
Pin 6 (VDD) = VDD
RFC to RF2
Pin 4 (CTRL) = Low
Single-pin control mode enables the switch to
operate with a single control pin (pin 4) supporting
Table 6. Complementary-pin Control Logic a +3-volt CMOS logic input, and requires a
Truth Table dedicated +3-volt power supply connection on
pin 6 (VDD). This mode of operation reduces the
Control Voltages Signal Path number of control lines required and simplifies the
Pin 6 (CTRL or VDD) = Low switch control interface typically derived from a
Pin 4 (CTRL) = High
RFC to RF1 CMOS Processor I/O port.
Pin 6 (CTRL or VDD) = High Complementary-pin control mode allows the

RFC to RF2
Pin 4 (CTRL) = Low switch to operate using complementary control
pins CTRL and CTRL (pins 4 and 6), that can be
directly driven by +3-volt CMOS logic or a suitable
Thermal Data Processor I/O port. This enables the PE4259 to
be used as a potential alternate source for SPDT
Psi-JT (JT), junction top-of-package, is a thermal
RF switch products used in positive control
metric to estimate junction temperature of a de-
voltage mode and operating within the PE4259
vice on the customer application PCB (JEDEC
operating limits.
JESD51-2).
JT = (TJ – TT)/P
Where
JT = junction-to-top of package characterization

parameter, °C/W
TJ = die junction temperature, °C
TT = package temperature (top surface, in the

center), °C
P = power dissipated by device, Watts
Table 7. Thermal Data

Parameter Typ Unit
Maximum junction temperature, TJMAX
(RF input power, CW = 31.5 dBm, +85 °C 99 °C
ambient)
JT 37 °C/W
JA, junction-to-ambient thermal resistance 104 °C/W
Page 4 of 10
PE4259
Evaluation Kit Figure 5. Evaluation Board Layout
The SPDT switch EK Board was designed to ease

customer evaluation of Peregrine’s PE4259. The
RF common port is connected through a 50Ω
transmission line via the top SMA connector, J1.
RF1 and RF2 are connected through 50Ω
transmission lines via SMA connectors J2 and J3,
respectively. A through 50Ω transmission is
available via SMA connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4

material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.0476”, trace
gaps of 0.030”, dielectric thickness of 0.028”,
metal thickness of 0.0021” and εr of 4.4.
J6 and J7 provide a means for controlling DC and

digital inputs to the device. J6-1 is connected to
the device VDD or CTRL input. J7-1 is connected
to the device CTRL input.
DOC-02396
Page 5 of 10
PE4259
Figure 6. Evaluation Board Schematic
J4 1 1 J5
N/A N/A
T-line Description
--
Model = CPWG J7
H = 28 mils CNTL
T = 2.1 mils
W = 47 mils
G = 30 mils
1
2
Er = 4.4
R2
1 K Ohm
U1 J3
1
PE4259/SC70-6 RF2
4 CTRL RF_2 3
J1
1 5 RFC GND 2
RFC 6 1
VDD RF_1
1 J2
1
RF1
C1
0.5pF
2
SEEASSY NOTE2 R1
1 K Ohm
1
C2
0.5pF General Comments
--
2
SEEASSY NOTE2
Transmission lines connected to J1, J2, and J3 should
1
2
J6 have exactly the same electrical length.

CNTLX/VDD The path from J2 to J3 including the distance through the part
should have the same length as J4 and J5 and be in parallel to
J4 to J5.
NOTES:
DOC-30626
1. USE PCB PART NUMBER: 101-0162-02.
2. ADD TWO 0.5PF CAPS IN SERIES TO BE SHUNTED ON THE J1 SMA INPUT.
SOLDER C1 SIDE 1 TO THE RF TRACE CLOSE TO THE J1 PIN.
SOLDER C1 SIDE 2 TO C2 SIDE 1.
SOLDER C2 SIDE 2 TO GROUND.
Page 6 of 10
PE4259
Typical Performance Data @ –40 °C to 85 °C (Unless Otherwise Noted)
Figure 7. Insertion Loss Figure 8. Isolation – Input to Output
Figure 9. Isolation – Output to Output Figure 10. Return Loss (Input)
Page 7 of 10
PE4259
Typical Performance Data @ VDD = 2.3V, T = 25 °C
Figure 11. Insertion Loss Figure 12. Isolation – Input to Output
Figure 13. Isolation – Output to Output Figure 14. Return Loss (Input and Output)
Page 8 of 10
PE4259
Figure 15. Package Drawing

6-lead SC-70
0.15 C
A 2.05±0.10 (2X) 0.65
1.30
B
6 4 0.90
0.10 C
1.25±0.10 2.10±0.10 0.90±0.10

2.10
0.10 C
0.15 C SEATING PLANE
(2X)
1 3 0.05±0.05 C
Pin #1 Corner
0.65 0.225±0.075
0.40
Top View Side View Recommended Land Pattern

DOC-76316
0.165±0.085
0.36±0.10
End View
Figure 16. Top Marking Specifications
PPP = Pin 1 Indicator

YWW PPP = Part Number
YWW = Date Code
PRT-50103
Page 9 of 10
PE4259
Figure 16. Tape and Reel Specifications
Pin 1
Tape Feed Direction
Table 7. Ordering Information

Order Code Part Marking Description Package Shipping Method
4259-63 259 PE4259G-06SC70-3000C Green 6-lead SC-70 3000 units / T&R

EK4259-01 PE4259-EK PE4259-06SC70-EK Evaluation Kit 1 / Box
Sales Contact and Information

For sales and contact information please visit www.psemi.com.
Advance Information: The product is in a formative or design stage. The datasheet contains design target No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.
specifications for product development. Specifications and features may change in any manner without notice. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,
Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later or in other applications intended to support or sustain life, or in any application in which the failure of the
date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no
possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to liability for damages, including consequential or incidental damages, arising out of the use of its products in
change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer such applications.
Notification Form). The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the
of this information. Use shall be entirely at the user’s own risk. following U.S. Patents: http://patents.psemi.com.
Page 10 of 10

Pe 4259 Ds

Uploaded by

Copyright:

Available Formats

Pe 4259 Ds

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Pe 4259 Ds

Uploaded by

Copyright:

Available Formats

Product Specification

The PE4259 is manufactured on Peregrine’s  High ESD tolerance of 2 kV HBM

Figure 1. Functional Diagram Figure 2. Package Type SC-70

CTRL CTRL or VDD

Table 1. Electrical Specifications @ +25 °C, VDD = 3V (ZS = ZL = 50Ω )

Parameter Condition Minimum Typical Maximum Unit

‘OFF’ switching time 50% CTRL to 25 dB isolation, 1 GHz 1.50 us

Notes: 1. Device linearity will begin to degrade below 10 MHz.

Figure 3. Pin Configuration (Top View) Table 4. Absolute Maximum Ratings

This pin supports two interface options:

Note: * All RF pins must be DC blocked with an external series capacitor or

Table 3. Operating Ranges

VDD Power supply voltage 1.8 3.0 3.3 V

IDD Power supply current

Control voltage low 0.3x VDD V

Table 5. Single-pin Control Logic Truth Table Control Logic Input

Pin 6 (CTRL or VDD) = High Complementary-pin control mode allows the

JT = (TJ – TT)/P

JT = junction-to-top of package characterization

TJ = die junction temperature, °C

TT = package temperature (top surface, in the

P = power dissipated by device, Watts

Table 7. Thermal Data

JA, junction-to-ambient thermal resistance 104 °C/W

Evaluation Kit Figure 5. Evaluation Board Layout

The SPDT switch EK Board was designed to ease

The board is constructed of a two metal layer FR4

J6 and J7 provide a means for controlling DC and

Figure 6. Evaluation Board Schematic

J6 have exactly the same electrical length.

Typical Performance Data @ –40 °C to 85 °C (Unless Otherwise Noted)

Figure 7. Insertion Loss Figure 8. Isolation – Input to Output

Figure 9. Isolation – Output to Output Figure 10. Return Loss (Input)

Typical Performance Data @ VDD = 2.3V, T = 25 °C

Figure 11. Insertion Loss Figure 12. Isolation – Input to Output

Figure 15. Package Drawing

1.25±0.10 2.10±0.10 0.90±0.10

Top View Side View Recommended Land Pattern

Figure 16. Top Marking Specifications

PPP = Pin 1 Indicator

Figure 16. Tape and Reel Specifications

Tape Feed Direction

Table 7. Ordering Information

4259-63 259 PE4259G-06SC70-3000C Green 6-lead SC-70 3000 units / T&R

Sales Contact and Information

You might also like