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    Question Paper Code:: Reg. No.

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    Samraj Jebasingh
    The document is a question paper for an electronics and communication engineering examination. It contains 16 questions testing knowledge of electronic circuits. The questions cover topics like biasing, stability factors, differential amplifiers, bootstrapping, small signal analysis of JFET and MOSFET amplifiers, gain bandwidth product, active loads, and cascode amplifier design.

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    Question Paper Code:: Reg. No.

    Uploaded by

    Samraj Jebasingh
    51 views5 pages
    The document is a question paper for an electronics and communication engineering examination. It contains 16 questions testing knowledge of electronic circuits. The questions cover topics like biasing, stability factors, differential amplifiers, bootstrapping, small signal analysis of JFET and MOSFET amplifiers, gain bandwidth product, active loads, and cascode amplifier design.

    Original Description:

    Anna university question

    Original Title

    X20442(EC6304)

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    The document is a question paper for an electronics and communication engineering examination. It contains 16 questions testing knowledge of electronic circuits. The questions cover topics like biasing, stability factors, differential amplifiers, bootstrapping, small signal analysis of JFET and MOSFET amplifiers, gain bandwidth product, active loads, and cascode amplifier design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    51 views5 pages

    Question Paper Code:: Reg. No.

    Uploaded by

    Samraj Jebasingh
    The document is a question paper for an electronics and communication engineering examination. It contains 16 questions testing knowledge of electronic circuits. The questions cover topics like biasing, stability factors, differential amplifiers, bootstrapping, small signal analysis of JFET and MOSFET amplifiers, gain bandwidth product, active loads, and cascode amplifier design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 5

    *X20442*

    Reg. No. :

    Question Paper Code : X 20442


    B.E./B.tech. Degree Examinations, NOVEMBER/DECEMBER 2020
    Third Semester
    Electronics and Communication Engineering
    EC 6304 – electronic circuits – i
    (Regulations 2013)

    Time : Three Hours Maximum : 100 Marks

    Answer all questions

    Part – A (10×2=20 Marks)

    1. Why is the operating point selected at the Centre of the active region ?

    2. Define Stability factor.

    3. What is the need of differential amplifier ?

    4. What is meant by bootstrapping ?

    5. Determine the output impedance of a JFET amplifier shown in Figure 3. Let


    gm = 2 mA/V and λ=0.


    Vi
    Vo

    Figure 3

    6. Compare between JFET and MOSFET amplifiers.


    X 20442 -2- *X12973*
    7. What is the reason for reduction in gain at lower and higher frequencies in case
    of amplifiers ?

    8. Determine the unity-gain bandwidth of a FET with parameters, Cgd = 10 fF,


    Cgs = 50 fF and gm = 1.2 mA/V.

    9. State the advantages of’ current steering circuit.

    10. Define active load and list the types of active load.

    Part – B (5×13=65 Marks)

    11. a) i) The parameters for each transistor in the circuit in Figure-5, are
    hfe = 100 and VBE = 0.7V . Determine the Q-point values of base, collector
    on
    and emitter currents in Q1 and Q2 . (6)

    –
    Figure 5
    ii) Determine the change in collector current produced in each bias referred
    to in Figures 6(a) and 6(b), when the circuit temperature raised from
    25°C to 105°C and ICBO = 15 nA @ 25°C. (7)


    Figure 6(a) Figure 6(b)
    (OR)
    *X12973*
    -3- X 20442
    b) i) Determine the quiescent current and voltage values in a p-channel JFET
    circuit (Vide Figure-7). (4)

    Vs

    VD

    –

    Figure 7

    ii) The circuit in Figure 8, let hfe = 100. (1) Find VTH and RTH for the base
    circuit. (2) Determine ICQ and VCEQ. (3) Draw the DC load line. (9)

    – –

    Figure 8

    12. a) Draw the a.c equivalent circuit of a CE amplifier with voltage divider bias
    and derive the expression for current gain, voltage gain, Input impedance,
    output admittance and overall current gain. (13)
    (OR)
    b) Explain the operation of cascade amplifier and derive Voltage gain, overall
    input Resistance overall current gain and output impedance. (13)

    13. a) i) Draw the small signal equivalent circuit of NMOS source follower. Also
    obtain the expression for the gain. (8)
    ii) With relevant circuit diagram, explain cascode NMOS amplifier circuit. (5)
    (OR)
    X 20442 -4- *X12973*

    b) Determine the small-signal voltage gain of a JFET amplifier. Consider the


    circuit shown in Figure 9 with transistor parameters : IDSS = 12 mA, VP = –4 V
    and λ = 0.008 V–1. Also draw the Small-signal equivalent circuit of common
    source JFET, assuming bypass capacitor acts as a short circuit. (13)

    R1
    V0
    Cc1

    V1


    Figure 9

    14. a) With neat sketch explain hybrid π CE transistor model. Derive the
    expression for various components in terms of ‘h’ parameters.

    (OR)

    b) Explain the high frequency analysis of JFET with necessary circuit diagram
    and gain bandwidth product.

    15. a) Draw and explain the operation of a simple MOSFET amplifier with
    active load and derive its voltage gain using small-signal equivalent circuit.

    (OR)

    b) With necessary diagrams, explain the operation of a CMOS differential


    amplifier. Using small signal analysis, derive the expression for its voltage
    gain.
    *X12973*
    -5- X 20442
    Part – C (1×15=15 Marks)
    16. a) Design the circuit given below such that IDQ = 100 µA, VSDQ =3V and
    VRS = 0.8V. Note that VRS is the voltage across the source resistor Rs. The value
    of the larger bias resistor, either R1 or R2 is to be 200 kΩ. Transistor parameter
    values are Kp = 100 µA/ V2 and VTP = –0.4 V . The conduction parameter, Kp
    may vary by ±5 percent.


    (OR)
    b) Design the cascode circuit shown below to meet the following specifications :
    VCE1 = VCE2 = 2.5 V, VRE = 0.7 V, IC1 ≅ IC2 ≅ 1mA, and IR1 ≅ IR2 ≅ IR3 = 0.10 mA.
    V+ = 9 V

    Vi

    –––––––––––––

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