Lab 5 Report PDF

Curtis Mayberry
EE 435
Lab 5: Single Stage Differential Amplifier

Introduction
In this lab we design a one stage differential amplifier. The amplifier was required to meet the following
specifications:
Vdd=-Vss=2.5V
Total Power<0.3mW (Opamp part)
Slew Rate: SR10V/us
DC Gain 40dB
Gain Bandwidth Product(GBW) 10MHz
Linear Output Swing Range: Vic-Vt2VoutVdd-0.3V
CMRR50dB
Input Common Mode Range (ICMR): ICMR50%(Vdd-Vss)
CL=5pF
Design
Figure 1: Basic single stage differential amplifier architecture with NMOS differential pair.
In order to begin the design the quiescent tail current was selected from the slew rate and power
requirement.
The final tail current was chosen to be 55A. The sizing of the current source transistor, M9, can then
be chosen based on the selected tail current.
Next the sizing of the differential pair, M1 and M2, was chosen to meet the gain-bandwidth product
requirement of the amplifier.
Finally the sizing of the active load, current mirroring transistors, M3 and M4, was chosen according to
the output swing range.
requirement:
choose upper bound, , in order to insure an accurate current mirror ratio of 1.
Implementation
The differential amplifier along with the voltage generation circuitry to generate Vg9 was implemented
as shown in figure 2. Vg9 is the gate voltage of the transistor which controls the tail current.
Figure 2: Differential amplifier schematic with a Vdd independent current source and bias voltage
generator.
Figure 3: differential voltage amplifier schematic
In order to set the tail current the sizing of the diode connected transistor in the voltage bias generating
circuit was swept in order to find the proper output voltage. The initial sweep indicated there were no
values that would set the desired tail current so the width of M9 was increased to 50m so the desired
current range was available.
The VEB of each transistor was then adjusted by adjusting the size of the transistors in order to increase
the VEB of M3 and M4 to ensure accurate current mirroring.
Having set the current to 55 A, the gain of the amplifier was ran and was slightly below the required
gain at DC. The tail current was decreased to 53A to raise the DC gain of the amplifier.
The final sizes, after tuning, turned out to be:

Results
Total Power
The total power consumed was 0.265 mW. It was calculated from the tail current value of 53A and a
VDD-VSS voltage of 5v.
DC gain, GB product, Gain and Phase Plots

The differential voltage gain and phase bode plots were created as shown in figures 4 and 5. The DC
gain requirement was meet with a DC gain of 41.06 dB. You can also see that the gain-bandwidth
product requirement was meet with a unity gain frequency of 10.03MHz as shown in the gain bode plot
in figure 4.
Figure 4: Gain bode plot

Figure 5: Phase bode plot
Slew Rate
Next the slew rate was measured by putting the amplifier in the buffer configuration shown in figure 6.
A pulse input between VDD and VSS was then applied and the maximum slope of the rising edge of the
pulse was found by running a transient simulation. The slew rate was found to be as shown in
figure 7.
Figure 6: Buffer configuration used to find the slew rate of the amplifier.
Figure 7: transient simulation of a step input used to determine the slew rate
Linear Output Swing Range

The linear output swing range was determined by sweeping the common mode input and determining
the linear output region as sown in figure 8. It was found to be 2.9827v.
Figure 8: linear output range plot
Common Mode Rejection Ratio (CMRR)

The CMRR was found to be . It was found by first finding the DC differential gain and then finding the DC
common mode gain. The DC differential gain was found above to be 41.05 dB and the DC common
mode gain was found to be -41.85 dB as shown in figure 9. The DC common mode gain was found by
setting both the positive and the negative differential inputs to a common input with a magnitude of 1
mV Once both gains were found, then the ICMR was calculated as:
Figure 9: Common mode gain bode plot.
Input Common Mode Range

The input common mode range was found by measuring the range of common mode input that the
differential gain remains at for a low frequency input. Hence the differential voltage was measured as
the common input voltage was swept as shown in figure 10. The input common mode range was found
to be 3.4v.
Figure 10: Common mode input range plot.
Telescopic Differential Amplifier Design

Next a challenge to increase the DC gain of the differential amplifier from above 40 dB to above 70 dB
was posed. I was able to accomplish this by cascading the differential amplifier to form what is called a
telescopic amplifier. The new amplifier architecture is shown in figure 11.
Figure 11: telescopic differential amplifier schematic.
The amplifier was created by cascading both the top PMOS current mirror and the bottom differential
pair to increase the output impedance and hence increase the gain of the amplifier. A resistor was
added do both of the top two transistors could be biased in a current mirror configuration. The size of
the resistor was found by adjusting its size while monitoring and balancing the Vgs values of the top two
transistor pairs. The bottom set of NMOS cascading transistors is biased at 800mv by using a second
bias generating circuit. The size of the cascading transistor was set equal to that of the original top pair
of transistors at
All other transistors remained the same size, with the exception of the diode connected transistors used
to set the bias voltages. The tail current dropped slightly to 52 uA after the cascode transistors were
added.
The DC gain was then found to be 75 dB as shown in figure 12. This is well above the requirement of 70
dB. The amplifier could be further tuned to meet many of the other specifications outlined for the
original differential amplifier if required.
Figure 12: Telescopic gain bode plot
Conclusion:
In this lab we designed a differential amplifier, one of the building blocks of electronics. Through the
process of designing first a basic differential amplifier and then a telescopic differential amplifier I was
able to learn a lot about the design flow and about the different amplifier properties. I look forward to
making a two stage differential amplifier in the following lab and learning more about how to design a
fully functioning high gain operational amplifier.

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Curtis Mayberry

Lab 5: Single Stage Differential Amplifier

choose upper bound, , in order to insure an accurate current mirror ratio of 1.

The final sizes, after tuning, turned out to be:

DC gain, GB product, Gain and Phase Plots

Figure 4: Gain bode plot

Linear Output Swing Range

Common Mode Rejection Ratio (CMRR)

Input Common Mode Range

Telescopic Differential Amplifier Design

Figure 12: Telescopic gain bode plot

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