Module-3.

2
Data-Processing Circuits and Flip- Flops

1
Books Referred
• Donald P Leach, Albert Paul Malvino & Goutam Saha: Digital
Principles and Applications, 7th Edition, Tata McGraw Hill, 2015
• Stephen Brown, Zvonko Vranesic: Fundamentals of Digital
Logic Design with VHDL, 2nd Edition, Tata McGraw Hill, 2005.

2
Objectives
• Determine the output of a multiplexer or demultiplexer based on
input conditions.
• Find, based on input conditions, the output of an encoder or
decoder.
• Draw the symbol and write the truth table for an exclusive-OR gate.
• Explain the purpose of parity checking.
• Show how a magnitude comparator works.
• Describe a PAL and PLA.
• Describe the half-adder, full-adder, and adder-subtractor.
• Describe how an Arithmetic Logic Unit can be operated.
• Describe the operation of the basic RS flip-flop and explain the
purpose of the additional input on the gated (clocked) RS flip-flop.
• Show the truth table for the edge-triggered. RS flip-flop, edge- 3
triggered D flip-flop and edge-triggered JK flip-flop.
DATA-PROCESSING CIRCUITS 4
MULTIPLEXERS-1
• Multiplex means many into one.
• A multiplexer (also called data selector) is a circuit with many
inputs but only one output. By applying control signals (Select
Input), can steer any input to the output.
• Below shows the block diagram of MUX. The circuit has n
input signals, m control signals and 1 output signal. Note that,
m control signals can select at the most 2m input signals thus n
≤ 2m .

5
MULTIPLEXERS-2
• The block diagram of
a 4-to-1 multiplexer
is shown below and
its truth table.
• Depending on control
inputs A, B one of the
four inputs Do to D3
is steered to output
Y.
6
MULTIPLEXERS-3
• 4-to-1 MUX logic
circuit
• Logic equation of this
circuit is a SOP
representation.

7
MULTIPLEXERS-4
• In other words, for AB = 00, the first AND gate to which D0 is
connected remains active and equal to Do and all other AND
gate are inactive with output held at logic 0.
• Thus, multiplexer output Y is same as D0. If D0 =0, Y=0 and if
D0 = 1, Y= 1.
• Commercial multiplexers ICs come in integer power of 2, e.g.
2-to-1, 4-to-1, 8-to- 1, 16-to-1 multiplexers.
• Write the 2 to 1 MUX block diagram, equation and it truth
table.

8
MULTIPLEXERS-5
• Write the 8 to 1 MUX block diagram, equation and it truth
table.

9
 MULTIPLEXERS-6
• IC 74151
D3 1 16 VCC

D2 2 15 D4
I
D1 3 C 14 D5
7
D0 4 13 D6
4
Y5 5 1 12 D7
5
Y5 6 11 S0
1
-Enable 7 10 S1

GND 8 9 S2

10
11
 MULTIPLEXERS-8
• Final Circuit diagram
0 04,D0 16,VCC
  Select Inputs  
Output
Y5 1 03,D1 08,GND
Minterm in
a b c d f
EVM
decimals Entry 02,D2 8:1
MUX
0 0 0 0 0 0 01,D3 I
0 1 0 (D0) C
0 0 0 1 0
7
2 15,D4 4 05,Y5
0 0 1 0 1 O/P
1 3 0 0 1 1 1 1 (D1) 1
14,D5 5
4 0 1 0 0 1 1
2 5 0 1 0 1 1 1 (D2)
13,D6
6 0 1 1 0 0
3 7 0 (D3) d 12,D7
0 1 1 1 0
8 1 0 0 0 X
4 9 X (D4)
1 0 0 1 X
0 07,E
10 1 0 1 0 X
5 11 1 0 1 1 X X (D5)
09,S2 10,S1 11,S0
12 1 1 0 0 0
6 13 d (D6)
1 1 0 1 1 12
14 1 1 1 0 0
7 15 d (D7)
1 1 1 1 1 a b c
MULTIPLEXERS-9
• Show how 4-to-1 multiplexer can be obtained using only 2-to-1 multiplexer.
• Logic equation for 2-to-1Multiplexer: Y= A’D0 + AD1
• Logic equation for 4-to-1 Multiplexer: Y = A'B' D0+ A'BD1 + AB' D2 + ABD3
• This can be rewritten as, Y= A'(B'D0 + BD1) +A (B'D2 + BD3)

13
MULTIPLEXERS-10
• Realize Y=A'B + B'C' + ABC using an 8-to-1 multiplexer.
• First we express Y as a function of minterms of three variables.
Thus
• Y = A'B + B'C' + ABC
• Y =A'B(C' + C)+B'C'(A' + A)+ ABC [As,X+X'= I]
• Y = A'B'C' + A'BC' + A'BC + AB'C' + ABC
• Comparing this with equation of 8 to 1 multiplexer, we find by
substituting D0 = D2 = D3 =D4 = D1 = 1 and D1 = D5 = D6 = 0.

14
MULTIPLEXERS-11
• Can it be realized above equation with a 4-to-1 multiplexer?
• The 4-to-1 multiplexer generates 4 minterms for different
combinations of AB. We rewrite given logic equation in such a
way that all these terms are present in the equation.
• Y =A'B+B'C' +ABC
• Y =A'B+ B'C'(A' +A)+ ABC [As,X +X' = I]
• Y =A'B'.C' + A'B.1 +AB'.C' + AB.C
• Compare above with equation of a 4-to-1 multiplexer. We see
D0= C', D1 = 1, D2 = C' andD3 = C generate the given logic
function.

15
MULTIPLEXERS-12
• Design a 32-to-1
multiplexer using two 16-
to-1 multiplexers and one
2-to-1 multiplexer.
• A 32-to-1 multiplexer
requires log232 =5 select
lines say, ABCDE. The Iower
4 select lines BCDE choose
16-to-1 multiplexer outputs.
The 2-to-1 multiplexer
chooses one of the output of
two 16-to-1 multiplexers
depending on what appears
in the 5th select line, A. 16
DEMULTIPLEXERS-1
• Demultiplex means one into many.
• A demultiplexer is a logic circuit with one input and many
outputs. By applying control signals, can steer the input signal
to one of the output lines. The circuit has 1 input signal, m
control or select signals and n output signals where n ≤ 2m.

17
DEMULTIPLEXERS-2
• For 1 to 2 DMUX
• The logic equation
• Y0 = DA’ Y1 = DA

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DEMULTIPLEXERS-3
• Write block diagram, truth table and logic equation of 1 to 4 DMUX.

• Y0 =
• Y1 = 19
• Y2 = S1
• Y3 = S1S0D
DEMULTIPLEXERS-4
• Write block diagram, truth table and log equation of 1 to 8
DMUX.

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DEMULTIPLEXERS-5
• Show how two 1-to-16
demultiplexers can be
connected to get a 1-
to-32 demultiplexer.
• A 1-to-32 demultiplexer
has 5 select veriable
ABCDE. Four of them
(BCDE) are fed to two 1-
to-16 DMUX. Fifth A
used to select the one
of these DMUX
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DECODER-1
• A decoder is similar to a demultiplexer, with one exception-there is no data
input.
• Also called binary-to-decimal decoder.
• The name decoder means translating of coded information from one format into
another.
• A binary decoder is a multi-input, multi-output combinational circuit that converts
a binary code of n input lines into a one out of 2n output code. 
• Depending on the number of input lines, the inputs of a binary code can be 2-bit
or 3-bit or 4-bit codes. Upon the availability of 2n lines, it activates the one of its
output by deactivating (making logic 0) all other input whenever it receives n
inputs.

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DECODER-2
• The most commonly used practical binary decoders are 2-to-4
decoder, 3-to-8 decoder and 4-to-16 line binary decoder.
• 2-to-4 decoder also called 1 of 4
• 3-to-8 decoder also called 1 of 8
• 4-to-16 line binary decoder also called 1 of 16

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DECODER-3
• 2-to-4 Binary Decoder (1 of 4 Decoder)

Input Output
A B Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0 24
1 1 0 0 0 1
 DECODER-4
• 3-to-8 Binary Decoder (1 of 8 Decoder)

A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
25
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
DECODER-5
• Similarly for 4 to 16 or 1 of 16 Decoder

26
DECODER-6
• Applications of Decoders
• Decoders are greatly used in applications where the particular output or group of outputs to be
activated only on the occurrence of a specific combination of input levels.
• Binary to Decimal Decoder
• Decoders are used to get the decimal digit corresponding to a specific input combination. A BCD
number needs 4 binary digits to represent the 0 to 9 decimal digits, thus it consists of 4 input
lines. It consists of 10 output lines corresponding to 0 to 9 decimal digits. (1 of 10 line decoder)
• Address Decoders
• Amongst its many uses, a decoder is widely used to decode the particular memory location in
the computer memory system. Decoders accept the address code generated by the CPU which
is a combination of address bits for a specific location in the memory. In a memory system, there
are several memory ICs are combined and each one has their unique address to distinguish from
other memory locations. In such cases a decoder built in the memory ICs circuitry, is used to
select a memory IC in response to a range of addresses by decoding the most significant bits of
the systems address, thereby a particular memory location or IC is selected.
• Instruction Decoder
• Another application of the decoder can be found in the control unit of the central processing
unit. This decoder is used to decode the program instructions in order to activate the specific
27
control lines such that different operations in the ALU of the CPU are carried out.
DECODER-7
• Show how using a 3-to-8 decoder and multi-input OR gates following Boolean
expressions can be realized simultaneously.
F1 (A, B, C) = ∑m(0, 4, 6);
F2(A, B, C) = ∑m(0, 5);
F3(A, B, C) = ∑m(1, 2, 3, 7)

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DECODER-8
• Implement a full adder circuit using a 3-to-8 line decoder.
• Sum output S = ∑m(1 2 4 7)
• Carry output Co= ∑m(3 5 6 7)

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DECODER-9
• BCD-TO-DECIMAL DECODERS (IC 7445)

30
DECODER-10
• Truth Table of 1 of 10 decoder

31
DECODER-11
• Circuit Connection

32
DECODER-12
• Seven Segment decoder

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DECODER-13
• 7446 decoder-driver

34
ENCODERS-1
• An encoder converts an active input signal into a coded output
signal.
• An encoder is a device which converts familiar numbers or
characters or symbols into a coded format. It accepts the
alphabetic characters and decimal numbers as inputs and
produces the outputs as a coded representation of the inputs.
• It is a combinational circuit that performs the opposite
function of a decoder.
• These are mainly used to reduce the number of bits needed to
represent given information.

35
ENCODERS-2
• Depending on the number of input lines, digital or binary encoders
produce the output codes in the form of 2 or 3 or 4 bit codes.
• An encoder is a multiplexer without its single output line.
• It is a combinational logic function that has 2n (or fewer) input lines
and n output lines, which correspond to n selection lines in a
multiplexer.
• The n output lines generate the binary code for the possible 2 n
input lines.

36
ENCODERS-3
• 4 – to – 2 Bit Binary Encoder

37
ENCODERS-4
• Decimal-to-BCD Encoder

38
ENCODERS-4
• Decimal-to-BCD Encoder
• Y3 = D8 + D9
• Y2 = D4 + D5 + D6 + D7
• Y1 = D2 + D3 + D6 + D7
• Y0 = D1 + D3 + D5 + D7 + D9

39
ENCODERS-5
• Priority Encoder
• A priority encoder is a practical form of an encoder. The
encoders available in IC form are all priority encoders.
• In this type of encoder, a priority is assigned to each input so
that, when more than one output is simultaneously active, the
input with the highest priority is encoded.
• Let us assume that the octal-to-binary encoder has an input
priority for higher-order digits.
• Let us also assume that input lines D2, D4 and D7 are all
simultaneously in logic ‘1’ state. In that case, only D7 will be
encoded and the output will be 111.
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ENCODERS-6
• Realize a logic circuit for Octal to Binary encoder.

41
EXCLUSIVE-OR GATES-1
• The exclusive-OR gate has a high output only when an odd
number of inputs is high.

• OR
• Y = A⨁B
42
EXCLUSIVE-OR GATES-2

43
EXCLUSIVE-OR GATES-2
• EX-NOR Gate
• Truth Table
A B Y
0 0 1
A
0 1 0 Y
B
1 0 0
1 1 1

• Y = A⨀B
• OR
• or
44
EXCLUSIVE-OR GATES-2
• Example

• We can write

45
EXCLUSIVE-OR GATES-3
• PARITY GENERATORS AND CHECKERS
• Even parity means an n-bit input has an even number of 1s.
For instance, 110011 has even parity because it contains four
1s.
• Odd parity means an n-bit input has an odd number of 1s. For
example, 110001 has odd parity because it contains three 1s.

46
EXCLUSIVE-OR GATES-4
• Parity Checker

47
EXCLUSIVE-OR GATES-5
• Parity Generation
• In a computer, a binary number may represent an instruction
that tells the computer to add, subtract, and so on; or the
binary number may represent data to be processed like a
number, letter, etc. In either case, you sometimes will see an
extra bit added to the original binary number to produce a
new binary number with even or odd parity.

48
EXCLUSIVE-OR GATES-6
• 9th -bit Shows Odd or
Even parity
• If X8=0 Indicate odd
parity
• X8=1 even parity

49
EXCLUSIVE-OR GATES-7
• Application
• Practical application of parity generation and checking
• Because of transients, noise, and other disturbances, 1-bit
errors sometimes occur when binary data is transmitted over
telephone lines or other communication paths.
• One way to check for errors is to use an odd-parity generator
at the transmitting end and an odd-parity checker at the
receiving end. If no 1-bit errors occur in transmission, the
received data will have odd parity.
• But if one of the transmitted bits is changed by noise or any
other disturbance, the received data will have even parity.
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EXCLUSIVE-OR GATES-8
• Lab Experiment
• Design and verify the Truth Table of 3-bit Parity Generator and 4-
bit Parity Checker using basic Logic Gates with an even parity bit.
• Parity Generator A
BC
00 01 11 10

Input Output 0 0 1 0 1

PG 1 1 0 1 0
A B C A B C
0 0 0 0 0 0 0 A=A
B=B
0 0 1 0 0 1 1
C=C
0 1 0 0 1 0 1
0 1 1 0 1 1 0
1 0 0 1 0 0 1
1 0 1 1 0 1 0
1 1 0 1 1 0 0
1 1 1 1 1 1 1
EXCLUSIVE-OR GATES-8
• Implementation using Basic Gates
A B C

PG

52
EXCLUSIVE-OR GATES-9
• Parity Checker AB
CP
00 01 11 10

A B C P PC
00 1 0 1 0
0 0 0 0 1
01 0 1 0 1
0 0 0 1 0
0 0 1 0 0 11 1 0 1 0
0 0 1 1 1
10 0 1 0 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
´
0 1 1 1 0 PC = [ ( A ⨁ B )⨁ C ] ⨁ P
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1 A
1 1 0 1 0
B
1 1 1 0 0
1 1 1 1 1
53
C
PC
P
EXCLUSIVE-OR GATES-9
• Implementation using Basic Gates
A B C P

PC
54
MAGNITUDE COMPARATOR-1
• Magnitude comparator compares magnitude two n-bit binary numbers.
• X and Y two 1-bit Input, then three outputs X = Y, X > Y and ,X < Y.
• The logic equations for the outputs can be written as follows, where G,
L, E stand for greater than, less than and equal to respectively.
(X> Y): G =XY' (X < Y): L =X'Y
(X= Y): E =X'Y' + XY = (XY' + X'Y)' = (G + L)'

55
MAGNITUDE COMPARATOR-2
• Design of a 2-bit comparator
• 4-variable (X: X1, X0 and Y: Y1,Y0) truth table and get logic
equations through any simplification technique like k-Map.
• But this procedure will become very complex when the
designing a comparator for 3-bit numbers or more.
• So from 1 -bit comparator we can write expression for greater
than, less than and equal terms.
• bit-wise greater than terms (G):G1 = X1 Y1’, Go= X0Y0'
• bit-wise less than term (L): L1 =X1'Y1, L0 =X0'Y0
• bit-wise equality term (E): E1 = (G1 + L1)', E0 =(G0+ L0)'

56
MAGNITUDE COMPARATOR-3
• bit-wise greater than terms (G) : G1 = X1 Y1’, Go= X0Y0'
• bit-wise less than term (L) : L1 =X1'Y1, L0 =X0'Y0
• bit-wise equality term (E) : E1 = (G1 + L1)' E0 =(G0+ L0)‘

• If X = Y when both the bits are equal then we can write:

(X= Y) = E1.E0
• X>Y if MSB of X1 is higher ( G1 = 1) than that of Y1. If MSB is
equal, given by E1 = 1, then LSB of X and Y is checked and if
found higher (G0 = 1) the condition X > Y is fulfilled so we can
write:
(X>Y) = G1+E1.G0
• Similarly for X<Y: 57
(X<Y) = L1+E1.L0
MAGNITUDE COMPARATOR-4
• X: Xn- 1 Xn-2 .. . X0 and Y: Yn-1 Yn-2 . .Y0
• We can write,
• (X= Y) = En-1.En-2···Eo
• (X> Y) = Gn-1 + En-1.Gn-2 + ... +En-1.En-2··· E1.G0
• (X < Y) = Ln-1 + En-1.Ln-2 + ... + En-1.En-2··· E1.L0
• where Ei, Gi and Li represent for ith bit Xi = Yi, Xi > Yi and Xi < Yi
terms respectively.

58
Programmable Logic Devices (PLDs)
• PROMs
• Programmable Array
Logic (PALs)
• Programmable logic
arrays (PLAs)

59
Programmable Array Logic (PAL)-1
• Programmable array logic (PAL) is a programmable array of
logic gates on a single chip. PALs are another design solution,
similar to a sum-of-products solution, product-of-sums
solution, and multiplexer logic.
• A PAL has a programmable AND array and a fixed OR array.

60
Programmable Array Logic (PAL)-2
• PAL with 4 inputs and
4 outputs
• In the x's on the
input side are fusible
links, while the solid
black bullets on the
output side are fixed
connections.

61
Programmable Array Logic (PAL)-2
• Actual Internal
Connection of AND
and OR Gate

62
Programmable Array Logic (PAL)-3
• Example of how to program a
PAL.

• The first desired product is

A’BC’D On the top input line in
figure shown
• Remove the first x, the fourth x,
the fifth x, and the eighth x.
• Then the top AND gate has an
output of A’BC’D 63
Programmable Logic Arrays (PLAs)-1
• Both its AND-gate
array and its OR-gate
array are fusible-linked
and programmable.
• A PLA having 3 input
variables (ABC) and 3
output variables (XYZ).
• There could be
additional OR gates at
the output if desired.
64
Programmable Logic Arrays (PLAs)-2
• An example, use a PLA to recognize each of the 10 decimal
digits represented in binary form and to correctly drive a 7-
segment display.
• Four bits (ABCD) are required to represent the 10 decimal
numbers. There must be 7 outputs (abcdefg), 1 output to drive
each of the 7 segments of the indicator.

65
Programmable Logic Arrays (PLAs)-3

66
Programmable Logic Arrays (PLAs)-4
• Implement the following Boolean
function using suitable PLA f1=
∑(0,1,4,6), f2= ∑(2,3,4,6,7), f3=
∑(0,1,2,6), f4= ∑(2,3,5,6,7)
• Draw a PLA circuit
simultaneously realize the
Boolean function Y3=A’BC’;
Y2=AC; Y1=AB’C+A’BC+ABC’;
Y0=A’BC’+A’BC+A’B’C’+ABC.
• Draw a PLA circuit
simultaneously realize the
Boolean function
X=A’B’C+AB’C’+B’C;
Y=A’B’C+AB’C’; Z=B’C.
• Design 7-segment decoder using 67
PLA.
HDL IMPLEMENTATION OF DATA
PROCESSING CIRCUITS-1
• The data flow model provides a different use of keyword
assign in the form of
assign X = S ? A : B;
• If, S = 1, X = A and if S = 0, X = B.

68
HDL IMPLEMENTATION OF DATA
PROCESSING CIRCUITS-2
Realize a 2 to 1 multiplexer using assing statement

module module
mux2to1(A,D0,D1,Y); mux2to1(A,D0,D1,Y);
input A,DO,D1; input A,D0,D1;
output Y; output Y;
assign Y=(~A&D0) I (A&D1); assign Y= A? D1:DO;
endmodule /*Conditional
assignment*/
endmodule
69
HDL IMPLEMENTATION OF DATA
PROCESSING CIRCUITS-3
2 to 1 MUX using the behavioural model using if ... else statement and using
case statement.
module module mux2to1(A,D0,D1,Y);
mux2to1(A,D0,D1,Y); input A,D0,D1;
input A,D0,D1; output Y;
output Y; reg Y;
reg Y; always@ (A or D0 or D1)
case (A)
always@ (A or D0 or D1)
0 : Y=D0;
if (A==1) Y=D1;
1 : Y=D1;
else Y=D0; endcase
endmodule endmodule 70
HDL IMPLEMENTATION OF DATA
PROCESSING CIRCUITS-4
• Design a 4 to 1 multiplexer, using conditional ‘assign’ and
‘case’ statements.
• We can use nested condition for assign statement.
• If A=1, condition ( B ? D3:D2) is evaluated.
• Then if B = 1, Y=D3.
• Similarly, the other combinations of A and B are evaluated and
Y is assigned a value from D2 to D1.

• For case statement concatenate A and B by using operator {...}

and generated four possible combinations, For a particular
value of AB.
71
HDL IMPLEMENTATION OF DATA
PROCESSING CIRCUITS-5
Using assign Using case
module mux4to1 module mux4tol(A,B,DO,Dl,D2,D3,Y);
input A,B,DO,Dl,D2,D3;
(A,B,DO,Dl,D2,D3,Y);
output Y;
input A,B,DO,Dl,D2,D3 reg Y;
output Y; always @(A or B or DO or Dl or D2 or D3)
case ({A,B})
assign Y = A?(B?D3:D2):(B?D1:D0); 0: Y=D0;
endmodule 1: Y=D1;
2: Y=D2;
3: Y=D3;
endcase
endmodule
72
HDL IMPLEMENTATION OF DATA
PROCESSING CIRCUITS-6
• BUS Representation in HDL
• BUS or vector representation in HDL
• Consider S as a select input defined by two binary digits S[1]
and S[0]
• Written in HDL as [1:0] S
• Output Y is 4 bit long, one of which goes high for a particular
combination of select inputs if data( enable) input is high.
• Written in HDL as [3:0] Y

73
HDL IMPLEMENTATION OF DATA
PROCESSING CIRCUITS-7
• Design of a 1 to 4 demultiplexer
module demuxlto4(S,D,Y);
input [1:0] S;
input D;
output [3:0] Y;
reg [3:0]Y;
always @ (S or D)
case ({D,S}) //Concatenation of D and S to give 3 bits, D is MSB
3'b100:Y=4'b0001; // If D=1, S=00, Y=0001
3'b101:Y=4'b0010;
3'b110:Y=4'b0100;
3'b111:Y=4'b1000;
default: Y= 4'b0000; //For other combinations D=0, then Y=0000
endcase 74
endmodule
HDL IMPLEMENTATION OF DATA
PROCESSING CIRCUITS-8
• A verilog HDL code for a digital circuit is given as follows. Can you
describe the function it performs?
module unknow (A,B,C,Y);
input [3:0] A,B;
input [2:0] C;
output [2:0] Y;
reg [2:O] Y;
always @ (A or B or C)
if (A<B) Y=3'b001;
else if (A>B) Y=3'b010;
else Y=C;
endmodule
• HDL compares two 4-bit numbers A and B and generates a 3 bit 75
output Y.
Arithmetic Building Blocks-1
• Objective
• Describe the half-adder, full-adder, and adder-subtractor.
• Describe how an Arithmetic Logic Unit can be operated.

76
Arithmetic Building Blocks-2
• Half-Adder
• When we add two binary numbers, we start with the least
significant column. This means that we have to add two bits
with the possibility of a carry. The circuit used for this is called
a half-adder.

77
Arithmetic Building Blocks-2
• Full-Adder
• A full-adder, a logic circuit that can add 3 bits at a time

78
Arithmetic Building Blocks-3
• Controlled Inverter

79
Arithmetic Building Blocks-4
• A Low INVERT produces
• Y1···Yo=0110 1110
• But a High INVERT results in
• Y1 ... Yo= 1001 0001
• During a subtraction, we first need to take the 2's complement
of the subtrahend. Then we can add the complemented
subtrahend to obtain the answer.
• With a controlled inverter, we can produce the 1's
complement. There is an easy way to get the 2 's complement.

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ARITHMETIC LOGIC UNIT-1
• ALU is an integral part of central processing unit or CPU of a
computer. It comes in various forms with wide range of
functionality.
• Like normal addition, subtraction, increment, decrement
operations.
• As logic unit it performs usual AND, OR, NOT, EX-OR and many
other complex logic functions.
• It also comes with PRESET and CLEAR options, invoking which
all the function outputs are made 1 and 0 respectively.
• Normally, a mode selector input (M) decides whether ALU
performs a logic operation or an arithmetic operation.
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