Microelectronics: Jun-Hong Weng

Microelectronics
Chapter 7 CMOS Amplifiers
Jun-Hong Weng
Tunghai University
Department of Electrical Engineering
Chapter 7 CMOS Amplifiers
 7.1 General Considerations
 7.2 Common-Source Stage
 7.3 Common-Gate Stage
 7.4 Source Follower
 7.5 Summary and Additional Examples
Microelectronics jhw@ thu.edu.tw

MOS Biasing MOS 偏壓=固定電壓
𝑅2
利用分壓 V𝑋 = 𝑅 𝑉𝐷𝐷 ………………………(1)
1 +𝑅2
利用跨壓 V𝑋 = 𝑉GS + 𝑉RS = 𝑉GS + ID R S ………(2)
逆 1 =(2)
+V 2𝑅2
GS - 𝑉GS = − 𝑉1 − 𝑉𝑇𝐻 + 𝑉12 + 2𝑉1 ( 𝑉 − 𝑉𝑇𝐻 )
𝑅1 + 𝑅2 𝐷𝐷
1
𝑉1 =
𝑊
𝜇𝑛 𝐶𝑜𝑥 𝐿 𝑅𝑆
M1 Saturation V𝑌 > V𝑋 − V𝑇𝐻 (一順一逆)
 Voltage at X is determined by VDD, R1, and R2.

 VGS can be found using the equation above, and ID can be found by
using the NMOS current equation.

MOS Biasing
𝑅2
利用分壓 V𝑋 = 𝑅 𝑉𝐷𝐷 ………………………(1)
1 +𝑅2
利用跨壓 V𝑋 = 𝑉GS + 𝑉RS = 𝑉GS + ID R S ………(2)

1 =(2)
𝑅2
𝑉 =𝑉GS + ID R S 𝑀1 Saturation
𝑅1 +𝑅2 𝐷𝐷
+V 𝑅2 1 1 𝑊
GS - ⇒ 𝑉𝐷𝐷 −𝑉GS = 𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2
𝑅1 + 𝑅2 𝑅𝑆 2 𝐿
𝑅2 1 𝑊
⇒ 𝑉𝐷𝐷 −𝑉GS = 𝜇𝑛 𝐶𝑜𝑥 𝑅𝑆 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2
𝑅1 + 𝑅2 2 𝐿
𝑅2 𝑊
⇒2 𝑉𝐷𝐷 −𝑉GS = 𝜇𝑛 𝐶𝑜𝑥 𝑅𝑆 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2
𝑅1 + 𝑅2 𝐿
2𝑅2 𝑊
⇒ 𝑉𝐷𝐷 −2𝑉GS = (𝜇𝑛 𝐶𝑜𝑥 𝑅𝑆 )(𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2
𝑅1 + 𝑅2 𝐿
𝑊 2𝑅2
⇒ (𝜇𝑛 𝐶𝑜𝑥 𝑅𝑆 )(𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 +2𝑉GS − 𝑉 =0
𝐿 𝑅1 + 𝑅2 𝐷𝐷

MOS Biasing
2
1 2𝑅2 1
⇒ (𝑉𝐺𝑆 − 𝑉𝑇𝐻 ) +2𝑉GS − 𝑉𝐷𝐷 =0
𝑊 𝑅 1 + 𝑅2 𝑊
(𝜇𝑛 𝐶𝑜𝑥 𝐿 𝑅𝑆 ) (𝜇𝑛 𝐶𝑜𝑥 𝐿 𝑅𝑆 )
2 2 1 2𝑅2 1
⇒ 𝑉𝐺𝑆 − 2𝑉𝐺𝑆 𝑉𝑇𝐻 + 𝑉𝑇𝐻 +2𝑉GS 𝑊 − 𝑅 +𝑅 𝑉𝐷𝐷 𝑊 =0
𝜇𝑛 𝐶𝑜𝑥 𝐿 𝑅𝑆 1 2 (𝜇𝑛 𝐶𝑜𝑥 𝐿 𝑅𝑆 )
2
1 2
2𝑅2 1
⇒ 𝑉𝐺𝑆 +2 − 𝑉𝑇𝐻 𝑉GS + 𝑉𝑇𝐻 − 𝑉𝐷𝐷 =0
𝑊 𝑅1 + 𝑅2 𝑊
𝜇𝑛 𝐶𝑜𝑥 𝐿 𝑅𝑆 (𝜇𝑛 𝐶𝑜𝑥 𝐿 𝑅𝑆 )
1 1 2 2 2𝑅2 1
取正 −2 𝑊 − 𝑉𝑇𝐻 + 4( 𝑊 − 𝑉𝑇𝐻 ) − 4(𝑉𝑇𝐻 − 𝑅1 + 𝑅2 𝑉𝐷𝐷 𝑊 )
𝜇𝑛 𝐶𝑜𝑥 𝑅𝑆 𝜇𝑛 𝐶𝑜𝑥 𝑅𝑆 𝜇𝑛 𝐶𝑜𝑥 𝑅𝑆
𝐿 𝐿 𝐿
⇒ 𝑉GS =
2
1 1 2 2𝑅2 1
=− 𝑊 − 𝑉𝑇𝐻 + ( 𝑊 − 𝑉𝑇𝐻 )2 − 𝑉𝑇𝐻 + 𝑉𝐷𝐷 𝑊 )
𝜇𝑛 𝐶𝑜𝑥 𝑅𝑆 𝜇𝑛 𝐶𝑜𝑥 𝑅𝑆 𝑅1 +𝑅2 𝜇𝑛 𝐶𝑜𝑥 𝑅𝑆
𝐿 𝐿 𝐿
1 1 1 2 2 2𝑅2 1
=− − 𝑉𝑇𝐻 + )2 − 2 𝑉𝑇𝐻 + 𝑉𝑇𝐻 − 𝑉𝑇𝐻 + 𝑉
𝑊
𝜇𝑛 𝐶𝑜𝑥 𝑅𝑆
𝑊
𝑊
𝜇𝑛 𝐶𝑜𝑥 𝑅𝑆 𝑅1 +𝑅2 𝐷𝐷 𝜇𝑛 𝐶𝑜𝑥 𝑊𝑅𝑆
𝐿 𝐿 𝐿 𝐿
1 1 1 2𝑅2
=− − 𝑉𝑇𝐻 + ( )2 + 2 ( 𝑉 − 𝑉𝑇𝐻 )
𝑊
𝑊
𝑊
𝜇𝑛 𝐶𝑜𝑥 𝑅𝑆 𝑅1 +𝑅2 𝐷𝐷
𝐿 𝐿 𝐿

Example
求當M1 維持飽和時，R D 之最大值。VTH =

0.5𝑉, 𝜇𝑛 𝐶𝑜𝑥 = 100 𝜇𝐴Τ𝑉 2 , 𝑊 Τ𝐿 = 5Τ0.18 且𝜆 = 0。
4kΩ 必會:MOS飽和→一順一逆，飽和電流公式
Sol:方法1(直接解)
𝑅 10
步驟1.V𝑋 = 2 𝑉𝐷𝐷 = × 1.8 = 1.2857
𝑅1 +𝑅2 10+4
步驟2.V𝑋 = 𝑉GS + 𝑉RS = 𝑉GS + ID R S
1 𝑊
10kΩ 1kΩ =𝑉GS + 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 𝑅𝑆
2 𝐿
=𝑉GS +1388.889(𝑉𝐺𝑆 − 0.5)2 × 1000
Razavi 7.1 2
步驟3. 1.2857 = 𝑉GS + 1.3888(𝑉𝐺𝑆 − 𝑉𝐺𝑆 + 0.25)
2 V 1.2857
⟹ 𝑉𝐺𝑆 -𝑉𝐺𝑆 + 0.25 + GS =
1.3888 1.3888
2
⟹ 𝑉𝐺𝑆 -𝑉𝐺𝑆 + 0.72𝑉𝐺𝑆 + 0.25 = 0.9257
2
⟹ 𝑉𝐺𝑆 -0.28𝑉𝐺𝑆 -0.6757=0
0.28± 0.282 +4×0.6757
⟹ 𝑉𝐺𝑆 = (取正)
2
⟹ 𝑉𝐺𝑆 =0.97384≅ 0.974
Example
𝑉𝑅𝑆 V −𝑉
步驟4.𝐼𝐷 = = 𝑋 GS
𝑅𝑆 𝑅𝑆
1.2857−0.974
= = 3.117 × 10−4 ≅ 312𝜇𝐴
1𝐾
4kΩ 步驟5.V𝑌 = 𝑉𝑋 − 𝑉𝑇𝐻
1.2857 = 1.22857 − 0.5 = 0.7857 ≅ 0.786
𝑉 −𝑉 1.8−0.786 1.014(𝑉)
步驟6. 𝑅𝐷 = 𝐷𝐷 𝑌 = = = 3250 Ω
I𝐷 312𝜇(𝐴) 312𝜇(𝐴)
0.974 = 3.25𝑘Ω
10kΩ 1kΩ
Razavi 7.1

Example

Sol:方法2(用公式解等同方法1)
步驟1.
2𝑅2
𝑉GS = − 𝑉1 − 𝑉𝑇𝐻 + 𝑉12+ 2𝑉1 ( 𝑉 − 𝑉𝑇𝐻 ) ≅ 0.974
𝑅1 + 𝑅2 𝐷𝐷
10kΩ 1kΩ 1 1
𝑉1 = =
𝑊
Razavi 7.1 𝜇𝑛 𝐶𝑜𝑥 𝐿 𝑅𝑆 100 × 5/0.18 × 10000
步驟2.
𝑉 V −𝑉 1.2857−0.974 −4 ≅ 312𝜇𝐴
𝐼𝐷 = 𝑅𝑅𝑆 = 𝑋𝑅 GS= = 3.117 × 10
𝑆 𝑆 1𝐾
步驟3.V𝑌 = 𝑉𝑋 − 𝑉𝑇𝐻
𝑉𝐷𝐷 −𝑉𝑌
步驟4.. 𝑅𝐷 = = 3.25𝑘Ω
I𝐷

Example

Sol:方法3(疊代法)
步驟1.
𝑅2 10
V𝑋 = 𝑅 +𝑅 𝑉𝐷𝐷 = 10+4 × 1.8 = 1.2857 ≅1.286
1 2
步驟2.
10kΩ 1kΩ 假設VGS1 =1V⇒ 𝑉𝑅𝑆 = 𝑉𝑋 − 𝑉𝐺𝑆1 = 1.286 − 1 = 0.286(𝑉)
⟹ 𝐼𝐷1 = 𝑉𝑅𝑆 Τ𝑅𝑠
Razavi 7.1 = 286(𝑚𝑉)/1(𝑘Ω)=286 × 10−6 = 286𝜇𝐴
1 𝑊
步驟3. 將𝐼𝐷1 代入飽和區電流公式𝐼𝐷 = 2 𝜇𝑛 𝐶𝑜𝑥 𝐿 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 ，
驗證VGS 是否符合假設值(VGS1 =1V)
1 𝑊
𝐼𝐷1 = 2 𝜇𝑛 𝐶𝑜𝑥 𝐿 (𝑉𝐺𝑆2 − 𝑉𝑇𝐻 )2 ⟹ 𝑉𝐺𝑆2 = 0.954 V
步驟4.. 因𝑉𝐺𝑆2 ≠ 𝑉𝐺𝑆1 不相等，所以利用𝑉𝐺𝑆2 再算一次電流(𝐼𝐷2 )

Example

Sol:方法3(疊代法)
步驟4.. 因𝑉𝐺𝑆2 ≠ 𝑉𝐺𝑆1 不相等，所以利用𝑉𝐺𝑆2 再算一次電流(𝐼𝐷2 )
𝑉𝐺𝑆2 = 0.954 V ⟹ 𝐼𝐷2 = (𝑉𝑋 −𝑉𝑅𝑆 )Τ𝑅𝑠 = 332 𝜇𝐴
1 𝑊
步驟5. 將𝐼𝐷1 代入飽和區電流公式𝐼𝐷 = 2 𝜇𝑛 𝐶𝑜𝑥 𝐿 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 ，
10kΩ 1kΩ 驗證VGS3 是否符合假設值(VGS2 =0.954V)
1 𝑊
𝐼𝐷2 = 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆3 − 𝑉𝑇𝐻 )2 ⟹ 𝑉𝐺𝑆3 = 0.989 V
2 𝐿
Razavi 7.1 步驟6.. 因𝑉𝐺𝑆3 ≠ 𝑉𝐺𝑆2 不相等，所以利用𝑉𝐺𝑆3 再算一次電流(𝐼𝐷3 )
𝑉𝐺𝑆3 = 0.989 V ⟹ 𝐼𝐷3 = (𝑉𝑋 −𝑉𝑅𝑆 )Τ𝑅𝑠 = 297 𝜇𝐴
步驟7.V𝑌 = 𝑉𝑋 − 𝑉𝑇𝐻 =1.286-0.5=0.786
𝑉𝐷𝐷 −𝑉𝑌 1.8−0.786

步驟8. 𝑅𝐷 = = = 3.41𝑘Ω
I𝐷 297 𝜇𝐴

Example
當M1 維持飽和時，R D =2.5kΩ。求(a) 𝑊 Τ𝐿 最大值

; (b)當 𝑊 Τ𝐿 = 5Τ0.18 , R𝑆 之最小值。
2.5kΩ
𝑉𝑇𝐻 = 0.5𝑉, 𝜇𝑛 𝐶𝑜𝑥 = 100 𝜇𝐴Τ𝑉 2 且𝜆 = 0。
4kΩ
Sol:
(a)
𝑅2 10
步驟1.. V𝑋 = 𝑅 +𝑅 𝑉𝐷𝐷 =10+4 × 1.8 = 1.2857=1.286
1 2
V𝐷𝐷 −𝑉𝑌
𝐼𝐷 = = 406 𝜇𝐴
1kΩ 𝑅𝐷
10kΩ
步驟2.V𝑅𝑆 = 𝑅𝑆 𝐼𝐷 = 406 𝑚𝑉 ⟹ 𝑉𝐺𝑆 = 1.286 − 0.406 = 0.88 𝑉
1 𝑊
Razavi 7.2 步驟3. 𝐼𝐷 = 2 𝜇𝑛 𝐶𝑜𝑥 𝐿 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 ⟹ 𝑊 Τ𝐿 = 56.2
(b)
步驟1.當 𝑊 Τ𝐿 = 5Τ0.18 , 𝐼𝐷 = 406 𝜇𝐴
1 𝑊
⟹ 𝐼𝐷 = 2 𝜇𝑛 𝐶𝑜𝑥 𝐿 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 ⟹ 𝑉𝐺𝑆 = 1.041 𝑉
步驟2.𝑉𝑋 − 𝑉𝐺𝑆 =245mV
𝑉 −𝑉
步驟3. 𝑅𝑠 = 𝑋 I 𝐺𝑆 = 604Ω
𝐷

Self-Biased MOS Stage
𝑉𝐷𝐷 = 𝐼𝐷 𝑅𝐷 + 𝑉𝐺𝑆 + 𝐼𝐷 𝑅𝑆
當𝑅𝐷 = 1𝑘Ω, 𝑅𝐺 = 20𝑘Ω, 𝑅𝑆 = 200Ω, 𝑉𝑇𝐻 =
𝐼𝐷
0.5𝑉, 𝜇𝑛 𝐶𝑜𝑥 = 100 𝜇𝐴Τ𝑉 2 且𝜆 = 0,(a)
(a)求M1 電流;(b)當ID 減少2倍, R D 為何?
I=0 Sol:
(a)利用MOS飽和區電流公式&跨壓
Razavi 7.3 (b)同(a)利用MOS飽和區電流公式&跨壓
 The circuit above is analyzed by noting M1 is in saturation and no

potential drop appears across RG.

Current Sources
(a)&(b)可當電流源，為何? 飽和區電流公式
1.當電流源⇒電流穩定 1 𝑊
2. (a)&(b)的電流有無穩定? 𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2
2 𝐿
(c)&(d)可當電流源，為何?
3.當電流源⇒電流穩定
4. (c)&(d)的電流有無穩定?
 When in saturation region, a MOSFET behaves as a current
source.
 NMOS draws current from a point to ground (sinks current),
whereas PMOS draws current from VDD to a point (sources
current).
Common-Source Stage
𝑉𝑖𝑛 = 𝑉1
𝑔𝑚
𝑉𝑜𝑢𝑡
𝐴𝑉 = = 𝑔𝑚 𝑅𝐿
𝑉𝑖𝑛
𝐴𝑉 =𝑔𝑚 𝑅𝐿 =𝑔𝑚 𝑅𝐷 ⟹ 𝐴𝑉 = −𝑔𝑚 𝑅𝐷
讓𝑀1 維持飽和的條件:
VDS ≥ VGS − 𝑉𝑇𝐻 𝑊
𝑔𝑚 = 2𝜇𝑛 𝐶𝑜𝑥 ( )𝐼𝐷
⟹ 𝑉𝑜𝑢𝑡 ≥ 𝑉𝐺𝑆 − 𝑉𝑇𝐻 𝐿
⟹ 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 ≥ V𝑖𝑛 − 𝑉𝑇𝐻

Operation in Saturation
當𝐼𝐷 = 1𝑚𝐴，VTH = 0.5𝑉, 𝜇𝑛 𝐶𝑜𝑥 = 100 𝜇𝐴Τ𝑉 2 且𝜆 = 0。

證明M1 工作於Saturation，並求AV =?
Sol:(a)
1 𝑊 2𝐼𝐷
𝐼𝐷 = 2 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 ⟹ 𝑉𝐺𝑆 = 𝑊 +𝑉𝑇𝐻
𝐿 𝜇𝑛 𝐶𝑜𝑥 𝐿
⟹ 𝑉𝐺𝑆 = 1.1V
Razavi 7.4 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 = 0.8
𝑉𝐺𝑆 − 𝑉𝑇𝐻 = 0.6𝑉 ⟹ 𝑉𝐷𝑆 ≥ 𝑉𝐺𝑆 − 𝑉𝑇𝐻 ⟹ Sat.區
(b)
1 𝑊
𝜕𝐼𝐷 𝜕[2𝜇𝑛 𝐶𝑜𝑥 𝐿 (𝑉𝐺𝑆 −𝑉𝑇𝐻 )2 ] 𝑔𝑚
𝑔𝑚 = = ⟹ 𝑉𝐺𝑆 − 𝑉𝑇𝐻 = 𝑊 代入飽和區電流公式
𝜕𝑉𝐺𝑆 𝜕𝑉𝐺𝑆 𝜇𝑛 𝐶𝑜𝑥 𝐿
1 𝑊 1 𝑊 𝑔 𝑊 1
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 = 𝜇𝑛 𝐶𝑜𝑥 ( 𝑚 𝑊)2 ⟹ 𝑔𝑚 = 2𝜇𝑛 𝐶𝑜𝑥 ( )𝐼𝐷 =
2 𝐿 2 𝐿 𝜇𝑛 𝐶𝑜𝑥 𝐿 300Ω
𝐿
𝐴𝑉 = −𝑔𝑚 𝑅𝐷 =3.33

CS Stage
VDD
=0
VDD
0
RL
RL Rout
Rout
Vout
Vout Vin
Vin
ro
Rin
Rin Vin=V1
Av   g m RL Av   g m RL || rO 
Rin   Rin  
Rout  RL Rout  RL || rO

CS Stage with Current-Source Load
為何可以當電流源?⟹ VGS 固定
𝑟𝑜𝑝
𝑟𝑜𝑝
𝑟𝑜𝑛 當從Drain看電阻時，通常𝜆 ≠0
⟹ 𝑟𝑜 (𝑟𝑜 ≠ 𝑅𝑜𝑛 ) 𝑟𝑜𝑛
Av   g m1 rOP || rON 
Rout  rOP || rON
 To alleviate the headroom problem, an active current-source load
is used.
 This is advantageous because a current-source has a high output
resistance and can tolerate a small voltage drop across it.

PMOS CS Stage with NMOS as Load
哪一顆當電流源?(為何?) ⟹ M1 ，VGS 固定
哪一顆輸入訊號?⟹ M2 ⟹ 𝑔𝑚2
𝑟𝑜𝑝 𝑅𝑜𝑢𝑡
𝑟𝑜𝑛 當從Drain看電阻時，通常𝜆 ≠0 ⟹ 𝑟𝑜
𝑅𝑜𝑢𝑡 = 𝑟𝑜𝑝 ∥ 𝑟𝑜𝑛
𝐴𝑉 = −𝑔𝑚 𝑅𝐿 = −𝑔𝑚2 𝑅𝑜𝑢𝑡 =−𝑔𝑚2 (𝑟𝑜𝑝 ∥ 𝑟𝑜𝑛 )
 Similarly, with PMOS as input stage and NMOS as the load, the
voltage gain is the same as before.

CS Stage with Diode-Connected Load
𝑟𝑜2
R 𝑈𝑃 R 𝑈𝑃 R 𝑈𝑃
R 𝑑𝑜𝑤𝑛
𝑟𝑜1
≠0⟹ 𝑟𝑜
=0⟹無𝑟𝑜 𝐴𝑉 = −𝑔𝑚 𝑅𝐿
𝐴𝑉 = −𝑔𝑚 𝑅𝐿
𝐴𝑉 = −𝑔𝑚 𝑅𝐿 = −𝑔𝑚1 𝑅𝑈𝑃 = −𝑔𝑚1 (𝑅𝑈𝑃 ∥ 𝑅𝑑𝑜𝑤𝑛 )
1
= −𝑔𝑚1 𝑅𝑈𝑃 1 = −𝑔𝑚1 [ ∥ 𝑟𝑜2 ∥ 𝑟𝑜1 ]
1 = −𝑔𝑚1 𝑔𝑚2
= −𝑔𝑚1 𝑔𝑚2
𝑔𝑚2 𝐼𝐶1 1 1. 當MOS接成Diode時MOS視為
= − 1
(𝑊Τ𝐿)1 𝑉𝑇 𝐼𝐶2 Τ𝑉𝑇 電阻，通常是R 𝑜𝑛 = 𝑔
=− ≅1 𝑚
𝑊Τ𝐿)2
2. 當從Drain看電阻時，
通常𝜆 ≠0 ⟹ 𝑟𝑜

CS Stage with Diode-Connected PMOS Device
≠0⟹ 𝑟𝑜
𝐴𝑉 = −𝑔𝑚 𝑅𝐿
= −𝑔𝑚2 (𝑅𝑈𝑃 ∥ 𝑅𝑑𝑜𝑤𝑛 )
R 𝑈𝑃 1
= −𝑔𝑚2 [ 𝑟𝑜2 ∥ ( ∥ 𝑟𝑜1 )]
R 𝑑𝑜𝑤𝑛 𝑔𝑚1
當MOS接成Diode時MOS視為電阻，
1
通常是R 𝑜𝑛 = 𝑔
𝑚
Razavi 7.7
 Note that PMOS circuit symbol is usually drawn with the source
on top of the drain.

CS Stage with Degeneration
𝐺𝑚
當=0⟹無𝑟𝑜
口訣: 𝑣𝑖𝑛 = 𝑣1 + 𝑔𝑚 𝑣1 𝑅𝑆
Source端有電阻時， 𝑣𝑜𝑢𝑡 = −𝑔𝑚 𝑣1 𝑅𝐷
AV = −G𝑚 𝑅𝐿 中 𝑣𝑜𝑢𝑡 −𝑔𝑚 𝑣1 𝑅𝐷 −𝑔𝑚 𝑣1 𝑅𝐷
= =
𝐺𝑚 縮小
1 𝑣𝑖𝑛 𝑣1 + 𝑔𝑚 𝑣1 𝑅𝑆 𝑣1 (1 + 𝑔𝑚 𝑅𝑆 )
(1+𝑔𝑚 𝑅𝑆 ) −𝑔𝑚 𝑅𝐷
= = −𝐺𝑚 𝑅𝐷
(1+𝑔𝑚 𝑅𝑆 )
 Similar to bipolar counterpart, when a CS stage is degenerated, its
gain, I/O impedances, and linearity change.

Example of CS Stage with Degeneration
𝑣𝑜𝑢𝑡 𝑔𝑚1 𝑔𝑚1

= −𝐺𝑚 𝑅𝐿 = − 𝑅𝐷 = − 𝑅𝐷
𝑣𝑖𝑛 1 + 𝑔𝑚1 𝑅𝑆 1
(1 + 𝑔𝑚1 )
1 𝑔𝑚2
𝑅𝐿 = 𝑅𝐷 ，𝑅𝑆 =
𝑔𝑚2
 A diode-connected device degenerates a CS stage.

CS Stage with Gate Resistance
當≠0⟹有𝑟𝑜
R 𝑈𝑃 RL
R 𝑑𝑜𝑤𝑛
V𝑖𝑛
𝑣𝑜𝑢𝑡 −𝑔𝑚 𝑅L 口訣:

= −𝐺𝑚 𝑅L = 1. Source端有電阻時，
𝑣𝑖𝑛 (1 + 𝑔𝑚 𝑅𝑆 ) AV = −G𝑚 𝑅𝐿 中
𝑅𝐿 = 𝑅𝑈𝑃 ∥ 𝑅𝑑𝑜𝑤𝑛 𝐺𝑚 縮小
1
(1+𝑔𝑚 𝑅𝑆 )
𝑅𝑑𝑜𝑤𝑛 = 𝑟𝑜 + (1 + 𝑔𝑚 𝑟𝑜 )𝑅𝑆 2.MOS有𝑟𝑜 又Source端有電阻時，
𝑣𝑜𝑢𝑡 −𝑔𝑚 𝑅L 電阻放大 1 + 𝑔𝑚 𝑟𝑜
⇒ = −𝐺𝑚 𝑅L =
𝑣𝑖𝑛 (1 + 𝑔𝑚 𝑅𝑆 )
𝑔𝑚
=− {𝑅𝑈𝑃 ∥ 𝑟𝑜 + 1 + 𝑔𝑚 𝑟𝑜 𝑅𝑆 }
1 + 𝑔𝑚 𝑅𝑆
Output Impedance of CS Stage with Degeneration
MOS有𝑟𝑜 又Source端有電阻時，推導
1. 𝑉𝑋 = 𝑉1 + 𝑉𝑅𝑠 =𝑉1 +(𝑖𝑟𝑜 𝑅𝑠 )
2. 𝑖𝑋 = 𝑖𝑟𝑜 + 𝑔𝑚 𝑉1
𝑖𝑟𝑜 3. 𝑉1 = −𝑖𝑋 𝑅𝑠
4. 𝑟𝑜 電流
𝑖𝑟𝑜 = 𝑖𝑋 − 𝑔𝑚 𝑉1 = 𝑖𝑋 − 𝑔𝑚 −𝑖𝑋 𝑅𝑠
=𝑖𝑋 + 𝑔𝑚 𝑖𝑋 𝑅𝑠 = 𝑖𝑋 + 𝑖𝑋 𝑔𝑚 𝑅𝑆
𝑉 (𝑉 +𝑉 )
5. 𝑅𝑋 = 𝑋 = 1 𝑅𝑠
𝑖𝑋 𝑖𝑋
𝑖𝑋 𝑅𝑠 +(𝑖𝑋 +𝑖𝑋 𝑔𝑚 𝑅𝑆 )𝑟𝑜
=
𝑖𝑋
=𝑅𝑆 + 𝑟𝑜 +𝑔𝑚 𝑅𝑆 𝑟𝑜
=𝑟𝑜 +(1+𝑔𝑚 𝑟𝑜 ) 𝑅𝑆
 Similar to the bipolar counterpart, degeneration boosts output

impedance.

Output Impedance Example (I)
當≠0⟹ 𝑟𝑜
𝑅𝑠
Razavi 7.9
1 1
1. 𝑅𝑠 有和𝑟𝑜 ⟹ 𝑅𝑠 = ∥ 𝑟𝑜2
𝑔𝑚 𝑔𝑚2
2. 𝑅𝑠 電阻放大 1 + 𝑔𝑚 𝑟𝑜
𝑅𝑜𝑢𝑡 =𝑟𝑜 +(1+𝑔𝑚 𝑟𝑜 ) 𝑅𝑆
1
=𝑟𝑜1 +(1+𝑔𝑚1 𝑟𝑜1 ) 𝑅𝑆 ==𝑟𝑜1 +(1+𝑔𝑚1 𝑟𝑜1 )( ∥ 𝑟𝑜2 )
𝑔𝑚2
 When 1/gm is parallel with rO2, we often just consider 1/gm.

CS Core with Biasing
V𝐺 V𝐺 V𝐺
訊號遇電容短路
⟹ 耦合電容
𝑅𝑖𝑛 = 𝑅1 ∥ 𝑅2 𝑅𝑖𝑛 = 𝑅𝐺 + (𝑅1 ∥ 𝑅2 )
𝑉𝐺 = 𝑉𝑖𝑛 𝑅𝑖𝑛 = 𝑅1 ∥ 𝑅2 (𝑅1 ∥ 𝑅2 )
𝑉𝐺 = 𝑉𝑖𝑛 𝑉𝐺 = 𝑉𝑖𝑛 ×
𝑉𝑜𝑢𝑡 𝑅𝐺 + (𝑅1 ∥ 𝑅2 )
𝐴𝑉 = 𝑉𝑜𝑢𝑡 𝑉𝑜𝑢𝑡 𝑉𝑜𝑢𝑡 𝑉𝐺
𝑉𝑖𝑛 𝐴𝑉 = = −𝑔𝑚 𝑅𝐷 𝐴𝑉 = = ×
𝑔𝑚
=− 𝑅𝐷 𝑉𝑖𝑛 𝑉𝑖𝑛 𝑉𝐺 𝑉𝑖𝑛
1+𝑔𝑚 𝑅𝑆 (𝑅1 ∥𝑅2 ) 𝑔
=𝑉𝑖𝑛 × × (− 1+𝑔𝑚 𝑅 𝑅𝐷 )
𝑅𝐺 +(𝑅1 ∥𝑅2 ) 𝑚 𝑆
 Degeneration is used to stabilize bias point, and a bypass capacitor can be used
to obtain a larger small-signal voltage gain at the frequency of interest.

Common-Gate Stage
∆𝑉
V𝑖𝑛 + ∆𝑉 ⟹ V𝐺𝑆 − ∆𝑉 ⟹ 𝐼𝐷 − ∆𝐼𝐷 ⟹ V𝑜𝑢𝑡 + ∆𝐼𝑅𝐷 ⟹ V𝑜𝑢𝑡 + 𝑅
1Τ𝑔𝑚 𝐷
⟹ V𝑜𝑢𝑡 + 𝑔𝑚 ∆𝑉𝑅𝐷
Av  g m RD
 Common-gate stage is similar to common-base stage: a rise in

input causes a rise in output. So the gain is positive.

Signal Levels in CG Stage
M1 in saturation 條件:
𝑉𝑜𝑢𝑡 ≥ 𝑉𝑏 − 𝑉𝑇𝐻 (𝑉𝐷𝑟𝑎𝑖𝑛 ≥ 𝑉𝐺𝑎𝑡𝑒 − 𝑉𝑇𝐻 )
𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 ≥ 𝑉𝑏 − 𝑉𝑇𝐻
 In order to maintain M1 in saturation, the signal swing at Vout

cannot fall below Vb-VTH.

I/O Impedances of CG Stage
𝑅𝑜𝑢𝑡
×
𝑅𝑖𝑛
×
𝑅𝑜𝑢𝑡 = (𝑅𝑢𝑝 ∥ 𝑅𝑑𝑜𝑤𝑛 )=𝑅𝐷
1
𝑅𝑖𝑛 =
𝑔𝑚
 The input and output impedances of CG stage are similar to those

of CB stage.
CG Stage with Source Resistance
1
𝑉𝑜𝑢𝑡 V𝑜𝑢𝑡 𝑉𝑋 𝑔𝑚 1
𝐴𝑉 = = ∙ = 𝑔𝑚 𝑅𝐷 ∙ = 𝑔𝑚 𝑅𝐷 ∙
𝑉𝑖𝑛 𝑉𝑋 𝑉𝑖𝑛 1 1 + 𝑔𝑚 𝑅𝑆
𝑅𝑆 +
𝑔𝑚
𝑔𝑚
= 𝑅𝐷
1+𝑔𝑚 𝑅𝑆
 When a source resistance is present, the voltage gain is equal to

that of a CS stage with degeneration, only positive.
Generalized CG Behavior
當≠0⟹ 𝑟𝑜
Rout  1  g m rO RS  rO
 When a gate resistance is present it does not affect the gain and
I/O impedances since there is no potential drop across it ( at low
frequencies).
 The output impedance of a CG stage with source resistance is
identical to that of CS stage with degeneration.
Example of CG Stage
Razavi 7.9
R 𝑈𝑃 求=0的增益，和≠0時的輸出阻抗
𝑅𝑜𝑢𝑡
R 𝑑𝑜𝑤𝑛
步驟1. 1 1
V𝑜𝑢𝑡 V𝑜𝑢𝑡 V𝑋 ∥ 𝑔𝑚1
𝑔𝑚1 𝑔𝑚2
= ∙ = 𝑔𝑚1 𝑅𝐷 ∙ = 𝑅𝐷
𝑉𝑖𝑛 𝑉𝑋 𝑉𝑖𝑛 1 1 1 + (𝑔𝑚1 + 𝑔 )𝑅
𝑚2 𝑆
𝑅𝑆 + 𝑔 ∥ 𝑔
步驟2. 𝑚1 𝑚2
𝑅𝑜𝑢𝑡 = 𝑅𝑢𝑝 ∥ 𝑅𝑑𝑜𝑤𝑛
1
𝑅𝑑𝑜𝑤𝑛 =𝑟𝑜 +(1+𝑔𝑚 𝑟𝑜 ) 𝑅𝑆 =𝑟𝑜1 + (1+𝑔𝑚1 𝑟𝑜1 )(𝑔 ∥ 𝑟𝑜2 ∥ 𝑅𝑆 )
𝑚2
1
𝑅𝑜𝑢𝑡 = 𝑅𝐷 ∥ [𝑟𝑜1 + (1+𝑔𝑚1 𝑟𝑜1 )( 𝑔 ∥ 𝑟𝑜2 ∥ 𝑅𝑆 )]
𝑚2
 Diode-connected M2 acts as a resistor to provide the bias current.

CG Stage with Biasing
V𝑜𝑢𝑡 V𝑜𝑢𝑡 V𝑋
= ∙
𝑉𝑖𝑛 𝑉𝑋 𝑉𝑖𝑛
1
(𝑔 ∥ R 3 )
𝑚1
= 𝑔𝑚1 𝑅𝐷 ∙
1
𝑅𝑆 + 𝑔 ∥ 𝑅3
𝑚1
訊號遇電容短路⟹ 耦合電容
 R1 and R2 provide gate bias voltage, and R3 provides a path for DC

bias current of M1 to flow to ground.
Source Follower Stage 源極隨耦器(共汲極)
當≠0⟹ 𝑟𝑜
𝑅𝑜𝑢𝑡
推導:
𝑉𝑜𝑢𝑡 = 𝑔𝑚1 𝑣1 (𝑅𝐿 ∥ 𝑟𝑜 )……………..(1)
𝑉𝑖𝑛 = 𝑣1 + 𝑣𝑜𝑢𝑡 ……...……………..(2)
(1) V𝑜𝑢𝑡 𝑔𝑚1 𝑣1 (𝑅𝐿 ∥𝑟𝑜 ) 𝑔𝑚1 (𝑅𝐿 ∥𝑟𝑜 ) 𝑔𝑚1
= = = = (𝑅𝐿 ∥ 𝑟𝑜 )
(2) 𝑉𝑖𝑛 𝑣1 +𝑔𝑚1 𝑣1 (𝑅𝐿 ∥𝑟𝑜 ) 1+𝑔𝑚1 (𝑅𝐿 ∥𝑟𝑜 ) 1+𝑔𝑚1 (𝑅𝐿 ∥𝑟𝑜 )
V𝑜𝑢𝑡 𝑔𝑚1
公式: = 𝐺𝑚 𝑅L = (𝑅𝐿 ∥ 𝑟𝑜1 )
𝑉𝑖𝑛 1+𝑔𝑚1 (𝑅𝐿 ∥𝑟𝑜1 )

Source Follower Example
V𝑜𝑢𝑡
求 =?
𝑉𝑖𝑛
1 𝑅𝑜𝑢𝑡 1 𝑅𝑜𝑢𝑡
𝑔𝑚1 𝑔𝑚1
Razavi 7.16
V𝑜𝑢𝑡 𝑔𝑚1
公式: = 𝐺𝑚 𝑅L = 𝑟𝑜1 ∥ 𝑟𝑜2
𝑉𝑖𝑛 1+𝑔𝑚1 𝑟𝑜1 ∥𝑟𝑜2
1 1 NOTE:
Rout  || rO || RL  || RL 1
1.計算AV時有用到𝑔 ,所以𝑅L 不代入𝑔
1
g m1 g m1 𝑚 𝑚
1
2.但計算輸出阻抗時，須考慮𝑔
𝑚
 In this example, M2 acts as a current source.

Source Follower with Biasing
解 1.判別M1有無在飽和區?
電 VDS ≥ VGS − 𝑉𝑇𝐻
流 2.飽和區電流公式
VG 題 1 𝑊
VS
ID = 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2
2 𝐿
型
𝑉𝐷𝐷 = 𝑉𝐺 = 𝑉𝐺𝑆 + 𝐼𝐷 𝑅𝑆
訊號遇電容短路⟹ 耦合電容 1 𝑊
*交流短路但直流斷路 ID = 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝑆 − 𝑉𝑇𝐻 )2
2 𝐿
*此題電流大小由M1決定
 RG sets the gate voltage to VDD, whereas RS sets the drain current.
 The quadratic equation above can be solved for ID.

Supply-Independent Biasing
*此題電流大小由電流源決定
M2的Gate端是固定電壓→決定ID2→ ID1= ID2
所以Vb決定M1和M2的電流，也就說M2的電流決定總路徑電流
和上一頁PPT不同觀念
 If Rs is replaced by a current source, drain current ID becomes

independent of supply voltage.
Example of a CS Stage
當≠0⟹ 𝑟𝑜
𝑅𝑜𝑢𝑡
1
1. M3兩隻腳→視為電阻→
2. ≠0⟹ VDS 間有𝑟𝑜
𝑔𝑚
 1 
Av   g m1  || rO1 || rO 2 || rO 3 
 g m3 
1
Rout  || rO1 || rO 2 || rO 3
g m3
 M1 acts as the input device and M2, M3 as the load.

For the following amplifier circuit, please
1. sketch the small-signal equivalent circuit, (10%)
2. find the transistor W/L ratio such that the input resistance 𝑅𝑖𝑛 is matched (equals to
75Ω) (15%)
3. find the small-signal gain (𝑣𝑜𝑢𝑡 Τ𝑣𝑖𝑛 ) (15%)
4. and find the output resistance 𝑅𝑜𝑢𝑡 . (15%)
[Assume 𝜇𝑛 𝐶𝑜𝑥 = 120 𝜇𝐴Τ𝑉 2, 𝑉𝑡𝑛 = 0.7𝑉, 𝑉𝐷𝐷 = 𝑉𝑆𝑆 = 15𝑉, and 𝜆𝑛 =0.]
VDD
Rout
100 k
CC2
Vout
M1
40 k
75 CC1
Vin
Rin 100 µA
-VSS 108 台大電子(A)

Vout
Sol: + 100 k
1. Vgs gmVgs
40 k
-
Rin Rout
75
PPT CH6-pp.21, pp.30
1 Vin
2.𝑅𝑖𝑛 =
𝑔𝑚
1 1 𝑊
= = = 75 ⇒ = 7407.407
𝑊 𝑊 𝐿
2𝐶𝑜𝑥 𝐿 𝐼𝐷 2 × 120 × 10−6 × 100 × 10−6 × 𝐿
≅ 7407 PPT CH6-pp.30
𝑊
3. 𝑔𝑚 = 2𝐶𝑜𝑥 𝐼
𝐿 𝐷
= 2 × 120 × 10−6 × 100 × 10−6 × 7407 = 0.01333
𝑚𝐴
≅ 13.33( ) PPT CH7-pp.30
𝑉
𝑔 13.33(𝑚𝐴Τ𝑉) 𝑉
𝐴𝑉 = 1+𝑔𝑚 𝑅 𝑅𝐿 = 1+13.33×10−3 ×0.075×103 × 40 ∥ 100 𝑘Ω = 190.42 𝑉
𝑚 𝑆
4. 𝑅𝑜𝑢𝑡 = 40 ∥ 100 = 28.57 𝑘Ω

Example
VDD For the common-gate amplifier in Fig. 𝑉𝐷𝐷 = 5𝑉, −𝑉𝑠𝑠 = −5𝑉,
𝑅𝐷 = 8𝑘Ω and 𝐶𝐶1 and 𝐶𝐶2 are ideal capacitors. The parameters of
RD
CC2 The MOSFET are given as 𝜇𝑛 𝐶𝑜𝑥 𝑊 Τ𝐿 = 1𝑚𝐴/𝑉 2
Output 1. If an input resistance of 1𝑘Ω is needed,
find the value of the bias current I. PPT CH6-pp.30

2. Use the value of current I in 1. If the amplifier is used as a current
CC1 amplifier, please draw the equivalent circuit model and specify the
Iutput values of the parameters.
I
 Sol:
-VSS 1 𝑊
1.𝑅𝑖 = 1𝑘Ω = ⟹ 𝑔𝑚 = 1 𝑚𝐴Τ𝑉 , 𝑔𝑚 = 2𝐶𝑜𝑥 𝐼 ⟹ 1 mA = 2 × 1 × 𝐼𝐷
𝑔𝑚 𝐿 𝐷
108台大電子學(C)
⟹ 𝐼𝐷 = 0.5 𝑚𝐴
1
2. 𝑅𝑖 = = 1𝑘Ω
𝑔𝑚
Io
𝑅𝑜𝑢𝑡 = 𝑅𝐷 = 8 𝑘 Ii
𝑖𝑜
𝐴𝐼 = =1 Rin Av·Ii
𝑖𝑖 Rout

作業1.

作業2.
Sol.

作業3.

作業4.

作業5.
Sol:

作業6. VDD=1.8V (b)因(𝑉𝐺𝑆 −𝑉𝑇𝐻 )𝑚𝑎𝑥 = 0.6
𝑉𝐺𝑆 =1 → 𝑉𝐺𝑠 = 𝑉𝐺 − 𝑉𝑆
R1 RD=500 1 = 𝑉𝐺 − 100Ω × 200𝑚𝑉
→ 𝑉𝐺 =1.2V
𝑅2
𝑉𝐺 = 1.8 × = 1.2
𝑅1 +𝑅2
Rin
𝑅2 2 𝑅2
→ = → = 2……(1)
𝑅1 +𝑅2 3 𝑅1
R2 Rs=100
𝑅𝑖𝑛 = 𝑅1 ∥ 𝑅2 ≥ 30𝑘Ω………(2)
由(1)(2)
𝑅1 = 50 𝑘Ω, 𝑅2 = 100 𝑘Ω
(a)由題知𝑉𝑅𝑆 =200mV→ 𝐼𝐷𝑆 𝑅𝑆 = 200𝑚𝑉,
→ 𝐼𝐷𝑆 × 100𝛺 = 200 × 10−3 𝑉 ⇒ 𝐼𝐷𝑆 = 2𝑚𝐴
因𝑀1 保持Saturation → 𝑉𝐷𝑆 ≥ 𝑉𝐺𝑆 − 𝑉𝑇𝐻 , (𝑉𝐷 − 𝑉𝑆 ) ≥ 𝑉𝐺𝑆 − 𝑉𝑇𝐻
→ [1.8-(2 × 10−3 ) × 500] − 0.2 ≥ 𝑉𝐺𝑆 − 𝑉𝑇𝐻 → 0.6≥ 𝑉𝐺𝑆 − 𝑉𝑇𝐻
1 𝑊 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 ，又 ( )𝑚𝑖𝑛 → (𝑉𝐺𝑆 −𝑉𝑇𝐻 )𝑚𝑎𝑥 = 0.6
2 𝐿 𝐿
1 𝑊 𝑊
200 × 10−3 = (200 × 10−6 ) ( )𝑚𝑖𝑛 × 0.6 ⇒( )𝑚𝑖𝑛 ≅ 56
2 𝐿 𝐿

 作業7. VDD=1.8V
RD 2k
(b)
Vout 當=0⟹無𝑟𝑜
Vin
M1
𝑊
𝐴𝑉 = 𝑔𝑚 𝑅𝐿 = 2𝐶𝑜𝑥 𝐼 𝑅
𝐿 𝐷 𝐷
(a) 30
1 𝑊 = 2 × (200 × 10−6 ) × × 0.5𝑚𝐴 × 2000
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 0.18
2 𝐿 =11.55
−3 1 −6 30 2
0.5 × 10 = (200× 10 )( )
(𝑉𝐺𝑆 − 𝑉𝑇𝐻 )
2 0.18
→ 𝑉𝐺𝑆 = 0.573 𝑉
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝑉𝑅𝐷 = 1.8 − 0.5 × 10−3 × 2000
= 0.8 V
∵ 𝑉𝐷𝑆 > 𝑉𝐺𝑆 − 𝑉𝑇𝐻 →M1 in Saturation

 作業8.
VDD=1.8V 𝑊
𝑔𝑚2 = 2𝐶𝑜𝑥 ( )𝟐 𝐼𝐷𝟐
𝐿
M2 2
= 2 × 200 × 10−6 × × 2.17 × 10−3 =0.00311
0.18
Vout 𝑊
Vin
M1
𝑔𝑚1 = 2 × 200 × 10−6 × ( )𝟏 × 2.17 × 10−3
𝐿
𝑊
= 868 × 10−9 × ( )𝟏
𝐿
1 1
𝐴𝑉 = −𝑔𝑚1 𝑅𝐿 = −𝑔𝑚1 ∥𝑟 ∥𝑟 𝐴𝑉 = −𝑔𝑚1
𝑔𝑚2 𝑜1 𝑜2 𝑔𝑚2
1
≅ −𝑔𝑚1 ( ) 𝑊 1
𝑔𝑚2 →7= 868 × 10−9 × ( )𝟏 × [ ]
1 𝑊 𝐿 0.00311
𝐼𝐷2 = 𝜇𝑛 𝐶𝑜𝑥 ( )2 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 𝑊
2 𝐿 → 49 = 868 × 10−9 × ( )𝟏 × [103.3𝐾]
200×10−6 2 𝐿
= × × (1.8 − 0.4)2 𝑊
2 0.18 → ( )𝟏 =546
𝐿
= 2.17𝑚𝐴=𝐼𝐷1

 作業9. VDD=1.8V
R1 RD
Vout
C2
VB
Vin
I1
R2 C1
∵ 𝑉𝐷𝑆 ≥ 𝑉𝐺𝑆 − 𝑉𝑇𝐻 →M in Saturation

𝑅2
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 2𝑚𝐴 × 𝑅𝐷 ≥ 𝑉𝐺𝑆 − 𝑉𝑇𝐻 = 𝑅 × 1.8 − 0.4
1 +𝑅2
𝑅2
1.8 − 𝑅 × 1.8 + 0.4 ≥ 2𝑚𝐴 × 𝑅𝐷
1 +𝑅2
2.2 𝑅2 1.8
−𝑅 × 2𝑚𝐴 ≥ 𝑅𝐷
2𝑚𝐴 1 +𝑅2
𝑅2
1.1 kΩ − 𝑅 × 0.9 𝑘Ω ≥ 𝑅𝐷
1 +𝑅2

VDD=1.8V
作業10. If (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )=0.1V
−3
1
⟶ 1.06 × 10 = × 𝑔𝑚 × 0.1
R1 RD 2
⟶ 𝑔𝑚 = 21.2 𝑚
Vout 𝑔𝑚
C1 𝐴𝑉 = 4 = 𝐺𝑚 𝑅𝐿 = × 𝑅𝐷
1 + 𝑔𝑚 𝑅𝑆
21.2×10−3
Vin ⟶4= × 𝑅𝐷
1+(21.2×10−3 )×189
R2 RS ⟶ 𝑅𝐷 ≅ 947Ω
∵ 0.1 V = 𝑉𝐺𝑆 − 𝑉𝑇𝐻 = 𝑉𝐺𝑆 − 0.4
⟶ 𝑉𝐺𝑆 = 0.5 = 𝑉𝐺 − 𝑉𝑆 = 𝑉𝐺 − 0.2
P = IV = 𝐼𝐷𝑆 𝑉𝐷𝐷 ⟶ 𝑉𝐺 = 0.7 𝑉
⟶ 1 − 5% × 2 × 10−3 = 𝐼𝐷𝑆 × 1.8 𝑃
𝐼𝑅1 +𝑅2 =
𝑉
95%×2×10−3
⟶ 𝐼𝐷𝑆 = = 1.06 𝑚𝐴 = 5% ×
2×10−3
= 5.56 × 10−3 𝐴
1.8
1.8
𝑉𝑅𝑆 = 𝐼𝐷𝑆 𝑅𝑆 ⟶ 200𝑚𝑉 = 1.06𝑚𝐴 × 𝑅𝑆 𝑉 1.8
⟶ 𝑅𝑆 = 189Ω 𝑅1 + 𝑅2 = = = 32.4 𝑘Ω……(1)
𝐼 5.56×10−3
1 𝑊 𝑅
𝐼𝐷𝑆 = 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 𝑉𝐺 = 0.7 𝑉 = 2 × 1.8……..(2)
𝑅1 +𝑅2
2 𝐿
1 𝑊 由(1)(2)
= 𝑔𝑚 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 ) , 𝑔𝑚 = 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )
2 𝐿
⟶ 𝑅1 =12.6 𝑘Ω , 𝑅2 =19.8 𝑘Ω

𝑊 𝑊
𝑔𝑚 = 2𝐶𝑜𝑥 𝐼 = 2 × 200 × × 1.06 × 10−3 = 21.2 𝑚
𝐿 𝐷 𝐿
𝑊
⟶ = 1060
𝐿
𝑊
𝑅1 =12.6 𝑘Ω , 𝑅2 =19.8 𝑘Ω , 𝑅𝑆 = 189Ω , 𝑅𝐷 ≅ 947Ω , = 1060, 𝐼𝐷𝑆 = 1.06 𝑚𝐴
𝐿

Microelectronics: Jun-Hong Weng

Uploaded by

Copyright:

Available Formats

Microelectronics: Jun-Hong Weng

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Microelectronics: Jun-Hong Weng

Uploaded by

Copyright:

Available Formats

Microelectronics

Chapter 7 CMOS Amplifiers

 7.2 Common-Source Stage

 7.3 Common-Gate Stage

 7.4 Source Follower

 7.5 Summary and Additional Examples

Microelectronics jhw@ thu.edu.tw

利用跨壓 V𝑋 = 𝑉GS + 𝑉RS = 𝑉GS + ID R S ………(2)

M1 Saturation V𝑌 > V𝑋 − V𝑇𝐻 (一順一逆)

 Voltage at X is determined by VDD, R1, and R2.

Microelectronics jhw@ thu.edu.tw

利用跨壓 V𝑋 = 𝑉GS + 𝑉RS = 𝑉GS + ID R S ………(2)

Microelectronics jhw@ thu.edu.tw

Microelectronics jhw@ thu.edu.tw

求當M1 維持飽和時，R D 之最大值。VTH =

Microelectronics jhw@ thu.edu.tw

求當M1 維持飽和時，R D 之最大值。VTH =

Microelectronics jhw@ thu.edu.tw

求當M1 維持飽和時，R D 之最大值。VTH =

Microelectronics jhw@ thu.edu.tw

求當M1 維持飽和時，R D 之最大值。VTH =

𝑉𝐷𝐷 −𝑉𝑌 1.8−0.786

Microelectronics jhw@ thu.edu.tw

當M1 維持飽和時，R D =2.5kΩ。求(a) 𝑊 Τ𝐿 最大值

Microelectronics jhw@ thu.edu.tw

Razavi 7.3 (b)同(a)利用MOS飽和區電流公式&跨壓

 The circuit above is analyzed by noting M1 is in saturation and no

Microelectronics jhw@ thu.edu.tw

Microelectronics jhw@ thu.edu.tw

當𝐼𝐷 = 1𝑚𝐴，VTH = 0.5𝑉, 𝜇𝑛 𝐶𝑜𝑥 = 100 𝜇𝐴Τ𝑉 2 且𝜆 = 0。

Microelectronics jhw@ thu.edu.tw

Microelectronics jhw@ thu.edu.tw

Microelectronics jhw@ thu.edu.tw

Microelectronics jhw@ thu.edu.tw

Microelectronics jhw@ thu.edu.tw

Microelectronics jhw@ thu.edu.tw

Microelectronics jhw@ thu.edu.tw

𝑣𝑜𝑢𝑡 𝑔𝑚1 𝑔𝑚1

 A diode-connected device degenerates a CS stage.

Microelectronics jhw@ thu.edu.tw

𝑣𝑜𝑢𝑡 −𝑔𝑚 𝑅L 口訣:

 Similar to the bipolar counterpart, degeneration boosts output

Microelectronics jhw@ thu.edu.tw

Microelectronics jhw@ thu.edu.tw

Microelectronics jhw@ thu.edu.tw

 Common-gate stage is similar to common-base stage: a rise in

Microelectronics jhw@ thu.edu.tw

 In order to maintain M1 in saturation, the signal swing at Vout

Microelectronics jhw@ thu.edu.tw

 The input and output impedances of CG stage are similar to those

 When a source resistance is present, the voltage gain is equal to

 Diode-connected M2 acts as a resistor to provide the bias current.

Microelectronics jhw@ thu.edu.tw

 R1 and R2 provide gate bias voltage, and R3 provides a path for DC

Microelectronics jhw@ thu.edu.tw

 In this example, M2 acts as a current source.

Microelectronics jhw@ thu.edu.tw

 If Rs is replaced by a current source, drain current ID becomes

 M1 acts as the input device and M2, M3 as the load.