ISSN(Online) : 2456-8910

International Journal of Innovative Research in Applied Sciences and Engineering (IJIRASE)

Volume 3, Issue 1, DOI: 10.29027/IJIRASE.v3.i11.2019, 423-427 , July 2019

Improving Robustness of Dual Port SRAM by finding additional bugs in design

using ESPCV flow to compare Schematics v/s Verilog on 12LP GF Technology
as an example

Sneha Sharma Madhu Shandilya O. P. Meena Naresh Gandham

1
Electronics and Communication Engineering, MANIT, Bhopal(M.P.)
2
Electronics and Communication Engineering, MANIT, Bhopal(M.P.
3
Electronics and Communication Engineering, MANIT, Bhopal(M.P.
4
SMTS, Invecas Technologies Pvt. Ltd., Bangalore (Karnataka)
1
[email protected]

Abstract: Robustness in design is one of the major memory cell. As shown in figure, it consists of two
concerns in memory design, this will be checked with the pull up transistors that are PMOSs and two pull down
help of various verification techniques used in the industry. transistors that are NMOSs. The single port SRAM
Functional verification is used to check whether the design has only one port for accessing data and address. So,
meets the specification. Evolution in verification has led to either it can read or write at one time. The 8T SRAM
the development of formal verification tools nowadays. The
symbolic simulators involve the formal verification
memory cell is somewhat similar to that of single port
technique along with the simulation approach. This makes SRAM. It consists of two ports for data access and
debugging of circuit faults easier. ESP-CV is a symbolic address paths. Thus, it is known as dual port memory.
simulator designed for functional verification and sequential In this kind of memory cell each address and data
equivalence checking of custom memory design. Symbolic ports can read and write separately. The Read and
simulation compares two design i.e. behavioral RTL verilog Write operation of 8T SRA is similar to that of 6T
and transistor-level SPICE netlist by generating testbenches SRAM.
for different cycles. This article includes the basic flow of
ESP-CV simulation and how this flow helps in improving
robustness of SRAM design. This tool is used early in the 1.2 SYMBOLIC SIMULATION:
design flow because of its ability to read RTL models and
Spice netlists directly. This article also diagrams the key There are three methods presently available for
difficulties of memory check, and proceeds to depict how functional equivalence check to the designers, these
symbolic simulation and its basic advancements offer points are - conventional simulation, cone-based equivalence
of interest for confirming full-custom circuit design. checking, and symbolic simulation. The initial two
techniques are known by everyone while the symbolic
Index terms: RTL, IMDK, FINFET, SRAM, ESP-CV simulation is gaining interest from couple of years
and is more advanced and commercially available.
1. INTRODUCTION: Each method has its advantages and the best method
depends on the application kind.
1.1 SRAM
Static random -access memory (SRAM) is the basic Symbolic simulation is becoming more trending for
building block for silicon on chip (SoC) technology full custom memory design configuration in the course
because of its high speed, low power consumption and of few years. In symbolic simulation symbols like 0, 1,
compatibility with standard technology. SRAM are x and z are applied as inputs in comparison to only bits
used in various applications like Personal computers to generate RTL description and SPICE level circuit.
(PC), Mobile communications, consumer electronics The simulator passes these symbols from input to
etc. In any chip the memory requires greater part while output. Then further the output conditions are checked
the memory cell array covers most of the part in for all possible combination of inputs and it is
memory. The speed with which read and write observed whether the output condition matches for
operation occurs in memory cell array is increasing both the models.
nowadays, so the memory unit configuration is crucial
advancement in VLSI design.The single port SRAM
consist of six transistors basically, it is the standard

Vol. 3 (1), July 2019, www.ijirase.com 423

 ISSN(Online) : 2456-8910
International Journal of Innovative Research in Applied Sciences and Engineering (IJIRASE)
Volume 3, Issue 1, DOI: 10.29027/IJIRASE.v3.i11.2019, 423-427 , July 2019

2. ESPCV FLOW
It is very important to assert that the SRAM design is
able to perform the desired functionality as per
described by Verilog Reference model. In order to
check for the functionality ESP simulation is being
done where the transistor level Spice netlist is matched
with Rtl reference verilog model. The use of Symbolic
Fig. 1.: Single port SRAM simulation for functional verification of design
provides the full coverage using lesser number of
symbolic cycle.It is compatible with most of the
competing technologies and works absolutely fine
with existing design environment.

We have been working on GF 12LP FINFET

technology which provides much improvement in
circuit density and performance in comparison to
previous technologies. We have done ESP simulation
for many instances which is Dual ported SRAM
design with particular specification of wordlines,
Bitlines, mux etc.

Fig. 2. Double port SRAM

Fig. 4. Functional Equivalence Check using ESP-CV

Fig. 3. Symbolic Simulation

Vol. 3 (1), July 2019, www.ijirase.com 424

 ISSN(Online) : 2456-8910
International Journal of Innovative Research in Applied Sciences and Engineering (IJIRASE)
Volume 3, Issue 1, DOI: 10.29027/IJIRASE.v3.i11.2019, 423-427 , July 2019

Here are the steps for ES-PCV simulation: following testbenches are generated:
(i) esp.tb.bin: binary testbench
1. Setting up ESP Environment: Making (ii) esp.tb.dit: address/data are made
directories, Loading modules and opening symbolic,
xterm to run the simulation. Here we have whereas control pins are binary
used ESP/N-2017 version of ESP-CV. (iii) esp.tb.ptl: control pins are symbolic
(iv) esp.tbl.2ph: checks on both phase of
clock
2. Generating Reference model and transistor
level model: The Reference Model is the RTL
reference code written in verilog. We are 7. Verification and Debugging: ESP-CV do the
generating this using IMDK. The transistor symbolic simulation which is event driven.
level model is the SPICE netlistgenerated ESP checks the outputs of the two models by
directly from schematic using virtuoso. searching the entire input vector space, if
ESP finds the input vector which lead
3. Generating techfile.edm and esp.tcl: The mismatch of the two models or it has
ESP-CV may not show appropriate searched the entire input vector space, it will
functionality with the default models, so to stop the symbolic simulation. If the design is
get better idea we create edm file with the passed then coverage report is generated, if
PDK models. All models like pfet, slvtpfet, errors are found then debugging is done.
lvtnfetetc is to be specified there. The ESP
tool provides a TCL shell command line
interface. Esp.tcl is a main file which is used 3. ERRORS FOUND IN DESIGN
during simulation and where netlist and
verilog are being included. It also contains all Here, the reference instance is
other variables set for the simulation. IN12LP_SDPB_W00064B016M04S2_HDCBTG
where there are 64 words, 16 bits, mux-04
4. Setting up Constraints, ports and Supplies: In configuration with single bank having 2 subarrays.
esp.tcl all supplies are configured including
virtual nets, also it contains all ports to be 1. Width of MCLK: As internal clock is being
matched, set variable for mentioning generated for performing different operations, the
unmatched ports. All the testbench attributes width of the clock was not appropriate for
are set with their functionality, all the accessing farthest bank. This led to errors in the
constraints are set as shown in Fig. 5. functional check.

2. Address sequence: Due to modified sequence

of address in verilog there were few errors.

3. Address collission: As in Dual port we can

Fig. 5. Setting constraints in esp.tcl read and write from both the ports at same
time, sometimes if the address of both the
5. Start Simulation: Initially tool will read all ports is same then data may be lost.
the input files, supplies and ports will be
checked. If it will have any parsing errors, log 4. Design issues: This is the main part which is
file is to be checked for unmatched ports. to be focused, the schematic designed may have
some manual errors. ESP-CV let you to do
6. Generating testbenches: The Testbench is complete functional check and with help of
generated after all ports has been matched. waveforms we can trace the error. During the
ESP call esptbgen to generate a testbench. simulation we have found two errors, in different
The ESP tool creates testbenches with set of instances. The pins were swapped in the
cycles in the order – INIT, BINCYCLE, schematic due to which there was a mismatch.
SYMCYCLE and FLUSHCYCLE. The

Vol. 3 (1), July 2019, www.ijirase.com 425

 ISSN(Online) : 2456-8910
International Journal of Innovative Research in Applied Sciences and Engineering (IJIRASE)
Volume 3, Issue 1, DOI: 10.29027/IJIRASE.v3.i11.2019, 423-427 , July 2019

Fig. 6. Manual Errors

4. DEBBUGGING THESE ERRORS
1. The width of MCLK can be increased accordingly
by providing delay to the one which generates MCLK
in Fig. 8.Simulation Passed after Correction
timing system circuit.

Table 1. Comparison of other simulation techniques with

symbolic simulation

Criteria Other Symbolic

Simulation Simulation
Techniques
Based on This cannot It can explore
number of check all the all possible
input possible combinations
Fig. 7.Mclk width
combinations combination as symbols are
it can check. even if taken used to
months for propagate
simulations. through both
2. The address sequence was corrected in the models.
schematic (netlist). The extent to It can miss As it starts
3. In this case the address of one port is inverted, so which it can corner case early in the
that it will not access same bitcell. find bugs. scenarios as design, it can
4. All the design issues are corrected as per the error limited test catch bugs
traced in the waveform. vectors are almost at each
given. corner.
5. RESULTS Ability to It may Automatically
observe effects propagate bugs isolate the
The Report for the Functional mode is shown in the of change in to output pins cause of bugs
fig. 8. This shows that the SPICE netlist and the design but needs to be and incorrect
verilog behavioral model matches for all the exposed. behaviors.
testbenches. This also indicates that the design is
clean. The Comparison of ESP Simulation with other
Conventional techniques is also shown in the table
below

Vol. 3 (1), July 2019, www.ijirase.com 426

 ISSN(Online) : 2456-8910
International Journal of Innovative Research in Applied Sciences and Engineering (IJIRASE)
Volume 3, Issue 1, DOI: 10.29027/IJIRASE.v3.i11.2019, 423-427 , July 2019

6.CONCLUSION
ESP-CV gives quick and broad coverage, empowering
users to quickly discover bugs and have the certainty
that the Verilog reference model is practically
indistinguishable to its transistor-level
implementation. In practical work, we have discovered
various mismatches between the circuit schematic and
the RTL description, which help us a great deal to
extend our understanding of the behavior description
of circuit also to the circuit debug.

7. REFERENCES

1. Du Hongyan, TAN Mangiong, TIAN Xianhua, XU

Hongliang “ESP verification for Custom SRAM Array
Design “, 4th International Conference on Computer Science
and Education,2009.
2. Maisagalla Gopal, D Siva Sankar Prasad, Balwinder Raj
“8T SRAM cell Design for Dynamic & leakage Power
Reduction,International Journal of Computer
applications,2013.
3. Mehmet F. Hocaglug, “A comparison between qualitative
simulation: Bridging the conceptual Gap”, AI,simulation and
planning in High Autonomy Systems – AIS2002.
4.Vikas Gupta, Sonam Rawat, “A Study on Recent
Advancements in VLSI Technology using FinFETs”, P.K.
University Shivpuri, MP, India
5. KunChen,Wei-tao Pan, ”A research of Dual-Port SRAM
cell using 8T Kai-ji Zhang”, Pei-jun Ma Key Laboratory of
WideBand-gap Semiconductor Materials and Devices of
Ministry of Education, School of Microelectronic, Xidian
University, Xi’an 710071, China
6. ESP User Guide Version N-2017.12, December 2017

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