XPM CDC Generator V1.0: Logicore Ip Product Guide

XPM CDC Generator v1.
LogiCORE IP Product Guide

Vivado Design Suite
PG382 (v1.0) February 9, 2021

Table of Contents
Chapter 1: Introduction.............................................................................................. 4
Features........................................................................................................................................ 4
IP Facts..........................................................................................................................................5
Chapter 2: Overview......................................................................................................6
Navigating Content by Design Process.................................................................................... 6
Core Overview..............................................................................................................................6
Licensing and Ordering.............................................................................................................. 6
Chapter 3: Product Specification........................................................................... 8

Performance................................................................................................................................ 8
Port Descriptions.........................................................................................................................8
Chapter 4: Designing with the Core................................................................... 11

General Design Guidelines.......................................................................................................11
CDC Type.................................................................................................................................... 12
Chapter 5: Design Flow Steps.................................................................................31

Customizing and Generating the Core................................................................................... 31
Constraining the Core...............................................................................................................33
Simulation.................................................................................................................................. 34
Synthesis and Implementation................................................................................................34
Chapter 6: Upgrading................................................................................................. 35
Appendix A: Verification, Compliance, and Interoperability...............36
Appendix B: Debugging.............................................................................................37
Finding Help on Xilinx.com...................................................................................................... 37
Debug Tools............................................................................................................................... 38
Simulation Debug......................................................................................................................39
Hardware Debug....................................................................................................................... 39
PG382 (v1.0) February 9, 2021 www.xilinx.com

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XPM CDC Generator 2
Appendix C: Additional Resources and Legal Notices............................. 40
Xilinx Resources.........................................................................................................................40
Documentation Navigator and Design Hubs.........................................................................40
References..................................................................................................................................41
Revision History......................................................................................................................... 41
Please Read: Important Legal Notices................................................................................... 41

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XPM CDC Generator 3
Chapter 1: Introduction
Chapter 1
Introduction
The Xilinx® LogiCORE™ IP XPM CDC core is a constructor that generates various Clock Domain
Crossing blocks – Single-bit Array Synchronizer, Asynchronous Reset Synchronizer, Synchronizer
via Gray Encoding, Bus Synchronizer with Full Handshake, Pulse Transfer, Single bit Synchronizer,
and Synchronous Reset Synchronizer.
Features
• Supports toggling of simulation related messages.
• Supports up to 1024-bit input signal.
• Supports multi-stage synchronizing registers.
• Supports synchronous and asynchronous resets.
• Supports Full Handshake bus synchronizer, which allows sending handshake signals between
the clock domain individually.
• Following are the available CDCs:
○ xpm_cdc_array_single
○ xpm_cdc_async_rst
○ xpm_cdc_gray
○ xpm_cdc_handshake
○ xpm_cdc_pulse
○ xpm_cdc_single
○ xpm_cdc_sync_rst

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XPM CDC Generator 4
Chapter 1: Introduction
IP Facts
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family1 Versal™ ACAPs, UltraScale+™ devices, UltraScale™ devices,
Zynq® UltraScale+™ MPSoCs, Zynq®-7000 SoCs, 7 series FPGAs
Supported User Interfaces CDC Interface
Provided with Core
Design Files System Verilog
Example Design N/A
Test Bench N/A
Constraints File N/A
Simulation Model N/A
Supported S/W Driver N/A
Tested Design Flows
Design Entry IP Integrator
Simulation For supported simulators, see Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page.
Notes:
1. For a complete list of supported devices, see the Vivado® IP catalog.
2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.

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XPM CDC Generator 5
Chapter 2: Overview
Chapter 2
Overview
Navigating Content by Design Process

Xilinx® documentation is organized around a set of standard design processes to help you find
relevant content for your current development task. All Versal™ ACAP design process Design
Hubs can be found on the Xilinx.com website. This document covers the following design
processes:
• Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardware
platform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado®
timing, resource use, and power closure. Also involves developing the hardware platform for
system integration. Topics in this document that apply to this design process include:
• Port Descriptions
• Customizing and Generating the Core
Core Overview
The generator core uses CDC blocks in Xilinx® devices to extend the functionality and capability
of a single primitive to various configurable CDCs. Sophisticated algorithms within the Vivado®
Synthesis core produce optimized solutions to provide convenient access to memories for a wide
range of configurations.
Licensing and Ordering

This Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado®
Design Suite under the terms of the Xilinx End User License.
Information about other Xilinx® LogiCORE™ IP modules is available at the Xilinx Intellectual
Property page. For information about pricing and availability of other Xilinx LogiCORE IP modules
and tools, contact your local Xilinx sales representative.

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XPM CDC Generator 6
Chapter 2: Overview
License Checkers
If the IP requires a license key, the key must be verified. The Vivado® design tools have several
license checkpoints for gating licensed IP through the flow. If the license check succeeds, the IP
can continue generation. Otherwise, generation halts with an error. License checkpoints are
enforced by the following tools:
• Vivado Synthesis
• Vivado Implementation
• write_bitstream (Tcl command)
IMPORTANT! IP license level is ignored at checkpoints. The test confirms a valid license exists. It does not
check IP license level.

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XPM CDC Generator 7
Chapter 3: Product Specification
Chapter 3
Product Specification
This chapter includes details on performance and port descriptions.
Performance
Performance and resource usage for a XPM CDC Generator core varies depending on the
configuration and features selected during core customization.
Port Descriptions
The following table describes XPM CDC Generator core ports.
Table 1: Port Descriptions
Handling
Port I/O Width Domain Sense Function
if Unused
dest_clk I 1 N/A EDGE_RISING Active The clock signal for the destination clock
domain.
dest_out O WIDTH dest_clk N/A Active src_in synchronized to the destination clock
domain. This output is registered.
src_clk I 1 N/A EDGE_RISING 0 Unused when SRC_INPUT_REG = 0. Input
clock signal for src_in if SRC_INPUT_REG = 1.
src_in I WIDTH src_clk N/A Active Input single-bit array to be synchronized to
the destination clock domain. It is assumed
that each bit of the array is unrelated to the
others. This is reflected in the constraints
applied to this macro.
To transfer a binary value losslessly across
the two clock domains, use the
XPM_CDC_GRAY macro instead.
dest_arst O 1 dest_clk N/A Active src_arst asynchronous reset signal
synchronized to destination clock domain.
This output is registered.
Note: Signal asserts asynchronously but

deasserts synchronously to dest_clk. The
width of the reset signal is at least
(DEST_SYNC_FF*dest_clk) period.

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XPM CDC Generator 8
Table 1: Port Descriptions (cont'd)
Handling
if Unused
src_arst I 1 N/A N/A Active Source asynchronous reset signal.
dest_out_bin O WIDTH dest_clk N/A Active Binary input bus (src_in_bin) synchronized to
destination clock domain. This output is
combinatorial unless REG_OUTPUT is set to
1.
src_in_bin I WIDTH src_clk N/A Active Binary input bus that is synchronized to the
destination clock domain.
dest_req O 1 dest_clk LEVEL_HIGH Active This assertion of this signal indicates that
new dest_out data has been received and is
ready to be used or captured by the
destination logic.
• When DEST_EXT_HSK = 1, this signal is
deasserted when the source handshake
acknowledges that the destination clock
domain has received the transferred
data.
• When DEST_EXT_HSK = 0, this signal
asserts for one clock period when the
dest_out bus is valid.
src_rcv O 1 src_clk LEVEL_HIGH Active Acknowledgment from destination logic that
src_in has been received.
This signal is deasserted when the
destination handshake has fully completed,
thus completing a full data transfer. This
output is registered.
src_send I 1 src_clk LEVEL_HIGH Active The assertion of this signal allows the src_in
bus to be synchronized to the destination
clock domain.
• This signal should only be asserted when
src_rcv is deasserted, indicating that the
previous data transfer is complete.
• This signal should only be deasserted
when src_rcv is asserted, acknowledging
that the destination logic has received
the src_in.
dest_pulse O 1 dest_clk LEVEL_HIGH Active Outputs a pulse that is the size of one
dest_clk period when a pulse transfer is
correctly initiated on src_pulse input. This
output is combinatorial unless REG_OUTPUT
is set to 1.
dest_rst_in I 1 dest_clk LEVEL_HIGH 0 Unused when RST_USED = 0. Destination
reset signal if RST_USED = 1.
Resets all logic in the destination clock
domain. To fully reset the macro, src_rst and
dest_rst must be asserted simultaneously
for at least ((DEST_SYNC_FF
+ 2) * dest_clk_period) + (2 * src_clk_period).

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XPM CDC Generator 9
Handling
if Unused
src_pulse I 1 src_clk EDGE_RISING Active The rising edge of this signal initiates a
pulse transfer to the destination clock
domain.
The minimum gap between each pulse
transfer must be at the minimum
2*(larger(src_clk period, dest_clk period)).
This is measured between the falling edge of
a src_pulse to the rising edge of the next
src_pulse. This minimum gap guarantees
that each rising edge of src_pulse will
generate a pulse the size of one dest_clk
period in the destination clock domain.
When RST_USED = 1, pulse transfers are not
guaranteed while src_rst and/or dest_rst are
asserted.
src_rst I 1 src_clk LEVEL_HIGH 0 Unused when RST_USED = 0. Source reset
signal if RST_USED = 1.
Resets all logic in the source clock domain.
To fully reset the macro, src_rst and dest_rst
must be asserted simultaneously for at least
((DEST_SYNC_FF
+ 2) * dest_clk_period) + (2 * src_clk_period).
dest_rst_out O 1 dest_clk N/A Active This is src_rst synchronized to the
registered.

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XPM CDC Generator 10
Chapter 4: Designing with the Core
Chapter 4
Designing with the Core

This chapter describes the steps required to turn a XPM CDC Generator core into a fully
functioning design integrated with the user application logic. It is important to note that
depending on the configuration of the XPM CDC Generator core, only a subset of the
implementation details provided is applicable. The guidelines in this chapter give information
about creating the most successful implementation of the core.
General Design Guidelines

The Vivado® Synthesis implements a CDC primitive based on user selections, automating the
process of primitive instantiation and concatenation. This is used to build custom CDC modules
in the Vivado Design Suite IP catalog. You can configure the core and rapidly generate a highly
optimized custom CDC type.
Use the Example Design

Each instance of the XPM CDC Generator core created by the Vivado design tool is delivered
with an example design that can be implemented in a device and then simulated. This design can
be used as a starting point for your own design or can be used to sanity-check your application in
the event of difficulty. See the Example Design content for information about using and
customizing the example designs for the core.
Registering Signals
To simplify timing and increase system performance in a programmable device design, keep all
inputs and outputs registered between the user application and the core. This means that all
inputs and outputs from the user application should come from, or connect to, a flip-flop. While
registering signals might not be possible for all paths, it simplifies timing analysis and makes it
easier for the Xilinx® tools to place and route the design.
Recognize Timing Critical Signals

The constraints provided with the example design identify the critical signals and timing
constraints that should be applied.

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Make Only Allowed Modifications

You should not modify the core. Any modifications can have adverse effects on system timing
and protocol compliance. Supported user configurations of the core can only be made by
selecting the options in the customization IP dialog box when the core is generated.
CDC Type
The XPM CDC Generator core creates Single-bit Array Synchronizer, Asynchronous Reset
Synchronizer, Synchronizer via Gray Encoding, Bus Synchronizer with Full Handshake, Pulse
Transfer, Single bit Synchronizer, and Synchronous Reset Synchronizer.
For each configuration, optimizations are made within the Vivado® Synthesis to minimize the
total resources used. The following information is provided for each macro, where applicable:
• Name, description, macro group, macro subgroup, and family

• Schematic symbol
• Introduction
• Logic diagram (if any)
• Port descriptions
• Design entry method
• Available attributes

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XPM_CDC_ARRAY_SINGLE
MACRO_GROUP: XPM
MACRO_SUBGROUP: XPM_CDC
XPM_CDC_ARRAY_SINGLE
src_in[n:0] dest_out[n:0]
src_clk
dest_clk
X15897-031116
Introduction
This macro synthesizes an array of single-bit signals from the source clock domain to the
For proper operation, the input data must be sampled two or more times by the destination
clock. You can define the number of register stages used in the synchronizers. An optional input
register can be used to register the input in the source clock domain prior to it being
synchronized. You can also enable a simulation feature to generate messages to report any
potential misuse of the macro.
Note: This macro expects that the each bit of the source array is independent, and does not have a defined
relationship that needs to be preserved. If each bit of the array has a relationship that needs to be
preserved, use the XPM_CDC_HANDSHAKE or XPM_CDC_GRAY macros.
Port Descriptions
Handling
if Unused
dest_clk I 1 N/A EDGE Active Clock signal for the destination clock
_RISING domain.
dest_out O WIDTH dest_clk N/A Active This is src_in synchronized to the
registered.
src_clk I 1 N/A EDGE 0 Unused when SRC_INPUT_REG = 0. Input
_RISING clock signal for src_in if SRC_INPUT_REG =
1.

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Handling
if Unused
src_in I WIDTH src_clk N/A Active Input single-bit array to be synchronized to
destination clock domain. It is assumed
that each bit of the array is unrelated to
the others. This is reflected in the
constraints applied to this macro.
To transfer a binary value losslessly across
the two clock domains, use the
XPM_CDC_GRAY macro instead.
Design Entry Method
Table 3: Design Entry Method
Design Entry Yes/No

Instantiation Yes
Inference No
IP and IP Integrator Catalog Yes
Available Attributes
Table 4: Available Attributes
Allowed
Attribute Type Default Description
Values
DEST_SYNC_FF DECIMAL 2 to 10 4 Number of register stages used to synchronize
signal in the destination clock domain.
INIT_SYNC_FF DECIMAL 0, 1 0 • 0: Disable behavioral simulation initialization
value(s) on synchronization registers.
• 1: Enable behavioral simulation initialization
SIM_ASSERT_CHK DECIMAL 0, 1 0 • 0: Disable simulation message reporting.
Messages related to potential misuse will not
be reported.
• 1: Enable simulation message reporting.
Messages related to potential misuse will be
reported.
SRC_INPUT_REG DECIMAL 1, 0 1 • 0: Do not register input (src_in)
• 1: Register input (src_in) once using src_clk
WIDTH DECIMAL 1 to 1024 2 Width of single-bit array (src_in) that will be
synchronized to destination clock domain.

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XPM_CDC_ASYNC_RST
MACRO_GROUP: XPM
XPM_CDC_ASYNC_RST
src_arst dest_arst
dest_clk
X15902-031116
Introduction
This macro synchronizes an asynchronous reset signal to the destination clock domain. The
resulting reset output is guaranteed to assert asynchronously in relation to the input but the
deassertion of the output will always be synchronous to the destination clock domain.
You can define the polarity of the reset signal and the minimal output pulse width of the macro
when asserted. The latter is controlled by defining the number of register stages used in the
synchronizers.
Note: The minimum input pulse assertion is dependent on the setup and hold requirement of the reset or
set pin of the registers. See the respective DC and AC switching characteristics data sheets for the
targeted architecture.
Port Descriptions
Handling
if Unused
dest_arst O 1 dest_clk N/A Active This is the src_arst asynchronous reset
signal synchronized to the destination
clock domain. This output is registered.
Note: Signal asserts asynchronously but

deasserts synchronously to dest_clk. Width
of the reset signal is at least
(DEST_SYNC_FF*dest_clk) period.
dest_clk I 1 N/A EDGE Active Destination clock.

_RISING
src_arst I 1 N/A N/A Active Source asynchronous reset signal.

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Design Entry Method
Design Entry Yes/No

Instantiation Yes
Inference No
Allowed
Values
signal in the destination clock domain. This
parameter also determines the minimum width of
the asserted reset signal.
RST_ACTIVE_HIGH DECIMAL 0, 1 0 Defines the polarity of the asynchronous reset
signal.
• 0: active-Low asynchronous reset signal
• 1: active-High asynchronous reset signal

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XPM_CDC_GRAY
MACRO_GROUP: XPM
XPM_CDC_GRAY
src_in_bin[n:0] dest_out_bin[n:0]
src_clk
dest_clk
X15898-031116
Introduction
This macro synchronizes a binary input from the source clock domain to the destination clock
domain using gray code. For proper operation, the input data must be sampled two or more
times by the destination clock.
This module takes the input binary signal, translates it into Gray code and registers it,
synchronizes it to the destination clock domain, and then translates it back to a binary signal. You
can define the number of register stages used in the synchronizers. You can also enable a
simulation feature to generate messages to report any potential misuse of the macro.
Because this macro uses Gray encoding, the binary value provided to the macro must only
increment or decrement by one to ensure that the signal being synchronized has two successive
values that only differ by one bit. This ensures lossless synchronization of a Gray coded bus. If
the behavior of the binary value is not compatible with Gray encoding, use the
XPM_CDC_HANDSHAKE macro or an alternate method of synchronizing the data to the
An additional option (SIM_LOSSLESS_GRAY_CHK) is provided to report an error message when

any binary input values are found to violate the Gray coding rule where two successive values
must only increment or decrement by one.
Note: When the XPM_CDC_GRAY module is used in a design and report_cdc is run, the synchronizer in
this module is reported as a warning of type CDC-6, Multi-bit synchronized with ASYNC_REG property.
This warning is safe to ignore because the bus that is synchronized is gray-coded. Starting in 2018.3, this
warning has been suppressed by adding a CDC-6 waiver to the Tcl constraint file.
You should run report_cdc to make sure the CDC structure is identified and that no critical
warnings are generated, and also verify that dest_clk can sample src_in_bin[n:0] two or
more times.

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Port Descriptions
Handling
if Unused
_RISING
dest_out_bin O WIDTH dest_clk N/A Active Binary input bus (src_in_bin) synchronized
to destination clock domain. This output is
1.
src_clk I 1 N/A EDGE Active Source clock.
_RISING
src_in_bin I WIDTH src_clk N/A Active Binary input bus that will be synchronized
to the destination clock domain.
Design Entry Method
Design Entry Yes/No

Instantiation Yes
Inference No
Allowed
Values
REG_OUTPUT DECIMAL 0, 1 0 • 0: Disable registered output
• 1: Enable registered output
be reported.
reported.

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Table 10: Available Attributes (cont'd)
Allowed
Values
SIM_LOSSLESS DECIMAL 0, 1 0 • 0: Disable simulation message that reports
_GRAY_CHK whether src_in_bin is incrementing or
decrementing by one, guaranteeing lossless
synchronization of a gray coded bus.
• 1: Enable simulation message that reports
whether src_in_bin is incrementing or
decrementing by one, guaranteeing lossless
synchronization of a gray coded bus.
WIDTH DECIMAL 2 to 32 2 Width of binary input bus that will be synchronized
to destination clock domain.

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XPM_CDC_HANDSHAKE
MACRO_GROUP: XPM
XPM_CDC_HANDSHAKE
src_in[n:0] dest_out[n:0]
src_send src_rcv
src_clk
dest_ack dest_req
dest_clk
X15899-031116
Introduction
This macro uses a handshake signaling to transfer an input bus from the source clock domain to
the destination clock domain. One example of when this macro should be used is when the data
being transferred is not compatible with the XPM_CDC_GRAY macro that uses Gray encoding.
For this macro to function correctly, a full handshake—an acknowledgment that the data transfer
was received and a resetting of the handshake signals—must be completed before another data
transfer is initiated.
You can define the number of register stages used in the synchronizers to transfer the handshake
signals between the clock domains individually. You can also include internal handshake logic to
acknowledge the receipt of data on the destination clock domain. When this feature is enabled,
the output (dest_out) must be consumed immediately when the data valid (dest_req) is
asserted.
You can also enable a simulation feature to generate messages to report any potential misuse of
the macro. These messages generate errors when the signaling provided to the macro violates
the usage guidance above.
Note: When the XPM_CDC_HANDSHAKE module is used in a design and report_cdc is run, the data
bus that is synchronized in this module is reported as a warning of type CDC-15, Clock Enable Controlled
CDC. This warning is safe to ignore. Starting in 2018.3, this warning has been suppressed by adding a
CDC-15 waiver to the Tcl constraint file.
You should run report_cdc to make sure the CDC structure is identified and that no critical
warnings are generated, and also verify that dest_clk can sample src_in[n:0] two or more
times.

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External Handshake
The following waveform shows how back-to-back data is sent when the external handshake
option is used.
Figure 3: External Handshake Timing Diagram
Internal Handshake
The following waveform shows how back-to-back data is sent when the internal handshake
option is enabled.
Figure 4: Internal Handshake Timing Diagram
Port Descriptions
Handling
if Unused
dest_ack I 1 dest_clk LEVEL 0 Destination logic acknowledgement if
_HIGH DEST_EXT_HSK = 1. Unused when
DEST_EXT_HSK = 0.
Asserting this signal indicates that data on
dest_out has been captured by the
destination logic.
This signal should be deasserted once
dest_req is deasserted, completing the
handshake on the destination clock
domain and indicating that the destination
logic is ready for a new data transfer.
_RISING

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Handling
if Unused
dest_out O WIDTH dest_clk N/A Active Input bus (src_in) synchronized to
registered.
dest_req O 1 dest_clk LEVEL Active Assertion of this signal indicates that new
_HIGH dest_out data has been received and is
ready to be used or captured by the
destination logic.
will deassert once the source
handshake acknowledges that the
destination clock domain has received
the transferred data.
asserts for one clock period when
dest_out bus is valid.
_RISING
src_in I WIDTH src_clk N/A Active Input bus that will be synchronized to the
src_rcv O 1 src_clk LEVEL Active Acknowledgement from destination logic
_HIGH that src_in has been received.
This signal will be deasserted once
destination handshake has fully
completed, thus completing a full data
transfer. This output is registered.
src_send I 1 src_clk LEVEL Active Assertion of this signal allows the src_in
_HIGH bus to be synchronized to the destination
clock domain.
• This signal should only be asserted
when src_rcv is deasserted, indicating
that the previous data transfer is
complete.
• This signal should only be deasserted
once src_rcv is asserted,
acknowledging that the src_in has
been received by the destination logic.
Design Entry Method
Design Entry Yes/No

Instantiation Yes
Inference No

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Allowed
Values
DEST_EXT_HSK DECIMAL 1, 0 1 • 0: An internal handshake will be implemented
in the macro to acknowledge receipt of data
on the destination clock domain. When using
this option, the valid dest_out output must be
consumed immediately to avoid any data loss.
• 1: External handshake logic must be
implemented by the user to acknowledge
receipt of data on the destination clock
domain.
be reported.
reported.
SRC_SYNC_FF DECIMAL 2 to 10 4 Number of register stages used to synchronize
signal in the source clock domain.
WIDTH DECIMAL 1 to 1024 1 Width of bus that will be synchronized to

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XPM_CDC_PULSE
MACRO_GROUP: XPM
XPM_CDC_PULSE
src_pulse dest_pulse
src_rst
src_clk
dest_rst_in
dest_clk
X15900-020421
Introduction
This macro synchronizes a pulse in the source clock domain to the destination clock domain. A
pulse of any size in the source clock domain, if initiated correctly, generates a pulse the size of a
single destination clock period.
clock. You can define the number of register stages used in the synchronizers. An optional source
and destination reset can be used to reset the pulse transfer logic. You can also enable a
simulation feature to generate messages which report any potential misuse of the macro.
The implementation of this macro requires some feedback logic. When simulating the macro
without the optional reset signals, the input pulse signal (src_pulse) must always be defined
because there is no reset logic to recover from an undefined or ‘x’ propagating through the
macro.
This macro also requires the following minimum gap between subsequent pulse inputs:
2*(larger(src_clk period, dest_clk period))
The minimum gap is measured between the falling edge of a src_pulse to the rising edge of
the next src_pulse. This minimum gap will guarantee that each rising edge of src_pulse will
generate a pulse the size of one dest_clk period in the destination clock domain.
When using the optional reset signals, src_rst and dest_rst_in must be asserted
simultaneously for at least the following duration to fully reset all the logic in the macro:
((DEST_SYNC_FF+2)*dest_clk_period) + (2*src_clk_period)

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When reset is asserted, the input pulse signal should not toggle and the output pulse signal is not
valid and should be ignored.
The following waveform demonstrates how to reset the macro and transfer back-to-back pulses
while abiding the minimum gap between each pulse.
Figure 5: Timing for Macro and Transfer Back-to-Back Pulses
Port Descriptions
Handling
if Unused
_RISING
dest_pulse O 1 dest_clk LEVEL Active Os a pulse the size of one dest_clk period
_HIGH when a pulse transfer is correctly initiated
on src_pulse input. This output is
1.
dest_rst_in I 1 dest_clk LEVEL 0 Unused when RST_USED = 0. Destination
_HIGH reset signal if RST_USED = 1.
Resets all logic in destination clock
domain. To fully reset the macro, src_rst
and dest_rst_in must be asserted
simultaneously for at least ((DEST_SYNC_FF
+2)*dest_clk_period) + (2*src_clk_period).
_RISING
src_pulse I 1 src_clk EDGE Active Rising edge of this signal initiates a pulse
_RISING transfer to the destination clock domain.
The minimum gap between each pulse
transfer must be at the minimum
2*(larger(src_clk period, dest_clk period)).
This is measured between the falling edge
of a src_pulse to the rising edge of the next
src_pulse. This minimum gap will
guarantee that each rising edge of
src_pulse will generate a pulse the size of
one dest_clk period in the destination clock
domain.
When RST_USED = 1, pulse transfers will
not be guaranteed while src_rst and/or
dest_rst_in are asserted.

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Handling
if Unused
src_rst I 1 src_clk LEVEL 0 Unused when RST_USED = 0. Source reset
_HIGH signal if RST_USED = 1.
Resets all logic in source clock domain.
To fully reset the macro, src_rst and
dest_rst_in must be asserted
simultaneously for at least ((DEST_SYNC_FF
+2)*dest_clk_period) + (2*src_clk_period).
Design Entry Method
Design Entry Yes/No

Instantiation Yes
Inference No
Allowed
Values
RST_USED DECIMAL 1, 0 1 • 0: No resets implemented.
• 1: Resets implemented.
When RST_USED = 0, src_pulse input must always
be defined during simulation because there is no
reset logic to recover from an x-propagating
through the macro.
be reported.
reported.

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XPM_CDC_SINGLE
MACRO_GROUP: XPM
XPM_CDC_SINGLE
src_in dest_out
src_clk
dest_clk
X15896-031116
Introduction
This macro synchronizes a one bit signal from the source clock domain to the destination clock
domain.
clock. You can define the number of register stages used in the synchronizers. An optional input
register may be used to register the input in the source clock domain prior to it being
synchronized. You can also enable a simulation feature to generate messages to report any
potential misuse of the macro.
Port Descriptions
Handling
if Unused
dest_clk I 1 N/A EDGE Active Clock signal for the destination clock
_RISING domain.
dest_out O 1 dest_clk N/A Active This is src_in synchronized to the
registered.
src_clk I 1 N/A EDGE 0 Input clock signal for src_in if
_RISING SRC_INPUT_REG = 1.
Unused when SRC_INPUT_REG = 0.
src_in I 1 src_clk N/A Active Input signal to be synchronized to dest_clk
domain.

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Design Entry Method
Design Entry Yes/No

Instantiation Yes
Inference No
Allowed
Values
be reported.
reported.
SRC_INPUT_REG DECIMAL 1, 0 1
• 0: Do not register input (src_in)
• 1: Register input (src_in) once using

src_clk

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XPM_CDC_SYNC_RST
MACRO_GROUP: XPM
XPM_CDC_SYNC_RST
src_rst dest_rst_out
dest_clk
X15901-020421
Introduction
This macro synchronizes a reset signal to the destination clock domain. Unlike the
XPM_CDC_ASYNC_RST macro, the generated output will both assert and deassert
synchronously to the destination clock domain.
clock. You can define the number of register stages used in the synchronizers and the initial value
of these registers after configuration. You can also enable a simulation feature to generate
messages which report any potential misuse of the macro.
Port Descriptions
Handling
if Unused
_RISING
dest_rst_out O 1 dest_clk N/A Active This is src_rst synchronized to the
registered.
src_rst I 1 N/A N/A Active Source reset signal.
Design Entry Method
Design Entry Yes/No

Instantiation Yes
Inference No

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Allowed
Values
INIT DECIMAL 1, 0 1 • 0: Initializes synchronization registers to 0
• 1: Initializes synchronization registers to 1
The option to initialize the synchronization
registers means that there is no complete x-
propagation behavior modeled in this macro. For
complete x-propagation modeling, use the
xpm_cdc_single macro.
be reported.
reported.

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Chapter 5: Design Flow Steps
Chapter 5
Design Flow Steps

This section describes customizing and generating the core, constraining the core, and the
simulation, synthesis, and implementation steps that are specific to this IP core. More detailed
information about the standard Vivado® design flows and the IP integrator can be found in the
following Vivado Design Suite user guides:
• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
• Vivado Design Suite User Guide: Designing with IP (UG896)
• Vivado Design Suite User Guide: Getting Started (UG910)
• Vivado Design Suite User Guide: Logic Simulation (UG900)
Customizing and Generating the Core

This section includes information about using Xilinx® tools to customize and generate the core in
the Vivado® Design Suite.
If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design
Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP
integrator might auto-compute certain configuration values when validating or generating the
design. To check whether the values do change, see the description of the parameter in this
chapter. To view the parameter value, run the validate_bd_design command in the Tcl
console.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado
Design Suite User Guide: Getting Started (UG910).
Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary
from the current version.
The following section defines the possible customization options in the XPM CDC Generator
core Vivado IDE.

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User Parameters
The following table shows the relationship between the fields in the Vivado® IDE and the user
parameters (which can be viewed in the Tcl Console).
Table 23: User Parameters
Allowed
Values
DEST_SYNC_FF DECIMAL 2 to 10 4 The number of register stages used to synchronize
INIT_SYNC_FF DECIMAL 0, 1 0 • Disable behavioral simulation initialization value(s)
on synchronization registers.
• Enable behavioral simulation initialization value(s)
on synchronization registers.
SIM_ASSERT_CHK DECIMAL 0, 1 0 • Disable simulation message reporting. Messages
related to potential misuse will not be reported.
• Enable simulation message reporting. Messages
related to potential misuse will be reported.
SRC_INPUT_REG DECIMAL 1, 0 1 • Do not register input (src_in)
• Register input (src_in) once using src_clk
WIDTH DECIMAL 1 to 1024 2 Width of the single-bit array (src_in) that will be
synchronized to the destination clock domain.
REG_OUTPUT DECIMAL 0, 1 0
• 0: Disable registered output
SIM_ASSERT_CHK DECIMAL 0, 1 0 • Disable simulation message reporting. Messages

related to potential misuse will not be reported.
• Enable simulation message reporting. Messages
related to potential misuse will be reported.
SIM_LOSSLESS_GRAY_CHK DECIMAL 0, 1 0 • Disable simulation message that reports whether
src_in_bin is incrementing or decrementing by one,
guaranteeing lossless synchronization of a gray
coded bus.
• Enable simulation message that reports whether
src_in_bin is incrementing or decrementing by one,
guaranteeing lossless synchronization of a gray
coded bus.
DEST_EXT_HSK DECIMAL 1, 0 0 • An internal handshake will be implemented in the
macro to acknowledge receipt of data on the
destination clock domain. When using this option,
the valid dest_out output must be consumed
immediately to avoid any data loss.
• The user must implement external handshake logic
to acknowledge receipt of data on the destination
clock domain.
REG_OUTPUT DECIMAL 0, 1 0 • 0: Disable registered output.
• 1: Enable registered output.

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Table 23: User Parameters (cont'd)
Allowed
Values
When RST_USED = 0, src_pulse input must always be
defined during simulation because there is no reset
logic to recover from an x-propagating through the
macro.
When RST_USED = 0, src_pulse input must always be
defined during simulation because there is no reset
logic to recover from an x-propagating through the
macro.
WIDTH DECIMAL 1 to 1024 1 Width of the bus that is synchronized to the destination
clock domain.
INIT DECIMAL 1, 0 1 • Initializes synchronization registers to 0
• Initializes synchronization registers to 1
The option to initialize the synchronization registers
means that no complete x- propagation behavior is
modeled in this macro. For complete x-propagation
modeling, use the xpm_cdc_single macro.
Output Generation
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896).
Constraining the Core

Required Constraints
This section is not applicable for this IP core.
Device, Package, and Speed Grade Selections
Clock Frequencies

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Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
For comprehensive information about Vivado® simulation components, as well as information
about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation
(UG900).
Synthesis and Implementation

For details about synthesis and implementation, see the Vivado Design Suite User Guide: Designing
with IP (UG896).

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Chapter 6: Upgrading
Chapter 6
Upgrading
This appendix is not applicable for the first release of the core.

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Appendix A: Verification, Compliance, and Interoperability
Appendix A
Verification, Compliance, and

Interoperability
The XPM CDC Generator core and the associated XPM libraries are rigorously verified using
advanced verification techniques, including a constrained random configuration generator and a
cycle-accurate bus functional model.
Simulation
The Embedded Memory Generator core has been tested with the Xilinx® Vivado® Design Suite,
Xilinx XSIM, Cadence Incisive Enterprise Simulator (IES), Synopsys VCS, and VCS MX, and
Mentor Graphics QuestaSim.

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Appendix B: Debugging
Appendix B
Debugging
This appendix includes details about resources available on the Xilinx® Support website and
debugging tools.
If the IP requires a license key, the key must be verified. The Vivado® design tools have several
license checkpoints for gating licensed IP through the flow. If the license check succeeds, the IP
can continue generation. Otherwise, generation halts with an error. License checkpoints are
enforced by the following tools:
• Vivado Synthesis
• Vivado Implementation
• write_bitstream (Tcl command)
IMPORTANT! IP license level is ignored at checkpoints. The test confirms a valid license exists. It does not
check IP license level.
Finding Help on Xilinx.com

To help in the design and debug process when using the core, the Xilinx Support web page
contains key resources such as product documentation, release notes, answer records,
information about known issues, and links for obtaining further product support. The Xilinx
Community Forums are also available where members can learn, participate, share, and ask
questions about Xilinx solutions.
Documentation
This product guide is the main document associated with the core. This guide, along with
documentation related to all products that aid in the design process, can be found on the Xilinx
Support web page or by using the Xilinx® Documentation Navigator. Download the Xilinx
Documentation Navigator from the Downloads page. For more information about this tool and
the features available, open the online help after installation.

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Answer Records
Answer Records include information about commonly encountered problems, helpful information
on how to resolve these problems, and any known issues with a Xilinx product. Answer Records
are created and maintained daily ensuring that users have access to the most accurate
information available.
Answer Records for this core can be located by using the Search Support box on the main Xilinx
support web page. To maximize your search results, use keywords such as:
• Product name
• Tool message(s)
• Summary of the issue encountered
A filter search is available after results are returned to further target the results.
Technical Support
Xilinx provides technical support on the Xilinx Community Forums for this LogiCORE™ IP product
when used as described in the product documentation. Xilinx cannot guarantee timing,
functionality, or support if you do any of the following:
• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.
To ask questions, navigate to the Xilinx Community Forums.
Debug Tools
There are many tools available to address XPM CDC Generator design issues. It is important to
know which tools are useful for debugging various situations.
Vivado Design Suite Debug Feature

The Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly into
your design. The debug feature also allows you to set trigger conditions to capture application
and integrated block port signals in hardware. Captured signals can then be analyzed. This
feature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx®
devices.

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The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including:
• ILA 2.0 (and later versions)

• VIO 2.0 (and later versions)
See the Vivado Design Suite User Guide: Programming and Debugging (UG908).
Simulation Debug
For details about simulating a design in the Vivado® Design Suite, see the Vivado Design Suite
User Guide: Logic Simulation (UG900) for information on the Global System Reset.
Hardware Debug
Hardware issues can range from link bring-up to problems seen after hours of testing. This
section provides debug steps for common issues. The Vivado® debug feature is a valuable
resource to use in hardware debug. The signal names mentioned in the following individual
sections can be probed using the debug feature for debugging the specific problems.
General Checks
Ensure that all the timing constraints for the core were properly incorporated from the example
design and that all constraints were met during implementation.
• Does it work in post-place and route timing simulation? If problems are seen in hardware but
not in timing simulation, this could indicate a PCB issue. Ensure that all clock sources are
active and clean.
• If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the
locked port.
• If your outputs go to 0, check your licensing.

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Appendix C: Additional Resources and Legal Notices
Appendix C
Additional Resources and Legal

Notices
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.
Documentation Navigator and Design Hubs

Xilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, and
support resources, which you can filter and search to find information. To open DocNav:
• From the Vivado® IDE, select Help → Documentation and Tutorials.

• On Windows, select Start → All Programs → Xilinx Design Tools → DocNav.
• At the Linux command prompt, enter docnav.
Xilinx Design Hubs provide links to documentation organized by design tasks and other topics,
which you can use to learn key concepts and address frequently asked questions. To access the
Design Hubs:
• In DocNav, click the Design Hubs View tab.

• On the Xilinx website, see the Design Hubs page.
Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.

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References
These documents provide supplemental material useful with this guide:
1. Vivado Design Suite: AXI Reference Guide (UG1037)

2. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
3. Vivado Design Suite User Guide: Designing with IP (UG896)
4. Vivado Design Suite User Guide: Embedded Processor Hardware Design (UG898)
5. Vivado Design Suite User Guide: Logic Simulation (UG900)
6. Vivado Design Suite User Guide: Implementation (UG904)
7. Vivado Design Suite User Guide: Programming and Debugging (UG908)
8. Vivado Design Suite User Guide: Getting Started (UG910)
9. ISE to Vivado Design Suite Migration Guide (UG911)
Revision History
The following table shows the revision history for this document.
Section Revision Summary

02/09/2021 Version 1.0
Initial Release. N/A
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XPM CDC Generator v1.

LogiCORE IP Product Guide

PG382 (v1.0) February 9, 2021

Chapter 3: Product Specification........................................................................... 8

Chapter 4: Designing with the Core................................................................... 11

Chapter 5: Design Flow Steps.................................................................................31

Appendix A: Verification, Compliance, and Interoperability...............36

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Navigating Content by Design Process

Licensing and Ordering

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Table 1: Port Descriptions

Note: Signal asserts asynchronously but

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Table 1: Port Descriptions (cont'd)

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Table 1: Port Descriptions (cont'd)

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Designing with the Core

General Design Guidelines

Use the Example Design

Recognize Timing Critical Signals

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Make Only Allowed Modifications

• Name, description, macro group, macro subgroup, and family

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Table 2: Port Descriptions

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Table 2: Port Descriptions (cont'd)

Design Entry Method

Table 3: Design Entry Method

Design Entry Yes/No

Table 4: Available Attributes

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Table 5: Port Descriptions

Note: Signal asserts asynchronously but

dest_clk I 1 N/A EDGE Active Destination clock.

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Design Entry Method

Table 6: Design Entry Method

Design Entry Yes/No

Table 7: Available Attributes

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An additional option (SIM_LOSSLESS_GRAY_CHK) is provided to report an error message when

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Table 8: Port Descriptions

Design Entry Method

Table 9: Design Entry Method

Design Entry Yes/No

Table 10: Available Attributes

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Table 10: Available Attributes (cont'd)

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Figure 3: External Handshake Timing Diagram