USB 3.

1
What you need to know

REFERENCE GUIDE
Content
This quick reference guide provides an overview of key USB 3.1 specifications
(rev 1.0 July 23, 2013) and important testing considerations for testing both
USB transmitters and receivers.

Benefits of Implementing Type-C............................................................................................................ 03

Type-C Pin Definitions............................................................................................................................... 04
USB 3.1 Generation Comparison............................................................................................................. 05
USB 3.1 Transmitter Measurement Overview......................................................................................... 06
Data Scrambling........................................................................................................................................ 07
End-to-End PHY Validation....................................................................................................................... 08
Compliance Patterns................................................................................................................................ 09
Transmitter Electrical Parameters......................................................................................................10-11
Receiver Electrical Parameters............................................................................................................... 12
Normative Receiver Tolerance Compliance Test Parameters............................................................... 13
LFPS Transmitter Electrical Specifications & Timing for SuperSpeed Designs.............................14-15
Gen 1 Reference CTLE.............................................................................................................................. 16
Gen 2 Reference Equalizer Function ...................................................................................................... 17
Reference DFE........................................................................................................................................... 17
Initiating Loopback - Power On Device.............................................................................................18-19
Receiver Tolerance Test Overview ( JTOL )............................................................................................ 20
Challenges of TX Testing for Type-C Devices......................................................................................... 21
Challenges of RX Testing for Type-C Devices........................................................................................ 22
Key Considerations................................................................................................................................... 23

02
Benefits of Implementing Type-C

POWER DELIVERY TYPE-C

More Power with USB Power More Flexibility with new reversible
Delivery (100W) USB Type-C connector

ALTERNATE MODE USB IF

More Protocols (DisplayPort, More Speed with USB 3.1 (10 Gbit/s)
Thunderbolt, HDMI, etc.)

03
Type-C Pin Definitions

Tx High-speed Data Path Rx High-speed Data Path

(USB, or TBT/DP Alt-Mode) USB 2.0 (USB, or TBT/DP Alt-Mode)

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12

GND TX1+ TX1- V BUS CC1 D+ D- SBU1 V BUS RX2- RX2+ GND

GND RX1+ RX1- V BUS SBU2 D- D+ CC2 V BUS TX2- TX2+ GND
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12

Cable
Bus Plug Configuration Detection
Power • One becomes VCONN, cable power
Cable
• CC is used for USB-PD communication
Ground

Sideband Use
(not used for USB, only
Alt-modes)

04
USB 3.1 Generation Comparison

USB 3.1 GEN 1 GEN 2

Data Rate 5 Gb/s 10 Gb/s

Encoding 8b/10b 128b/132b

Target Channel Cable + Host/Device Channels (-20dB, 2.5GHz) Cable + Board Ref Channels (-23dB, 5GHz)

LTSSm LFPS, TSEQ, TS1, TS2 LFPSPlus, SCD, TSEQ, TS1, TS2

Reference Tx EQ De-emphasis 3-tap (Preshoot/De-emphasis)

Reference Rx EQ CTLE CTLE + 1-tap DFE

JTF Bandwidth 4.9 MHz 7.5 MHz

Eye Height (TP1) 100 mV 70 mV

TJ@BER 132 ps (0.66 UI) 67.1 ps (0.671 UI)

Backwards Compatibility Yes Yes

Connector Std. A, Micro, Type-C Std. A, Micro, Type-C

05
USB 3.1 Transmitter Measurement Overview

GEN 1 GEN 2
Overview Overview

Sigtest Tektronix Compliance Sigtest Tektronix Compliance

MEASUREMENT
v.3.2.11.2 DPOJET Pattern v4.0.23 DPOJET Pattern

Jitter Budget (RJ, DJ and TJ) Yes Yes CP0,CP1 Yes Yes CP9,CP10

Eye Diagram Yes Yes CP0 Yes Yes CP9

Width@BER Yes Yes CP0 Yes Yes CP9

Height@BER - - - No Yes CP9

SSC Deviation No Yes CP1 Yes Yes CP10

SSC Modulation Rate No Yes CP1 Yes Yes CP10

Differential pk-pk Voltage No Yes CP0 No Yes CP9

Tx Equalization - - - Yes Yes CP13,14,15

LFPS Yes Yes - Yes Yes -

06
Data Scrambling
GEN 1 DATA SCRAMBLING OPERATION NORMATIVE
The scrambling function is implemented using a free running Linear Feedback Shift Register 128b/132b DECODE
(LFSR). On the transmit side, scrambling is applied to characters prior to the 8b/10b encoding.
RULES
On the receive side, descrambling is applied to characters after 8b/10b decoding. The LFSR is
The physical layer shall encode the data on
reset whenever a COM symbol is sent or received.
a per block basis. Each block shall comprise
a 4-bit Block Header and a 128-bit payload.
The data scrambling rules are as follows:
The 4-bit header is set to 0011b for data and
1. The LFSR implements the polynomial: G(X)=X16+X5+X4+X3+1
1100b for control blocks. This header format
2. The LFSR value shall be advanced eight serial shifts for each Symbol except for SKP. allows for the correction of single bit errors in
the header information.
3. All 8b/10b D-codes, except those within the Training Sequence Ordered Sets shall be
scrambled. Ordered sets are control blocks, and all data is
4. K codes shall not be scrambled. sent in data blocks. The following is a list of the
control blocks.

GEN 2 DATA SCRAMBLING OPERATION • TS1 Ordered Set

• TS2 Ordered Set
The scrambler used for Gen 2 operation is different than the scrambler used for Gen 1 operation. • TSEQ Ordered Set
For Gen 2, the LFSR uses the following polynomial: G(X) = X23 + X21 + X16 + X8 + X5 + X2 + 1. • SYNC Ordered Set
• SKP Ordered Set
The scrambler has the following modes of operation: • SDS Ordered Set
1. The scrambler advances and is XORed with the data.

2. The scrambler advances and is bypassed (not XORed with the data).

3. The scrambler does not advance and is bypassed (not XORed with the data).

07
End-to-End PHY Validation

TP0 – Near End Measurements are specified at TP1 TP1 – Far End
The picture above demonstrates how the signal degrades over a lossy channel when it travels from a transmitter to a receiver. This provides a perspective
to the user that the eye at the receiver is likely closed and they need to implement a receiver with CTLE and DFE to open the eye.

Also many high speed serial standards specify the compliance test points at the pins which is TP0. For USB, the compliance test is specified at TP1,
which is the far end, close to the receiver.

08
Compliance Patterns
LFPS SINGLE GEN 1 CP9 During the testing process the DUT (device
under test) sometimes skips a pattern or
toggles the patterns twice leading to a
wrong pattern being tested. Visually it is
not easy to look at the oscilloscope screen
and quickly identify which pattern is being
tested.
LFPS PLUS GEN 2 CP10
Use the screenshots below to serve as a
quick reference guide for troubleshooting
when the compliance test fails due to a
pattern mismatch.

Print this page and place it on your bench

CP0 CP13 so it is handy the next time you are testing.

CP1 CP14 CP15

09
Transmitter Electrical Parameters
Here are some of the critical parameters from the specification that you need to consider for your designs.

Transmitter Normative Electrical Parameters

Gen 1 Gen 2
Symbol Parameter Units Comments
(5.0 GT/s) (10 GT/s)

99.97 (min)
199.94 (min) The specified UI is equivalent to a tolerance of ±300 ppm for each device. Period
UI Unit Interval 100.03 ps
200.06 (max) does not account for SSC induced variations.
(max)
Differential p-p 0.8 (min) 0.8 (min)
VTX-DIFF-PP V Nominal is 1 V p-p
Tx voltage swing 1.2 (max) 1.2 (max)
Low-Power
0.4 (min) 0.4 (min) Refer to Section 6.7.2. There is no de-emphasis requirement in this mode. De-
VTX-DIFF-PP-LOW Differential p-p V
1.2 (max) 1.2 (max) emphasis is implementation specific for this mode.
Tx voltage swing
3.0 (min) Not Nominal is 3.5 dB for Gen 1 operation. Gen 2 transmitter equalization
VTX-DE-RATIO Tx de-emphasis dB
4.0 (max) applicable recommendations are described in Section 6.7.5.2.
72 (min) 72 (min)
RTX-DIFF-DC DC differential impedance Ω
120 (max) 120 (max)
The amount of voltage Detect voltage transition should be an increase in voltage on the pin looking at
VTX-RCV-DETECT change allowed during 0.6 (max) 0.6 (max) V the detect signal to avoid a high impedance requirement when an “off” receiver’s
Receiver Detection input goes below ground.
75 (min) 75 (min) All Transmitters shall be AC coupled. The AC coupling is required either within the
CAC-COUPLING AC Coupling Capacitor nF
200 (max) 265 (max) media or within the transmitting component itself.
Not
tCDR_SLEW_MAX Maximum slew rate 10 ms/s This is a df/ft specification; refer to Section 6.5.4 for details.
applicable
Not ppm/
SSCdfdt SSC df/dt 1250 (max) See note 1.
applicable μs

Note 1. Measured over a 0.5μs interval using CP10. The measurements shall be low pass filtered using a filter with 3 dB cutoff frequency that is 60 times the modulation rate. The filter stopband rejection shall be greater or equal to a second
order low-pass of 20 dB per decade. Evaluation of the maximum df/dt is achieved by inspection of the lowpass filtered waveform.

Souce: USB-IF

10
Transmitter Electrical Parameters (continued)
Here are some of the critical parameters from the specification that you need to consider for your designs.

Transmitter Informative Electrical Parameters

Gen 1 Gen 2
Symbol Parameter Units Comments
(5.0 GT/s) (10 GT/s)

tMIN-PULSE-Dj Deterministic min pulse 0.96 0.96 UI Tx pulse width variation that is deterministic

tMIN-PULSE-Tj Tx min pulse 0.90 0.90 UI Min Tx pulse at 10-12 including Dj and Rj

tTX-EYE Transmitter Eye 0.625 (min) 0.646 (min) UI Includes all jitter sources

tTX-DJ-DD Tx deterministic jitter 0.205 (max) 0.170 (max) UI Deterministic jitter only assuming the Dual Dirac distribution

Tx input capacitance for return

CTX-PARASITIC 1.25 (max) 1.1 (max) pf Parasitic capacitance to ground
loss
Transmitter DC common mode 18 (min) 18 (min) DC impedance limits to guarantee Receiver detect behavior. Measured
RTX-DC Ω
impedance 30 (max) 30 (max) with respect to AC ground over a voltage of 0-500 mV.
Transmitter shortcircuit current
ITX-SHORT 60 (max) 60 (max) mA The total current Transmitter can supply when shorted to ground.
limit
Transmitter DC common-mode 0 (min) 0 (min) The instantaneous allowed DC common-mode voltages at the
VTX-DC-CM V
voltage 2.2 (max) 2.2 (max) connector side of the AC coupling capacitors.
Tx AC common mode voltage
VTX-CM-AC-PP_ACTIVE 100 100 (max) mVp-p Maximum mismatch from Txp + Txn for both time and amplitude.
active
VTX-CM-DC-ACTIVE-IDLE- Absolute DC Common Mode
200 (max) 200 (max) mV
DELTA
Voltage between U1 and U0
Electrical Idle
0 (min) 0 (min)
VTX-IDLE-DIFF-AC-pp Differential Peak – Peak Output mV
10 (max) 10 (max)
Voltage
DC Electrical Idle 0 (min) 0 (min) Voltage shall be low pass filtered to remove any AC component.
VTX-IDLE-DIFF-DC mV
Differential Output Voltage 10 (max) 10 (max) This limits the common mode error when resuming U1 to U0.

11
Receiver Electrical Parameters
Here are some of the critical parameters from the specification that you need to consider for your designs.

Receiver Normative Electrical Parameters

Gen 1 Gen 2
Symbol Parameter Units Comments
(5.0 GT/s) (10 GT/s)

UI Unit Interval 199.94 (min) 99.97 (min) ps UI does not account for SSC caused variations.
200.06 (max) 100.03 (max)
RRX-DC Receiver DC common mode impedance 18 (min) 18 (min) Ω DC impedance limits are needed to guarantee Receiver detect.
30 (max) 30 (max) Measured with respect to ground over a voltage of 500 mV
maximum.
RRX-DIFF-DC DC differential impedance 72 (min) 72 (min) Ω
120 (max) 120 (max)
ZRX-HIGH-IMP-DC- DC Input CM Input 25k (min) 25k (min) Ω Rx DC CM impedance with the Rx terminations not powered,
POS
1
Impedance for V>0 during Reset or power measured over the range 0 – 500 mV with respect to ground.
down
VRX-LFPS-DET- LFPS Detect Threshold 100 (min) 100 (min) mV Below the minimum is noise.
DIFFp-p
300 (max) 300 (max) Must wake up above the maximum.
Note 1. Only DC Input CM Input Impedance for V >0 is specified. DC Input CM Input Impedance for V <0 is not guaranteed and could be as low as 0 Ω.

Receiver Informative Electrical Parameters

Gen 1 Gen 2
Symbol Parameter Units Comments
(5.0 GT/s) (10 GT/s)

VRX-DIFF-PP-POST- Differential Rx peak-to-peak voltage 30 (min) 30 (min) mV Measured after the Rx EQ function (Section 6.8.2).
EQ

tRX-TJ Max Rx inherent timing error 0.45 (max) 0.394 (max) UI Measured after the Rx EQ function (Section 6.8.2).

tRX-DJ-DD Max Rx inherent deterministic timing error 0.285 (max) 0.21 (max) UI Maximum Rx inherent deterministic timing error.

CRX-PARASITIC Rx input capacitance for return loss 1.1 (max) 1.0 (max) pF

VRX-CM-AC-P Rx AC common mode voltage 150 (max) 150 (max) mV Measured at Rx pins into a pair of 50 Ω terminations into
Peak ground.
Includes Tx and channel conversion, AC range up to 5 GHz
V RX- CM-DC-AC-
Rx AC common mode voltage during 200 (max) 200 (max) mV Measured at Rx pins into a pair of 50 Ω terminations into
TIVE-IDLE-DELTA_P the U1 to U0 transition Peak ground.
Includes Tx and channel conversion, AC range up to 5 GHz

12
Normative Receiver Tolerance Compliance Test
Parameters
Here are some of the critical parameters from the specification that you need to consider for your designs.

Input Jitter Requirements for Rx Tolerance Testing

Gen 1 Gen 2
Symbol Parameter Units Notes
(5.0 GT/s) (10 GT/s)

f1 Tolerance corner 4.9 7.5 MHz

JRj Random Jitter 0.0121 0.01308 UI rms 1

JRj_p-p Random Jitter peak- peak at 10-12 0.17 0.184 UI p-p 1,4

JPj_500kHz Sinusoidal Jitter 2 4.76 UI p-p 1,2,3

JPj_1MHz Sinusoidal Jitter 1 2.03 UI p-p 1,2,3

JPj_2MHz Sinusoidal Jitter 0.5 0.87 UI p-p 1,2,3

JPj_4MHz Sinusoidal Jitter N/A 0.37 UI p-p 1,2,3

JPj_f1 Sinusoidal Jitter 0.2 0.17 UI p-p 1,2,3

JPj_50MHz Sinusoidal Jitter 0.2 0.17 UI p-p 1,2,3

JPj_100MHz Sinusoidal Jitter N/A 0.17 UI p-p 1,2,3

V_full_swing Transition bit differential voltage swing 0.75 0.8 V p-p 1

Preshoot = 2.7
V_EQ_level Non transition bit voltage (equalization) -3 dB 1
De-emphasis = -3.3

Notes:
1. All parameters measured at TP1.
2. Due to time limitations at compliance testing, only a subset of frequencies can be tested. However, the Rx is required to tolerate Pj at all frequencies between the compliance test points.
3. During the Rx tolerance test, SSC is generated by test equipment and present at all times. Each JPj source is then added and tested to the specification limit one at a time.
4. Random jitter is also present during the Rx tolerance test.
5. The JTOL specs for Gen 2 comprehend jitter peaking with re-timers in the system and has a 25dB/decade slope.

13
LFPS Transmitter Electrical Specifications
and Timing for SuperSpeed Designs
Here are some of the critical parameters from the specification that you need to consider for your designs.

Normative LFPS Electrical Specification

Symbol Minimum Typical Maximum Units Comments

tPeriod 20 100 ns

tPeriod for SuperSpeedPlus 20 80 ns

VCM-AC-LFPS VTX-CM-AC-PP-ACTIVE mV See Table 6-18 in the complete USB 3.1 specifications rev 1.0 July 23, 2013.

VCM-LFPS-Active 10 mV

VTX-DIFF-PP-LFPS 800 1200 mV Peak-peak differential amplitude

VTX-DIFF-PP-LFPS-LP 400 600 mV Low power peak-peak differential amplitude

Measured at compliance TP1, as shown in Figure 6-19 in the complete USB 3.1
tRiseFall2080 4 ns
specifications rev 1.0 July 23, 2013.
Measured at compliance TP1, as shown in Figure 6-19 in the complete USB 3.1
Duty Cycle 40 60 %
specifications rev 1.0 July 23, 2013.

14
LFPS Transmitter Electrical Specifications
and Timing for SuperSpeed Designs
(continued)
LFPS Transmitter Timing for SuperSpeed Designs1

tBurst tRepeat

Minimum Number
Minimum Typical Maximum Minimum Typical Maximum
of LFPS Cycles 2

Polling.LFPS 0.6 μs 1.0 μs 1.4 μs 6 μs 10 μs 14 μs

Ping.LFPS8 40 ns 200 ns 2 160ms 200ms 240ms

Ping.LFPS for SuperSpeedPlus9 40 ns 160 ns 2

tReset3 80 ms 100ms 120 ms

U1 Exit4,5 600 ns7 2 ms

U2/Loopback Exit4,5 80 μs7 2 ms

U3 Wakeup4,5 80 μs7 10 ms

Notes:
1. If the transmission of an LFPS signal does not meet the specification, the receiver behavior is undefined. 6. A Port in U2 or U3 is not required to keep its transmitter DC common mode voltage. When a port begins U2 exit
2. Only Ping.LFPS has a requirement for minimum number of LFPS cycles. or U3 wakeup, it may start sending LFPS signal while establishing its transmitter DC common mode voltage. To
3. The declaration of Ping.LFPS depends on only the Ping.LFPS burst. make sure its link partner receives a proper LFPS signal, a minimum of 80 μs tBurst shall be transmitted. The
4. Warm Reset, U1/U2/Loopback Exit, and U3 Wakeup are all single burst LFPS signals. tRepeat is not applicable. same consideration also applies to a port receiving LFPS U2 exit or U3 wakeup signal.
5. The minimum duration of an LFPS burst shall be transmitted as specified. The LFPS handshake process and 7. A port is still required to detect U1 LFPS exit signal at a minimum of 300ns. The extra 300ns is provided as the
timing are defined in Section 6.9.2 of the complete USB 3.1 specifications rev 1.0 July 23, 2013. guard band for successful U1 LFPS exit handshake.
8. This requirement applies to SuperSpeed only designs (are only capable of operating at 5Gb/s).
9. This requirement applies to SuperSpeedPlus designs (capable of operating at 10Gb/s and higher speeds).

15
Gen 1 Reference CTLE
USB 3.1 allows the use of receiver equalization to meet system timing and
voltage margins. For long cables and channels the eye at the Rx is closed,
and there is no meaningful eye without first applying an equalization function.
The Rx equalizer may be required to adapt to different channel losses using
the Rx EQ training period. The exact Rx equalizer and training method is
implementation specific.

The equation for the Continuous Time Linear Equalizer (CTLE) used to
develop the specification is the compliance Rx EQ transfer function described
below.

where Adc is the DC gain

ωz = 2πfz is the zero frequency
ωp1 = 2πfp1 is the first pole frequency
ωp2 = 2πfp2 is the second pole frequency

16
Gen 2 Reference Equalizer Function
Equation below describes the frequency response for the Gen 2 Reference
Continuous Time Linear Equalizer (CTLE) that is used for compliance testing.
The equation describes the same first order CTLE as contained in equation
for Gen 1

where Aac is the high frequency peak gain

Adc is the DC gain
ωp1 = 2πfp1 is the first pole frequency
ωp2 = 2πfp2 is the second pole frequency

Reference DFE
In addition to the 1st order CTLE, a one-tap reference DFE is used in transmitter compliance testing. The DFE behavior is described by the equation and
Figure below. The limits on d1 are 0 to 50mV.

where yk is the DFE differential output voltage

y*k is the decision function output voltage, |y*k| = 1
xk is the DFE differential input voltage
d1 is the DFE feedback coefficient
k is the sample index in UI

17
Initiating Loopback - Power On Device
GEN 1

POLLING 65536 256 - 65536 256 - 65536 BDAT

LFPS TSEQ TS1 TS2

4 msec

To get the DUT into loopback, the BERT sends pattern sequences and the device under test (DUT) needs to respond to these sequences for a successful
loopback. Once the loopback is successful, JTOL testing can begin.

Gen 1 Loopback Sequence:

»» Transmit 400 Polling.LFPS (4 msec).

»» Transmit 65536 TSEQ.

»» Transmit 256-65536 TS1.

»» Transmit 256-65536 TS2 with loopback bit set.

»» Start transmitting the BDAT test pattern for 2 msec before starting error calculations.

Note that all jitter sources are added during all transmissions to the device under test. If the device does not go into loopback it fails the test.

18
Initiating Loopback - Power On Device
GEN 2

2-32 SCD1 2-32 SCD2 4-32 LBPM 4-32 LBPM 524288-577288

TSEQ

31-65536 31-65536
CP9 Tektronix’ New BSX Series
TS1 TS2 BERTScope can easily
tackle your USB test and
measurement challenges.
Gen 2 Loopback Sequence:

»» LFPS/LFPS Plus:
• 2-32 SCD1
• 2-32 SCD2
• 4-32 LBPM (w PHY capability)
• 4-32 LBPM (w PHY ready)

»» 524,288 - 577,288 TSEQ It is preferred for the BERT to transmit as close to 524,288 TSEQ as possible

»» 31 - 65536 TS1 (SYNC, 31 TS1, SKP - repeat to up to 65536 total TS1)

»» 31 - 65536 TS2 with loopback bit set

»» Start transmitting the CP9 test pattern. Transmit CP9 for 2 msec before starting error calculations.

Note that all jitter sources are added during all transmissions to the device under test. If the device does not go into loopback it fails the test.

19
Receiver Tolerance Test Overview ( JTOL )
»» 8 test points for USB 3.1 Gen 1 and 9 test points GEN 1 JTOL TABLE
USB 3.1 Gen2
Frequency SJ RJ
»» SSC Clocking is enabled 500 kHz 400ps 2.42ps RMS
1 MHz 200ps 2.42ps RMS
»» BER Test is performed at 10-10 for USB 3.1 Gen 1
2 MHz 100ps 2.42ps RMS
»» For Gen 2 - BER Test is performed at each Sj tone for 2 mins
4.9 MHz 40ps 2.42ps RMS

»» Preshoot/De-emphasis enabled 10 MHz 40ps 2.42ps RMS

20 MHz 40ps 2.42ps RMS
»» Stress verified by TJ/Eye Height
33 MHz 40ps 2.42ps RMS
»» Each SJ term in the table is tested one at a time after 50 MHz 40ps 2.42ps RMS
the device is in loopback mode

The only test the user needs to perform for receiver compliance testing is
JTOL. The above high level bullets are important to remember when you
GEN 2 JTOL TABLE
are running jitter tolerance test. Failure to set these right parameters can Frequency SJ RJ
lead to being non-compliant and failure of test.
500kHz 476ps 1.308ps RMS
1MHz 203ps 1.308ps RMS
2MHz 87ps 1.308ps RMS
4MHz 37ps 1.308ps RMS
7.5MHz 17ps 1.308ps RMS
15MHz 17ps 1.308ps RMS
30MHz 17ps 1.308ps RMS
50MHz 17ps 1.308ps RMS
100MHz 17ps 1.308ps RMS

20
Challenges of TX Testing for Type-C Devices

FROM COMPLEXITY TO CONFIDENCE

 Beyond Compliance  Reduce Validation Time  Global Collaboration
Only relying on compliance tests is not sufficient Test times always play a vital role when access Collaborating with global teams can be
when you are working on characterizing and to the DUT is limited. As designs mature and challenging especially when there isn’t an easy
margining your parts. You need standard move to manufacturing, even 5 mins of savings way to share and analyze waveforms. This
specific measurements built into the oscilloscope on a production floor translates to huge ROI. wastes time, energy and can be quite frustrating.
along with analysis tools such as vertical and
horizontal jitter decomposition to understand Ability to run these measurements using python Easily collaborate more efficiently with
device behaviors. scripts and being able to easily integrate them co-workers, suppliers and customers
into the bigger automation environment is vital. worldwide with Tektronix’ solution. You can
To build confidence on the margin on your This reduces a lot of manual intervention of the analyze waveforms in an offline mode, send
devices, you need the ability to render an tests, simplifying the validation process and them to the necessary people and then work
eye diagram with extrapolation using BER improves productivity of the team. together remotely to solve design issues.
contours and analyze the channel effect on
the signal at the far end. With Tektronix’ solution you can finish both
USB Gen 1 and Gen 2 test suites in less
When a device fails a compliance test, you need than 20 minutes.
the ability to load those same measurements on
the scope, gate them using cursors along with
visual search capabilities.

Tektronix’ DPOJET and SDLA are the SMA cables to scope Host

analysis and debugging tools, which help Ping.LFPS from

accomplish testing beyond compliance. signal generator

(pattern toggle)

1m USB
Type-C
cable

21
Challenges of RX Testing for Type-C Devices

FROM COMPLEXITY TO CONFIDENCE

 Protocol Awareness  Debug  Beyond Compliance
With the complexity of the USB specifications, When compliance testing fails it is time Receivers can be expensive to design and over
it is hard to track down where in the loopback consuming to find the root cause. The ability to designing margins on the Receiver can be even
sequence does your device under test fail. You see some trends in failures to derive conclusions more expensive. To ensure that the Receiver
need the ability to visually look at the pattern is vital. has sufficient margin to pass compliance, be
sequence trace being sent by the BERT to the competitive while maintaining the cost of the
DUT and understand which part of the sequence The fastest and easiest way is to have parts can be a tricky affair.
is not being looped back. sophisticated error analysis tools at your
disposal. The bit-error location tool on Margin analysis tools on the BERTScope
Having protocol awareness built into Tektronix’ BERTScope provides insight on helps you understand the margin available
the BERTScope enables the user to the randomness or systematic behavior of on early designs and make the right kind
troubleshoot loopback sequence issues errors being reported during JTOL test. This of trade off decisions before you finalize
and provides insight in terms of timing allows you to isolate the issues, be it on the your designs. The ability to test beyond
issues or pattern sequence being non- design side or due to channel effects. compliance with such margin tools makes
compliant. the difference for your product to be a
winner in market place.

Tektronix’ New BSX

Series BERTScope can
easily tackle your USB
test and measurement
challenges.

22
Key Considerations
Things to think about before planning your USB testing and certification for compliance:

»» How will you get more insight into »» How will you automate all the
measurements failures reported by measurements to reduce test times? Don’t waste your time.
SigTest for characterization? Make sure your device passes the first time.
»» How will you ensure that your device will
»» How will you execute SSC measurements, be certified by USBIF?
which are not available in SigTest for Gen Ensure you partner with a certified and approved
1 Testing? »» How do you plan to resolve loopback
vendor for the USBIF so you have the confidence
initialization challenges? your design will pass compliance testing. Visit
»» How will you ensure that your device one of Tektronix’ suites at the next plugfest:
interoperability is within the compliance »» How do you plan to debug issues when
limits for last 3 generations of USB Spec? your DUT fails JTOL test? • USB 3.1 Gen2 Tx & Rx – USBIF Approved
Gold Test Suite

»» How will you manage to test beyond »» How do you plan to build competitive • USB 3.1 Gen1 Tx & Rx – USBIF Approved
the compliance test limits for margin specifications for your products, which Gold Test Suite
analysis? highlight margins on your products? • USB 2.0 – USBIF Approved Gold Test Suite

»» How will you test at the far end and • USB PD – USBIF Approved Gold Test Suite
simulate the receiver adaptation for
different DFE values?

Need help in answering these questions.

Your Tektronix Account Manager will be happy to help, just give them a call.

To contact any of our worldwide offices for assistance please refer to the telephone numbers on the next page.

23
 Contact Information:
Reference URLs: Australia* 1 800 709 465
Austria 00800 2255 4835
USB3.1 Base spec and supplemental specs
Balkans, Israel, South Africa and other ISE Countries +41 52 675 3777
http://www.usb.org/developers/docs/
Belgium* 00800 2255 4835
Brazil +55 (11) 3759 7627
USB Type-C cable and connector specification
Canada 1 800 833 9200
http://www.usb.org/developers/usbtypec/
Central East Europe / Baltics +41 52 675 3777
Central Europe / Greece +41 52 675 3777
Compliance Test Specification (CTS)
Denmark +45 80 88 1401
http://www.usb.org/developers/compliance/ssusb_testing/
Finland +41 52 675 3777
France* 00800 2255 4835
Tektronix USB3.1 solution, MOIs, Webinars, Application Notes:
Germany* 00800 2255 4835
https://www.tek.com/usb
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Portugal 80 08 12370
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Singapore 800 6011 473
South Africa +41 52 675 3777
Find more valuable resources at TEK.COM Spain* 00800 2255 4835
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Switzerland* 00800 2255 4835
Taiwan 886 (2) 2656 6688
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United Kingdom / Ireland* 00800 2255 4835
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Information in this publication supersedes that in all previously published material.
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