Clamping Circuits

2.
15 CLAMPING CIRCUITS
A clamping circuit is a circuit that reproduces the input signal on the output side
by shifting it either up or down.
2.15.1 Clamping circuit to shift the waveform down

Let us consider the circuit given in Figure 2.56. When the diode conducts, the
output voltage is equal to the forward voltage of the diode. For an ideal diode,
the output voltage is zero when it conducts. Let v D ( t ) be the voltage across the
diode when it conducts. Then, the current in the diode is
v s ( t ) − VB − v D ( t )
i D (t ) =
R
From this equation, it is evident that the diode will conduct as long as
v s ( t ) ≥ VB + v D ( t )
and the output voltage across the diode is
v o (t ) = v D (t )
For an ideal diode, v o ( t ) = 0 because v D ( t ) = 0.
Figure 2.56: A clamping circuit
. Since we want the input voltage to be reproduced exactly without any

clipping, the maximum value of v s ( t ) must not be greater than VB . If v s ( t ) is
greater than VB , then the circuit will also behave as a limiter. On the other hand,
when is v s ( t ) less than VB , the diode does not conduct. The output voltage is
simply the input voltage minus VB . Thus, the output waveform has been shift
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down by VB as shown in Figure 2.57 when Vsm ,the maximum value of v s ( t ) , is
less than [VB − v D ( t )]. .

The input and output waveforms are given in Figure 46a and b,
respectively. Note that the waveform is shifted in the direction of the arrow of
the diode. This is a good way to remember the shift.
Figure 2.57: Output voltage of the circuit given in Figure 2.56.
In practice, the clamping circuit uses a capacitor instead of a dc voltage

source as shown in Figure 2.58. The only condition is that the time constant RC
of the circuit must be greater than the time period of the waveform T so that
capacitor barely discharges during its discharging process. For all practical
purposes, we assume that this condition is met as long as RC ≥ 10 T.

Figure 2.58: Clamping circuit with a capacitor
This is how the circuit in Figure 2.58 works. During the positive half-cycle
of the input waveform, the diode is forward biased and the capacitor charges to
a maximum positive voltage of [Vsm − v D ( t )] with the polarity as shown. Note that
Vsm is the maximum value of the input voltage and v D ( t ) is the corresponding
voltage across the diode.

During the negative half-cycle, the diode is reversed biased. The
capacitor will now tend to discharge through R and the voltage source v s ( t ) in
an attempt to charge in the opposite direction. If the time constant, RC, is much
greater than the time-period of the input waveform, the capacitor discharge is
almost negligible. Thus, the voltage across the capacitor stays almost at its
maximum value. In other words, the capacitor behaves like a constant voltage
source very similar to that in Figure 2.56.
2.15.2 Clamping circuit to shift the waveform up

Consider the circuit shown in Figure 2.59 with a time constant RC much
greater than the time period T of the input waveform. For all practical purposes,
let us assume that this condition is met as long as RC ≥ 10 T.

This is how this circuit works.
During the positive half-cycle of the input waveform, the diode is reverse
biased and the capacitor cannot charge through R due to its large time constant.
Thus, the capacitor voltage stays basically at zero. Hence, the output voltage is
the same as the input voltage.
During the negative half-cycle, the diode is forward biased. For an ideal
diode, the capacitor charges to its maximum value of Vsm with the polarity as
shown. The output voltage is zero as the ideal diode is now conducting.
During the next positive half-cycle, the diode is reverse biased again. The
output voltage is algebraic sum of the voltage across the capacitor and the input
voltage. During this cycle, the capacitor cannot discharge owing to its large time
constant again. From now onward, the capacitor voltage stays at Vsm with the
polarity as shown in the figure. Thus, the capacitor behaves like a constant
voltage source whose value is equal to the maximum value of the input voltage
source for an ideal diode in the circuit.
The input and the output voltage waveforms are given in Figure 2.60.
Note that the output voltage has shifted up, its minimum value is zero, and the
maximum value is 2 Vsm . Once again, note that the shift is in the direction of the
arrow of the diode. Since there is no voltage source in series with the diode, the
minimum output voltage under deal condition is zero.
Figure 2.59: Clamping circuit for upward shift

Figure 2.60: (a) Input and (b) output waveforms of the clamping circuit
given in Figure 2.59.
2.15.3 Another Example of a Clamping Circuit

Consider the circuit given in Figure 2.61a, where the capacitor is initially
uncharged and the input voltage is given in Figure 2.62a.
As the input voltage jumps to its high value of 3 V, the ideal diode is
forward biased and the corresponding circuit is given in Figure 2.61b. The
capacitor immediately charges up to 2 V with the polarity as indicated in Figure
2.62b, and the output voltage is 1 V in accordance with the ideal-diode
assumption. The capacitor remains charged until the input voltage reverses its
polarity.
Figure 2.61: (a) A claming circuit, (b) when diode conducts, and (c) when
diode is reverse biased.

When the input voltage becomes negative ( – 3 V), the diode is reverse
biased as shown in Figure 2.61c. The current completes its path through the
resistor. If the time constant (RC) is very large, the capacitor voltage basically
remains unaffected and there is a 6 V drop across R with the polarity as shown
in the figure. Thus, the output voltage is – 5 V.
(a) (b)
Figure 2.62: (a) Input and (b) output waveforms of the claming circuit given
in Figure 2.61a

2.15.4 APPLICATIONS OF CLAMPING CIRCUITS
Let us now discuss couple of applications of clamping circuits, namely ac
voltmeter and the voltage doubler circuit.
AC Digital Voltmeter
A clamping circuit allows us to measure the peak value of an ac voltage
with a dc voltmeter. However, the scale can as well be calibrated to read the
effective (or rms) value of the alternating voltage being measured.
The circuit shown in Figure 2.63 consists of a clamper circuit and a low-
pass filter. The two resistors in the circuit, R 1 and R 2 , are very large and are
selected to draw negligible current from the input voltage source. The clamping
circuit shifts the maximum value of the input voltage to zero when the diode is
treated as an ideal component. When the input voltage varies as shown in
Figure 2.64a, the output voltage at the clamper circuit varies from 0 to – 2 Vsm ,
where Vsm is the peak value of the input signal v s ( t ) . The output voltage v1 ( t ) of
the clamper circuit, therefore, has a dc value of – Vsm .

The output of the clamper circuit is the input to an RC filter. The value of
capacitor C 2 is very large so that its impedance is negligible in comparison with
R 2 . In other words, C 2 is basically a short circuit at the frequency of the input
signal. Thus, the output voltage of the filter is almost dc, as shown by the dark
solid line in Figure 2.64b, and its value is – V M .
Figure 2.63: AC voltmeter circuit

Figure 2.64: (a) Input and (b) output waveforms of an ac digital voltmeter
circuit
A Voltage Doubler Circuit

Another application of the clamping circuit, which is usually exploited in
the generation of high voltage, is the voltage doubler circuit. In its simplest
form, the voltage doubler circuit is given in Figure 2.65. The output stage of this
circuit is referred to as the peak detector. In this case, the output voltage is
equal to the peak-to-peak value of the input voltage.
Figure 2.64: A voltage doubler circuit
Let us assume that the input voltage is a sinusoid as shown in Figure

2.66a. Its mathematical expression is
v s ( t ) = Vsm sin(ωt ) V

Then the output voltage of the clamping circuit, as shown in Figure
2.66b, is
v1 ( t ) = Vsm + Vsm sin(ωt ) V
The capacitor C 2 charges to the maximum value of v1 ( t ) , which, of

course, is 2Vsm . Since the capacitor C 2 is very large and so is the input
resistance of a dc voltmeter, the dc voltmeter reading is twice the maximum
value of the input voltage.
Figure 2.66: (a) Input and (b) output voltages of the Voltage doubler circuit

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2.

2.15.1 Clamping circuit to shift the waveform down

For an ideal diode, v o ( t ) = 0 because v D ( t ) = 0.

Figure 2.56: A clamping circuit

. Since we want the input voltage to be reproduced exactly without any

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less than [VB − v D ( t )]. .

Figure 2.57: Output voltage of the circuit given in Figure 2.56.

In practice, the clamping circuit uses a capacitor instead of a dc voltage

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voltage across the diode.

2.15.2 Clamping circuit to shift the waveform up

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Figure 2.59: Clamping circuit for upward shift

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2.15.3 Another Example of a Clamping Circuit

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the clamper circuit, therefore, has a dc value of – Vsm .

Figure 2.63: AC voltmeter circuit

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A Voltage Doubler Circuit

Figure 2.64: A voltage doubler circuit

Let us assume that the input voltage is a sinusoid as shown in Figure

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The capacitor C 2 charges to the maximum value of v1 ( t ) , which, of

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