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    DSD Lab Experiment-8 (A) : To Design and Implement A SR Flip-Flop Using Behavioural Modeling

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    raman Mehta
    This document describes designing and implementing an SR flip-flop using behavioral modeling. It includes the circuit diagram, truth table, VHDL code for the SR flip-flop, testbench code to simulate it, and screenshots of the simulation and Logisim circuit showing the SR flip-flop works as intended according to the truth table.

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    DSD Lab Experiment-8 (A) : To Design and Implement A SR Flip-Flop Using Behavioural Modeling

    Uploaded by

    raman Mehta
    34 views8 pages
    This document describes designing and implementing an SR flip-flop using behavioral modeling. It includes the circuit diagram, truth table, VHDL code for the SR flip-flop, testbench code to simulate it, and screenshots of the simulation and Logisim circuit showing the SR flip-flop works as intended according to the truth table.

    Original Title

    UE185067_Expt-8(A)

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    This document describes designing and implementing an SR flip-flop using behavioral modeling. It includes the circuit diagram, truth table, VHDL code for the SR flip-flop, testbench code to simulate it, and screenshots of the simulation and Logisim circuit showing the SR flip-flop works as intended according to the truth table.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    34 views8 pages

    DSD Lab Experiment-8 (A) : To Design and Implement A SR Flip-Flop Using Behavioural Modeling

    Uploaded by

    raman Mehta
    This document describes designing and implementing an SR flip-flop using behavioral modeling. It includes the circuit diagram, truth table, VHDL code for the SR flip-flop, testbench code to simulate it, and screenshots of the simulation and Logisim circuit showing the SR flip-flop works as intended according to the truth table.

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    DSD LAB

    EXPERIMENT-8(A)
     
    AIM : T
    ​ O DESIGN AND IMPLEMENT A SR FLIP-FLOP USING 
    BEHAVIOURAL MODELING. 
     
    APPARATUS USED : E
    ​ DA PLAYGROUND , LOGISIM  
     
    THEORY :  
    BLOCK DIAGRAM :  
     

     
     
     
     
     
     
     
     
     
     
    CIRCUIT DIAGRAM :  

     
     
     
    TRUTH TABLE :  
     

    CLK S R Q Q’

    0 x x Qprv Q’prv

    1 0 0 Qprv Q’prv

    1 0 1 0 1

    1 1 0 1 0

    1 1 1 – –

     
     
     
     
    PROGRAM CODE :  
    VHDL CODE : 
    library IEEE; 
    use IEEE.STD_LOGIC_1164.ALL; 
     
    entity SR_FLIPFLOP_SOURCE is 
    Port ( S,R,RST,CLK : in STD_LOGIC; 
    Q,Qb : out STD_LOGIC); 
    end SR_FLIPFLOP_SOURCE; 
     
    architecture Behavioral of SR_FLIPFLOP_SOURCE is 
     
    begin 
     
    process (S,R,RST,CLK) 
     
    begin 
     
    if (RST = '1') then 
    Q <= '0'; 
    Qb <='0'; 
    elsif (CLK='1')then 
    if (S /= R) then 
    Q <= S; 
    Qb <= R; 
    elsif(S ='0' and R = '0')then 
    Q <= Q; 
    Qb <= Qb; 
    end if; 
    elsif (S = '1' AND R = '1') then 
    Q <= 'Z'; 
    Qb <= 'Z'; 
     
    end if;  
    end process; 
    end Behavioral; 
    TESTBENCH CODE : 
    library IEEE; 
    use IEEE.STD_LOGIC_1164.ALL; 
     
    entity testbench is 
    end entity; 
     
    architecture tb of testbench is 
     
    component SR_FLIPFLOP_SOURCE is 
    Port ( S,R,RST,CLK : in STD_LOGIC; 
    Q,Qb : out STD_LOGIC); 
    end component; 
     
    signal S_tb, R_tb, RST_tb, CLK_tb, Q_tb, Qb_tb : STD_LOGIC; 
     
    begin 
    uut: SR_FLIPFLOP_SOURCE port map(S_tb, R_tb, RST_tb, CLK_tb, Q_tb, Qb_tb); 
     
    Stim : process 
    begin 
    RST_tb <= '0'; 
    wait for 10ns; 
    RST_tb <= '1'; 
    wait for 10ns; 
    RST_tb <= '0'; 
    wait for 10ns; 
    CLK_tb <='0'; 
    wait for 10ns; 
    CLK_tb<='1'; 
    wait for 10ns; 
     
    S_tb <= '1'; 
    R_tb <= '0'; 
    wait for 20 ns; 
     
    S_tb <= '0'; 
    R_tb <= '0'; 
    wait for 20 ns; 
     
    S_tb <= '0'; 
    R_tb <= '1'; 
    wait for 20 ns; 
     
    S_tb <= '1'; 
    R_tb <= '1'; 
    wait for 20 ns; 
    assert false report "Test done." severity note; 
    wait; 
     
    end process; 
    end tb; 
     
     
     
     
     
    PROGRAM SCREENSHOT : 

     
     
    SIMULATION : 

     
     
     
     
     
     
    LOGISIM SCREENSHOT : 

     
     

     
     
     
     
     
     
     
     
     
      
     
    RESULT : ​THE PROGRAM AND SIMULATION OF S
    ​ R FLIP-FLOP​ IS 
    WORKING PROPERLY. 
     

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