Fundamentals of Fault Detection

LGLite + Load Board

APPLIED DIGITAL MICROSYSTEMS PVT LTD

D-216, ANSA INDUSTRIAL ESTATE, SAKI VIHAR ROAD,
ANDHERI EAST, MUMBAI 400 072.
Tel: (91-22 -)28470817, 66924483/4
Email: [email protected]
Web: admpl.com
 Introduction to LGLite – ATE training

LGLite-ATE - a new generation three-in-one product includes an Interactive

Pattern Generator, Logic Analyzer and a Frequency Counter. The combination of
Pattern Generator and Logic Analyzer is a powerful tool for designing; debugging
and automated testing of digital discrete and C/CPLD/FPGA based designs.

Testing determines whether or not a device under test (DUT) operates correctly
by comparing known output to the DUT response. Functional testing refers to a
test procedure in which any functional or non-functional inputs may be applied to
a DUT to observe its behavior. LGLiteATE provides tools to apply patterns,
observe the response and evaluate the DUT for the specifications it has been
designed. To perform these tests the user has to develop a test flow, known as
test program, that tells the tester how a particular test needs to be run. Once the
test program is developed the DUT can be tested under varying operating
conditions.

Testing Semiconductor device for all possible failures is not feasible. We have to
restrict the class of faults to be considered. This restricted class is called a fault
model. Since there are many types of defects, such as bridging faults and stuck-
at faults, that need to be detected, a number of different test methods are often
used on an IC. Students learn various methods for generating test patterns to
study fault analysis.

How to Test Device Faults

Usual workflow of testing DUT faults is shown below.
1. First, load DUT you want to test.
2. Generate a test set that will be applied to the inputs of circuit.
3. Select measurement options: scope of defects and mode of test.
4. Run the test.
5. After test is finished – Create a report about the results of experiment.
Device Faults Modeling and Testing Procedure

Testing a device can be performed at different points from design concept

through full device fabrication. The existences of a fault in a circuit will likely
causes failures of operation. By modeling the effects of each type of fault, one
can predict the consequences of a particular fault on the operation of an IC.

Bridging fault refers to two or more signal lines shorted together. Sometimes, a
bridging fault can be regarded as 1-dominant (OR bridge) when the adjacent
shorted line is forced to 1. It can also be treated as 0-dominant (AND bridge)
when the adjecent-shorted line is forced to 0.

Stuck-at fault at the gate level means a node of a circuit is constantly 0 or 1.

These nodes can be inputs or outputs of logic gates or flip-flops. In a stuck-open
fault, the transistor is always OFF (it does not conduct current). In a stuck-on
fault, the transistor is always ON (it always conducts).

Simulation
When the design of circuit is being developed with EDA tools, the design needs
to be simulated to ensure all functions are correct before fabrication. In this step,
a VHDL net list of a design that has whole structure of the circuit, is simulated.

Device debug and characterization test

Some of the initial fabricated devices are used as samples to verify the operation
of a design, using full functional test and parametric tests (including DC and AC
parametric tests) before the design is sent to production.

The purpose of characterization test is determining limits of device parameters

at which the device will be operational. The purpose of functional test is mainly
detecting whether a device has stuck-at faults or other faults that affect logic
states. These samples need to be tested in different operating environments to
observe how behavior changes based on different operating conditions. Some
specific sequences of input test vectors may lead to device failures. If these
failures are analyzed deeply, one can find problems in the fabrication process
and the chosen test limits. These sample chips can be compared to the designed
simulation model

Production test is used to distinguish faulty devices from good devices.

Moreover, devices need to be tested on Automatic Test Equipment (ATE). Since
a large number of devices must be tested, the test time plays an important role in
this step, requiring the design of efficient tests.
Typical characterization test program flow

In characterization test, there are number of tests that are designed for testing
electrical parameters. In this step, engineers are required to set up both ATE and
test programs

In functional test, a sequence of test vectors is applied to a device to check

whether the output functions are the same as expected. For example, if a device
has 60 pins, and each pin has binary state (0 or 1), the number of possible test
vectors is 260. A 250 Mhz ATE will require 1281023 hours to finish all functional
test.

During Contact test for device packaging, tests are performed to identify
package pin is shorted to other pins or a package pin is open to the internal die.

Device DC parameters test such as leakage current, and input and output
voltage are tested to ensure tested values are within the electrical specifications.

Power supply current tests usually include gross IDD current test, static IDD
current test, dynamic IDD current test and power supply bump test. Power supply
Current test can measure current consumed when device is powered up. In this
test, measuring the current value from a power supply can determine if some
physical defects exist inside the chip.
IDDQ testing is a supplemental test method to find bridging and other faults in
CMOS circuits by measuring quiescent power supply current for a bridging fault,
the IDDQ test vector set generated by automatic test pattern generation (ATPG)
is to toggle on and off as many transistors as possible.

The main purpose of AC parametric test is to make sure that the device can
meet all timing specifications

Production test is typically performed by using GO/NOGO testing. In order to

minimize the cost of test, test time is required to be reduced as much as
possible. Again, the functional test is performed to detect stuck-at faults or other
faults that affect logic states in production test.

The user creates Test programs that run on the ATE to perform device testing.
The Test program has three main inputs:
1. ATE to device pin mapping,
2. Test Vector List and
3. Test vector Sequence flow.
The ATE to device pin mapping describes the names of the DUT signal that is
connected to the ATE Drive or Response channels. The Test Vector lists the
names of each individual test vector and specifies the voltage level and signal
transition for each drive and response pin. The Test Vector Sequence
determines which predefined test vectors should be used and sequenced for a
specific test.
 Test Pattern Generation for Digital Circuit Fault

The central element of the Digital Circuit Fault study is standard 74xx digital chip
based simple circuit implemented on Load Board with programmable shorts and
opens inserted using simple flying leads. LGLite with Load board allows you to
experiment with various aspects of faults in device testing.

The document describes learning methods for generating tests for simple faults
for combinational circuits on Load Board using NAND, NOR, AND, OR gates
which have no feedback loops or memory elements as shown above.

Circuit Implementation on Load Board

The berg stick and flying leads can be used to wire connection between gates to
implement the test circuit shown above. Also test faults can be easily inserted.
Basic fault models for LGLiteATE testing
1) Stuck-at fault model. A signal, or gate output, is stuck at a 0 or 1 value,
independent of the inputs to the circuit.
2) Bridging fault model. Two signals are connected together when they
should not be. Since there are n^2 potential bridging faults, we normally
restrict to signals that are physically adjacent in the design.

Testing a gate for SSL fault

AND – OR Circuit with Stuck at Fault

A test pattern for a potentially defective circuit is a set of inputs for the circuit that
will cause the circuit outputs to be different if the circuit is defective than if it is
defect-free. To derive the input set, we must have some model for possible
defects (faults) in the circuit. We will use the model most popular with existing
testing systems: the single stuck-at model. In this model, a defective circuit is
assumed to behave as if it were defect-free, with the exception of one wire that is
tied to either logic 0 or logic 1.

To generate a test pattern for above circuit with a wire stuck at 1, we must
ensure that the wire “E” in question should take on the logic value 0 in a correctly
functioning circuit. If this is not the case, the circuit outputs will be the same
whether or not the circuit is malfunctioning because the faulty circuit and the
good circuit would show the same values. The wire E is labeled with a 0/1 to
denote that wire E is the site of a fault such that E will carry the value 0 if the
circuit is functioning correctly and will carry the value 1 if the circuit is defective.
When a line has a different value in the faulted and un-faulted circuits, it is said to
have a discrepancy.
We now depict two different test patterns, the first one detects E stuck-at 1 and
the second test pattern does not detect E stuck-at 1. We say that the first test
pattern covers E stuck-at 1 and next test pattern fails to cover E stuck-at 1.

The best way of creating a test pattern is by means of structural method. To

generate a test pattern, we assign values corresponding to the discrepancy at
the faulted line and then search for consistent values for all circuit lines such that
the discrepancy is visible at a circuit output.

The Structural test pattern generation is performed using three basic operations:
1) Fault Sensitization
2) Fault Propagation and
3) Line Justification

Fault sensitization is the process of generating a discrepancy at the fault site.

We should look for a particular line stuck at 0, and then this line must take on the
value 1 in the correctly functioning circuit.

Fault propagation is the process of moving a discrepancy closer to a circuit

output. Using our notation, we want to get a 0/1 or a 1/0 to a circuit output. We
need the E line stuck at 1 to be propagated to output X. Note that if line F is given
a value of 1 then the fault is not visible at output X.

Line justification is the process of assigning consistent values to all other lines
in the circuit that were not assigned values through fault sensitization or fault
propagation.
Specifying test sequence

Test Vectors should be created using Notepad editor line by line (each line is
interpreted as a separate vector in the sequence) by using “0” and “1” symbols.
The length of each vector should be equal to the number of inputs of selected
circuit. The test vector can be loaded using OpenVCTFile menu option.

Exhaustive test

Instead of entering test set manually you can use Pattern menu exhaustive
sequence. You can always save entered/generated test sequence to file by using
“Save…” button. Later the test set can be modified and loaded by opening this
test file.

Exhaustive test set will contain all the possible input test vectors for selected
circuit. For our 4 input example (A, B, C, D)” circuit the following vectors will be
required: “0000” , “0001”, “0010”, …….”1110”, ”1111”.

Random test
By pressing “Random Test” option in the pattern men, you will get a number of
test vectors that were generated randomly. The desired quantity of random
vectors can be adjusted using the field located next to the button. The length of
each vector will be equal to the number of inputs selected in the menu.
Test Fault Options:
First of all you can limit the scope of defects to test by inserting one of the
following faults using flying leads:
1. Stuck-at faults – either 0 or 1
2. Input shorts – shorting two different inputs
3. Input to output shorts

Interpreting results
The results of test that was applied to defect in the pattern testing mode should
be tabulated and shown as follows

Test Vector -ABCD X – output Result (Pass/Fail)

Each row in the Test Vector column corresponds to test vector from the test set.
The first column lists the entire test vectors were applied to the device inputs.
The last column indicates whether the selected defect was detected (“FAIL”
condition) by the vector or not (“PASS” condition). The PASS/FAIL condition is
determined by comparing of expected output value X (correct value) with actually
received output during the test. That is shown in column “X”. Symbols “0” and “1”
mean the expected values of the output X. Marks “OK” or “Fail” indicate if the
actual value of output X (that was received during the test) was correct or not. If
at least one of the outputs gets incorrect value (“Fail”) then the corresponded test
will be marked as “FAIL”.

Testing AND- OR Logic for stuck at fault

Step 1. Provide POWER to both the chip “7408 & 7432”

A logic analyzer is not meant to provide supply voltage to your DUT on Load-
board. If you attempt to do so, your chip may draw more current than the logic
analyzer can supply. So for any DUT, you will need to provide VCC & GND from
an external power supply.

Step 2. Attach Pattern Generator to your DUT “A,B,C,D”:

Configure LG-Lite PG Channel #1 thru #8 as Pattern Generator. Using flat cable,

attach LGLite channel 1-4 to Load-board first header . Connect output flying lead
wire #1, #2 , #3 and #4 from Load-board to ZIF DUT PIN #1(A), #2(B) , #4(C)
and #5(D) of the 7408 AND Gate.

The output of both the AND gates PIN #3(E) and #6(F) should now be connected
to 74LS32 OR gate PIN #1 and #2. The PIN #3 (X) of the OR Gate is the output.

Note, all components (the DUT, and all cables) must share a common-ground
point. This is true for any testing you do with LGLite.

Step 3. Attach Logic Analyzer to your DUT –“X”:

The pattern-generator provides stimulus to your DUT. We now need to attach the
logic analyzer cables to your DUT to monitor the output of the pattern generator
(PG) & the DUT’s response to the PG stimulus. Connect LGLite LA input flying
lead wire PIN #9 from Load-board to ZIF 7432 DUT PIN #3(X) of OR gate.
Step 4. Configure LGLite – LA/PG to Test CMOS device (DUT)

The configure menu option allows the user to configure the channels in-group of
8 as LA or PG. We configure first 8 channels (1-8) as PG and next 8 channels
(9-16) as LA.

The PG channels will provide 'Drive' or a 'test pattern' to your DUT CHIP on the
Load board. LA channels will record output signals from your DUT CHIP in
response to the drive signal you create.

Step 5. From the Waveform menu, choose->clock or the clock button

Set the clock frequency to match the clock frequency of your DUT. Note, even if
your device is combinational, it still has a frequency at which the data must be
presented to the chip. Clocking can be from 50Mhz to 1Khz.

Step 6.From the LGATE menu, choose: OpenVCTfile

This is where you will setup the test vector (or pattern) to stimulate your DUT.
The Vector file is in plain text. The openVCTfile loads the vector and can be seen
in the waveform window. This vector is text implementation of truth table for your
test circuit with a fault. The Vector sequence uses the defined vectors for writing
into the PG – RAM. Note the vector sequence is nothing but the structure-
based pattern to detect stuck at fault.
Programming the LGLite ATE using English Script symbols.

Test engineers are valuable assets that provide a matter of expertise to the
development of test and measurement sequences. However, their productivity is
greatly enhanced by our unique and tested text based approach to test program
development without the need to resort to becoming a software developer,
engaging a software development team or to even think about the software
development process.

The following list summarizes the major objectives of Script based Test:
1. Be capable of storing test data for all semiconductor devices as file.
2. Provide a common format for storage and transmission of data.
3. Provide a basis for portable data reporting and analysis software.
4. Decouple data message format and database format
5. Provide support for optional (missing or invalid) data.
6. Provide complete and concise documentation for developers and users.
7. Make it easy for Engineers to write their own reports or reformat data for
their own database

Symbol Header Description

#TYPLGC Identifies a LGLite ATE Vector file
#REM Comment which is not executed
#CHN NN XXXX Pin Mapping : LG channel number NN
LG Pin Name XXXX
#VEC XXXX Defines Vector and its Vector Name
#REC A 32 bit binary record for later use
#CMP A 32 bit binary compare record
#TRC (VEC XXXX) Writes vector record in LGLite Memory

The VEC XXX

#REC XXXXXXXX XXXXXXXX XXXXXXXX XXXXX111
#REC XXXXXXXX XXXXXXXX XXXXXXXX XXXXX011
#CMP XXXXXXXX XXXXXXXX XXXXXXXL XXXXX011

The #VEC XXXX defines a new named Vector XXXX and the associated 32
bit binary REC data to be written in LGLite ATE memory. In a drive state, the
pin driver of the buffer is engaged and forces the voltage on the pin to be low
or high as determined by a 0 or 1 in the REC pattern. Compare states CMP
are no drive states that use the Logic Analyser inputs to assess incoming
data. To represent the compare states that a pin can take, L, H is defined in
the CMP pattern.

The #TRC XXXX command writes the named vector record sequentially in
LGLite memory.
Step 7: RUNNING THE TEST:

The Waveform window loads the test vector. Click on Go button. Make certain
that your DUT has “VDD” and “GND” properly connected to it from an outside
power supply, as discussed earlier.

The LGLite-ATE is our flagship ATE training product and is the first completely
codeless ATE training tool. Our unique approach to Text based Test program
development allows test engineers to interact with DUT and LGLite-ATE
hardware to allow for the shortest time to develop and learn device testing.

Through our Windows GUI application for test sequence loader, test engineers
can achieve very high levels of ATE training and deliver consistent, documented,
versioned and structured test labs without writing a single line of code. LGLite-
ATE removes the need for the test engineer to be software developers or to
interact with a software development team. Once the Test program is developed
without coding in Windows Notepad, the resulting Test program can be loaded
and executed using LGLite-ATE. The combination of Real time Logic Analyser
and Pattern Generator helps achieve consistent test executions since "what you
code is what you see”.