electronics

Article
A Fast Transient Response Digital LDO with a
TDC-Based Signal Converter
Hongda Zhang, Peiyuan Wan *, Jiarong Geng, Zhaozhe Liu and Zhijie Chen
College of Microelectronics, Faculty of Information Technology, Beijing University of Technology, Beijing 100124,
China; [email protected] (H.Z.); [email protected] (J.G.); [email protected] (Z.L.);
[email protected] (Z.C.)
* Correspondence: [email protected]; Tel.: +86-(010)-6739-1269




Received: 24 December 2019; Accepted: 8 January 2020; Published: 10 January 2020


Abstract: The digital low drop-out regulator (LDO) has been used widely in digital circuits for its
low supply voltage characteristics. However, as the traditional digital LDOs regulate the output
voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. This paper
presents a digital LDO to improve transient response speed with a multi-bit conversion technique.
The proposed technology uses a voltage sensor and a time-to-digital converter to convert the output
voltage to digital codes. Based on a 65-nm CMOS process, the proposed DLDO reduces the settling
time from 147.8 ns to 25.2 ns on average and the response speed is improved by about six times.

Keywords: low drop-out regulator; digital control; fast response; embedded power management

1. Introduction
Process scaling causes the continuous reduction in supply voltage. In particular, the application of
the Internet of things (IoT) makes the low operating supply voltage more important than ever. In such
conditions, dynamic range and bandwidth of integrated circuits are reduced, thus the stability is harder
to control. The fine-grained supply voltage management faces a real challenge. In contrast to analog
low drop-out regulator (LDO), digital LDOs (DLDO) exhibiting ultra-low operating voltage [1–6].
Hence, the DLDO has been widely used in the low source supply voltage conditions and digital
load circuits.
The traditional DLDO employs a barrel shifter, whose output code switches 1 bit in a clock
cycle [7]. When there is a large transient, it takes a long time to regulate the output voltage to the target
value. Some studies have attempted to enhance the transient performance using adaptive regulation
technology [8–13], but the circuit complexity increases obviously and the multiple times regulation is
still required. In [14–16], DLDO with a flash analog-to-digital converter (ADC) is proposed. The ADC
converts the output voltage to the digital domain and a digital controller provides a multi-bit regulation.
Since the comparator offset increases the error of ADC, there may be a deviation in the regulation.
In [17–19], a time-to-digital converter (TDC) is employed to replace ADC. To convert the output voltage
to digital codes, the TDC alters the buffer-gate’s propagation delay by changing the power supply of
the buffer-gate. However, the relationship between the power supply and the propagation delay of
buffer-gate is nonlinear, and the resolution of TDC is degraded. In this paper, a voltage sensor based
on capacitor charging is introduced. Since the proposed TDC operates by changing the time intervals
rather than buffer-gate’s propagation delay, the linearity is improved. With a digital controller behind
TDC, a multi-bit regulation is achieved and the transient response speed is increased.
This paper is organized as follows. Inl Section 2, the fast response DLDO is proposed with circuit
architecture and system dynamic model. Section 3 discusses the circuit implementation of the proposed

Electronics 2020, 9, 132; doi:10.3390/electronics9010132 www.mdpi.com/journal/electronics

Electronics 2020, 9, 132 2 of 13

DLDO. In Section 4, the circuit performance is simulated and the simulation results are shown. Finally,
conclusions are drawn in Section 5.

2. System Overview

2.1. The Architecture of the Proposed DLDO

Figure 1 shows circuit diagrams for the baseline DLDO and the proposed DLDO. The proposed
DLDO consists of three components. The first component is the TDC-based signal converter, which
provides a digital code of the output voltage VOUT to a digital controller. As the second component,
the digital controller outputs a regulation code to drive a PMOS array according to the different inputs.
Finally, the PMOS array M provides appropriate current to regulate the VOUT .

Up 1
VREF 1 u[62:0]
e e*

Ă
Comparator
+ - 0
Down 0

Barrel shifter

VOUT

RL CL

(a)

High-linearity TDC-based PMOS array

signal converter Digital controller
VREF, D[5:0]
Ă VOUT, D - + e u[62:0]
Digital PI
DFFs Controller
Digital
Voltage Subtractor M
sensor TDC

VOUT

RL CL

(b)

Figure 1. The circuit architecture of (a) baseline DLDO and (b) proposed DLDO.

In the TDC-based signal converter, a voltage sensor generates a time signal related to VOUT by
capturing the charging time of a capacitor. The TDC behind the voltage sensor converts the time
signal to a digital code VOUT,D . Subtracting VOUT,D from the reference voltage code VREF,D , the digital
subtractor produces an error value e and drives the digital PI controller to vary the number of turned-on
transistors in M. When the error value e is 0, VOUT,D is equal to VREF,D and output voltage VOUT is
regulated to the target value.
Electronics 2020, 9, 132 3 of 13

In contrast to the conventional DLDO, the proposed circuit regulates its output voltage using a
digital PI controller rather than a shift register. Hence, the number of turned-on transistors can be
switched multi-bits in a clock cycle. A faster response is achieved in the proposed circuit.

2.2. System Hybrid Model

To understand the overall system behavior, a system hybrid model for the proposed DLDO is
shown in Figure 2. The relationship between input and output of the TDC-based signal converter is
rounding linearly and the TDC-based signal converter is modeled as a cascade between gain KTDC and
a rounding function. TDC-based signal converter operates periodically, and the rounding function is
followed by a zero-order holder (ZOH). Since the digital PI controller accumulates the previous output
of the digital subtractor, it acts as the superposition of a gain Kp and an ideal integrator in discrete-time.
The power MOSFETs are driven by a digital circuit, and their parasitic gate capacitances affect the
settling time. The effect is modeled as a time delay e−sTDEL , where TDEL is the delay caused by the
parasitic gate capacitances. The corresponding transfer function in the z-domain is z−TDEL . The load
and power MOSFETs can be approximated as an RC load with gain KDC . The s-domain model of the
load and power MOSFETs is

KDC
P (s) = s (1)
1 + FLOAD

where FLOAD is the output pole frequency and can be written as FLOAD = 1/(2π · RLOAD · CLOAD ).
The corresponding P(z) in z-domain can be represented as

KDC FLOAD z
P (z) = (2)
z − e− FLOAD /FS
where FS is the sampling frequency and FS = 1/T. Thus, the open-loop transfer function between
VREF, D and VOUT can be written as

K −K /F
 
z1−TDEL z − p KPI S
G (z) = K · (3)
(z − 1) z − e− FLOAD /FS

where the open-loop gain K = KDC KP FLOAD . Taking the TDC-based signal converter and the
zero-order holder into account, the entire closed-loop transfer function of the proposed DLDO in
z-domain is

 
K · z1−TDEL z − KP −KKPI /FS
Q (z) =   (4)
z2 + KTDC Kz2−TDEL − 1 + e− FLOAD /FS z − KTDC K KP −KKPI /FS z1−TDEL + e− FLOAD /FS

Because TDEL is much smaller than 1, Equation (4) can be approximated to

 
K · z z − KP −KKPI /FS
Q (z) =   (5)
(1 + KTDC K ) z2 − 1 + e− FLOAD /FS + KTDC K KP −KKPI /FS z + e− FLOAD /FS

Equation (5) provides insights into the stability of the proposed DLDO. Compared with the
transfer function of the traditional DLDO in [20], the PI controller produces an extra zero at z =
(KP − KI /FS ) /KP . The bandwidth and transient response speed of the proposed system are increased.
Electronics 2020, 9, 132 4 of 13

TDC-based Signal VREF, D

Converter
PI Controller
+
VOUT, D e
Round
-
Zero Order
Holder

Output Node: VOUT

Load and
Power MOSFETs
Figure 2. The system hybrid model for the proposed DLDO.

Figure 3 shows the pole plots of the proposed system under different sampling frequency and
integration gain conditions. The simulation parameters are listed in Table 1. As illustrated in the plots,
a large sampling frequency damages the system stability. In addition, the higher integration gain of
the digital PI controller leads to decreasing stability. Hence, large FS and KI should be avoided in the
selection of parameters. In Figure 4, the pole plots of the proposed system under variable load are
shown and the simulation parameters in Table 1 are used. As illustrated in the plots, the increasing
load resistance, which results in a lower load current, reduces the stability of the proposed system.
Meanwhile, the decreasing load capacitance degrades the system stability as well. When the load
capacitance is decreased to 13 pF, the pole is close to the unit circle, and the system is in critical stability.

1 1
Increasing FS
(Step = 15 MHz) KI = 15e7
Imaginary Axis

0.5
Imaginary Axis

0.5 Increasing KI
FS = 40 MHz (Step = 1e7)
0 0 KI = 4e7
FS =
-0.5 160 MHz -0.5

-1 KI = 3e7 -1 FS = 100 MHz

-1 -0.5 0 0.5 1 -1 -0.5 0 0.5 1
Real Axis Real Axis
(a) (b)

Figure 3. The pole plot of the proposed system under: (a) variable sampling frequency; and (b) variable
integration gain.

Table 1. The simulation parameters of the system hybrid model.

KP KTDC KDC RLOAD CLOAD FLOAD TDEL

1 38 0.02 10 Ω 500 pF 32 MHz 10 ps
Electronics 2020, 9, 132 5 of 13

0.3 1
Increasing RL CL = 13 pF
0.2 (CL = 500 pF) Decreasing CL
0.5

Imaginary Axis
(RL = 10 Ω)
Imaginary Axis

0.1
RL = 12 Ω RL = 50 Ω CL = 15 pF
0 0

-0.1
-0.5
-0.2 KI = 3e7 KI = 3e7

-0.3
FS = 100 MHz -1 FS = 100 MHz
0.7 0.8 0.9 1 -1 -0.5 0 0.5 1
Real Axis Real Axis
(a) (b)

Figure 4. The pole plot of the proposed system under: (a) variable load resistance; and (b) variable
load capacitance.

3. Circuit Implementation

3.1. Voltage Sensor

The transformation of the output voltage from analog to digital is achieved by a TDC-based
signal converter, which contains a voltage sensor and a time-to-digital converter. Figure 5 illustrates
the circuit scheme of the voltage sensor. During phase φ1 , two plates of the charge capacitor CC are
pre-charge to VOUT and VIL , respectively, where VIL is the acceptable high level of the buffer-gate
in TDC. After the capacitor is pre-charged, the voltage difference between node A and node B is
(VOUT − VIL ). At the moment the phase is switched, node A is connected to ground. Because the
voltage difference between the two plates of a capacitor does not change suddenly, the voltage of node
B is (VIL − VOUT ). During phase φ2 , node B is charged by a constant current source I, which is supplied
by a PMOS of a current mirror. Since VIL is usually lower than half the supply voltage, the source-drain
voltage of the PMOS is large enough and the PMOS operates in the saturation region. Under such
a condition, the drain current is slightly affected by the source-drain voltage. Hence, the linearity of
the voltage sensor is not greatly affected by the change of the voltage of node B. The charging current I
is stable in the range of concern.

Charge
Φ2 OUT
A B
CC Φ2
Φ2 Φ1 Φ1 Φ1
Pre-charge

VOUT VIL
Figure 5. The circuit scheme of the voltage sensor.
Electronics 2020, 9, 132 6 of 13

When the voltage of node B rises to VIL , the voltage level turns to logic “1” and the TDC is
triggered. During the process, the charge variation in CC can be expressed as

∆QC = I · ∆t (6)

where ∆t is the time interval of node B is charged from (VIL − VOUT ) to VIL . Meanwhile, the voltage
variation of node B is [VIL -(VIL -VOUT )]. The relationship between ∆QC and the voltage change during
∆t is

∆QC = CC · [VIL − (VIL − VOUT )] (7)

Combining Equations (6) and (7), ∆t can be expressed as

CC
∆t = VOUT (8)
I
Hence, the output voltage is converted to a time interval by varying the initial voltage of CC .
In the voltage sensor, a parasitic capacitance exists in the capacitor CC , which causes a slight
change of about 20–30 fF in CC . In the proposed circuit, the charging capacitance is 250 fF, which is
much larger than the parasitic capacitance. Because the resolution of the proposed 6-bit TDC-based
voltage converter is about 25 mV, the circuit response is not modified by the slight fluctuation of CC .

3.2. Time-to-Digital Converter

The circuit scheme of the time-to-digital converter is shown in Figure 6. As an all digital circuits,
TDC is implemented by logical synthesis. The input ports of the TDC are connected to the clock φ and
the output of the voltage sensor. In the delay line, the propagated time of each buffer is td . Figure 7
shows the timing diagram of the TDC-based signal converter. At the beginning of phase φ2 , signal “1”
is transmitted in the delay line. When the voltage sensor generates a positive edge, the D flip-flops are
triggered, and ports Di (i = 1, 2, · · · , n) output the voltage level of node Pi (i = 1, 2, · · · , n). The number
of buffers transmitted by signal “1” is N = [∆t/td ]. According to Equation (8),
 
CC
N= VOUT (9)
I · td
Using the voltage sensor and TDC, the transformation of VOUT from analog to digital can
be achieved.

P1 P2 Pn-1 Pn
Φ td td td td

D D D D
Q Q Q Q

OUT

Δt D1 D2 Dn-1 Dn
Figure 6. The circuit scheme of the time-to-digital converter.
Electronics 2020, 9, 132 7 of 13

Φ Φ1 Φ2
VOUT
A
GND
B Δt
VDD
VIL
OUT, B OUT
VIL-VOUT
Logic “0” Logic “1” GND

Pi

td Di = 1
Di Di = 0

Figure 7. The timing diagram of the TDC-based signal converter.

3.3. Digital Controller

The delay line in TDC outputs a 64-bit thermometer-coded digital signal VOUT,D . The digital
subtractor subtracts the temperature code from the reference voltage VREF,D and outputs an error
value e. Driven by the error value, the output of the digital PI controller at kth clock cycle can be
expressed as

k
u ( k ) = KP e ( k ) + KI ∑ e ( j) (10)
j =0

When there is a steady-state error, VOUT,D is not equal to the VREF,D and the output of digital
subtractor is non-zero. Under such a condition, the accumulative component of Equation (10) causes
the PI to output a variable value. The digital code VOUT,D is forced to approach the VREF,D until
steady-state error is eliminated. When the circuit is stable, VOUT,D is equal to the VREF,D and the output
of the digital subtractor is 0. Since the accumulative component of the digital PI controller no longer
changes, a stable voltage is outputted continuously.

4. Simulation and Results

4.1. TDC-Based Signal Converter

The proposed fast response DLDO was realized in a 65-nm TSMC technology. It occupies an
active area of 0.017 mm2 and the layout is shown in Figure 8. The current injection of the switches
in the TDC-based voltage converter introduces the voltage errors to the output voltage of switches.
To describe the effect, the voltage errors were measured and the results are shown in Figure 9. In the
circuit, the charging capacitor is 250 fF and the charging current I is 120 µA. According to the results,
the current injection causes the positive errors at node A and node B under different VOUT conditions.
The resolution of the proposed TDC-based voltage converter is about 25 mV, which is larger than
the maximum voltage error. Hence, the current injection will not affect the accuracy of the proposed
circuit. Figure 10 shows the comparison of linearity between the conventional TDC and the proposed
TDC. The test points are fitted into a quadratic function. According to the fitting results, the coefficients
of the quadratic term of the conventional TDC and the proposed TDC are −47.1 and −2.8 × 10−14 ,
respectively. Relative to the conventional TDC, the performance of linearity is improved in the
proposed design.
Electronics 2020, 9, 132 8 of 13

Voltage sensor
TDC &

PMOS Array
Digital Controller

Clock generator

Figure 8. The layout of the proposed fast response DLDO.

30 Node A
Node B
Voltage Error (mV)

25

20
15

10

5
0
0 0.2 0.4 0.6 0.8 1
VOUT (V)
Figure 9. The voltage error caused by the current inject of switches.

50
y=-47.1x2+160.1x-60.37 40 y=-2.8×10-14x2+40x+5
40
Digital Output
Digital Output

30
30

20 20

10
Test points 10 Test points
0 Fitting curve Fitting curve
0.5 0.6 0.7 0.8 0.9 1 0 0.2 0.4 0.6 0.8 1
Analog Input Analog Input
(a) (b)

Figure 10. The comparison of linearity for: (a) conventional TDC; and (b) proposed TDC.

4.2. Proposed DLDO

To describe the transient response speed of the proposed circuit, the settling time TS with variable
load was simulated. The settling time is defined as the time of the output voltage recovers to 90% of
Electronics 2020, 9, 132 9 of 13

the droop voltage. As shown in Figure 11, the proposed DLDO reduces the settling time under each
condition. The settling time is decreased to only 17.1% of the baseline design of DLDO (from 147.8 ns
to 25.2 ns) on average. In other words, the proposed circuit improves the response speed by about six
times. Under the variations of sampling frequency and load current, the settling time was evaluated as
well. In Figure 12, the increasing sampling frequency results in a shorter TS . The settling time when
f S = 100 MHz is about half that of f S = 50 MHz. Compared with the heavy load condition, settling
time is shorter in the light load condition under each frequency.

Baseline DLDO Baseline DLDO

200 Proposed DLDO 200 Proposed DLDO
Settling Time (ns)

Settling Time (ns)

150 150

100 100

50 50

0 0
480 500 520 540 560 580 11 11.5 12 12.5 13 13.5
CL (pF) RL (Ω)
(a) (b)

Figure 11. The settling time when: (a) load resistance is 11 Ω; and (b) load capacitance is 500 pF.

60
CL = 500 pF

50 ILOAD = 80 mA
Settling Time (ns)

(Heavy)
40

30

20
ILOAD = 55 mA
(Light)
10
50 60 70 80 90 100
fS (MHz)
Figure 12. The settling time under the variations of sampling frequency and load current.

Figure 13 shows the measured transient responses of the baseline DLDO and the proposed DLDO
with a load step of 80 mA. With VIN = 1 V, VOUT = 0.85 V (step up) or VOUT = 0.65 V (step down),
f S = 100 MHz and CL = 500 pF, we measured a 25 ns (step up) or 64 ns (step down) settling time.
Compared with the baseline case, the proposed DLDO shows a significantly faster settling time.
The output voltage is measured for a target voltage of from 0.95 to 0.65 V with VIN ranging from 0.7
to 1.1 V. As shown in Figure 14, the effect of the line voltage on the output voltage is slight. A line
regulation of 15 mV/V is achieved. The output voltage with a load current range from 55 to 85 mA
is measured. As shown in Figure 15, the circuit regulates the output voltage from 0.95 to 0.65 V, and
a load regulation of <0.8 mV/mA is achieved. A performance comparison with published DLDO is
given in Table 2, which includes both the ALDO and DLDO. In comparison to those prior designs
in Table 2, this paper achieves the shortest response time, the best figure of merit (FOM) of speed [21],
and competitive current efficiency.
Electronics 2020, 9, 132 10 of 13

Baseline DLDO Proposed DLDO

ILOAD = 80 mA ILOAD = 80 mA

TS = 175 ns TS = 25 ns

Vdroop = 336 mV Vdroop = 371 mV

300 400 500 600 700 800 300 400 500 600 700 800
Time (ns) Time (ns)
(a) (b)

Baseline DLDO Proposed DLDO

ILOAD = 80 mA ILOAD = 80 mA

Vdroop = 164 mV Vdroop = 158 mV

TS = 144 ns TS = 64 ns

300 400 500 600 700 800 300 400 500 600 700 800
Time (ns) Time (ns)
(c) (d)

Figure 13. The measured transient responses of the baseline DLDO and the proposed DLDO for a load:
step up (a,b); and step down (c,d).

1 VREF = 0.95 V
Output Voltage (V)

0.9 VREF = 0.85 V

0.8 VREF = 0.75 V

0.7 VREF = 0.65 V

0.6
0.7 0.8 0.9 1 1.1
Line Voltage (V)

Figure 14. The output voltage under the variations of line voltage.

1 VREF = 0.95 V
Output Voltage (V)

0.9 VREF = 0.85 V

0.8 VREF = 0.75 V

0.7 VREF = 0.65 V

0.6
55 60 65 70 75 80 85
Load Current (mA)

Figure 15. The output voltage under the variations of load current.
Electronics 2020, 9, 132 11 of 13

Table 2. Comparison with published LDO designs.

Paper 2015 [22] 2018 [23] 2019 [24] 2018 [25] This Work
Type Analog Digital Analog Digital Digital
Process 180 nm 65 nm 55 nm 65 nm 65 nm
Active area [mm2 ] 0.021 NA 0.042 0.012 0.017
VIN [V] 1.3–1.8 0.8–1 <0.8 0.5–1 0.7–1.1
VOUT [V] 1.2 0.75–0.95 0.6 0.35–0.95 0.65–1.05
Quiescent IQ [µA] 10 24 0.016 45.2 495
IMAX [mA] 25 13 10 2.8 120
Peak current efficiency η [%] 99.9 99.8 99.8 98.4 99.6
Line regulation [mV/V] 0.5 NA 0.5 NA 15
Load regulation [mV/mA] 0.14 NA 1.05 NA 0.6
Load capacitor CL [nF] 4700 0.2 1000 0.1 0.5
Max voltage droop [mV] @ 2@ 100 @ 70 @ 46 @ 371 @
Load step 25 mA 6 mA 10 mA 1.76 mA 80 mA
Response time TR * [ns] 376 3.3 7000 2.63 2.1
FOM ** [ps] 150 13.3 11.4 67.1 8.7
* TR = CL ∗ Vdroop /IMAX ; ** FOM = TR ∗ IQ /IMAX .

5. Conclusions
This paper presents a fast response DLDO with a TDC-based signal converter for decreasing
the settling time. The voltage sensor and TDC convert the output voltage from analog to digital.
The digital controller provides a multi-bit regulation and improves transient response performance.
The simulation results show that the proposed fast response DLDO can decrease the settling time to
17.1% of the baseline design of DLDO on average, and a FOM of 8.7 ps is achieved.

Author Contributions: Conceptualization, H.Z., J.G., and Z.C.; Data curation, P.W. and Z.L; Investigation, J.G.
and Z.L.; Methodology, H.Z. and J.G.; Resources, P.W. and Z.C.; Writing—original draft, H.Z.; and Writing—review
and editing, P. W. and Z.C. All authors have read and agreed to the published version of the manuscript.
Funding: This work was supported by Beijing Natural Science Foundation Project No.4184083, and National
Natural Science Foundation of China, Key Project No.61731019.
Conflicts of Interest: The authors declare no conflict of interest.

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