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    Truth Table Capacitance: 0.6 M CMOS

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    Guilherme Castro
    This document describes the specifications and characteristics of an AND6 chip, which is a 6-input AND gate with 1x drive strength and fabricated using a 0.6 μm CMOS process. It provides the truth table, area, power consumption, delay times, output slopes, and other AC characteristics for the AND6 gate under different load and input slope conditions. The AND6 gate has a die area of 1.08 mil^2 and power consumption of 2.83 μW/MHz. Its delay times and output slopes are dependent on the output load capacity and input signal slope.

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    Truth Table Capacitance: 0.6 M CMOS

    Uploaded by

    Guilherme Castro
    57 views2 pages
    This document describes the specifications and characteristics of an AND6 chip, which is a 6-input AND gate with 1x drive strength and fabricated using a 0.6 μm CMOS process. It provides the truth table, area, power consumption, delay times, output slopes, and other AC characteristics for the AND6 gate under different load and input slope conditions. The AND6 gate has a die area of 1.08 mil^2 and power consumption of 2.83 μW/MHz. Its delay times and output slopes are dependent on the output load capacity and input signal slope.

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    AND6 datasheet

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    This document describes the specifications and characteristics of an AND6 chip, which is a 6-input AND gate with 1x drive strength and fabricated using a 0.6 μm CMOS process. It provides the truth table, area, power consumption, delay times, output slopes, and other AC characteristics for the AND6 gate under different load and input slope conditions. The AND6 gate has a die area of 1.08 mil^2 and power consumption of 2.83 μW/MHz. Its delay times and output slopes are dependent on the output load capacity and input signal slope.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    57 views2 pages

    Truth Table Capacitance: 0.6 M CMOS

    Uploaded by

    Guilherme Castro
    This document describes the specifications and characteristics of an AND6 chip, which is a 6-input AND gate with 1x drive strength and fabricated using a 0.6 μm CMOS process. It provides the truth table, area, power consumption, delay times, output slopes, and other AC characteristics for the AND6 gate under different load and input slope conditions. The AND6 gate has a die area of 1.08 mil^2 and power consumption of 2.83 μW/MHz. Its delay times and output slopes are dependent on the output load capacity and input signal slope.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    CUB

    Austria Mikro Systeme International


    R AND6 0.6 µm CMOS

    AND6 is a 6-input AND gate with 1x drive strength.

    Truth Table Capacitance


    A B C D E F Q Ci (pF)
    L X X X X X L A 0.050
    A
    X L X X X X L B 0.043
    B
    X X L X X X L C C 0.047
    AND6 Q
    X X X L X X L D D 0.050
    X X X X L X L E E 0.043
    X X X X X L L F F 0.047
    H H H H H H H

    Area Power
    2
    1.08 mils 2.83 µW / MHz

    Delay [ns] = tpd.. = f(SL, L) with SL = Input Slope [ns] ; L = Output Load [pF]
    Output Slope [ns] = op_sl.. = f(L) with L = Output Load [pF]

    AC Characteristics : Tj = 25°C VDD = 3.3V Typical Process

    AC Characteristics

    SL = 0.1 SL = 2.0
    Characteristics Symbol
    L = 0.1 L = 0.7 L = 1.0 L = 0.1 L = 0.7 L = 1.0

    tpdar 0.54 1.84 2.58 0.59 1.89 2.58


    Delay A to Q
    tpdaf 0.58 1.68 2.21 0.91 2.01 2.55
    tpdbr 0.57 1.88 2.60 0.58 1.89 2.56
    Delay B to Q
    tpdbf 0.64 1.73 2.28 0.99 2.12 2.67
    tpdcr 0.57 1.88 2.60 0.54 1.83 2.47
    Delay C to Q
    tpdcf 0.70 1.77 2.35 1.06 2.20 2.71
    tpddr 0.54 1.92 2.51 0.60 1.89 2.57
    Delay D to Q
    tpddf 0.60 1.69 2.21 0.95 2.01 2.53
    tpder 0.58 1.95 2.59 0.57 1.87 2.56
    Delay E to Q
    tpdef 0.66 1.75 2.28 1.02 2.11 2.62
    tpdfr 0.59 1.95 2.56 0.53 1.83 2.51
    Delay F to Q
    tpdff 0.72 1.83 2.33 1.11 2.19 2.74

    op_slar 1.07 5.32 7.46 1.02 5.28 7.37


    Output Slope A to Q
    op_slaf 0.75 3.78 5.05 0.73 3.62 5.02
    op_slbr 1.08 5.31 7.43 1.05 5.31 7.37
    Output Slope B to Q
    op_slbf 0.75 3.61 5.07 0.77 3.70 5.27

    Sept. 1996 - 36 - Rev. N/C


    CUB
    Austria Mikro Systeme International
    R AND6 0.6 µm CMOS

    SL = 0.1 SL = 2.0
    Characteristics Symbol
    L = 0.1 L = 0.7 L = 1.0 L = 0.1 L = 0.7 L = 1.0
    op_slcr 1.08 5.31 7.46 1.05 5.30 7.37
    Output Slope C to Q
    op_slcf 0.78 3.60 5.10 0.81 3.66 4.98
    op_sldr 1.08 5.31 7.50 1.02 5.30 7.37
    Output Slope D to Q
    op_sldf 0.81 3.67 4.97 0.83 3.65 4.96
    op_sler 1.07 5.32 7.47 1.02 5.28 7.37
    Output Slope E to Q
    op_slef 0.82 3.58 4.98 0.83 3.60 4.97
    op_slfr 1.05 5.32 7.55 1.05 5.30 7.35
    Output Slope F to Q
    op_slff 0.85 3.70 4.92 0.86 3.60 4.92

    Sept. 1996 - 37 - Rev. N/C

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