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    16EC32 Final

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    santosh saraf
    This document contains the instructions and questions for the Analog Electronics semester end examination. It is divided into 5 units. Unit I and II contain compulsory questions, while students must answer one question from Units III to V. The questions assess various topics like the working of clippers, clampers, biasing configurations, feedback amplifiers, oscillators, power amplifiers, CMOS, JFET, and MOSFET circuits. Students are required to derive expressions, determine circuit parameters, explain concepts, and draw circuit diagrams with calculations.

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    16EC32 Final

    Uploaded by

    santosh saraf
    18 views3 pages
    This document contains the instructions and questions for the Analog Electronics semester end examination. It is divided into 5 units. Unit I and II contain compulsory questions, while students must answer one question from Units III to V. The questions assess various topics like the working of clippers, clampers, biasing configurations, feedback amplifiers, oscillators, power amplifiers, CMOS, JFET, and MOSFET circuits. Students are required to derive expressions, determine circuit parameters, explain concepts, and draw circuit diagrams with calculations.

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    16EC32-Final

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    This document contains the instructions and questions for the Analog Electronics semester end examination. It is divided into 5 units. Unit I and II contain compulsory questions, while students must answer one question from Units III to V. The questions assess various topics like the working of clippers, clampers, biasing configurations, feedback amplifiers, oscillators, power amplifiers, CMOS, JFET, and MOSFET circuits. Students are required to derive expressions, determine circuit parameters, explain concepts, and draw circuit diagrams with calculations.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    18 views3 pages

    16EC32 Final

    Uploaded by

    santosh saraf
    This document contains the instructions and questions for the Analog Electronics semester end examination. It is divided into 5 units. Unit I and II contain compulsory questions, while students must answer one question from Units III to V. The questions assess various topics like the working of clippers, clampers, biasing configurations, feedback amplifiers, oscillators, power amplifiers, CMOS, JFET, and MOSFET circuits. Students are required to derive expressions, determine circuit parameters, explain concepts, and draw circuit diagrams with calculations.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    USN 16EC32

    III Semester B.E. / B. Arch. / MCA Semester End Examination, Nov. / Dec. 2017-18
    Analog Electronics
    Time: 3 Hours Max. Marks: 100

    Instructions 1 Questions in UNIT I and UNIT II are compulsory.


    : .
    2 Solve any one question from UNIT III to V
    .
    3
    .
    4
    .

    UNIT - I

    1 a. Draw and Explain working of a series negative clipper. 6M

    ( Level [2], CO [1], PO [1] )

    b. Explain the operation of positive clamper. 6M

    ( Level [2], CO [1], PO [1] )

    c. Derive the expression for stability factor (S) for fixed bias configuration. 8M

    ( Level [3], CO [1], PO [4] )

    UNIT – II

    2 a. Derive an expression for voltage gain, input and output impedances voltage divider
    6M
    bias amplifier with emitter bypass capacitor using re model

    ( Level [3], CO [2], PO [1] )

    b. Determine voltage gain, input and output impedances of fixed bias amplifier with hie
    6M
    = 1.2 kΩ, hfe = 400, hoe = 1µS, RB = 1MΩ, RC =10 kΩ

    ( Level [3], CO [2], PO [4] )

    c. Derive an equation for Miller input and output capacitance. 8M

    ( Level [3], CO [2], PO [4] )

    UNIT – III

    3 a. Derive an expression for gain, input impendence and output impendence of voltage
    shunt negative feedback and also mention the advantages and disadvantages of 6M
    negative feedback.

    ( Level [3], CO [5], PO [4] )

    b. With neat diagram explain BJT Hartley oscillator. Calculate the operating frequency
    6M
    of BJT RC phase shift oscillator for R = 3 kΩ, C = 1500 pF and RC=10 kΩ.
    ( Level [3], CO [5], PO [4] )

    c. Derive an expression for gain, input impendence and output impendence of voltage
    series negative feedback and also mention the advantages and disadvantages of 8M
    negative feedback.

    ( Level [3], CO [5], PO [4] )

    4 a. For distortion readings of D2 = 0.15, D3 = 0.01, and D4 = 0.05, calculate the total
    6M
    harmonic distortion.

    ( Level [3], CO [6], PO [1] )

    b. Explain with neat circuit diagram Class A power amplifier and derive the expression
    6M
    for efficiency.

    ( Level [3], CO [6], PO [1] )

    c. Explain with neat circuit diagram Class B complementary symmetry power amplifier
    8M
    and derive the expression for efficiency.

    ( Level [2], CO [6], PO [4] )

    UNIT – IV

    5 a. Draw and explain CMOS inverter with neat sketch. 6M

    ( Level [2], CO [4], PO [1] )

    b. Determine the value of gm for a JFET (IDSS = 8mA and Vp = -6V) when biased at 6M
    VGS= Vp/4.

    ( Level [3], CO [3], PO [4] )

    c. For a self biased JFET calculate RD and RS with VDD = 20 V, IDSS = 10mA, VGS = -3V 8M
    at ID = 4mA. Assume that the Q point is at the center of the operating region.

    ( Level [3], CO [3], PO [4] )

    6 a. Explain the working principle of n-channel JFET and draw drain and transfer 10M
    characteristics.

    ( Level [2], CO [3], PO [1] )

    b. Explain the working principle of n-channel depletion type MOSFET and draw drain 10M
    and transfer characteristics.

    ( Level [2], CO [3], PO [1] )

    UNIT – V

    7 a. Draw the JFET small signal model for given gfs = 2.8 mS and gos = 25 μS. 5M

    ( Level [3], CO [5], PO [4] )

    b. Determine Zi, Z0, and AV for JFET self bias configuration. 10M

    ( Level [3], CO [5], PO [4] )


    c. The fixed-bias configuration with an operating point defined by VGSQ = -2.2 V and IDQ
    = 5 mA, with IDSS = 10 mA and V P = -8 V. The network is as Fig. 3 with an applied
    signal Vi . The value of yos is provided as 30 μS.
    a. Determine gm .
    b. Find rd . 5M
    c. Determine Zi .
    d. Calculate Zo .
    e. Determine the voltage gain Av .
    f. Determine Av ignoring the effects of rd .
    ( Level [2], CO [5], PO [4] )

    8 a. Give the difference between BJT and FET. 5M

    ( Level [2], CO [4], PO [4] )

    b. Draw the small signal equivalent circuit of a common gate FET amplifier and derive 7M
    expression for input and output impedance and voltage gain
    ( Level [3], CO [4], PO [1] )

    c. Draw the small signal equivalent circuit of a common drain FET amplifier and derive 8M
    expression for input and output impedance and voltage gain

    ( Level [3], CO [4], PO [1] )

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