Solve RF/AMS Design Challenges Using the Cadence

Virtuoso Solution and Tensilica DSPs

A Pipeline ADC Calibration and Testing Case Study

As the number of radio frequency/analog mixed-signal (RF/AMS) applications rapidly increases in

today’s market, designers are seeing more challenges such as die performance, yield and lifespan, and
complex testing. This white paper presents a new method to address these challenges by applying
digital calibration and compensation in RF/AMS designs. This solution implements an embedded
Cadence® Tensilica® processor with DSP using Cadence Virtuoso® AMS Designer and Cadence Tensilica®
Xtensa® Xplorer.

Introduction
Contents Process and environment variations conspire against radio frequency and
Introduction.......................................1 analog mixed-signal (RF/AMS) designers by adversely affecting die perfor-
Cadence Tensilica Processors..............3 mance, yield, and lifespan. Designers are faced with a classic tradeoff: design
Tensilica DSPs for Mixed-Signal margins can be increased to mitigate these effects, but too often at steep
Testing and Calibration.......................3 power and area penalties. In addition to these challenges, ever-increasing
Pipeline ADC and Error Modeling.......4 levels of silicon integration demand complex testing of RF/AMS compo-
Sub-ADC Stage Error Modeling..........5 nents for product qualification. [1] Die testing is indispensable, yet expensive,
particularly for RF/AMS circuits due to the need for specialized automated test
Differential Non-Linearity (DNL)
Error...................................................6 equipment (ATE). Reduced testing can lead to increased levels of escapes—
Integral Non-Linearity (INL) Error........6
undetected products with failures—that can exponentially increase costs as
silicon products traverse the integration chain.
Pipeline ADC Calibration via an
Embedded Cadence Tensilica Meanwhile, as the cost of CMOS digital component and testing costs diminish
Processor ...........................................7
by comparison, designers are beginning to consider hybrid solutions to RF/
Virtuoso AMS Designer Solution AMS problems that incorporate digital calibration and compensation, and test
Using Real Number Models................9
circuitry. Embedded digital signal processors (DSPs) are now sufficiently small
Optimizing an Xtensa Processor to serve as viable options for complementing RF/AMS cores. Two IEEE Journal
Using Xplorer...................................11
articles [2] [3] propose embedded DSPs perform a variety of tasks (such as
Conclusion.......................................14
listed in Table 1 and Table 2) with a series of goals:
Additional Information.....................14
• Extend silicon life
References........................................15
• Simplify the digital design process
• Optimize test coverage and costs
• Increase manufacturing yields, reduce current consumption, and adapt to
varying environmental conditions [3]

Programmable DSPs reduce the risks associated with developing a complex

system-on-chip (SoC) where all problems cannot be predicted in the pre-silicon
stage. Programmability allows for post-silicon upgrades and fixes, potentially
saving silicon re-spins and supporting aggressive product cycles.
 Solve RF/AMS Design Challenges Using the Cadence Virtuoso Solution and Tensilica DSPs

Table 1: DSP-Assisted RF/AMS Calibration Tasks

Component Impairment DSP Solution

RF transceiver • IQ imbalance • Estimate impairment and calibration
• DC offset parameters

• Carrier offset • Adjust analog components

(e.g., tuner LO frequency)
• In-band ripple
• Digital compensation
• Spectral mask violations
(e.g., DC offset removal)
Analog-to-digital • Nonlinear distortion • Optimize calibration parameters
converter (ADC)/ • Missed codes (e.g., programmable gains, capacitors)
Digital-to-analog • Optimize/apply correction filters
• Poor effective number of bits (ENOB),
converter (DAC) (e.g., Volterra filter)
signal to noise and distortion ratio
(SINAD), spurious free dynamic range
(SFDR)
High-speed parallel Non-uniform timing Measure and compensate timing delays
ADC
SerDes PHY • Voltage and temperature variations • Optimize parameters with a high-level
• Frequency selective channels: silicon, state machine
package, and PCB variation • Generate training for equalizer adap-
tation

Table 2: DSP-Assisted RF/AMS Testing Tasks

DSP Function Application

Spectral analysis (FFT) Measure ADC/DAC ENOB, SINAD, SFDR
Histogram ADC/DAC integral and differential nonlinearity (INL/DNL), ENOB
Arbitrary signal generation Probe RF/AMS blocks with arbitrary signals (e.g., sinusoid, ramp)
Error vector magnitude Replace vector spectrum analyzer (VSA) and other high-cost test equipment
(EVM), bit error rate (BER)

Advanced and robust solutions are necessary to tackle design and verification challenges in hybrid designs that
consist of RF/AMS and digital components. Cadence serves the market with advanced tools, flows, and methodol-
ogies that help analog designers overcome these challenges. Cadence Virtuoso and Incisive® tools, such as Cadence
Virtuoso AMS Designer, SimVision™, and vManager™ solutions, provide a complete design and verification solution
for analog, RF, mixed-signal, memory, and SoC designs. The Cadence integrated mixed-signal (MS) implementation
solution offers a variety of capabilities to circuit and verification engineers, including:
• Ability to browse design hierarchy to view signals and design details
• Ability to interchange from transistor-level to behavioral-level blocks
• Integrated analog and digital solvers
• Intuitive interactive debugging platforms, which is essential for applying debugging techniques
• High performance for MS verification

This paper discusses a case study of a pipeline ADC [4] that is integrated with an embedded Cadence Tensilica
processor. The processor is used to correct typical ADC non-idealities that decrease performance parameters
such as signal-to-noise-and-distortion-ratio (SINAD), spurious free dynamic range (SFDR), differential and integral
nonlinearity (DNL and INL), and effective number of bits (ENOB). The AMS circuitry and Tensilica processor are
integrated and modeled in the Cadence Virtuoso AMS Designer and Xtensa Xplorer development environments,
providing a high level of integration and compatibility and a simplified design and verification process.

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 Solve RF/AMS Design Challenges Using the Cadence Virtuoso Solution and Tensilica DSPs

This document includes a brief overview of Tensilica processors and the ConnX D2 DSP used in this case study.
It reviews the structure of the pipeline ADC and the types of non-idealities that may be encountered in this type
of mixed-signal block, and discusses the application of the processor to estimate the parameters for pipeline
ADC error correction. The Virtuoso AMS Designer environment is used to design and test the system, and the
Eclipse-based Xtensa Xplorer integrated development environment (IDE) is used for processor configuration
and customization.

Cadence Tensilica Processors

Cadence Tensilica processors can be optimized to run a class of applications very efficiently, striking a balance
between die area, energy, and performance that is closely matched to the tasks to be performed. Starting with the
baseline Xtensa architecture, designers can add VLIW (very long instruction word), SIMD (single instruction multiple
data), DSP, and custom instructions to speed up critical operations. The Xtensa Xplorer IDE allows customers to
profile their code and develop their own processors, or to select a ready-to-use processor designed by Cadence.
These processors range widely in performance and size, from 32-bit embedded controllers to 128-way SIMD/VLIW
vector processors. They are all supported by a single C/C++ software development tool chain, with application-
specific libraries and third-party ecosystems matched to the end use. Table 3 lists Tensilica DSP families that can be
included in Tensilica processors, and the common types of applications for which they are optimized.

Table 3: Cadence Tensilica DSPs

Tensilica DSP Family Application

Fusion Multi-functional DSP for IoT
HiFi Audio / voice / speech
Vision Imaging / computer vision
ConnX Communications / baseband

If a different design balance is needed for a specific testing/calibration application, an engineer can use Xtensa
Xplorer to make adjustments to lower cost or increase throughput, such as changing the memory configuration or
multiplier hardware size, or adding a second load/store unit or a single or double-precision floating-point unit. The
Xplorer IDE is also used for software development, so that hardware and software engineers have the same views
of the design as it progresses from architectural exploration to post-silicon application development.

Tensilica DSPs for Mixed-Signal Testing and Calibration

Mixed-signal testing and calibration makes extensive use of digital signal processing. In our case study, advanced
DSP functions are used for least-squares parameter estimation and spectral analysis of signal quality. The Tensilica
ConnX D2 DSP (Figure 1) is a small general-purpose fixed-point DSP that is a good initial fit for this application.

Data Vector General

Data Load/
Memory Up to 32 bits Register File Register File
Store Unit 0
Interface
(Local Wide Vector:
Data Load/ 32 x 32 bits
Memory Up to 32 bits 8 x 40 bits
Store Unit 1
or Cache)

Xtensa
Instruction Processor
Memory 2-Way SIMD
Interface Up to Slot 0 Slot 1 MAC/ALU
Optional
(Local 64 bits Extensions
Memory 2-Way VLIW Decoder
or Cache) Computational Units

Figure 1: ConnX D2 DSP Architecture

However, with the recently released Fusion F1 DSP, we recommend it as the starting point for new designs. The
Fusion F1 DSP offers up to four-way single instruction/multiple data (SIMD), in this case four 16-bit MAC opera-
tions per cycle, compared to the two-way SIMD in the ConnX D2 DSP. The ConnX D2 and Fusion DSPs are

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 Solve RF/AMS Design Challenges Using the Cadence Virtuoso Solution and Tensilica DSPs

compared in Table 4. Using the Xtensa Xplorer options, these DSPs can be included in a Tensilica processor with
a click, and further optimization is still possible. Designed to be programmed in C with ITU-T/ETSI-compatible
intrinsics, these DSPs can sustain a throughput of two or four saturating fixed-point multiply-accumulate (MAC)
operations per clock through a combination of SIMD and multi-issue flexible length instruction extensions (FLIX)
operations, with a loop buffer to eliminate branching overhead. Real and complex vector operations and specialized
circular and bit-reversed address modes support fast Fourier transform (FFT) and other transform algorithms. Fixed-
point algorithms are fast and efficient, but have limited dynamic range compared to floating-point implementa-
tions. To give the programmer the ability to choose freely between fixed- and floating-point implementations, the
Tensilica processor configured for this case study includes a single-/double-precision IEEE 754-compliant floating-
point unit that adds floating-point registers and ALUs with throughput of one add, subtract, multiply, or fused
multiply-add operation per cycle.

Table 4: ConnX D2 and Fusion DSP Comparison

Characteristic ConnX D2 DSP Fusion F1 DSP

MACs per cycle 2 2 or 4
SIMD width 2-way 2- or 4-way
VLIW Dual issue (optional 3-way issue) Dual issue
Load / store Single or dual 32-bit Single 64-bit

Pipeline ADC and Error Modeling

A typical pipeline ADC consists of a cascade of multiple sub-ADC stages, each stage extracting a few bits of overall
ADC resolution at a time [4]. Figure 2 illustrates a 12-bit pipeline ADC example with a 3-bits-per-stage architecture.
Each stage consists of a sample-and-hold (S/H), a 3-bit flash ADC, a 3-bit DAC, and an amplifier (excluded in the
last stage). The most significant bits (MSBs) are converted by the first stage. The remaining bits are converted
by the stages that follow until the least significant bits (LSBs) are converted by the last stage. The input of each
stage is sampled by the S/H block and the sampled output (Vin ) is sent to the flash sub-ADC that resolves 3 bits.
This 3-bit output (Di) is converted back to an analog signal through the DAC. The “residual signal” (Vout ), which is
the DAC output subtracted from the S/H output (Vdiff ) and amplified by the gain of G (nominally G = 8 for a 3-bit
stage), feeds the next stage of the ADC until 12 bits have been resolved. Due to data latency that is introduced
from the time the analog input is first sampled until the LSBs have been resolved by the last stage, a time alignment
module is added to synchronize and concatenate all stage output bits corresponding to the same sample.

Time Alignment
12-bit output to
FIFO and DSP

(MSB) Bit 11-9 Bit 8-6 Bit 5-3 Bit 2-0 (LSB)

Sine wave
Stage 1 Stage 2 Stage 3 Stage 4

Vin Vdiff Vout

S/H x8
3-bit flash ADC

ADC DAC

Di
3 bit

Figure 2: 12-Bit, 4-Stage Pipeline ADC

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The nominal output Vout of each stage is given by

𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 = 𝐺𝐺 𝑉𝑉𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 

(1)
(𝐷𝐷𝐷𝐷−3.5)𝑉𝑉𝑟𝑟𝑟𝑟𝑟𝑟
𝑉𝑉𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 = [𝑉𝑉𝑖𝑖𝑖𝑖 −
(2)
4
] 

Non-idealities in sub-ADC stages can introduce errors to ADCs, reducing performance and accuracy. Different
types of errors occur in the pipeline stages, mainly due to sub-ADC comparator offsets, operational amplifier
(OPAMP) non-linear gain with signals, capacitor mismatches, OPAMP finite gain and bandwidth, and OPAMP
offset. These cause residual gain and offset errors in each stage that manifest as integral and differential
non-linearities (INL and DNL) errors in the ADC and show up as harmonic or intermodulation distortion
components in the ADC output spectrum.

Sub-ADC Stage Error Modeling

The non-linear gain error and OPAMP offset are introduced in the amplifier of each stage modifying the ideal
residual output equation (1). Parameters �, �, and Vos model the non-idealities as follows:

� models the constant gain error of the residual amplifier by changing gain G to:

𝐺𝐺 = 𝐺𝐺𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 (1 − 𝛽𝛽) (3)

� models the gain compression error in the residual amplifier by changing (1) to:
3
𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 = 𝐺𝐺(𝑉𝑉𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 − 𝛼𝛼 𝑉𝑉𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 ) (4)

Vos models the offset voltage of the residual amplifier by changing (4) to:
3
𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 = 𝐺𝐺(𝑉𝑉𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 − 𝛼𝛼 𝑉𝑉𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 ) + 𝑉𝑉𝑜𝑜𝑠𝑠 (5)

For an ideal ADC, the residual waveform of each stage is always within the range of the next sub-ADC stage.
However, the contribution of gain and offset errors will force the residual waveform to go outside of the range,
leading to output code errors. These incorrect codes will be added in the overall ADC transfer function. For a
severely impaired pipeline ADC, the digital output “sticks” on a code and “jumps” over an output region whenever
the residual waveform is outside of the sub-ADC range [5] (see Figure 3). Additionally, the transfer curve can
display non-monotonic behaviour for some ADC impairments when codes “dip.”

16
15
14
13
12
11
10
“Dips”/Non-monotonic-codes
Digital output

9
8
7
6 “Jumps”/Missing codes
5
4
3
“Sticks”
2
1
0
-1
-2
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Analog input voltage

Figure 3: ADC Transfer Function with Missing Codes Due to Over-Range Error

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Differential Non-Linearity (DNL) Error

Differential non-linearity (DNL) describes the deviation between the ideal analog input step-size to the actual
step-size observed for each ADC code. The ideal step-size is 1 LSB. This deviation is represented in units of LSBs. In
Figure 4, DNL is measured as –0.6 LSBs at code 14 and +0.25 LSBs at code 19. Usually, the maximum value of the
DNL curve is quoted for an ADC instead of the whole DNL curve [6].
21

20

19

18
Digital output
DNL Error:
17
– 0 .60 LSB

16 DNL Error:
+0.25 LSB
15

14

13

12
0.45 0.5 0.55 0.6 0.65

Analog input voltage

Figure 4: Differential Nonlinearity

Integral Non-Linearity (INL) Error

Integral non linearity (INL) describes the deviation of the actual analog input to digital output code transfer
function with respect to the ideal transfer function for each ADC code. This deviation is represented in units of
LSBs. By definition, INL for a particular code is the summation of the DNL array elements up to that code. Usually
the maximum value of the INL curve is quoted for an ADC instead of the whole INL curve. Figure 5 shows two sets
of curves. The straight gray line is the ideal transfer function. The quantized red curve represents an ideal ADC
output. The INL for this ideal ADC is 0.5 LSB. The quantized blue curve represents the output of an ADC with
distortion. The INL error here is greater than 0.5.
2

0
INL Error
-2

-4

-6
Digital output

-8

-10

-12
Non-Ideal Pipeline ADC
-14
Ideal Pipeline ADC
-16

-18
-0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0

Analog input voltage

Figure 5: Integral Nonlinearity

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Pipeline ADC Calibration via an Embedded Cadence Tensilica Processor

This case study demonstrates the calibration and testing of a pipeline ADC via an embedded Tensilica processor
that includes the ConnX D2 DSP. Note that we recommend using the recently released Fusion F1 DSP as the starting
point for new designs.

The methodology estimates and corrects ADC nonlinearities applied to an AMS SoC. The case study uses Cadence
Virtuoso and Incisive tools for modeling AMS circuitry and solving SoC-level mixed-signal verification challenges ,
and Cadence Xtensa Xplorer for processor configuration and emulation. A 12-bit, 20Msps pipeline ADC based on
a subranging architecture is followed by the Cadence Tensilica ConnX D2 processor and a digital correction filter
to estimate and correct the ADC errors, respectively. See Figure 6. A non-linearity gain error is introduced in the
amplifier block of each sub-ADC stage modeling the effect of capacitor mismatch, finite op-amp gain, and various
switch-induced offsets. Therefore, the actual amplifier gain G is different than the ideal (G ideal =8). The gain and
the residual output of the amplifier are calculated using equations (3) and (4). The gain compression error � and
constant gain error � have been chosen as 2%1 and 1%2 respectively.

Testbench Control

Control / Data

ADC
to SoC Signal
Correction
Filter Procession

Sinusoid Calibration Parameters

Generator External Tensilica Processor
Test with DSP IRAM
Mission Mission • Calibration
ADC FIFO
Mode Signal Mode • Control
• Arbitrary
Loopback Waveform DRAM
Generation
mode select
• Signal Analysis

DAC
sinusoid, ramp SoC

Verilog-AMS
RTL and SystemC Model
Real Number Modeling

Figure 6: Pipeline ADC Architecture with Embedded Tensilica Processor

This example presents two scenarios:

• A sinusoid signal is generated externally and converted to a digital signal through the pipeline ADC. A processor
is added to calibrate ADC non-idealities, which are corrected through the filter.
• A digital signal is generated internally by the processor and is converted to analog through the DAC. The analog
signal feeds the ADC and is converted again to digital. The ADC non-linearities are calibrated and corrected
through the processor and compensation filter.

An analog multiplexer (MUX), controlled by the processor, is used to select the input of the ADC as either an
external signal or internal loopback signal. The external signal can be either a calibration stimulus (such as a
sinusoid) or the “mission mode” signal for regular operation of the SoC. The internal loopback signal is generated
by the processor for calibration and testing.

The correction filter can be included as software running on the processor or as a hardware block outside of the
processor. The hardware implementation of the correction filter saves power as the processor can be shut off while
the filter is in operation. Alternatively, the processor can be used for other tasks such as calibration of other RF/
AMS components on the SoC.

1
�: Parameter representing the sub-ADC stage’s gain compression (with signal). This parameter is calculated from the OPAMP’s 1dB
compression point, translating it to the sub-ADC’s compression point and then to its gain error. An error of 2% is a typical number for
50-60dB gain circuit.
2
�: Constant gain error uncertainty that occurs mainly due to capacitive mismatch. We can compensate for a capacitive mismatch as low
as 1% (7- to 8-bit matching).

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The analog signal is converted to a 12-bit signal through the 4-stage pipeline ADC. The ADC begins sampling data
(sampling rate 20Msps) and storing it to the FIFO. After the FIFO is loaded with 4,096 samples, an interrupt is sent
from the FIFO controller to the processor announcing that the data is ready. The processor reads the data and
starts performing least squares (LS) estimation of the digital compensation parameters [7], which is completed in
under 500K cycles. Assuming a clock rate of 400MHz, processing time is less than 1.25msec. Once the parameters
are derived, they are programmed by the processor into the compensation filter, which corrects the distortions in
the digitized signal. At this point, calibration is complete and the system can start processing “mission mode” data.

Parameter estimation and digital correction using the processor and the compensation filter is illustrated in
Figure 7. The processor is modelled in SystemC. Initially, the processor applies a phase-locked loop (PLL) to the
distorted output samples of the ADC and generates a synthetic tone that is locked in frequency and phase to the
ideal input tone. The synthesized ideal signal along with ADC calibration samples are subsequently passed to a
digital processing block to form LS equations, which estimate the coefficients that feed the compensation filter.
The processor solves the LS problem by performing Cholesky decomposition of the observation matrix followed
by forward/backward substitution. The PLL is allowed to run for 4,096 samples and the last L=1024 samples are
used for the LS estimation. After coefficient estimation, the processor is shut off to conserve power.
Compensated
Correction Signal
Filter

Filter
ADC Output
Coefficients
with
Distortions Least Squares
Estimation

Synthesized
Phase-Locked
Ideal Signal
Loop

Figure 7: Digital Parameter Estimation and Correction

The digital correction algorithm that is used in this example improves important ADC dynamic performance
measures, such as SINAD, SFDR, and ENOB as shown in Table 5. All of these metrics are calculated directly on the
processor by applying an FFT to the distorted and compensated signals. Figure 8 and Figure 9 shows the distorted
pipeline ADC output and post digital correction signal spectrums, respectively. As Table 5 shows, SINAD, SFDR,
ENOB, and ADC INL errors are significantly reduced.

The case study shows the clear advantages of using a Tensilica processor with the ConnX D2 option for calibration
and testing. Its fixed-point dual MAC unit is used to efficiently implement the PLL. The data collected from
the PLL is further processed by the dual MAC to generate the LS inner product matrices (for example, At A and
At b for Ax=b). Meanwhile, the Cholesky decomposition (for example, At A= LLt ) and forward (e.g., Ly=At b ) and
backward (e.g., Lt x=y) substitution steps are easily implemented using the processor’s floating-point unit.

Figure 8: Pipeline ADC Spectrum Output

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Figure 9: Compensated Signal Spectrum

Table 5: ADC Dynamic Performance Measures

Performance Metric Distorted Signal Compensated Signal Improvement

SFDR (dB) 62.1 86.8 24.7
SINAD (dB) 57.9 71.0 13.1
ENOB (bits) 9.3 11.5 2.2
INL range (LSB) (-5,+5) (-1,+1) 4

Virtuoso AMS Designer Solution Using Real Number Models

In this example, the pipeline ADC is modeled in Verilog-AMS using wreal (real wire) real-number modeling (RNM).
Cadence has developed a Verilog-AMS-based RNM solution that allows high-performance and reasonably accurate
modeling of analog behavior to aid verification of mixed-signal designs. With RNM, an analog block can be
described as a signal-flow model. Real numbers can represent voltage and current level, and real signals change
values based on discrete events [8]. Therefore, the simulation is executed by a digital simulation engine without
needing analog solvers. This results in high simulation performance—the simulation is nearly as fast as pure digital
simulation, making RNM essential for large mixed-signal SoC verification. Less modeling effort is required to
develop RNM than a traditional analog behavioral model—and because there are no analog engines, convergence
issues are avoided.

Mixed-signal verification becomes more and more difficult as more design and verification challenges are
introduced in mixed-signal designs. Cadence tools such as Virtuoso AMS Designer, Virtuoso Analog Design
Environment, Virtuoso Visualization and Analysis (ViVA), Incisive vManager, and SimVision provide a complete
design and verification solution for analog, RF, mixed-signal, memory, and SoC designs. Cadence Virtuoso AMS
Designer Simulator supports both top-down and bottom-up design flows with the ability to interchange different
levels of abstraction. Design levels can change from transistor-level to behavioral-level. This solution provides
comprehensive behavioral language support for Verilog-AMS and other languages such as Verilog-A, VHDL-AMS,
System Verilog, etc. Verilog-AMS wreal models, as well as SV-RNM, are fully supported.

Cadence Virtuoso AMS Designer is a robust mixed-signal verification solution based on analog and digital
simulation engines integrated in a single kernel. Virtuoso Analog Design Environment XL, along with the Virtuoso
AMS Designer simulator, provide an advanced design and simulation environment. In Virtuoso Analog Design
Environment XL, you can simulate multiple testbenches simultaneously to verify in a single run the performance
across multiple tests. You can also run multiple simulations using sweeps or corners to parameterize multiple
variables, model files, etc. Specifications can be set up for specific expressions and indicators are given both in
words (pass/fail/near) and in color (green/red/yellow) showing whether the values of the expressions are less than,
greater than, or near specifications. Virtuoso Analog Design Environment XL also supports Monte Carlo analysis,

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which is useful for verifying how robust the design will be in production [9]. Figure 10 shows an example of how
the results are presented in Virtuoso Analog Design Environment XL after running a simulation using corners
and specifications.

Figure 10: Virtuoso Analog Design Environment XL Environment

Virtuoso AMS Designer links the Cadence Virtuoso custom design platform with the Cadence Incisive functional
verification platform [10].Cadence SimVision debug solution is essential for mixed-signal verification. It provides
a unified graphical environment for the Virtuoso AMS Designer simulator and other Cadence simulators. The
SimVision debug solution is made up of several debugging tools, each with its own window. The Design Browser
(Figure 11) lets you navigate the design hierarchy, access the objects in the design, and monitor signal value
changes during and after the simulation. The Source Browser (Figure 12) provides access to the source code, and
lets you set breakpoints and run forward or backward through the simulation, starting at any point in simulation
time. The Waveform window (also shown in Figure 12) lets you view software and hardware states, such as struc-
tures, fields, and variables, as well as design under test (DUT) analog, real, and logic signals.

Figure 11: SimVision Design Browser

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Figure 12: SimVision Source Browser and Waveform Window

This case study uses SimVision post-processing features for debugging. The Source Browser fully supports
Verilog-AMS with RNM, which aids in monitoring real signals and variables values. Figure 13 shows the SimVision
Waveform window, displaying the outputs of an ideal ADC (ideal_signal), an ADC with non-idealities (distorted_
signal), and the ConnX D2 DSP, as well as the correction filter (corrected_signal) correcting the ADC non-ideal-
ities. The distorted_signal includes the non-linearities that were introduced in each stage of the pipeline ADC and
cause the distortion of the ADC output. ConnX D2 DSP, along with the correction filter, corrects those non-linear-
ities, restoring the distorted signal and providing the corrected signal as output. As Figure 13 shows, corrected_
signal and ideal_signal are almost identical signals since the DSP restores the distorted signal.

Figure 13: SimVision Display for Ideal, Distorted, and Corrected Signals

Optimizing an Xtensa Processor Using Xplorer

Cadence Xtensa Xplorer provides a single environment for processor and software design, enabling processor
architects and programmers to work in the same design environment, using the same tools, making it easier to
work together through the entire project design cycle to produce a highly efficient product. Xplorer can be used to
configure Tensilica processors and to build and debug software so that users have full-project management for the
system and the software in a single platform. The Xplorer IDE is a full-featured software development workbench
that includes tools for software development, simulation, profiling, debugging, hardware trace, processor configu-
ration/extension, and building variants of software tools. For this case study, Xtensa Xplorer is used to configure
and build a Tensilica processor with the ConnX D2 DSP and a floating-point unit. The same Xtensa Xplorer SDK is
used to develop and debug the software.

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 Solve RF/AMS Design Challenges Using the Cadence Virtuoso Solution and Tensilica DSPs

Step 1: Select Configuration Options

The first step for processor optimization is to select the configuration options that will be included in the processor
and the software development tools. Figure 14 shows some of the processor configuration options available,
such as DSPs and floating-point/math hardware. Other configuration options such as local memories, bus
interfaces, interrupts, and direct I/O and Queue interfaces are also available. The Queue interface in particular is
useful in connecting the processor directly to the AMS components, bypassing the need for complex and power-
hungry system bus implementations. If click-box options do not yield enough optimization, Xplorer can be used
to define new instructions, registers, states, and ALUs to reduce clock cycles and increase data throughput for
specific operations.

Figure 14: Example Processor Configuration Options in Xtensa Xplorer

Step 2: Write Software and Benchmark

Once the processor has been built, designers need to write software and benchmark it against performance
requirements. Users typically develop their code in C/C++ and debug it at the C/C++ source and assembly
instruction levels.

Figure 15 shows a few of the Xplorer window options that a user can select to open within the IDE to easily
develop software. For example, Xplorer provides the following window options:
• Project tree view to organize code
• Console view
• Memory view
• Syntax-aware editor
• Code browsing with graphically showing the breakpoints and the current line executed
–– C/C++ source view
–– Assembly code view
• Contextual help
• Debug view that organizes all debug sessions currently running with control of each debug session
• View with list of local variables, all breakpoints, expressions evaluated, processor registers, memory
contents, etc.

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 Solve RF/AMS Design Challenges Using the Cadence Virtuoso Solution and Tensilica DSPs

Figure 15: Xtensa Xplorer Programming Environment

Step 3: Optimize Desired System Parameters

C code usually delivers good performance on Tensilica processors, but performance can be limited by resource
conflicts or memory latency. Figure 16 shows one of the Xplorer tools that helps identify what is limiting program
performance. A graphical view of the processor’s pipeline state is correlated with the instructions, spotlighting
pipeline “bubbles” where the processor has been stalled so that programmers can rearrange the code and data to
reduce pipeline stalls. Xplorer also supports typical software profiling, stack tracing, and code utilization reporting.

Figure 16: Graphical Processor Pipeline View

Xplorer also estimates power, area, and processor clock speed based on the selected configuration (see Figure
17). If the performance, die area, or power consumption of the processor does not meet the requirements, the
processor configuration can be iterated quickly to change features and target speeds.

Figure 17: Performance, Area, and Power Estimator View

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 Solve RF/AMS Design Challenges Using the Cadence Virtuoso Solution and Tensilica DSPs

Conclusion
Applying an embedded processor to digital correction and testing of a pipeline ADC brings the benefits of
programmability to an AMS design. A Tensilica processor can be configured with a small DSP and a floating-
point unit to implement advanced signal processing algorithms to generate input stimulus signals, estimate digital
correction parameters, and measure the resulting ADC performance metrics. Results show a significant perfor-
mance improvement for the pipeline ADC.

Including a processor in an RF/AMS design has many other advantages, spanning all phases of a product’s life.
Starting at the inception phase, the processor can be used to tighten design margins by compensating for process,
voltage, and temperature (PVT) variations to save on power and area. The processor can be optimized further to
efficiently perform specialized functions that accelerate digital calibration and testing of RF/AMS components.

During the production testing phase at the foundry, an on-board processor can perform calibration and testing
procedures to detect failed products. Standalone testing is possible via a loopback scheme where the processor
generates test signals that are output through the DAC and are fed back into other RF/AMS components.
Standalone testing facilitates qualification of SoCs in parallel, thereby reducing test time and costs, and also
reducing or eliminating dependence on expensive ATE equipment that is specialized for RF/AMS validation. A
processor provides all of these benefits and allows for firmware upgrades to continuously improve test coverage.
Also, since the processor resides on the SoC, it has access to RF/AMS components that external equipment cannot
reach due to available I/O connectivity and timing delays.

In addition to qualification testing, periodic calibration and testing of components can be conducted in the
field when the device is idle or even during operation through background testing [11]. Digital correction and
calibration of the RF/AMS components in the field would improve overall system performance, extend the life of
the product as CMOS components slowly deteriorate, and support dynamic fault detection to meet functional
safety requirements.

Additionally, advanced tools are necessary for designing and testing RF/AMS components. Cadence Virtuoso and
Incisive tools provide comprehensive design and verification solutions that meet the needs of circuit and verification
engineers and solve their challenges. Those solutions were applied for testing the pipeline ADC and verified its
performance improvement due to the contribution of the Tensilica processor.

Additional Information
For more information on the unique abilities and features of the Cadence Tensilica Xtensa processors, see
ip.cadence.com.

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 Solve RF/AMS Design Challenges Using the Cadence Virtuoso Solution and Tensilica DSPs

References
[1] “Mixed-Signal Design Challenges and Requirements” White Paper.
https://www.cadence.com/rl/Resources/white_papers/mixed_signal_challenges_wp.pdf

[2] “A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi
Transceiver” Solid-State Circuits, IEEE Journal of 48.7 (2013): 1669-1679, Carballido, Jorge, et al. http://ieeexplore.
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[3] “Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS” Staszewski,
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[5] “ADC Architectures V: Pipelined Subranging ADCs”, Walt Kester.

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[6] “Understanding and Minimising ADC Conversion Errors”, Microcontroller Applications (Application Note).
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[7] “Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters”
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[8] “Solutions for Mixed-Signal Soc Verification Using Real Number Models” White Paper.
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[9] “ADE in IC6.1: Value and Benefits Summary“. http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:do

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[10] “Incisive Debug Analyzer User Guide”, Product Version 14.1 June 2014. http://support.cadence.com/wps/
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[11] “Digital Domain Measurement and Cancellation of Residue Amplifier Nonlinearity in Pipelined ADCs”
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