IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO.

11, NOVEMBER 2014 2515

Low Power Design Techniques for Single-Bit

Audio Continuous-Time Delta Sigma ADCs
Using FIR Feedback
Amrith Sukumaran and Shanthi Pavan, Senior Member, IEEE

Abstract—Single-bit continuous-time delta-sigma modulators clock generation and distribution can consume significant cur-
(CTDSM) using FIR feedback DACs inherit the appealing aspects rent. This, unfortunately, is difficult to estimate during the archi-
of both single-bit and multibit designs, without the disadvantage of tectural design phase. Moreover, mismatch in the unit elements
either approaches. In this work, we give a method for stabilizing
a CTDSM that uses an FIR feedback DAC. Further, we show that of the feedback DAC degrade the inband SNDR of the modu-
increasing the number of taps beyond a certain number (dependent lator, necessitating some form of mismatch correction, like cal-
on the architecture and oversampling ratio of the modulator) does ibration or dynamic element matching (DEM). This further in-
not improve performance. The results of our analysis are incorpo- creases the power dissipation and design time of the quantizer.
rated in the design of a third-order audio CTDSM which achieves In contrast, using a single-bit quantizer, where the feedback
a peak A-weighted SNR of 102.3 dB (raw SNR of 98.9 dB) and a
spurious-free dynamic range of 106 dB in a 24 kHz bandwidth, DAC is inherently linear, dramatically simplifies the quantizer
while consuming only 280 µW from a 1.8 V supply. design. However, the full-scale two-level feedback waveform
places increased demands on the linearity of the loop filter, as
Index Terms—Active-RC, analog-to-digital conversion, com-
pensation, continuous-time, FIR DAC, integrator, oversampling, well as increases the sensitivity of the modulator to clock jitter.
Sigma-Delta. From the discussion above, it is seen that a multibit loop com-
plicates the quantizer design at the expense of a simplified loop
filter. The opposite is true in a single-bit modulator. Recog-
I. INTRODUCTION nizing this, several recent works have attempted to alleviate the

H IGH resolution analog-to-digital converters for audio linearity and clock jitter problems associated with a single-bit
applications have traditionally been realized as multibit design. [4] and [5] use integrators based on opamp assistance,
delta sigma modulators, employing switched capacitor cir- which is a circuit technique that enhances the linearity of an
cuitry. However, continuous-time modulators (CTDSM) opamp in a power efficient manner. [6] uses a feedback DAC
are becoming increasingly popular even in these low bandwidth which incorporates a finite impulse response filter (FIR-DAC).
applications due to their low power consumption and the ease The FIR DAC principle is not new [7], [8] – however, relatively
with which they can be driven. Most high performance audio few designs seem to have exploited this technique. The basic
CTDSMs [1]–[3] which have achieved linearity and noise idea behind the FIR DAC is to feedback a filtered version of
comparable to a discrete-time design, however, have used the single-bit quantizer output, as shown in Fig. 1(a). Due to the
multibit quantizers. high frequency attenuation of the FIR filter, the DAC output is
Using a multi-level quantizer has several advantages. First, a multi-level waveform, like in a multibit quantizer. Thanks to
the increased number of levels enables a lower over sampling this, the FIR-DAC approach has low clock jitter sensitivity and
ratio (OSR) to achieve a desired signal to quantization noise relaxes the linearity requirements of the loop filter. In practice,
ratio (SQNR). The reduced step size in the feedback waveform the filter and DAC combination are implemented in a semi-dig-
reduces the sensitivity of the modulator to clock jitter, as well as ital fashion, as shown in Fig. 1(b), which makes the FIR DAC in-
the slew rates required of the opamps in the loop filter. However, herently linear in spite of mismatch. Due to the single-bit quan-
the complexity of the ADC used in the quantizer increases ex- tizer, the ADC design is simple and consumes very little power.
ponentially with the number of bits. Even though the compara- A modulator employing a single-bit quantizer and an FIR DAC,
tors in the quantizer lend themselves to low power operation, therefore, combines the best features of single-bit and multibit
operation. The aim of this work is to investigate the possibility
of achieving a dynamic range in excess of 100 dB, and a corre-
Manuscript received January 19, 2014; revised May 14, 2014; accepted June
21, 2014. Date of publication July 22, 2014; date of current version October 24, spondingly excellent linearity using a single-bit CTDSM with
2014. This work was supported in part through the Center for Analog and Mixed an FIR feedback DAC.
Signal Design, IIT Madras, by the Department of Information Technology, Gov-
FIR feedback presents several design challenges. Due to the
ernment of India.
A. Sukumaran and S. Pavan are with the Electrical Engineering Depart- delayed nature of the feedback waveform, the modulator needs
ment, Indian Institute of Technology Madras, Chennai 600036, India (e-mail: to be carefully stabilized to restore the noise transfer function
[email protected]; [email protected]).
(NTF). An issue particularly relevant to a continuous-time over-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. sampled converter based on an FIR filter is the robustness of
Digital Object Identifier 10.1109/JSSC.2014.2332885 loop compensation in the face of time constant variations in the

0018-9200 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
2516 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014

Fig. 1. (a) Basic idea behind a single-bit CTDSM with an FIR feedback and
(b) a semi-digital realization of the FIR DAC.

loop filter. Our analysis and simulations show that the sensi-
tivity of an FIR DAC based CTDSM with respect to RC spread
is similar to that of a conventional design. Another issue is the Fig. 2. (a) Prototype CIFF-B modulator and (b) FIR-DAC CTDSM based on
the prototype.
choice of the number of taps in the FIR filter. At first glance, it
appears as if increasing the number of taps must result in im-
TABLE I
proved performance (as the shaped quantization noise is more DISCRETE-TIME TRANSFER FUNCTIONS FOR EACH PATH THROUGH THE LOOP
heavily filtered). In this work, we show that there is little (if FILTER, ASSUMING AN NRZ DAC PULSE SHAPE
any) benefit as the number of taps is increased beyond a cer-
tain value. Rise-fall asymmetry of the feedback DAC waveform
causes inter symbol interference, which manifests as even order
distortion and an elevated in-band noise floor at high input am-
plitudes. This has to be considered during the design phase, in
a high resolution modulator such as this.
This paper, which is a more detailed version of [9], presents
an FIR DAC based single-bit CTDSM that addresses these is-
sues. The modulator, designed in a 0.18 m CMOS process,
achieves a dynamic range of 103 dB and an SFDR(spurious free back [11]) design. At high frequencies, the STF(signal transfer
dynamic range) of 106 dB in a 24 kHz bandwidth while dissi- function) rolls off as . Due to feedforward, the output of
pating only 280 W from a 1.8 V supply. The test chip also has virtually no signal at the input frequency. This means that
includes a dither generator, DAC rise-fall asymmetry correc- its gain in the signal band (after dynamic range scaling) will be
tion circuitry, decimator and an SPI interface(serial peripheral large. Thanks to this, non idealities in the rest of the loop filter will
interface). The decimator, which filters out of band quantization be significantly attenuated when referred to the modulator input,
noise, and yields a 20 bit 48 KS/s sequence, consumes 100 W. just like in a CIFF(cascade of integrators with feedforward) de-
The design of the chip forms the subject of the rest of the paper, sign. The CIFF-B architecture, therefore, inherits the appealing
which is organized as follows. In Section II, we describe the aspects of both its parents. The gain of the loop filter from to
architecture and develop the stabilization technique that com- is . The coefficients are chosen so that the
pensates the loop for the delay introduced by the FIR DAC. We resulting NTF is maximally flat (assuming an NRZ(non return
give intuition for the optimal number of FIR filter taps for low to zero) DAC) and has an out-of-band gain of 1.5 in accordance
power operation. Section III discusses circuit design details. Ex- with Lee’s rule [12].
perimental results and comparison with state of the art designs The -domain transfer functions for the , and
are given in Section IV. Section V concludes the paper. paths, which are a ratio of polynomials in , and denoted by
, and respectively, are given in Table I. An
II. ARCHITECTURAL DEVELOPMENT NRZ pulse shape is assumed for the DAC. The numerators of
The architecture of the prototype modulator on which the FIR- these transfer functions, denoted by , and ,
CTDSM is based is a single loop design as shown in Fig. 2(a). all evaluate to unity for . The coefficients , and
The sampling rate is assumed to be 1 Hz. The third order loop can be determined by solving
filter is realized as a CIFF-B (cascade of integrators feedforward
and feedback) structure [10]. This architecture has several ad- (1)
vantages. The fast path around the quantizer (through and
) and the high gain path (through , and ) can be inde- The main feedback DAC ( ) in the prototype is then re-
pendently optimized, like in a CIFB(cascade of integrators feed- placed by an -tap FIR DAC, whose transfer function is de-
SUKUMARAN AND PAVAN: LOW POWER DESIGN TECHNIQUES FOR SINGLE-BIT AUDIO CONTINUOUS-TIME DELTA SIGMA ADCS USING FIR FEEDBACK 2517

noted by , as shown in Fig. 2(b). All taps of the FIR filter A useful observation to make regarding is the fol-
are assumed to be identical for ease of layout. Further the DC lowing. Since , it follows that has a zero at
gain of should be 1, to ensure that the in-band STF of the , enabling it to be expressed as
CTDSM is unity. Thus,
(8)

(2) where is a polynomial of order in . Further,

using (2) and l’Hopital’s rule, we see that
To stabilize the loop so that the NTF is restored, a compen-
sation FIR DAC with transfer function is added at the (9)
input of , and the loop filter coefficients are tuned, as shown
in Fig. 2(b). This means that the gain from to in both de- and (7) yields
signs should be the same at all (discrete-time) frequencies. In
[9], only the final results of the compensation process, enumer- (10)
ated below, were given due to paucity of space.
a) ; Referring to (3), is the only remaining unknown. Using
b) is an N-tap FIR filter. , and , (3)
Here, we derive these results. The intuition for (which is can be recast as follows
larger than ) and is the following. The main FIR DAC,
due to its lowpass nature, reduces the high frequency contribu-
tions of the and paths to the loop gain of the modu-
lator. To restore the loop gain (and thereby the NTF), the gain at (11)
high frequency has to be increased. This is accomplished by in-
creasing and through another FIR filter which excites
where , and denote the numerator polynomials of
the path.
, and respectively. Since and
In the discussion to follow, all hatted quantities refer to the
evaluate to 1 for , it is easy to see that
modulator with the FIR DAC. Equating the loop gains of both
has a zero at . This enables us to write
the modulators in Fig. 2, we have
(12)

(3) where is an order polynomial in . Using this,

and , (11) simplifies to
At very low frequencies (i.e ), the loop gain of both
CTDSMs is dominated by the third order path. Equating these (13)
gains, and recognizing that , we obtain
from which it is immediately apparent that has to be an
tap FIR filter. The theory above establishes that by tuning
(4) , and adding at the input of , the NTF can be restored
exactly. Once this recognized, the coefficients of can also be
determined either analytically as shown above, or by using nu-
Using in (3), and moving to the right hand
merical techniques, by proceeding along lines similar to [13].
side, we have
Fig. 3 shows the magnitude responses of the first, second and
third order paths in a conventional modulator and that with FIR
feedback. In the latter, the loop is assumed to have been com-
(5) pensated in accordance with the discussion above. From part
(b) of the figure, it is apparent that the second and third order
From the equation above, we see that is given by paths have reduced high frequency content due to the FIR filter.
To compensate for this loss, the gain of the first order path has
to be increased (in a frequency dependent way), and is accom-
plished by the compensating filter .

A. Choice of Number of Taps in the FIR DAC

(6)
It is tempting to increase the number of taps in the main FIR
Using Table I for , and , and observing that DAC without limit, since a longer FIR DAC results in better fil-
, we have tering of the quantization noise. Due to this, one would tend to
conclude that the magnitude of the error signal (in Fig. 2(b))
would reduce as increases. This is true for small – better
(7) filtering of the quantization noise does indeed reduce .
2518 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014

Fig. 3. Frequency responses of the first, second and third order paths of the loop gain function in (a) a single-bit modulator and (b) a modulator with a 12-tap FIR
DAC. The coefficients are tuned and the compensation filter is chosen so that the NTF is restored.

Fig. 4. Peak magnitude of the error signal exciting the input integrator versus
the number of taps in the main FIR DAC, for CIFB and CIFF-B loop filters.

Fig. 5. A comparison of the effect of clock jitter for several CTDSM design
However, beyond a certain point, no longer decreases due choices.
to the following.
The -transform of CTDSM output sequence is given by
, where and going through the calculations in (13) reveals that the DC gain
denote the transforms of the sampled input (assumed to be an of increases with . Both of these increase STF peaking
inband signal) and the quantization noise respectively. The error (see Fig. 8), causing the input component of the fed back signal
sequence is given by to be larger in magnitude and shifted in phase with respect
, where to . This means that even though the quantization noise
is the (lowpass) transfer function of the FIR DAC. The wave- component of is smaller, is larger even though
form processed by the loop filter is , is increased. The increased DC gain of is also problem-
where denotes the DAC pulse shape. The peak magnitude atic in a practical implementation, as the input signal component
of the error waveform, therefore, is influenced by two con- injected by the compensation DAC necessitates a lower unity
flicting factors. gain frequency for (after dynamic range scaling). Further, the
a) Shaped quantization noise, filtered by the FIR DAC. power dissipation of the clock generation and distribution cir-
b) An input component, proportional to the deviation of the cuitry increases with the number of taps.
STF from unity. The “optimal” number of taps to be used in the FIR DAC,
As the number of taps ( ) in the FIR DAC is increased, better therefore, is dependent on the loop filter topology (which in-
filtering of the shaped noise causes to reduce. On the fluences the STF) and the input signal frequency. In a CIFF-B
other hand, larger increases due to the design, it is a trade off between the amount of STF peaking
following. As seen from (10), increases with . Further, one is willing to tolerate, the increased power dissipation due
SUKUMARAN AND PAVAN: LOW POWER DESIGN TECHNIQUES FOR SINGLE-BIT AUDIO CONTINUOUS-TIME DELTA SIGMA ADCS USING FIR FEEDBACK 2519

Fig. 6. Effect of RC time constant variations on a CTDSM with (a) an NRZ DAC (b) 12-tap FIR DAC. The insets show the maximum stable amplitude (MSA)
as time constants deviate from their nominal values.

to the extra taps (without a corresponding decrease in ) inal values. The resulting NTFs and MSAs for the conventional
and the DC gain of , which has implications for the de- and FIR-CTDSM are shown in Fig. 6(a) and (b) respectively.
sign of . Simulation results of (normalized to the value It is seen that the out of band gains are similar in both cases.
that would be obtained without an FIR filter), as shown in Fig. 4 Since the high frequency gain of the NTF largely influences the
for CIFB and CIFF-B loop filters were used as a guide to decide MSA, it makes sense that both designs have similar MSAs as
that 12-tap FIR DACs represented a reasonable choice consid- time constants are varied. From this, we conclude that using an
ering the trade offs involved. FIR-CTDSM is not any more sensitive to systematic time con-
stant variations than its NRZ counterpart.
B. Effect of Clock Jitter
III. CIRCUIT DESIGN
It is well known that clock jitter degrades the performance of
a CTDSM by introducing errors in the waveform of the feed- A. Modulator Architecture
back DAC. The error due to jitter in each clock cycle is propor- A simplified single-ended schematic of the third order
tional to the height of the transition of the DAC waveform at CTDSM is shown in Fig. 7(a). As discussed in the preceding
the beginning of the cycle. Since a single-bit modulator results section, a CIFF-B loop filter is used. Negative resistors indicate
in a rail-to-rail feedback waveform, one should expect a severe inversion in the differential version. Active-RC integrators are
degradation of the inband SNR in the presence of clock jitter. used for low noise and high linearity. FIR DACs inject currents
The use of a single-bit quantizer + FIR DAC, or a multibit quan- proportional to the reference into the virtual grounds of the
tizer – can both address this problem. Fig. 5 compares the jitter opamps. feeds the input into the third integrator formed by
sensitivity of several CTDSM design choices. The signal band- - - . Without , the output of would consist of a
width is 24 kHz. White clock jitter, with an RMS value of 50 component proportional to . This is due to the following.
ps is assumed. The single-bit modulator has an OSR of 128. All The magnitude of the low frequency current in must be .
taps of the FIR DAC are equal. For the multibit case, a 12-level This means that the sum of the low frequency currents due to
quantizer, and an NTF with an out-of-band gain of 2.5 is used. the compensating FIR DAC ( ) and the voltage at the
Due to multibit operation, the OSR is reduced to 42, so as to re- output of must be , indicating that the second integrator
sult in the same SQNR as in the single-bit design. As seen from must “absorb” the low frequency output of . To avoid
Fig. 5, using an FIR DAC suppresses jitter noise of a single-bit saturation of this integrator, its integrating capacitor must be
modulator by about dB, and has the same per- large. Using to cancel the low frequency output of
formance as a 12-level multibit CTDSM operating at a third of (which is largely proportional to ) avoids this problem,
the sampling frequency. The ideal spectrum (without jitter) is enabling the use of a much smaller .
also shown for comparison. The NTF of the modulator has optimized zeros for reduced
in-band quantization noise. Since this is an audio design, the fre-
C. Effect of Time Constant Variations
quency of the NTF zeros is small (about 18 kHz), necessitating
A concern regarding an FIR DAC based CTDSM is the ef- the realization of large time constants. In our design, the com-
fect of time constant variations on the NTF, and the maximum plex zeros of the NTF are implemented using weak feedback
stable amplitude (MSA). To examine this, simulations were run around the second and third integrators, which are comprised
on CTDSMs with and without an FIR DAC. Under nominal con- of - - and - - , as explained below. The T-net-
ditions, both modulators were designed to have the same max- work formed by , and inject a current proportional to
imally flat NTF with an out of band gain of 1.5. All time con- the output of into the virtual ground node of , as shown
stants were then changed over a range from their nom- in Fig. 7(a). Since , the current flowing through
2520 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014

Fig. 7. (a) Simplified single-ended schematic of the CTDSM and (b) reusing the common-mode detector at the output of to realize and .

Fig. 8. Simulated STFs of a CIFF-B modulator with an NRZ DAC, and the
same modulator with a 12-tap FIR DAC (and a corresponding compensation
DAC) and input feedforward, as in Fig. 7.

is given approximately by . Without the

Fig. 9. Simplified schematic of the first operational amplifier.
T-network, would have to increase by a factor , re-
quiring a lot of area. In the differential implementation, taps
an appropriate point of the resistive common-mode detector, and feedforward. This is indeed seen in simulation results, as is
needed anyway, at the output of , as shown in Fig. 7(b). Thus, apparent from the plots of Fig. 8. The NTF is not effected by
no extra resistors are needed to realize and [14]. input feedforward.
1) Effect of the FIR DAC and Input Feedforward on the All integrating capacitors are realized as switchable banks,
Signal Transfer Function: The FIR DAC and the compensating to counter RC time constant variations. The opamps are two
filter , as well as input feedforward (through in Fig. 7) stage feedforward compensated structures. Thanks to the low
modify the STF of the modulator. The STF can be derived by frequency of operation (in relation to the speed of the process),
separating the modulator into continuous-time and discrete-time excess loop delay is negligible. For low noise operation, the
parts [15], as shown in the inset of Fig. 8. In this figure, 12-tap FIR DACs are implemented using resistors. Since the
denotes the equivalent discrete-time transfer function from DAC is realized as a semi-digital structure [16], they are inher-
to in Fig. 7. The STF of the modulator is seen to be ently linear: resistor mismatch only alters the transfer function
of the FIR filter, which is virtually inconsequential to modu-
(14) lator performance. Unfortunately, rise-fall asymmetry can cause
even order distortion due to inter symbol interference (ISI), like
where . For a CIFF-B modulator in an a conventional NRZ DAC. Use of FIR filtering does not
without feedforward or an FIR DAC, the STF would be that mitigate this problem [6]. Since reliable matching data for this
in the above equation with and . From the process was not available, an ISI tuning loop that equalizes the
discussion in Section II, , indicating that rise and fall times of the DAC pulse is implemented on-chip.For
one should expect an increased peaking in the signal transfer simplicity of layout, all taps in the main FIR DAC ( ) are
function with respect to a CIFF-B CTDSM without an FIR DAC made identical. Details of the individual blocks are given below.
SUKUMARAN AND PAVAN: LOW POWER DESIGN TECHNIQUES FOR SINGLE-BIT AUDIO CONTINUOUS-TIME DELTA SIGMA ADCS USING FIR FEEDBACK 2521

Fig. 10. (a) Simplified schematic of the half circuit of one tap of the FIR DAC feeding the first integrator and (b) block diagram of the ISI tuning loop.

B. Opamp Design
The noise and linearity of the first opamp in the loop filter
directly determine those of the modulator. The simplified block
diagram and schematic of the opamp are shown in Fig. 9. A
two stage feedforward compensated architecture is chosen to
achieve high gain. The first stage, whose signal path is formed
by transistors , reuses the input stage current, resulting in
low noise for a given power dissipation. The second gain stage
, is formed by . , which forms the feedforward
path and stabilizes the integrator, comprises of . Thanks Fig. 11. Addition of dither at the modulator input.
to the 12-tap FIR DAC, the linearity requirements of the opamp
are greatly relaxed, thereby enabling a low bias current in the
second stage (which is also reused to realize and ). The comparator consists of a preamplifier and a latch. Offset is
The common mode voltage at the output of each stage is stabi- reduced by using large devices and careful layout.
lized by separate CMFB loops.
D. Idle Tones and Dither
C. FIR DACs and ISI Tuning In-band idle tones manifest in the output sequence of a
Fig. 10(a) shows a single ended section of one of the taps single-bit modulator when it is excited by a small input.
of the FIR DAC. is the single-bit decision of the quantizer. For small DC inputs, the frequencies at which idle tones are
Rise-fall asymmetry in each of the single-ended feedback DAC generated are given by integral multiples of
waveforms causes Inter Symbol Interference(ISI). ISI renders [11], where , and denote the sampling frequency, DC
a nonlinear function of . A large part of this even level and the quantizer step size respectively. In this work, idle
order distortion is canceled due to differential operation [17]. tones are pushed out of band without affecting the inband noise
However, mismatches cause the residual distortion to leak into floor, by injecting a two-level waveform, which has a known
the differential output. In view of the extremely low levels of DC component, and a fundamental frequency of . (This
distortion desired in this work, and the lack of reliable resistor causes a DC offset in the output bit stream, which is of no
matching information, the modulator was designed so that the consequence in audio applications.) Simulations show that an
single ended feedback current waveforms have inherently low input offset of about needs to be added at the input
distortion. of the CTDSM to push the idle tones out of the signal band.
The origin of rise-fall asymmetry are the unequal resistances The dithering scheme is implemented as follows. To allow a
of the NMOS and PMOS switches driving the resistor , sufficient margin for random input offset of the CTDSM, a
as shown in Fig. 10(a). To correct this, the PMOS switches are dither whose DC component has amplitude is used,
realized as a 3-bit bank, as shown in Fig. 10(b). The comparator and injected into the modulator as shown in Fig. 11. The dither
compares with , which in turn drives a SAR (succes- signal is a square wave with 25% duty cycle and a fundamental
sive approximation register) loop in a manner so as to bring frequency of , resulting in a DC component of . This
close to . This way, the resistances of the NMOS is converted into a current through the large resistors , so
and PMOS switches are made roughly equal. Simulation re- as to result in an effective differential DC voltage of .
sults show that this coarse tuning is adequate to reduce to
dB levels. Resistors are large to reduce current drained E. Decimation Filter and SPI Digital Interface
from the supply. The ISI tuning loop, which runs at 12 kHz, can The decimation filter converts the single-bit output of the
be turned off to save power. The code generated by the SAR CTDSM at the oversampled rate(6.144 MHz) into a twenty bit
loop is given to the PMOS switches in all taps of the FIR DAC. output at the Nyquist rate(48 kHz). Down sampling is achieved
2522 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014

Fig. 12. Block diagram of the decimation filter.

Fig. 13. (a) Photograph of the testboard and layout and (b) schematic of the test setup.

in multiple stages as shown in Fig. 12. The first stage is a fourth b) DAC and DEM logic: Dynamic Element Matching
order 32-tap CIC filter, implemented as a Hogenauer structure (DEM) logic, needed in a multibit design, is not needed
[18]. This is followed by two halfband FIR low pass filters, each in the FIR-DAC case. Further, at high resolutions such as
of whose outputs are downsampled by a factor of 2. The filter or- this, inter symbol interference (ISI) in the unit elements
ders are 16 and 60 respectively. The twenty bit decimation filter of the DAC can degrade performance even with DWA
output is transferred outside through an SPI interface, which [20]. This will necessitate an ISI tuning loop like the one
also serves to load tuning bits needed in the design. used in our work, or a more complex DEM algorithm
which digitally shapes out ISI as in [20]. Our estimate is
F. Comparison With A Multibit Modulator Targeting the Same that, in spite of the increased sampling rate, the power
Specifications consumed by the digital portion of the FIR DAC (about
It is worthwhile to compare the power dissipation of a multi- 20 W) will be about the same as that in a multibit DAC
bit modulator with that of a single-bit (+FIR DAC) CTDSM (whose linearity is obtained through DEM).
designed in the same process. For this purpose, we use a c) Loop Filter: The output swing of the loop filter in the case
12-level quantizer operating at a third of the sampling rate. Each of a multibit modulator has to be as large as possible so as
sub-block of a CTDSM can be implemented in several ways, to relax the offset requirements on the flash comparators.
making it difficult to accurately assess the exact benefit of using a This dictates the use of an opamp with a peak-to-peak
single-bit quantizer. The comparison that follows is an estimate swing approaching the supply rails. This is most easily
based on our experience with the multibit design of [19]. possible with a Miller compensated opamp. Further, the
a) ADC : A 12-level quantizer needs 11 comparators. Due to load presented by the flash ADC is bound to be atleast
the reduced sampling rate, the dynamic power is reduced 20 times (considering increased routing parasitics) that
by a factor of 3. However, random offsets in the compara- presented by the single-bit ADC. From this discussion,
tors degrade inband noise performance, as seen from sim- it appears as if the opamps will burn considerably more
ulation results given in [19, Fig.12]. These results indi- power when compared to a single-bit design, where these
cate that the standard deviation of the comparator random constraints do not exist.
offset should be restricted to about 0.1 LSB to achieve a From the arguments above, it is apparent that the use of a
worst case SNDR of 105 dB. This means that the power single-bit modulator with an FIR DAC saves power on all
efficient comparator used in the single-bit design is not fronts, while achieving similar (or marginally better) perfor-
appropriate in a multibit scenario. Apart from the refer- mance. This is further borne out by our experimental results
ence ladder, an offset calibration loop will be necessary and comparison with state of the art modulators, presented in
to reduce SNDR degradation due to random offsets in the the following section.
flash ADC. Another aspect that is usually not considered
during the design phase is the power needed in the clock IV. MEASUREMENT RESULTS
generator, which supplies the clock phases needed for the The CTDSM, decimator and an SPI interface (to facilitate
operation of the comparators. Experience shows that this data transfer to/from the chip) were fabricated in a 0.18 m
can draw significant current. Our estimate, based on sim- CMOS process through the Europractice program. Fig. 13(a)
ulations of [19] is that the ADC will need to consume shows the layout and the test board used for characteriza-
atleast 50 W in this technology, as compared to 4 W tion. The active area of the chip, including the decimator, is
in the single-bit case (including the clock generator). 1.25 mm 1 mm.
SUKUMARAN AND PAVAN: LOW POWER DESIGN TECHNIQUES FOR SINGLE-BIT AUDIO CONTINUOUS-TIME DELTA SIGMA ADCS USING FIR FEEDBACK 2523

Fig. 14. (a) PSD of the CTDSM output at peak SNDR and (b) PSD of the decimated output.

Fig. 15. (a) PSD under idle channel conditions with(out) dither and (b) PSD for a input tone (with)out dither.

The test setup is shown in Fig. 13(b). An Audio Precision

AP-SYS 2700 was used as the input source. The test chip had
a provision to enable capture of either the singe-bit output of
the modulator at 6.144 MS/s, or the decimated output at 48
KS/s through an FPGA. Fig. 14(a) shows the PSD of the mod-
ulator at the amplitude that results in the peak SNDR. The peak
SNR, SNDR and dynamic range (DR) are 98.9 dB, 98.2 dB, and
103 dB respectively. The peak A-weighted SNR and SNDR are
102.3 dB and 101.5 dB respectively. The third harmonic dis-
tortion is seen to be about dB. The PSD computed at the
output of the decimation filter indicates virtually the same per-
formance, demonstrating the performance of the decimator.
Fig. 15(a) and (b) show the PSD of the decimated output, with
and without dither enabled, for an idle channel and
input respectively. It is seen that dither has successfully elim-
inated idle tones. Fig. 16 demonstrates the efficacy of the pro- Fig. 16. PSD of the decimated output with(out) ISI tuning, for a
posed ISI calibration scheme. When ISI correction is disabled, input tone. The second harmonic is largely eliminated.
second harmonic distortion is seen to be about dB. With
correction, the second harmonic is buried in the noise floor.
The inherently low (even without correction) indicates SN(D)R as a function of input amplitude. Table II shows a sum-
good resistor matching in this process. Fig. 17 shows the plot of mary of measured performance. Table III compares this work
2524 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014

with state of the art designs in the literature. [1]–[3], [21]–[24]

achieve SNDRs greater than 94 dB – they all employ multibit
quantizers. Our CTDSM achieves significantly better FoM and
a higher SNDR (excepting [23]), in spite of using a single-bit
architecture. [19] and [14] are audio CTDSMs targeting similar
specifications in the same process technology. It is interesting
to compare them with the modulator presented in this work, as
both were designed in our group. [19] is a multibit design, while
[14] is a single-bit CTDSM with the linearity of the first opamp
being enhanced by the assisted opamp technique. It is seen that
the modulator presented in this paper has an FoM better than that
of [19], a 12 dB higher SFDR, and achieves a higher SNDR at
the same time. This demonstrates the inherent architectural ad-
vantage of using FIR feedback.
Fig. 17. Measured SNR and SNDR. They are indistinguishable except at high V. CONCLUSIONS
amplitudes. The peak SNR, SNDR and Dynamic Range are 98.9 dB, 98.2 dB
and 103 dB respectively. We demonstrated that single-bit CTDSMs can achieve very
high linearity in a power efficient manner by using an FIR feed-
TABLE II
SUMMARY OF MEASURED PERFORMANCE
back DAC. A technique for compensating the loop for the
delay of the FIR DAC, thereby restoring the NTF of the mod-
ulator, was described. We showed that the number of taps in
the FIR DAC should be chosen based on the modulator ar-
chitecture and the OSR. Measurement results from a test chip
designed in a 0.18 m CMOS technology, which included a
decimator in addition to the modulator, showed that the modu-
lator achieves a peak A-weighted SNR of 102.3 dB, a peak raw
SNDR of 98.9 dB and an SFDR of 106 dB while dissipating
280 W from a 1.8 V supply. This performance translates to
an FoM of 88 fJ/lvl ( dB).The theory and
techniques described in this paper are, therefore, borne out by
our test results.

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