Eastern Mediterranean University

School of Computing and Technology

ITEC255
Computer Organization
ITEC255 - Computer Organization & Architecture

& Architecture

A TOP-LEVEL VIEW OF COMPUTER

FUNCTION AND INTERCONNECTION
(PART 2)
 Computer Function

• The discussion so far has focused only on the occurrence of a

single interrupt. However, multiple interrupts can occur.

• For example, a program may be receiving data from a

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communications line and printing results.

 The printer will generate an interrupt every time that it
completes a print operation.
 The communication line controller will generate an
interrupt every time a unit of data arrives.

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 Computer Function
• Two approaches can be taken to dealing with multiple interrupts.
1. The first is to disable interrupts while an interrupt is being
processed. A disabled interrupt simply means that the processor can
and will ignore that interrupt request signal. If an interrupt occurs
during this time, it generally remains pending and will be checked by
the processor after the processor has enabled interrupts. This
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approach is nice and simple, as interrupts are handled in strict

sequential order.

Interrupt Y

Sequential Interrupt
Processing

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 Computer Function

2. A second approach is to define priorities for interrupts and to allow

an interrupt of higher priority to cause a lower-priority interrupt
handler to be itself interrupted.
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Interrupt Y

Nested Interrupt
Processing

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 Computer Function

Example:
• Consider a system with three I/O devices: a printer, a disk and
a communications line, with increasing priorities of 2, 4 and 5,
respectively.
• A user program (priority=0) begins at t=0.
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• At t=10, a printer interrupt occurs.

• At t=15, a communications line interrupt occurs.
• While this routine is executing, a disk interrupt occurs at t=20.
• Assume that all the devices need 10 seconds to execute in the
CPU.
• Draw the timeline diagram for the above scenario using:
 Sequential interrupt processing
 Nested interrupt processing

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 t=0 UP (0)
t=10 P (2)
Computer Function t=20 D (4)
t=15 CL (5)
User program (0)
• Solution for t=0
sequential P (2)
interrupt t=10
t=10
processing P (2)
t=10 CL (5)
t=15
Queue
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UP CL D t=20 D (4)
(0) (5) (4) t=20
CL (5)
t=20

t=30
D (4)
t=30

UP (0)
t=40
t=40
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 t=0 UP (0)
t=10 P (2)
Computer Function t=20 D (4)
t=15 CL (5)
UP (0)
• Solution for t=0
nested P (2)
interrupt t=10
t=10
processing P (2) CL (5)
t=10
t=15
CL (5)
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t=15 D (4)
t=20
Queue
UP P D t=25
(0) (2) (4)
D (4)
t=25

P (2) t=35
t=35
UP (0)
t=40
t=40

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 Interconnection Structures

• A computer consists of a set of components or modules of

three basic types (processor, memory, I/O) that
communicate with each other. In effect, a computer is a
network of basic modules.
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• Thus, there must be paths for connecting the modules.

The collection of paths connecting the various modules is
called the interconnection structure.

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 Interconnection Structures
• Interconnection structure must support following types of
transfers:
 Memory to CPU: Processor reads an instruction or a unit
of data from memory.
 CPU to memory: Processor writes a unit of data to
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memory.
 I/O to CPU: Processor reads data from an I/O device.
 CPU to I/O: Processor sends data to an I/O device.
 I/O to or from memory: An I/O module is allowed to
exchange directly with memory, without going through
processor, using Direct Memory Access (DMA).

• Over the years, a number of interconnection structures have

been tried. By far the most common is the bus and various
multiple-bus structures.
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 Bus Interconnection

• A bus is a communication pathway connecting two or more

devices. A key characteristic of a bus is that it is a shared
transmission medium.
• Multiple devices connect to the bus, and a signal transmitted
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by any one device is available for reception by all other

devices attached to the bus.
• If two devices transmit during the same time period, their
signals will overlap and become garbled. Thus, only one
device at a time can successfully transmit.
• Typically, a bus consists of multiple communication pathways,
or lines. Each line is capable of transmitting signals
representing binary 1 and binary 0.

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 Bus Interconnection

• Over time, a sequence of binary digits can be transmitted

across a single line. Taken together, several lines of a bus can
be used to transmit binary digits simultaneously (in parallel).
• For example, an 8-bit unit of data can be transmitted over eight
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bus lines.
• Computer systems contain a number of different buses that
provide pathways between components at various levels of the
computer system hierarchy.
• A bus that connects major computer components (processor,
memory, I/O) is called a system bus.
• The most common computer interconnection structures are
based on the use of one or more system buses.

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 Bus Interconnection
• Bus Structure
 A system bus consists, typically, of from about 50 to
hundreds of separate lines. Each line is assigned a
particular meaning or function.
 Although there are many different bus designs, on any bus
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the lines can be classified into three functional groups:

data, address, and control lines.
 In addition, there may be power distribution lines that
supply power to the attached modules.

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 Bus Interconnection

 The data lines, collectively, are called the data bus.

 The data bus may consist of 32, 64, 128, or even more
separate lines, the number of lines being referred to as the
width of the data bus.
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 Because each line can carry only 1 bit at a time, the number
of lines determines how many bits can be transferred at a
time.
 The width of the data bus is a key factor in determining
overall system performance.
 For example, if the data bus is 32 bits wide and each
instruction is 64 bits long, then the processor must access
the memory module twice during each instruction cycle.

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 Bus Interconnection

 The address lines are used to designate the source or

destination of the data on the data bus.

 The width of the address bus determines the maximum

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possible memory capacity of the system.

 Furthermore, the address lines are generally also used to

address I/O ports.

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 Bus Interconnection

 The control lines are used to control the access to and

the use of the data and address lines.
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 Because the data and address lines are shared by all

components, there must be a means of controlling their
use.

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 Bus Interconnection
 Typical control lines include:
 Memory write: Causes data on the bus to be written into the addressed
location.
 Memory read: Causes data from the addressed location to be placed on
the bus.
 I/O write: Causes data on the bus to be output to the addressed I/O port.
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 I/O read: Causes data from the addressed I/O port to be placed on the
bus.
 Transfer ACK: Indicates that data have been accepted from or placed
on the bus.
 Bus request: Indicates that a module needs to gain control of the bus.
 Bus grant: Indicates that a requesting module has been granted control
of the bus.
 Interrupt request: Indicates that an interrupt is pending.
 Interrupt ACK: Acknowledges that the pending interrupt has been
recognized.
 Clock: Is used to synchronize operations.
 Reset: Initializes all modules.
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 Bus Interconnection

• The operation of the bus:

 If one module wishes to send data to another, it must do
two things:
 obtain the use of the bus
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 transfer data via the bus

 If one module wishes to request data from another module,

it must:
 obtain the use of the bus
 transfer a request to the other module over the
appropriate control and address lines
 it must then wait for that second module to send the
data
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 Bus Interconnection

 If a great number of devices are connected to bus, performance

will suffer. There are two main causes:
 Propagation delay: Time it takes for devices to coordinate
use of bus.
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 Bus may become a bottleneck as total data transfer

demand approaches the capacity of the bus.

 Most computers systems use multiple buses, generally laid

out in a hierarchy.

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 Bus Interconnection

Traditional hierarchical bus architecture:

• There is a local bus that connects processor to a cache memory
and that may support one or more local devices.
• Use of a cache structure insulates CPU from frequent accesses
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to main memory.
• Main memory can be moved off local bus onto a system bus.
• It is possible to connect I/O controllers directly onto system
bus. A more efficient solution is to make use one or more
expansion buses for this purpose:
 An expansion bus interface buffers data transfers between
system bus and I/O controllers on expansion bus.
 An expansion bus interface insulates memory-to-processor
traffic from I/O traffic.
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ITEC255 - Computer Organization & Architecture Bus Interconnection

Traditional hierarchical bus architecture

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 Bus Interconnection

High performance bus architecture:

• Traditional bus architecture is reasonably efficient but begins
to break down as higher and higher performance is seen in the
I/O devices.
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• Solution to this is to incorporate a high-speed bus. Specifically

designed to support high-capacity I/O devices.
 Brings high-demand devices into closer integration with
processor and at the same time is independent of processor.
 Changes in processor architecture do not affect high-speed
bus and vice-versa.

• This arrangement is sometimes known as a mezzanine

architecture.
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ITEC255 - Computer Organization & Architecture Bus Interconnection

High performance bus architecture

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 Peripheral component interconnect (PCI)
• The peripheral component interconnect (PCI) is a popular
high-bandwidth, processor-independent bus that can function as
a mezzanine or peripheral bus.

• Compared with other common bus specifications, PCI delivers

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better system performance for high-speed I/O subsystems (e.g.

graphic display adapters, network interface controllers, disk
controllers, and so on).

• But it is not just a high speed that makes PCI attractive. PCI is
specifically designed to meet economically the I/O requirements
of modern systems; it requires very few chips to implement and
supports other buses attached to the PCI bus.

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 Peripheral component interconnect (PCI)
• Figure shows a typical use of PCI in a single-processor system.
 A combined DRAM controller and bridge to the PCI bus provides tight
coupling with the processor and the ability to deliver data at high speeds.
 The bridge acts as a data buffer so that the speed of the PCI bus may
differ from that of the processor’s I/O capability.
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 Peripheral component interconnect (PCI)
• In a multiprocessor system, one or more PCI configurations may be connected
by bridges to the processor’s system bus.
 The system bus supports only the processor/cache units, main memory,
and the PCI bridges.
 Again, the use of bridges keeps the PCI independent of the processor
speed yet provides the ability to receive and deliver data rapidly.
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