A CMOS Switching Mode Amplifier with 3 V Output Swing

for Continuous-Wave Frequencies up to 4 GHz

R. Bieg, M. Schmidt, M. Berroth
Institute of Electrical and Optical Communications Engineering
University of Stuttgart, 70569 Stuttgart, Germany

Abstract — In this paper the design of a voltage-mode switching

mode amplifier in a 65-nm CMOS process in the GHz range is
described. The amplifier can be operated with a rectangular drive
signal with 50 % duty cycle up to 4 GHz and pseudo random
bit sequences up to 4 GBit/s. The calibrated broadband PAE of
the amplifier chip is 22 % at 2 GHz, 13 % at 3 GHz and 7 % at
4 GHz for a rectangular drive signal with 50 % duty cycle. The
broadband output power into 50 Ω is 15.3 dBm for 2 GHz, 14 dBm
for 3 GHz and 12 dBm for 4 GHz for a single ended measurement.

Index Terms — CMOS integrated circuits, Broadband

amplifiers, Microwave amplifiers

I. I NTRODUCTION
In today’s mobile communication systems high frequency
power amplifier are usually linear power amplifiers. Despite
their good linearity they suffer from bad efficiency. Switching
mode amplifiers (SA) are very efficient. In theory a SA achieves
100 % efficiency. Recent publications show efficiencies beyond
75 % [1], [2]. A brief overview over recently published PAs is
given in Table I.
This paper describes a switching mode amplifier in a 65 nm
CMOS process. Compared to SiGe or GaN the achievable
PA bandwidth and the output power in CMOS are smaller.
However CMOS itself is cheaper and the PA can be integrated Fig. 1. Switching mode amplifier built of stacked transistors.
onto the same die with the baseband processor. The breakdown
voltage of the CMOS transistors is 1 V and thus small for power
applications. In this paper a solution is presented how to achieve
an output swing of 3 V by stacking the transistors.
II. CMOS S WITCHING M ODE A MPLIFIER U SING S TACKED
T RANSISTORS
A. Output Switching Stage
Fig. 1 shows the switching mode amplifier stage at the output
of the chip. It is built of three stacked transistors for both,
the nFET- and the pFET-branch. For one branch this results
in the non-conducting case in three blocking transistors, each
with a breakdown voltage of 1 V. Therefore the overall voltage Fig. 2. Block diagram of the amplifier chip.
of 3 V is distributed equally on all 3 transistors. With this
technique fast CMOS transistors can be used to achieve both –
fast switching times and high output swing, which also means B. Circuit Overview
high output power. The switching mode amplifier output stage needs three
The drawback of this architecture can also be seen in Fig. 1: signals to be driven correctly. These signals need to be
three signals are needed to drive the amplifier stage. Hence the generated in the CML2CMOS circuit. This part generates four
driver needs to be bigger and also the positions of the slopes of signals in the different voltage ranges. The bottom-signal is
each signal to each other are important. Adjustable delay cells defined between 0 V and 1 V, the middle-signals between 1 V
are used to be able to set the positions of the slopes. This leads and 2 V and the top-signal between 2 V and 3 V. To be able to
to the following block diagram depicted in Fig. 2. correct the slopes of each signal delay cells are used with which

‹,(((
 TABLE I
S TATE OF THE ART SWITCHING MODE PA S

f Pout VDD
Reference Technology PA Topology
[GHz] [dBm] [V]
65 nm CMOS thick- two-stage stacked-
[3] 1.8 29.4 3.4
oxide FETs (230 nm) cascode with cascode driver
GaN transistor with comple-
[4] 0.25 μm GaN 0.5 31.76 201
mentary SiGe BiCMOS driver
[5] 45 nm CMOS SOI DAC with stacked FETs 0.1 13.82 4.0
This work 65 nm CMOS stacked FETs with active driver 3 14 3.0
1
Value taken from Fig. 10 in [4]
2
Value taken from Fig. 8 in [5]

the rising or the falling slope can be delayed. For the generation
100 18
of the control voltages an analog circuit is used, which shifts
16
the input control voltage into the correct voltage range. The 95
delayed signals then drive the output switching mode amplifier. 14

Output power [dBm]

Rise/Fall time [ps]
90 12
III. M EASUREMENT RESULTS
10
A. Rectangular Continuous-Wave Drive Signal with 50 % Duty 85
8
Cycle
80 6
The circuit is driven by a periodic rectangular drive signal.
P 4
Continuous-wave (CW) frequencies up to 4 GHz i.e. 8 GBit/s 75 out
Rise time 2
are possible. The measurement results of the rise and fall times, Fall time
the output power and the efficiency are discussed. 70 0
0.5 1 1.5 2 2.5 3 3.5 4
1) Rise and fall times: Short rise and fall times are a goal Signal frequency [GHz]

in the design of the switching mode amplifier to reduce power

Fig. 3. 10 % - 90 % rise- and fall times and output power vs. the
loss. In Fig. 3 the 10 % - 90 % rise and the 90 % - 10 % fall signal frequency for a periodic drive signal with a 50 % duty cycle.
times are depicted for different frequencies. The rise and fall
times vary for different frequencies because they depend on the

Peak−to−peak−amplitude / Rise time [mV/ps]

alignment of the driver signal edges. The simulated maximal 2.8 36
possible additional delay of the delay cells is 55 ps and thus too 2.7
Peak−to−peak−amplitude [V]

less for low frequencies. Unaligned edges result in higher rise 34

2.6
and fall times. For high frequencies the output swing reduces
and as a result the rise and fall times decrease. This can be 2.5 32
seen in Fig. 4. The peak-to-peak output amplitude and the 2.4
peak-to-peak amplitude / rise time are depicted. For frequencies 30
2.3
above 2.5 GHz the output swing and the rise time decrease. The
ratio between both decreases as well. 2.2
28
2) Output Power: For a periodic signal the output power can 2.1
be calculated by
2 26
 T
0.5 1 1.5 2 2.5 3 3.5 4
1 u2out Signal frequency [GHz]
Pout = · dt , (1)
T 0 RL Fig. 4. Uncalibrated peak-to-peak amplitude and peak-to-peak
where Pout is the broadband output power measured at the load amplitude / rise time vs. the signal frequency for a periodic drive
resistance RL = 50 Ω. Fig. 3 shows results of the calibrated signal with a 50 % duty cycle.
output power against the CW frequency. For a frequency of
1 GHz the measured output power is 15.5 dBm. For increasing
RL = 50 Ω the output power of an ideal switching mode
frequency Pout decreases to approximately 12 dBm at 4 GHz.
amplifier is calculated by
This reduction is due to the growing percentage of the transition
time vs. the whole period and due to decreasing output swing. 2
URMS 1.52
3) Efficiency: For efficiency considerations several Pout,ideal = = W = 45 mW , (2)
RL 50
definitions are made. The ideal switching mode amplifier
with 100 % efficiency has a full output swing with infinite where URMS is 1.5 V for a single ended measurement. Due to
steep transitions. For a 3 V output and a load resistance of dynamic and static losses the ideality factor for a real switching
 100
Ideality factor [%], Efficiency [%], PAE [%]

P /P
out out,ideal
η
80 p
PAE
p

60

40

Fig. 6. Uncalibrated eye-diagrams of the output voltage including

20 cable and setup losses using a PRBS 215 − 1 pulse train with left:
2 GBit/s, middle: 3 GBit/s, right: 4 GBit/s.
0
0.5 1 1.5 2 2.5 3 3.5 4
Signal frequency [GHz]
is the dynamic power loss due to the CMOS delay cells and
Fig. 5. Efficiency of the switching stage vs. the signal frequency for the driver and thus increases with the frequency.
a periodic drive signal with a 50 % duty cycle.
B. PRBS Pulse Train
The amplifier is also measured with a PRBS pulse train.
mode amplifier is: Pout /Pout,ideal < 100 %. In Fig. 5 the ideality Fig. 6 shows the uncalibrated eye diagrams. On the left the eye
factor is shown for different signal frequencies. For 4 GHz an diagram for 2 GBit/s and a PRBS 215 − 1 sequence is depicted.
ideality factor of 35 % was measured. The vertical opening of the eye is 2 V and the horizontal
The broadband output power of the PA will be analysed opening 356 ps. The ideal values are 3 V and 500 ps for the
in this paper. Therefore the unfiltered broadband efficiency is vertical eye opening and horizontal eye opening respectively.
defined as follows: The eye diagrams for higher bit rates are also depicted in Fig. 6.
The measured attenuation of the connected cables and adapters
Pout Pout is 0.24 dB for 2 GHz, 0.4 dB for 3 GHz and 0.58 dB for 4 GHz.
ηp = = . (3)
PDC Pout + Pstat + Pdyn
IV. C ONCLUSION
The unfiltered broadband power added efficiency (PAE) This article presents a switching mode amplifier with 3 V
results as output swing in 65-nm CMOS technology designed with
Pout − Pin stacked transistors to prevent breakdown of the transistors. The
P AEp = , (4) general structure, the measured rise and fall times, broadband
PDC
output power and calculated efficiency are demonstrated in
where Pin is the power of the input pulse train calculated in the the CW-frequency range from 0.5 GHz to 4 GHz. The high
same way as the output power. ηp and P AEp are almost equal bandwidth of the amplifier is shown. Finally, the measurement
because of the small input voltage swing. Due to static losses results of PRBS pulse trains at 2 GBit/s, 3 GBit/s and 4 GBit/s
in the CML buffer and the analog part as well as dynamic are given. Compared to SiGe or GaN the presented solution can
losses in the delay cells and driver, the broadband efficiency be built in cheaper CMOS technology and can be integrated
is reduced compared to the ideality factor. Fig. 5 also shows onto the same die with the baseband processor.
the broadband efficiency, which reaches values between 42 %
and 7 %. Additionally the broadband power added efficiency is R EFERENCES
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