Ninevah University

College of Electronics Engineering

Department of Systems and Control

Subject: Microprocessors II

Student Name:< Omer Sameer Ali >

Q1) Consider your first and last name (as characters data) are stored in MEM
starting at address PRNT_MY_NAME. Therefore, the number of characters
held in the buffer is identified by character count of your first and last
name (plus one character for space). While the data lines, status, and
control signal are connected as follow:

v Data bus lines connected to address of port 0 = 4000h

v Strobe output connected to address of port 1 = 4002h
v Busy signal connected to address of port 2 = 4004h

Write the required assembly code to program the I/O printer ports so that
printing your first and last name on the output port.

SOL :-

MOV CL,0Bh ; CL = number of characters (Omer Sameer)

MOV SI, Omer_Sameer ; character pointer

POLL_BUSY: MOV DX,4004h ; Move address of Busy signal to DX

IN AL,DX ; read logic value of busy to AL
AND AL,01h
JNZ POLL_BUSY ; keep polling until BUSY = 0

MOV AL,[SI]
MOV DX,4000h ; set DX to address of port 0
OUT DX,AL ; output and transfer the char to port 0

MOV AL,00h ; STB = ‘0’(enable the strobe signal)

MOV DX,4002h ; set DX to address of port 1
OUT DX,AL ; output to activate the control signal (strobe)

MOV BX, 0Fh ; to make the Strobe active for 16 CLK cycles
(delay for STB duration)
Repeat: DEC BX
JNZ Repeat
MOV AL,01h ; STB = ‘1’ (disable the strobe signal)
OUT DX,AL

INC SI
DEC CL
JNZ POLL_BUSY
DONE: HLT
Q3) It is required to repeatedly generate the following timing signal using the
timer/counter chip 82C54 that is connected to an 8086-based
microprocessor. Consider the starting address of the 82C54 chip is 70h,
and its clock frequency is 1 HZ. Write down the required program to
perform this task.

2 sec 15 sec ●●●●●

10 sec
Cycle N
Cycle 1

SOL :-

Address of counter 0 = Starting address = 70h

Address of counter 1 = Starting address + 1 = 70 h + 1 = 71h
Address of counter 2 = Starting address + 2 = 70 h + 2 = 72h
Address of control word Reg. = Starting address + 3 = 70 h + 3 = 73h

CLK (1 Hz) Vcc (5 v)

D0 – D7 82C54
CLK0 (1 Hz)
Counter 0
Count = 10 Gate0 = '1'
Mode 0
OUT0
Ao

Counter
Counter 11 CLK1 (1 Hz)
A1 Count = 22
Count Gate1
Mode 00
Mode
OUT1 total out for
one cycle
####
𝐑𝐃 CLK2 (1 Hz)
Counter
Counter 22
Count == 15
Count 15 Gate2
Mode
Mode 00
#####
𝐖𝐑 OUT2

####
𝐂𝐒
Determine the control word of each counter:

D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW/W1 RW/W0 M2 M1 M0 BCD

0 0 0 1 0 0 0 1 Counter 0

= 11 h

0 1 0 1 0 0 0 1 Counter 1

= 51 h

1 0 0 1 0 0 0 1 Counter 2

= 91 h

Writing the required Code:

Again : MOV DX,73h

MOV AL,11h ; set up counter0
OUT DX,AL
MOV AL,51h ; set up counter1
OUT DX,AL
MOV AL,91h ; set up counter2
OUT DX,AL

MOV DX,70h
MOV AL,10h ; Initialize counter0 with 0010h
OUT DX,AL

MOV DX,71h
MOV AL,02h ; Initialize counter1 with 0020h
OUT DX,AL

MOV DX,72h
MOV AL,15h ; Initialize counter2 with 15h
OUT DX,AL

JMP Again ; to repeat the cycle of the signal

Q2) For the figure given below, answer the followings:

a) What should be the control word if ports A, B, and C of an 82C55 PPI

chip are to be configured for mode 0 operation? Moreover, ports A and
B are to be used as inputs and C as an output.

b) Assume that PPI 2, shown in the figure below, is configured as in part

(a) above. Write a program that will input the data at ports A and B, add
these values together, and output the sum to port C.

Minimum-mode of 8086
with memory-mapped I/O ports

###
CS 2
SOL :-

a)

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 0 0 1 0

D7 = 1 for enable .
D6 D5 = 0 0 & D2 = 0 for mode 0 .
D4 = 1 for port A as input .
D1 = 1 for port B as input .
D3 & D0 for port C as output .

Control word = 92 h

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Port A :
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0

Port B :
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0

Port C :
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0

Control Register :
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0
Port A address = 00408 h
Port B address = 0040A h
Port C address = 0040C h
Control Register = 0040E h

Writing the required code :

MOV AX,0000h ; create data segment at 00000h

MOV DS,AX
MOV AL,92h ; configuring the PPI
MOV [40Eh],AL
MOV AL,[408h] ; Reading from port A
MOV BL,[40Ah] ; Reading from port B
ADD AL,BL
MOV [40Ch],AL ; Writing to port C
Q4) Design a memory interface for an 8086-basd microcomputer system.
Given that the microprocessor subsystem will provide 1MB of SRAM
that is organized as 512K x 16-bit, starting at address 07000h. Use only
the SRAM chips of capacity (256K x 8-bit) as needed to construct the
required subsystem memory. Assume that the 8086 microprocessor
address, data, status, and control busses are already demultiplexed and
buffered.
SOL :-

1M/256K = 4 chips of 62256 SRAM chips (in total) are needed

512K/256K = 2 chips of upper bank & the same is required to construct the lower bank

To address the upper and lower banks, a one (1-to-2) address decoder is required
to select one SRAM out of two chips from each bank-group.

Address Range
Start address is 07000h, and the capacity is 1 MB, then the No. of address lines (N)
required to access all locations

N = Log2 (1 MB ) = Log2 (210 * 210 ) à 20-bit is required for the address

(00000h through FFFFFh)
Thus the address range is :
Low = start address (07000h)
High= (𝑠𝑡𝑎𝑟𝑡 + 𝑠𝑡𝑜𝑟𝑎𝑔𝑒 𝑐𝑎𝑝𝑎𝑐𝑖𝑡𝑦 − 1) = (07000h + FFFFFh) = 106FFFh

Then the address range is (07000h through 106FFFh)

A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0

•
•
•

0 0 1 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1

###
M / 𝐈𝐎 Decoder Address Lines ######
𝐁𝐋𝐄
v A22 & A21 are decoded with the control signal M/IO to select memory
v A20 is the input of the 1 -to- 2 address decoder to select/enable one
SRAM chip from the upper group (bank0) and one SRAM chip from the
lower group (bank1)

v A0 is used as an enable control signal for lower bank (BLE)

A21

A22

v Bank-specific write signals:

The 8086 MPU reads/writes data from/to both upper and lower bank
groups :

• (D15 – D8) from high bank as needed with control signals (RD & HWR)
• (D7 – D0) from lower bank as needed with control signals (RD & LWR)
 Bank 0 8 bits
A19 – A0 D0 – D7

#####
𝐖𝐄
SRAM 0
####
𝐎𝐄 (256K * 8-bit)
Low - byte
###
𝐂𝐄
16

Bank 0
A19 – A0 D0 – D7
8 bits
#####
𝐖𝐄
SRAM 1
####
𝐎𝐄 (256K * 8-bit)
High - byte
###
𝐂𝐄
....0
𝑪𝑺 16 bits
Q0
A20 Address ....1
𝑪𝑺
Decoder Q1 D15 – D0
Bank 1
8 bits
A19 – A0 D0 – D7
#####
𝐖𝐄
SRAM 2
####
𝐎𝐄 (256K * 8-bit)
Low - byte
###
𝐂𝐄
16

Bank 1
A19 – A0 D0 – D7
#####
𝐖𝐄 8 bits
SRAM 3
####
𝐎𝐄 (256K * 8-bit)
High - byte
###
𝐂𝐄