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    Timing Specifications: Table 2

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    mhasansharifi
    This document provides timing specifications for an ADM485 chip. It includes propagation delays, rise/fall times, and enable/disable timing for the driver and receiver circuits. All specifications are given under minimum, typical, and maximum conditions within defined voltage, load, and test setup parameters.

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    Timing Specifications: Table 2

    Uploaded by

    mhasansharifi
    18 views1 page
    This document provides timing specifications for an ADM485 chip. It includes propagation delays, rise/fall times, and enable/disable timing for the driver and receiver circuits. All specifications are given under minimum, typical, and maximum conditions within defined voltage, load, and test setup parameters.

    Original Title

    ADM485 4

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    This document provides timing specifications for an ADM485 chip. It includes propagation delays, rise/fall times, and enable/disable timing for the driver and receiver circuits. All specifications are given under minimum, typical, and maximum conditions within defined voltage, load, and test setup parameters.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    18 views1 page

    Timing Specifications: Table 2

    Uploaded by

    mhasansharifi
    This document provides timing specifications for an ADM485 chip. It includes propagation delays, rise/fall times, and enable/disable timing for the driver and receiver circuits. All specifications are given under minimum, typical, and maximum conditions within defined voltage, load, and test setup parameters.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    ADM485

    TIMING SPECIFICATIONS
    VCC = 5 V ± 5%, all specifications TMIN to TMAX, unless otherwise noted.

    Table 2.
    Parameter Min Typ Max Unit Test Conditions/Comments
    DRIVER
    Propagation Delay Input to Output, tPLH, tPHL 2 10 15 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 22
    Driver Output to OUTPUT, tSKEW 1 5 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 22
    Driver Rise/Fall Time, tR, tF 8 15 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 22
    Driver Enable to Output Valid 10 25 ns RL = 110 Ω, CL = 50 pF, see Figure 23
    Driver Disable Timing 10 25 ns RL = 110 Ω, CL = 50 pF, see Figure 23
    Matched Enable Switching |tZH − tZL| 0 2 ns RL = 110 Ω, CL = 50 pF, see Figure 23 1
    Matched Disable Switching |tHZ − tLZ| 0 2 ns RL = 110 Ω, CL = 50 pF, see Figure 231
    RECEIVER
    Propagation Delay Input to Output, tPLH, tPHL 8 15 30 ns CL = 15 pF, see Figure 24
    Skew |tPLH − tPHL| 5 ns CL = 15 pF, see Figure 24
    Receiver Enable, tZH, tZL 5 20 ns CL = 15 pF, RL = 1 kΩ, see Figure 25
    Receiver Disable, tHZ, tLZ 5 20 ns CL = 15 pF, RL = 1 kΩ, see Figure 25
    Tx Pulse Width Distortion 1 ns
    Rx Pulse Width Distortion 1 ns
    1
    Guaranteed by characterization.

    Rev. F | Page 4 of 16

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