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    The University of The South Pacific: EE326 Embedded Systems

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    Vijendra Pandey
    This document contains the text of homework questions from an embedded systems course. Question 1 asks students to combine 1Kx8 ROMs into an 8Kx8 ROM. Question 2 calculates the average cost of access for a two-level cache with given hit rates and access costs. Question 3 performs capacity planning for a two-level memory system, calculating average access times and costs for different cache size options and determining the optimal design.

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    The University of The South Pacific: EE326 Embedded Systems

    Uploaded by

    Vijendra Pandey
    248 views2 pages
    This document contains the text of homework questions from an embedded systems course. Question 1 asks students to combine 1Kx8 ROMs into an 8Kx8 ROM. Question 2 calculates the average cost of access for a two-level cache with given hit rates and access costs. Question 3 performs capacity planning for a two-level memory system, calculating average access times and costs for different cache size options and determining the optimal design.

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    USP EE326 Embedded Systems Tutorial 3

    Original Title

    Tut-03-Sol

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    This document contains the text of homework questions from an embedded systems course. Question 1 asks students to combine 1Kx8 ROMs into an 8Kx8 ROM. Question 2 calculates the average cost of access for a two-level cache with given hit rates and access costs. Question 3 performs capacity planning for a two-level memory system, calculating average access times and costs for different cache size options and determining the optimal design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    248 views2 pages

    The University of The South Pacific: EE326 Embedded Systems

    Uploaded by

    Vijendra Pandey
    This document contains the text of homework questions from an embedded systems course. Question 1 asks students to combine 1Kx8 ROMs into an 8Kx8 ROM. Question 2 calculates the average cost of access for a two-level cache with given hit rates and access costs. Question 3 performs capacity planning for a two-level memory system, calculating average access times and costs for different cache size options and determining the optimal design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    The University of the South Pacific

    EE326 Embedded Systems

    HOMEWORK 3 Date: July 2018 Dr. Assaf M.

    Question 1 Compose 1Kx8 ROMs into an 8K×8 ROM.

    Question 2 Given a 2-level cache design where the hit rates are 88% for the smaller cache
    and 97% for the larger cache, the access costs for a miss are 12 cycles and 20 cycles,
    respectively, and the access cost for a hit is one cycle, calculate the average cost of access.

    Hit rate = .88

    1|Page
    The University of the South Pacific

    EE326 Embedded Systems

    HOMEWORK 3 Date: July 2018 Dr. Assaf M.


    L1 miss and L2 hit rate = 0.12 * 0.97
    L1miss and L2 miss rate = 0.12 * 0.03

    Avg. cost ≈ (0.88 * 1) + (0.12 * 0.97 * 12) + (0.12 * 0.03 * 20) ≈ 0.88 + 1.3968 + 0.072 ≈ 2.3488
    cycles

    Question 3 You are asked to perform capacity planning for a two-level memory system. The
    first level, M1, is a cache with three capacity choices of 64 Kbytes, 128 Kbytes, and 256 Kbytes.
    The second level, M2, is a main memory with a 4-Mbyte capacity. Let c1 and c2 be the costs per
    byte and t1 and t2 the access times for M1 and M2, respectively. Assume c1 = 20 c2 and t2 = 10 t1.
    The cache hit ratios for the three capacities are assumed to be 0.7, 0.9, and 0.98, respectively.

    a) What is the average access time ta in terms of t1 = 20ns in the three cache designs?
    (Note that t1 is the time from CPU to M1 and t2 is that from CPU to M2, not from M1 to
    M2).
    b) Express the average byte cost of the entire memory hierarchy if c2 = $0.2/Kbyte.
    c) Compare the three memory designs and indicate the order of merit in terms of average
    costs and average access times, respectively. Choose the optimal design based on the
    product of average cost and average access time.

    a) ta = h1t1 + (1 – h1)h2t2 = ht1 + (1 – h)10t1 = (10 – 9h)t1

    If h = 0.7, then ta = 3.7t1 = 74 ns.


    If h = 0.9, then ta = 1.9t1 = 38 ns.
    If h = 0.98, then ta = 1.18t1 = 23.6 ns.

    b) The average byte cost is

    c ≈ (c1 s1 + c2 s2) / (s1 + s2) ≈ (20 c2 s1 + 4K c2) / (s1 + 4K) ≈ (20 x 0.2 s1 + 0.2 x 4K) / (s1
    + 4K) ≈ (4 s1 + 0.8K) / (s1 + 4K)

    For s1 = 64K, then c ≈ 0.26.


    For s1 = 128K, then c ≈ 0.32.
    For s1 = 256K, then c ≈ 0.43.

    c) For the three design choices, the product of average access time and average cost is
    19.24, 12.16, and 10.15, respectively. Therefore, the third option is the best choice.

    2|Page

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