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    pr10 D Flip-Flop

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    yagnesh
    This document discusses a D flip-flop circuit. It is a modification of an RS flip-flop that uses a single data input D rather than separate set and reset inputs. The D input is passed directly to the S input of the RS flip-flop, while its complement is passed to the R input. The output Q will only change state to match the D input when a clock pulse is received, preventing changes to D from immediately propagating to Q. The truth table and working of the D flip-flop are explained.

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    pr10 D Flip-Flop

    Uploaded by

    yagnesh
    24 views1 page
    This document discusses a D flip-flop circuit. It is a modification of an RS flip-flop that uses a single data input D rather than separate set and reset inputs. The D input is passed directly to the S input of the RS flip-flop, while its complement is passed to the R input. The output Q will only change state to match the D input when a clock pulse is received, preventing changes to D from immediately propagating to Q. The truth table and working of the D flip-flop are explained.

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    pr10 D flip-flop

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    This document discusses a D flip-flop circuit. It is a modification of an RS flip-flop that uses a single data input D rather than separate set and reset inputs. The D input is passed directly to the S input of the RS flip-flop, while its complement is passed to the R input. The output Q will only change state to match the D input when a clock pulse is received, preventing changes to D from immediately propagating to Q. The truth table and working of the D flip-flop are explained.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    24 views1 page

    pr10 D Flip-Flop

    Uploaded by

    yagnesh
    This document discusses a D flip-flop circuit. It is a modification of an RS flip-flop that uses a single data input D rather than separate set and reset inputs. The D input is passed directly to the S input of the RS flip-flop, while its complement is passed to the R input. The output Q will only change state to match the D input when a clock pulse is received, preventing changes to D from immediately propagating to Q. The truth table and working of the D flip-flop are explained.

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    2CE302: Digital Electronics

    Practical 10
    AIM: To study D Flip-Flop circuit.

    THEORY:

    The D flip-flop shown in below figure is a modification of the clocked RS flip-flop. NAND
    gates 1 and 2 from a basic flip-flop and gates 3 and 4 modify it into a clocked RS flip-flop.
    The D input goes directly to the S input, and its complement, through gate 5 is applied to the
    R input.
    D R
    3 Q
    1
    C lo c k
    Q '
    2
    S 4
    5

    Generation of two signals in RS flip-flop to drive it is a disadvantage in many applications.


    Furthermore the forbidden condition of both R=S=1 may occur inadvertently. This has led to
    change R-S Flip-Flop i.e. a Flip-Flop that needs only a single data input. This Flip-Flop is
    shown in figure. The truth-table of D Flip-Flop is as under:

    CLK D Qn+1
    0 X Qn (Last state)
    1 0 0(Reset)
    1 1 1(Set)

    This kind of Flip-Flop prevents the value of D from reaching the Q output until a clock
    occurs.

    In general D Flip-Flop is a bi-stable circuit whose D input is transferred to the output only
    after clock pulse is received.

    PROCEDURE:
    1. Connect circuit as per the circuit diagram.
    2. Switch ON the power supplies for any condition of D and analyze the condition of
    output Q as per truth-table.
    3. Set D=0 and apply clock pulse. Analyze the condition of output Q and verify with
    truth-table.
    4. Set D=1 and apply clock pulse. Analyze the condition of output Q and verify with
    truth-table.
    PRACTICAL FIGURE:

    CONCLUSION:

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