Design of FPGA-Controlled Power Electronics and

Drives Using MATLAB Simulink

Yam P. Siwakoti Graham E. Town

Department of Engineering Department of Engineering
Macquarie University, Macquarie University,
NSW-2109, Australia. NSW-2109, Australia.
[email protected] [email protected]

Abstract-We present a simple and rapid prototyping

HDLCoding
technique for Field Programmable Gate Array (FPGAs)-based
digital controllers for power electronics and motor drives using ,
I
MATLAB's Simulink and HDL Coder design software. The
Manual Coding
MATLAB/Simulink models are optimized and converted to
target independent, specific and traceable Very High Speed
Integrated Circuit Hardware Description Language (VHDL) HDL CoderlMatiab Coder
code for FPGA programming. An example implementation of the
Fig. 1. HDL Coding methods for FPGA Programming
space vector pulse width modulation (SVPWM) technique is
presented, illustrating the design of a generic 3-phase voltage
Simulink and optimizes the models to meet speed-area-power
source inverter (VSI). Simulation and co-simulation, system level
objectives for the FPGA.
design, and verification for rapid prototyping of FPGA-based
digital controllers will assist power electronics engineers and
The MATLAB environment provides two model-based
researchers to develop and prototypes in a relatively short time tools for rapid system development: i) Xilinx System
by eliminating tedious and time-consuming manual coding. This Generator and ii) HDL Coder. Either of these approaches
enables increased productivity and facilitates the development of provide an effective FPGA design flow when used
power electronic controllers with more complex control independently. However, (as pointed out in [3]) "some projects
algorithms. benefit from a mixture of approaches - a workflow that
combines the native Simulink workflow, device-independent or
Index Terms-FPGA, rapid prototyping, model based design,
device-specific code, and code readability offered by Simulink
digital control, power electronics and drives, SVPWM.
HDL coder, with the Xilinx FPGA-specific features and
optimizations offered by Xilinx System Generator." [3]
I. INTRODliCTION
Model-based design in MATLAB & Simulink environment
The design of modern power electronic circuits and for FPGA prototyping is very flexible and makes
systems requires knowledge from multiple discipline areas, implementation of control algorithms in FPGA for power
including digital control, to develop innovative and custom­ electronics and motor drives a lot faster with no need of special
designed products and solutions in a short period of time [I]. attention to internal connections in the device prototype. The
MATLAB & Simulink enable an alternative way to prototype is used to verify various modulation strategies,
automatically generate readable and portable IEEE standards­ control functions, and power flow regulation algorithms for
compliant HDL (i.e. IEEE 1076 compliant VHDL code and various tailor made power electronic design and motor control
IEEE 1364-2001 compliant Verilog code) from MATLAB, applications in minimum time. Thus, by using an FPGA-based
Simulink and Stateflow models for a variety of FPGAs. Fig. 1
shows the various ways to generate HDL from MATLAB &
Simulink.
Manual coding is tedious, time consuming and error prone.
On the other hand, automatic code generation lets designers to
make changes in the system level model, and produce an
updated HDL implementation in minutes by regenerating the
HDL code. Fig. 2 (from [2]) illustrates the comparison of o 20 40 60 80 100
Schedule time (%)
model-based design using HDL coder and manual coding.
Model-based design reduces the total project development time � Requirements Phase Functional Design � Detailed Design

by 33% as compared to manual coding. In addition, MATLAB � HDL Creation iii HDL Verification D Hardware Iteration

model-based design facilitates creation of FPGA-based II Final ASIC/FPGA Implementations

Fig. 2. Comparison of time spent on FPGA prototyping by MATLAB

prototypes and automates HDL code verification by co­
Simulink model-based design and direct manual HDL coding [2].
simulating it with

978-1-4799-0482-2/l3/$31.00 ©20l3 IEEE 571

controller, the designer is able to build a fully dedicated digital
MATLAB, Simulink, Stateflow, Algorithms and System Design
system that is perfectly adapted to the control algorithm being (with Fixed·Point Quantization Analysis)
implemented.
Simulink HDL Coder
Moreover, FPGA technology is now considered very useful
by an increasing number of designers in myriad fields of
application due to short implementation time, confidentiality of Built System Model in Simulink
2) Analyse and Optimise the System Design
the algorithm and architecture, capable to meet many (Speed, Power, Area)

constraints for space applications, and it can be adapted to any 3) Elaborate Design for FPGA/ASIC
4) Generate HOL from Simulink Model
change in design by dynamic reconfiguration [4]. Some of the 5) Verify HDL (Cosimulation/Hardware-in-the-Loop)

benefits of using FPGA for controlling of electrical systems

compared to counterpart DSPs and microcontrollers are made HDL (VHDl/Verilos)

clear in the same paper. Tn fact, FPGA-based digital controllers

FPGA ASIC
have been implemented with success in many different
applications, such as power converters (e.g. PWM control of Fig. 3. Method to generate HDL Code from MATLAB and Simulink, with
DC-DC converters) [5-6], point of load converter [7], pulse code verification.
width-modulated (PWM) inverters [8-9], resonant inverters
[10], power-factor correction [II], interleaved converters [12], difficult aspect of implementing an algorithm on an FPGA.
multilevel converters [13], multilevel and matrix converters The real HDL code generation process starts by modeling the
[14], fuzzy logic control of power converters and electrical algorithm in MATLAB Simulink using a HDL Coder library of
drives (e.g. induction machine drives) [15-16], synchronous more than 200 blocks (MATLAB keeps on updating and
machine drives [17], neural network control of induction adding new blocksets) or Stateflow. The components and
motors [16], and switched reluctance motor drives [18]. blockset supported in HDL Coder can be found by typing
However, FPGA prototyping and design remains a mystery hdllib in the command window. Fig. 3 shows the code
to many novice power electronics designers who do not have a conversion and verification process in MATLAB Simulink
basic knowledge of VHDL or Verilog coding. In the same HDL Coder.
context, even manual coding experts find it difficult to meet the Once the Simulink model is created, HDL Workflow
short implementation times, due to the time required for Advisor guides in a step-by-step process to generate code from
debugging, modification of the control algorithms, and the model. Moreover it helps to check various other parameters
reimplementation and testing of the prototype. Model-based and setting that is required for optimal code generation and
design on other hand has many advantages compared to verification.
manual coding and is easy even for novice designers using
Ill. IMPLEMENTATION OF MODEL BASED DESIGN
MATLAB and Simulink as an integral part of modern power
electronic and control system design. Tn brief, using the model­ The implementation of HDL Coder in power electronics
based design, system architects and designers can spend more and drives is demonstrated by implementing a SVPWM
time on fme tuning the algorithms; modify models, hardware & modulation technique in a 3-<1> VSI for generic applications.
software co-simulation for verifications, and experimentation SVPWM refers to a special way of determining the switching
and less time on learning and writing HDL code. sequence of the upper three power transistors of a 3-<1> VST. It
This paper aims to fill the gap between power electronics generates less harmonic in the output voltages and or currents
designers and FPGA-based controller implementation through in the windings of the motor load, possibility to optimize for
system level model-based design where resource optimization lower switching losses, provides more efficient use of DC
has been included. Automatic generation of HDL Code is supply voltage as compared to direct sinusoidal modulation
described briefly in Section II. SVPWM is implemented in technique (voltage utilization of SVPWM is 2/..J3 times the
Simulink using the HDL Coder toolbox and blocksets to sine wave) and compatible with the digital controller [19]. The
demonstrate and design a 3-<1> VST. Details of the design are circuit model of typical SVPWM modulated 3-<1> VST is shown
presented step-by-step and finally the code is verified using co­ in Fig. 4. Switches SI to S6 are six power switches controlled
simulation and full hardware implementation. by switching variables SWI, SW2, SW3, SW4, SW5, SW6
that shapes the 3-<1> output voltage.
TT. CODE CONVERSION: MATLAB ISIMlJLINK TO VHDL
CODE

HDL describes electronics circuits in terms of the circuit's

operation, design, and tests to verify its operation by means of
simulation. At the first step of code conversion process, the
Vdc
new design ideas and algorithms are represented in terms of
mathematical models and are tested in MATLAB/Simulink
floating point data types. However, implementation of control
algorithms in FPGAs and ASICs require fixed-point data type
conversion to reduce hardware resources. This conversion
process often introduces quantization errors. As a consequence,
a signal scaling and word-length optimization becomes a
Fig. 4. SVPWM controlled VSI

572
 D
ufix24 En24
T1
T1
Scope1

T1,T2,T0I2 �;2 4 En24

boolean
1
SW1
CD
,
SW2

t,= If-ls : t,= IOns ufix24 En24

TO/2 SW3

�:� boolean

SW4

SW5
boolean
CD
SW6
To

Fig. 5. Final SVPWM model in Matlab Simulink using HDL Coder ufix24 En24
to automatically generate HDL Code for FPGA prototype. Is

Free-Running

The upper and lower switch of same leg is complement to

each other to avoid shoot-through, which damages the
switches. A dead-time is nonnally generated to avoid gating
[VdVq] 2
= '3
[I
0
-1/2 -1/2
-13/2 - -13/2
[] V1�: (2)

overlap when nearly coincident transitions take place at the

upper and lower switch of same leg. This can be achieved abc-dq transformation is modelled in Matlab/Simulink as
either by implementing dead-time during FPGA programming, shown in Fig. 7. The bloksets are HDL Coder compliant with
or using a MOSFET driver with inbuilt dead-time. Nowadays, fixed point output. The word length for each block is shown in
MOSFET drivers come with inbuilt dead-time and fault the signal path. sfix12_En4 means the data is signed 12 bit
shutdown capability [20], so it reduces the programming word length with 4 bit fraction length and ufixlO_En8 means
complexity and resource requirements of FPGA the data is unsigned 10 bit word length with 8 bit fraction
implementations. length. The operators, constants and blocks support different
In SVPWM the reference voltage is mapped into switching data types and representation of data is transparent to designers
space vector diagram and the duty cycles of the switches are in each signal path. Details on how to convert floating to fixed
calculated based on the mapping. There are six active states point will be discussed in Section TV.
(VI, V2, V3, V4, V5 and V6) and two zero states (VO and V7)
B. Determine �4 and Angle (0.)
which combined in a various ways to generate the output
voltage. Fig. 6 shows the basic switching vector and sector of For small switching time period Ts, Vrej can be considered
SVPWM techniques. Fig. 5 shows the final MATLAB approximately constant and can be expressed as
Simulink multirate model of SVPWM algorithm that r� d2 + 2 ) V . �(V V
(3) =
q
automatically generates the HDL code for the FPGA prototype.
The sampling rate of the model before the rate transition block
is 1 flS, and IOns after the rate transition block, for a master
and, angle
a
=
tan -, (l VVdq J (4)

Fig. 8 shows the implementation of above mathematical

clock speed of 100MHz. The switching frequency of the
expression in fixed point simulink blocks. Ready to use
inverter is determined by:
f Master Clock Speed
Cartesian2Polar block in Simulink is not supported by HDL
= (I)
Coder, so the above equation to calculate instantaneous atan
2"
function is implemented in floating point s-function
Where, n-m-bit free counter. For example, if n=12,
1 MATLAB code and then converted to fixed point.
J;=100xIQ6/2 2=24.4lkHz. The details of the each blockset is
sfix12
described in the following sub-sections. U1
sfix12
A. Transformation of abc-dq Reference Frame U2

The voltage equations in the abc reference frame is Vd

transformed to the dq reference frame that consists of the sfix12

horizontal (d) and vertical (q) axes. The relation between these U3 Product5

two reference frames is C1

+ Vq

sin(4pi/3)
Fig. 7. Inside abc2dq transformation block.
V4(01l) �_����--'::'.L-� .•d
(-2/3,0) Vl(lOO)
(2/3,0) �
D
ufiX24 EnS . UfiX24 En12.,
m
Vref
Add Sqrt

V5(001) V6(101)
sfix24 En14

(-1/3,-1/V3) (1/3,-1/V3) '01 .J sfix24 En14

GD
"'sfi""2
' 4o.E
. 0 4 ---1-___
"" "" -----ne atan2JIXPI
'02
Fig. 6. Switching map of SVPWM for thee phase VSI
573 Cordie

Fig. 8. Determination of Vref and Angle (a)

C. Determine Switching Time Duration (Tib Tn I], To)
The instantaneous time duration of switching vector
(T",Tn+1,To) for six switches are calculated in terms of a
reference voltage (Vrer), angle (a) , switching time period (Tz),
input voltage (Vdc) and sector (n). For the volt-second balance
in sector-I, from Fig. 6,
-> -> ->

Tl V" T,V, + T,V, (5)

i
=

SO, ( cos
(6)
T
L I;�f rl �
co: : :
e h} J
� v,.J,lI ::: i)tJ � v �.T2 [ t)]
e
cost "3)
e
�

2 2

Tz =1; +T2 +To (7)

Solving §5, §6 and §7 we get,
v'3T/ lv,,! I . ff
sm(--a)
(8) Fig. 10. Determination of sector (n)
7;
Vdc 3

And v'3T/ Iv,.,! I smeal

. (9) Sector I: 0° Sas 600 Sector II: 600 Sa S 120° Sector III : 120° � as 1800
To- = T, T'l � T'l
vd,. 51 ....-+--+
.. ---,I-,--+T---I
51 51 i
1--f--'.-'--+-+-+--I-,., I--H-'--+---'-+_,., 1--
Hence, switching time duration in any sector n
.. =--- . -ff -a+-ff)=
fJJ�lv"1 I sm( ---
fJJ�lv"1 I sm\ Jr)cosa-cos ( � -Jr)sma
. (10) 53 :_+-1-+--+-+-,-
-,-_ :53 I I 53 I i

)
n-I

s
. )1
--L:-+_,.,S5
I
" v�. 3 3 · v�. 3 --+__,., 551--......
551--+--"'-'--+
vo Vl;V2; V7 i V7 V2! V< vo
_l-
:r -+h i I i I
. n-J . n-J
VO !V3!V4 V7 i V7 :V4:V3 vo
(
vo !V3 V2; V7 V7 ;V2 V3! VO
v"31�lv�f I. n-J fJJ�IV�f I
Tn+! = --- sln(a--;r)= --- -cosaSlll-JT+smaCOS-ff
(11)
v" 3 v'k 3 3 ) TO/2 n:12:To/2:TO/2 12:Tl:TO/2 TO/2;T2 n:To/2 TO/2:n T2:TO/2
Sector v: 2400 � a � 3000
TO/linin TO/2ITo/2 [ n [n TO/2
Sector VI : 3000 � a � 3600

And '0, Tl - (T" + T,al) (12) 1 T

T, T, T,
J
T, T,

1
51 51 51 i
=

Where, _�,fs-+ switching frequency of the VST

T1 - J:
53 -,--,- _ :
:_H-,--+-+
53 I-N S3 -i-ii
551--f--'.-'--+-+-,--I-,.,55 J L 55 i J i L
vo VS: V4: V7 i V7 V4:VS: vo vo ;vs V6: V7 V7 :V6 vs; vo VO iVl;V6 V7 i V7 iV6 i vl VO
Fig. 9 shows the implementation of above mathematical TO/2 T2iTliTO/2iTO/2 TliT2iTO/2 TO/2iTl T2:TO/2 TO/2:T2 Tl:TO/2 TO/2:T2:Tl TO/2!TO/2:Tl:T2 TO/2
expression for Tn,Tn+],To in fixed point Simulink blocks.
Fig. 11. Space Vector PWM switching patterns and corresponding switching
D. Determine the Sector (n) time at each sector.

It is necessary to determine the location of the reference

voltage (which is rotating at co = 2nf) to exactly generate the
instantaneous duty cycle of each switch and switching
U3
sequence. The sector determination is implemented with
compare to constant logic as shown in Fig. 10.
E. Determine the Switching Time of Each Power Switch
The switching pattern, sequence and time period of high
side switch is determined based on the location i.e. angle (a)
and magnitude of reference voltage (Vref) as shown in Fig. 11.
ufix24 En24
The switching pattern and time is implemented for high side
TA
switch TA as shown in Fig. 12. Similar implementation is for U4
TB and TC.

Fig. 12. Determination of the switching time of high side switch TA

IV. FPGA PROGRAMMING

A. Floating Point to Fixed Point Conversion

Fixed point algorithm is implemented in FPGA for power,
perfonnance and cost reasons. However, conversion from
floating point to fixed-point is very challenging and time­
Fig. 9. Determination of switching time duration (Tn,Tn+"Tll) consuming, typically demanding 25 to 50 % of the total design
and implementation time. In a fixed point domain a pair (w, F)
574 is considered for each of the parameter in algorithms, where W
is word length and F is fraction length of the parameters. Large
Vc
Wand F result in better performance and lower Bit Error Rate
(BER) but design consume large resources in FPGA or Vy

implementation requires expensive FPGA. On the other hand,

Vb
smaller Wand F result in large BER whereas smaller footprint.
Optimization of wordlength to achieve best performance is
an interactive process with the user in a MATLAB fixed point
advisor which guides through the steps of converting floating
point to fixed point algorithm. It also verifies the generated
fixed-point code by comparing the floating and fixed point
result. Multiple iterations by adjusting the word length
settings, individually modifYing the data types as desired or
accepting the 'proposedfixed-point types' as recommended by
fixed-point advisor are required to meet the desired accuracy Fig. 14. Co-simulation scenario using ModelSim
(low BER) and optimum fixed point design. Fig. 13 shows the
control signal of SVPWM generated by both floating and
fixed point design and the corresponding error. The peak
�Em-m: I I I I I I: I I I I : I I I : I I I I 1:1 I ciTT1
� II I I I I I: I I I I I I: I I I I: I I I : I I I I I :I I I I I I I
conversion error is ±1.5%. This error should be kept minimal
to utilise the full modulation range or the DC link voltage.
�I I [I � � i � [DJDdJ[[JJ�DDD[-100JOOci-DDJDrl
B. Code Conversion (from *. mdllslx and *. mfiles to VHDL) �h::rDD[bDJ[DOtOJ-[ 0:0 [DO --:00 [ 0 0 0 :- J n [ � � I
� I I I I I I: I I I I: I I I I I I
I I I I I
The HDL Workflow Advisor in HDL Coder automatically
I: I I: I I :I
�h::TI 1 1: 1 1:1 1 :11 :1 1 :::rr::m1
converts MATLAB code (*. m files), Simulink (*. mdllslx
files) from floating-point to fixed-point and generates
Time [ms]
o 0.5 1 1.5 2 2.5 3

synthesizable VHDL and Verilog code. MATLAB generates

thousands of lines of VHDL codes in separate files for each
blocksets. The generated code can be traced bidirectional
to/from MATLAB and Simulink model. The HDL Workflow
Advisor also highlights critical path timing in Simulink to help
identifY speed bottlenecks and improve the performance of the
design.
C. Verification ms
• III
0.00000
IIII
0.5 ms
IIII IIII
1 ms
IIII IIII
1.5
IIII
ms
IIII
2 ms
IIII IIII
2.S ms
IIII IIII
3 ms

1) HDL co-simulation: The HDL Coder generates VHDL b)

and Verilog test benches using HDL co-simulation wizard that Fig. 15. Co-simulation results of SVPWM a) MATLAB Simulink model with
b) Mentor Graphics ModelSim
automatically connects to the HDL simulator e.g. Cadence
Incisive, Mentor Graphics ModelSim and Questa for rapid
2) FPGA in-the-loop (FIL) co-simulation: FIL test the
verification of generated HDL code. Fig. 14 shows the co­
design in real hardware for the generated HDL code. It
simulation scenario using Mentor Graphics ModelSim
generates a Simulink FIL block as shown in Fig. 16 that
(student version).
represents the HDL code. The programming file is loaded onto
This co-simulation streamlines the verification process and
helps to fix the error before hardware implementation. Fig. 15 an FPGA with JTAG connection. TX/RX of data from
shows the co-simulation results of SVPWM MATLAB and Simulink to FPGA is via gigabit Ethernet crossover cable that
Simulink model with ModelSim RTL-Ievel models. The model co-simulate and verifies the design in real time environment. It
was simulated for 3ms and it was found that the two results are helps to detect, isolate, identify and resolve bugs in the early
exactly same. stages of design process.

SVPWM M�

0) Time [ms]
b)
S\lPWM_SimulinkMm

ce_out

sw1
c)
s'tO.

vy !l,; sw3

FIL sw4

sw5
vb
sw6
Fig. 13. SVPWM control signals generated for one cycle (50Hz) by SVPWMJIL SCq:€2
a) Floating-Point Design; b) Fixed-Point Design and c) corresponding
conversion % Error. 575 Fig. 16. FPGA in-the-loop co-simulation
D. VHDL to bitstream and FPGA programming
The generated HDL code is bit-true, cycle-accurate and
synthesizable HDL code which is free from bugs. HDL Coder Ch 1 Freq
12.52kHz
offers integration with Xilinx ISE design suite that makes it
easy to implement algorithm in MATLAB and Simulink to Ch2 Freq
12.S1kHZ
target Xilinx FPGAs. Xilinx ISE compiles and generates the
bitstream file which is then loaded into the FPGA using JTAG
via the USB connection by iMPACT or Digilent Adept
software. Table 1 shows the Xilinx ISE13.4 compilation report
of resources utilization for SVPWM implementation in
Spartan-6 XC6SLX45.

13sep 2012
V. EXPERIMENTAL RESULTS AND DISCUSSIONS i1�� 800. OOOI'S 14:33:41

a)
The FPGA based approach to the automatic generation of PreVu __ 0 ___[",-:...
) ����c='
VHDL code for digital controlled power electronics and drives � .. .. .. ........ . .. ................ .... · UfJfJ�;;��it;h g�t�;igJ1�i
using MATLAB Simulink is verified by implementing
SVPWM modulated VSI in a Xilinx Spartan-6 platform.
The six driving pulses from FPGA are connected to signal
:/
amplification and isolation circuit via 8 pin PMOD connector.
R-i .. ,-
The power ground and logic ground are completely isolated

DC·'
from one another using HCPL2531 optoisolator. It protects
FPGA from circulating ground current and high voltage spikes >d
T�2f1S
(15kV/flS). Fig. 17(a) shows the FPGA generated SVPWM
control pulses for the high side switches.
Six SPW47N60C3 Cool MOS power MOSFET with best Lower switch gate signal
�
R1JS(on) are used for better efficiency design. The TTL level M 4.00)JS A ell 1 I-10.OmV
Ch4 5.00 V
SVPWM signal from FPGA is amplified to meet the gate u-+"..... 194.84QJls
28 sep 2012
17:31:26

drive voltage requirement of the switch (±20V) by driver IC b)

IR2130 from International Rectifier. It is a three phase high Fig. 17. SVPWM gating pulse from Spartan-6 FPGA for high side switch
(Chl---7SWI. Ch2---7SW3. Ch3---7SW5. Ch4---7SW6)
voltage bridge driver IC with three independent high and low
side referenced output channels and has protection against
fault [20]. The IR2130 also provides dead-time control to
avoid any shoot-through to protect the switches. A dead-time
(Td) of 2fls is introduced between high and low side switch as
shown in Fig. 17(b). Too short dead time (Td<lflS) causes
shoot-through current that reduces system efficiency; too long
a dead time (Td>3flS) increases THD, negatively impacting the
power quality.
The three phase line-to-line voltage of the VSI before filter
is shown in Fig. 18(a) and Fig. 18(b) shows the filtered output
voltage of the inverter. Small filter inductor (1.5mH) and
capacitor (1.5flF) is required to filter out the switching
harmonics. The THD of output voltage is only 3.8% and Crest 16Jan 2013
Factor is 1.52, well below the IEEE allowable limits for grid 13:33:09

connected inverter design or for motor drives application. The

standby power loss is only 0.25% of rated power of the
inverter (lkW).
Chl Freq
Table I: Device utilization summary of Spartan-6 XC6SLX45 50.12 Hz

(Xilinx ISE13.4 estimated values)

Ch2 Freq
49.96 Hz
Logic Utilization Used Available Utilization

Number of Slice Registers 1521 54576 2%

Number of Slice LUTs 6117 27288 22%

Number of fully used LUT-FF pairs 1460 6178 23%

Number of bonded lOBs 10 218 4%

16Jan 2013
Number of BUFG/BUFGCTRLs I 16 6% 0....",. , 9.7600ms 14:10:23

b)
Number of DSP48Als 21 58 36%
Fig. 18. Three phase voltage out from the VSI without loading
Number used as Memory 3 6408 1% a) before filter. b) after filter (Measured with high voltage differential probe
576 GE8115 with attenuation of 1000:1. Chl-7VRy• Ch2-7VyB• Ch3-7VBR)
 --
1l]!i2l�!Hl!rn!m1ID) Scoing. Lne Filter- Tire
Integ: Reset
-----:--:--
'IQ«)(»WA..
[I][(l!l[I][I][(JiI[I1l[[!i AVG • Freq Filter- �r. �:m �� REFERENCES
(J':3
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using similar Matlab model based design as described in this [8] Diego Puyal, Luis A. Barragan, Jesus Acero, Jose M. Burdio and
paper. For example, power flow control, grid synchronization, Ignacio Millan, "An FPGA-based digital modulator for full-or half:
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variable speed drive (VSD), DC link voltage control etc.;
pp. 1479-1483, September 2006.
however, it requires AID or DIA converters for proper data
[9] Ying-Yu Tzou and Hau-Jean Hsu, "FPGA realization of space-vector
interface to FPGA and various peripheral sensors (e.g. voltage PWM control IC for three-phase PWM inverters", IEEE Trans. Power
(V), current (I) or angular speed (m) etc.). Electronics, vol. 12, no. 6, pp. 953-963, November 1997.
Fig. 19 shows the performance of the inverter during [10] J. Tian, G. Berger, T. Reimann, M. Scherf, J. Petzoldt, "Design and
loading condition. The inverter is loaded with a delta implementation of a FPGA-based controller for resonant inverters",
IEEE Trans. Power Electronics, vol. 12, pp. 953-963, November 1997.
connected resistive load of 300[2 in each phase. The load
[11] Angel de Castro, Pablo Zumel, Oscar Garcia, T. Riesgo and 1. Uceda,
voltage and current shows a good performance of the inverter
"Concurrent and simple digital control of an AC/DC converter with
under loading conditions as well power factor correction based on FPGA", IEEE Trans. Power
Electronics, vol. 18, no. I, pp. 334-343, January 2003.

VI. CONCLlISIONS [12] Oscar Garcia, Pablo Zumel Angel de Castro and Jose A. Cobos,
"Automotive DC-DC bidirectional converter made with many
We have described a method to facilitate the development interleaved buck stages", IEEE Trans. Power Electronics, vol. 21, no. 3,
and implementation of FPGA-based digital controllers in pp. 578-586, May 2006.

power electronic converters and drives. The method is faster [13] Oscar Lopez, Jacobo Alvarez, Jesus Doval-Gandoy, Francisco D.
and provides a greater degree of confidence than traditional Freijedo, Andres Nogueiras, Alfonso Logo and Carlos M. Penalver,
"Comparison of the FPGA implementation of two multilevel space
manual HDL coding. To illustrate the method a laboratory vector PWM algorithms", IEEE Trans. Industrial Electronics, vol. 55,
prototype of a 1kW FPGA-controlled Voltage Source Inverter no. 4, pp. 1537-1547, April 2008.
(YSI) was described in detail in which the fixed-point control [14] R. Erikson, S. Angkititrakul and K. Almazeedi, "A new family of
algorithm was automatically generated from Simulink models multilevel matrix converters for wind power applications: Final report",
using the MATLAB HDL Coder, and verified before NREL Report NRELlSR-500-40051, December 2006.

implementation on a Xilinx Spartan-6 XC6SLX45 board. [15] Marcian N. Cirstea and Andrei Dinu, "A VHDL holistic modeling
approach and FPGA implementation of a digital sensorless induction
Experimental characterization of the resulting YSI converter
motor control scheme", IEEE Trans. Industrial Electronics, vol. 54, no.
resulted in 3.8% total hannonic distortion and line-to-line 4, pp. 1853-1864, August 2007.
crest factor of 1.52, well within the allowable range of IEEE [16] Da Zhang and Hui Li, "A stochastic-based FPGA controller for an
standards. The very close agreement between experiment and induction motor drives with integrated neural network algorithms",
simulation shows the efficacy of the method. The method is IEEE Trans. Industrial Electronics, vol. 55, pp. 551-561, Feb. 2008.

expected to be particularly useful for prototype development [17] Mohamed Wissem Naouar, Ahmad Ammar Naassani, Eric Monmasson
and IIhem Slama-Belkhodja, "FPGA-based predictive current controller
of other power electronic converters and electric drives with
for synchronous machine speed drive", IEEE Transactions on Power
more complicated interfacing and control algorithms. Electronics, vol. 23, no. 4, pp. 2115-2126, July 2008.

[18] Frede Blaabjerg, Philip C. Kjaer, Peter Omand Rasmussen and Calum
ACKNOWLEDGEMENTS
Cossar, "Improved digital current control methods in switched
This work was supported by the Australian Research reluctance motor drives", IEEE Transactions on Power Electronics, vol.
14, no. 3, pp. 563-572, May 1999.
Council (ARC), Triquint Semiconductor Inc. USA, and
[19] Richard Zhang, "High performance power converter systems for
Macquarie University, Australia. The authors would like to
nonlinear and unbalanced load/source", PhD Thesis, Virginia
thank Yokogawa for the loan of a WTl800 power analyzer; Polytechnic Institute and State University, 17th Sept. 1998.
and Sudeshna Bhattacharya (Application Support Engineer, [20] International Rectifier, Data Sheet No. 60019 Rev. P, "IR21301IR2132
MathWorks) for model verification (FIL) and Daryl Ning 3-phase bridge driver", http://www.irfcom/product-
(Senior Application Engineer, MathWorks) for providing577 info/datasheetsl datalir213O.pdf

valuable comments and suggestions.