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    B.Tech II Year II Semester (R13) Regular & Supplementary Examinations May/June 2016

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    Abson Mulenga
    This document contains questions from a past exam on computer organization and architecture. It includes questions about: - Defining computer organization and architecture, and differences between high-level and machine-level languages. - Addressing modes, overflow detection, selective clear and mask operations, microinstruction formats, and levels of memory hierarchy. - Peripheral devices, hardware interlocks, and characteristics of multiprocessors. - Memory subsystem organization, instruction set architecture design issues, instruction cycles, and data/program control instructions. - Implementing register transfer statements, designing control units, and generating control signals. - Memory hierarchy characteristics, common memory technologies, and direct memory access controllers. -

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    B.Tech II Year II Semester (R13) Regular & Supplementary Examinations May/June 2016

    Uploaded by

    Abson Mulenga
    32 views1 page
    This document contains questions from a past exam on computer organization and architecture. It includes questions about: - Defining computer organization and architecture, and differences between high-level and machine-level languages. - Addressing modes, overflow detection, selective clear and mask operations, microinstruction formats, and levels of memory hierarchy. - Peripheral devices, hardware interlocks, and characteristics of multiprocessors. - Memory subsystem organization, instruction set architecture design issues, instruction cycles, and data/program control instructions. - Implementing register transfer statements, designing control units, and generating control signals. - Memory hierarchy characteristics, common memory technologies, and direct memory access controllers. -

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    R13 june 2016 CO QP

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    This document contains questions from a past exam on computer organization and architecture. It includes questions about: - Defining computer organization and architecture, and differences between high-level and machine-level languages. - Addressing modes, overflow detection, selective clear and mask operations, microinstruction formats, and levels of memory hierarchy. - Peripheral devices, hardware interlocks, and characteristics of multiprocessors. - Memory subsystem organization, instruction set architecture design issues, instruction cycles, and data/program control instructions. - Implementing register transfer statements, designing control units, and generating control signals. - Memory hierarchy characteristics, common memory technologies, and direct memory access controllers. -

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    32 views1 page

    B.Tech II Year II Semester (R13) Regular & Supplementary Examinations May/June 2016

    Uploaded by

    Abson Mulenga
    This document contains questions from a past exam on computer organization and architecture. It includes questions about: - Defining computer organization and architecture, and differences between high-level and machine-level languages. - Addressing modes, overflow detection, selective clear and mask operations, microinstruction formats, and levels of memory hierarchy. - Peripheral devices, hardware interlocks, and characteristics of multiprocessors. - Memory subsystem organization, instruction set architecture design issues, instruction cycles, and data/program control instructions. - Implementing register transfer statements, designing control units, and generating control signals. - Memory hierarchy characteristics, common memory technologies, and direct memory access controllers. -

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    © All Rights Reserved
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    Download as pdf or txt
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    Code: 13A05401 R13


    B.Tech II Year II Semester (R13) Regular & Supplementary Examinations May/June 2016
    COMPUTER ORGANIZATION & ARCHITECTURE
    (Common to CSE and IT)
    Time: 3 hours Max. Marks: 70
    PART – A
    (Compulsory Question)
    *****
    1 Answer the following: (10 X 02 = 20 Marks)
    (a) Define the following terms.
    (i) Computer Organization. (ii) Computer Architecture.
    (b) Write any two differences between High level language and Machine level language.
    (c) What is Indirect addressing mode and Relative addressing mode?
    (d) What is an overflow? How does an overflow can be detected?
    (e) Define Selective clear and Mask Operations.
    (f) Draw the block diagram for microinstruction format.
    (g) What are the different levels of memory hierarchy in a computer?
    (h) What are the peripheral devices of a computer?
    (i) What is the purpose of hardware interlock in data dependency conflict?
    (j) Write the Characteristics of Multiprocessors.

    PART – B
    (Answer all five units, 5 X 10 = 50 Marks)
    UNIT – I

    P
    2 Explain about the Memory Subsystem Organization with neat diagrams.
    OR

    Q
    3 What are the Design issues of Instruction Set Architecture? Explain about the simple Instruction Set
    Architecture.

    5 (a)
    (b)
    P UNIT – II
    Draw and explain about the instruction cycle with flowchart.
    OR
    Discuss briefly about data transfer and data manipulation instructions.
    Write a note on program control instructions.
    UNIT – III
    6 (a) Show that the block diagram of the hardware that implements the following register transfer statement
    P:R2←R1.
    (b) Construct common bus system by using multiplexers.
    OR
    7 (a) What are the methods for designing a control unit? Design a circuit for hardwired control unit.
    (b) How controls signals are generated using micro-programmed control unit and explain with neat
    diagram?
    UNIT – IV
    8 (a) Analyze memory hierarchy in terms of speed, size and cost.
    (b) Illustrate the characteristics of some common memory technologies.
    OR
    9 What is the purpose of DMA? Draw the block diagram for DMA controller and explain about DMA
    transfer in a computer.
    UNIT – V
    10 What is parallel processing? How one can achieve Parallel processing with single CPU? Explain in
    detail.
    OR
    11 What are the different types of lnter-processor Arbitration Procedures? Explain in detail with neat
    diagrams.
    *****
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