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A general description of common-mode feedback in fully-differential

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Conference Paper · June 1990

DOI: 10.1109/ISCAS.1990.112716 · Source: IEEE Xplore

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 Analog Integrated Circuits and Signal Processing 4, 131-140 (1993)
© 1993 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

Control of the Common-Mode Component in CMOS Continuous-Time

Fully Differential Signal Processing

J.E DUQUE-CARRILLO
Department of Electronic and Electromechanical Engineering, University of Extremadura, (06071)Badajoz (Spain)

Received May 22, 1992; Revised November 13, 1992

Abstract. A general description of fully differential (FD) amplifiers with common-mode feedback (CMFB) net-
work is carried out in this article. The general requirements that any CMFB loop must satisfy allow us to deduce
three suitable figures of merit (linear interaction or conversion gain, relative performances and nonlinear inter-
action between the common-mode and differential-mode loops) in order to compare the different approaches. The
gain or transconductance, sensitivity to mismatching in the devices, and nonlinearity for every common-mode
(CM) signal detector block have been derived. By identifying all the input-output signal paths in a generic FD
amplifier with CMFB, the conversion signals are quantified. From the gain of the detector and the technique used
for injecting back the CM correction signal, the performances provided by the CMFB loops in regard to the
differential-mode counterpart are evaluated. From the CM signal detector nonlinearity, it is shown how the CM
loop impacts on the distortion (nonlinear interaction) on the amplifier. Finally, all the considerations are verified
by means of simulations, and the CMFB networks classified according to these figures of merit. A low-distortion
CMBF loop based on the current steering principle of injection is proposed as well.

1. Introduction been proposed which provides very high dc gain even

in submicron technologies. In regard to the continued
Higher integration levels and speeds of operation, along low supply voltage supported, one of the standard
with a decreased power consumption, are the most out- techniques to extend the dynamic range of analog blocks
standing profits obtained by the digital design from the is to use FD signal processing. A cancellation of even
continued and fast scaling of CMOS VLSI technologies. harmonics, even under the presence of the unavoidable
However, it impacts on the performance of analog mismatching in the devices, as well as the suppression
blocks in a very different way. A degradated output con- of all undesirable common-mode signals by the differ-
ductance, as well as a reduced dynamic range, are the ential circuitry, improves over one order of magnitude
most remarkable consequences of this scaling. The first the signal-to-noise in FD circuits with regard to the
one, which is due to channel length modulation in MOS single-ended counterparts. These undesirable signals
transistors, causes low figures of small-signal output can be generated either by analog blocks or analog and
resistance and hence, very low dc gains. The latter one digital blocks as in the case of mixed-mode circuits.
arises as a consequence of the more and more reduced From a design point of view, the only conceptual dif-
total supply voltage that, dictated by fabrication proc- ference between double- and single-ended signal proc-
esses, ICs can sustain. For that reason, analog blocks essing resides, indeed, in the extra feedback required
must now operate over a much higher portion of the to control the output common-mode component in FD
total power supply voltage, to maintain the same signal- amplifiers. This need arises from the fact that feedback
to-noise ratio as in technologies with higher channel around the amplifier just provides stabilization for the
lengths. In order to cancel the above effects, new tech- output differential-mode (DM) component, while the
niques are being incorporated by analog designers. common-mode (CM) is still operating in open-loop
Thus, very recently [1] a feedback cascode biasing has mode. The required control of the output amplifier CM
component must be provided by an additional internal
This work has been supported by C.I.C.Y.T. (Spain) under Grant feedback network which is known as common-mode
TIC-90-1059. feedback (CMFB) network. For that reason, an FD
132 Duque-Carrillo

amplifier may be considered as two merged amplifiers are verified by means of simulations in a case study,
for all practical purposes. In general, a CMFB network a ranking of CMFB networks is established, and a low-
must satisfy the following requirements: distortion CM loop based on the current steering prin-
ciple is proposed.
1. To set the output CM component at a preset dc
reference level (Vref) , which is usually where the
DM gain reaches a maximum value and/or the max- 2. Signal Paths in Fully Differential Amplifiers
imum symmetric voltage (or current) swing is
obtained FD amplifiers are commonly considered as merged
2. To process the CM component with a speed and amplifiers. The signal to be processed, which consists
accuracy similar to the ones which the DM com- of the DM component of two signals, is the input signal
ponent is processed by the FD amplifier of one amplifier. The second amplifier, which is part
3. To minimize the interaction of the processing of the of the CMFB network, must control the CM compon-
CM output component in the DM output compon- ent of the output signals. In order to satisfy the require-
ent, and vice versa ment 2, both amplifiers are usually merged at the very
Traditionally, not enough attention has been paid to front-end, in such a way that most of the signal paths
the design of CMFB networks for FD amplifiers. In are shared from the very beginning. Below, these
most textbooks and papers on analog IC design, DM amplifiers w i l l be termed as amp1 and amp2
feedback loops are studied much more deeply than their respectively.
CM counterparts. In them, it is a very common prac- Figure 1 illustrates a general block diagram of an
tice only to point out the need of controlling the CM FD amplifier with CM feedback [2]. The inputs in/+
behavior in FD amplifiers and show one of the pos- and in1- are the input terminals of the amplifier amp1.
sible ways to do it, for which most of the time an iden- In the feedback path, a CM signal detector appears.
tical CM loop structure is used and, of course, no prac- Ideally, the detector provides a voltage or current pro-
tical design consideration is given in regard to its very portional to the common-mode component of output
limited performance. Thus, a general treatment on signals Vo+ and Vo . In this case, it is assumed that its
CMFB loops would be very useful to compensate this output signal is a voltage Vs, yet, as we can observe
lack. Here, this task is tried. In particular, a general below, no substantial modification is introduced in the
description of a linearized FD amplifier with CMFB context of this work if the output of CM detector were
is made in Section 2. There, nonidealities have had to a current Is. Following the feedback path (figure 1),
be included in order to find out the different input- the output voltage (Vs) of the CM signal detector is
output signal paths, derive the expression of the effec- compared to the dc reference voltage Vrefto which the
tive gain associated to each of them and so, evaluate amplifier CM output component wants to be set. For
the linear interaction or conversion gains between the that reason both signals are applied to the input ter-
CM and DM loops. In Section 3, the gain or trans- minals (in2+ and in2- respectively) of the second
conductance, sensitivity to mismatching in the compon- amplifier amp2, which close the loop that provides the
ents, and nonlinearity are determined for every CM required stabilization in the output CM component. To
signal detector in CMOS technology. Furthermore it avoid conversion signal from output DM component to
is shown how the last parameter impacts on the total CM component, and vice versa, besides the only linear
harmonic distortion (THD) of the system, and as a con-
sequence, the excess of the distortion can be used to
vi+
measure the nonlinear interaction between CM and DM
amplifiers. All the possible ways of merging both vl- ~ ml-- MergedAmplifiers
amplifiers (loops), as well as the relative performance V~f ~ (ampl and amp2)
provided (gains and gain-bandwidths ratio) by each
strategy, are described in Section 4. These three
magnitudes constitute suitable figures of merit to com-
pare the different approaches existing to control the CM
component in FD amplifiers, because they indicate the Detector
degree of fulfillment of the requirements listed above
for any CMFB network. In Section 5, all considerations Fig. 1. Blockdiagram of an FD amplifier with CM feedback.
 Control of the Common-Mode Component in CMOS Signal Processing 133

dependence of Vs with the CM component, the paths course it tends to reduce the differential gain ADD. So,
from the inputs in2 + and i n 2 - to the outputs V+ and this loop can be called internal DM feedback loop, how-
Vo- must be identical. As can be observed below, the ever its gain LGDM = AsDADs is negligible with regard
comparison with the reference voltage is usually car- to LGcM. Note that other DM feedback (external) may
ried out in its own detector in current output CM signal exist around the amplifier. Figure 2 also shows the gain
detectors. Then, the secondary inputs (in2+ and in2-) paths which originate the conversion signal from CM
are also input terminals of the CM detector block. to DM, and vice versa. Their gains are (ALGcM =
In order to visualize all different signal paths ex- AcsAsD ) and (zXLGDM = ADsAsc), respectively.
isting in any FD amplifier, nonidealities must be in- By means of Mason's rule, the effective gains, which
chided. Thus, mismatchings in amplifiers amp1 and are denoted by an upper asterisk, can be derived by
amp2 are next considered. These mismatchings cause inspection from the flow graph of figure 2, resulting in
different gains from the inputs to the outputs Vo+ and
Vo- respectively. Moreover and from a general point , ADD(1 - L G c M ) + A D c A L G c M
ADD : D ~ ADD (2a)
of view, the small-signal output vs of CM detector can
be expressed as
, AcD(1-LGcM) + AccALGcM
Vs : OllVo,cm -k- Ol2Vo,dm -t- OL3V2o,dm (1)
ACD = D -~ ACD (2b)

where the first term, c~lVo,em, would be the only out- ADC(1--LGDM) + ADDALGDM
put if the CM signal detector were ideal, the term pro- ADC = D
portional to the DM output component, ~2Voam, arises
as a consequence of the unavoidable mismatches in the ADS
ADD ~ (2c)
CM sense components, and the last and nonlinear term,
a3~,dm, appears due to nonlinear/- V characteristic of
MOS transistors. Of course, other higher terms are in- , Acc( 1 -LGD M) + AcDALGDM
Acc = D
volved but in general, they can be considered as second-
order terms. ADs
To facilitate the calculations, a perfect linear (a3 = ~-- --AcD-'~CS ~. 0 (2d)
0) and nonmatched (a2 ¢ 0) CM signal detector
block will be firstly considered, and later, in the next where D = 1 - LGcM - LGDM. The approximations
section, the opposite case. The flow graph of figure 2 have been done taking into account the order of magni-
shows all the gain paths as well as the physical origin tude of the gains as a consequence of their physical
of them. We must realize that the coefficients oq and origin. Every loop in figure 2 has been assumed stable
O/2 are renamed Acs and ADs respectively in this and the sign of the gains included in their symbols.
linearized system. Also, the input and output amplifier Some remarkable conclusions can be deduced from
voltages have been represented by their respective CM the above set of expressions:
and DM components. Two different feedback loops can
be identified in figure 2. The loop between Vs and Vo,cm The effective open-loop DM gain ADD is nearly equal
is the CM loop and has a gain LGcM = AscAcs. The to ADD.
second loop affects the DM output component and of For typical values, the impact of CMFB loop on the
amplifier CMRR is not significant since CMRR* =
m~ A;D/A D ---- CMI .
However, mismatching on the CM detector can lead to
appreciable D M - C M conversion gain (ADc),
A mainly for high a2/oq and ADD values. Hence, we
denominate conversion-gain factor to the ratio a2/~a.

ADo(Asc)is the desired DM gain ofampl (amp2)

3. Common-Mode Signal Detectors in CMOS
ADc,Aco(Asp)arise from mismatchings in ampl (amp2) Technology
Acc is a consequence of a non-ideal bias current source in amp1
ADsdue to mismatching on CM detector
Ac~ is the gain of CM signal detector The CM signal detector most often used in CMOS tech-
nology are shown in Table 1. Their gain or transcon-
Fig. 2. Gain paths in FD amplifiers. ductance (cq = Acs), conversion signal (c~2 = ADS),
134 Duque-Carrillo

Table 1. CM signal detectors in CMOS technology.

CM DETECTOR PERFORMANCE OBSERVATIONS CM DETECTOR PERFORMANCE OBSERVATIONS

1. • Lthearity in itself 5.[51 • Transisto~ ~ t ia li-

• For practical IC n ~ ~ g i o a m voltage
RI R2
V ~ ~ ~ resistor values, controimd resistors
~ p l i i m r DM gaha is • R•, is proportional to
greatly reduced
• Amplifi~ n ~ d to be • Mobility modulatioa
buffered effects came a
nonlme~ co~ ffiei~at
~l = 1 • High D~ offset due to c~ [61
source follower~
• Oth~ buffers can be
&H Alo A3
~ e d to r e d ~ e the D~ 6. • V,¢ is the ~ f ~ e ~ e
offset voltage for the output
• Mi~atehthg b e t w e ~ CM eompoa~t
the p~sive ~sistors is • High noa-linearity
the dominant e~or th • Other imp
A Al~ 2I~ line~ terms exist
+ 1 ~r 313 ~, Vz
•T~-(v; +o )

1 I I
7,171 • Hood wa~conductam
~ = ~ ' ~ (2R + ~ ) a
c~
• Linearisy La ~gard to
• High DC offset ~o~, but oth~ now

~=~.~ • Highly n o n - l i n ~ CM
signal det~tor
lhaemt[~ exist

4[41 . Can r e d ~ e comide~-

bly the amplifier DM
819] • The~e c ~ f f ~ i m t s
gain thle to loading
eff~B for the CM part of I,l
and I a
. U n l ~ s otherwise indi-
• C h ~ k la-[a as a
cated, every tr~s~tor
r ~ i d ~ in its o ~ well ruction of v , ~
Butk modulation h ~
not b~ll comid~ed in
~s~ 0 the cakuistio~
Very ]hle~ stn/ct~e

and nonlinearity (cB) have been determined for each output signals can be chosen• To simplify the calcula-
configuration under the presence of local variations tions, now, a perfect matched (o~2 = 0) and nonlinear
(mismatches) between transistor magnitudes or com- (o~3 # 0) CM signal detector, along with a purely
ponents. Concretely, relative variations in threshold linear DM feedback around the amplifier (figure 3),
voltages (Vr) and transconductance parameters (3) are is studied. From these premises along with figure 3,
considered• Local VT variations come from different the following set of equations can be written:
charge quantities (oxide charge and depletion charge)
Vo,dm = hDDgVi,dm -- ADDfVo,dm + AsoVs (3a)
and nonuniform gate oxide thickness and substrate dop-
ing. Local/3 variations account for variations in carrier Vo,cm = ADcgVi,dm -- ADcfVo,dm + AscV S (3b)
mobility, aspect ratios (W/L), and gate oxide capaci-
YS = ZcsVo,cm "}- Ot3~oo,dm (3C)
tance per unit area as well. For transistors operating
in their triode region (high V6s - Vr values), mis- where g and f are the feedforward and feedback fac-
matches in/3 may be more important than the threshold tors respectively•
voltage counterparts, yet local VT variations can be the
dominant ones in transistors with low gate-source
voltage (saturation zone)• Usually, bias current mis-
matches are separately taken into account since they
also depend on the dc point [3]. All these variations FD amplifier VoAm

(A/3, AVT, and A/e) have been simultaneously consid- with CMFB Vo.cm

ered in the derivation of coefficients c¢ for each CM

signal detector. Second-order effects in MOS trans- Fig. 3. Block diagram to determine the impact of c~3 on THD.
istors, such as mobility reduction and channel length
modulation, have been neglected in the calculations. By solving the DM output signal Vo,dm from the
As a figure of merit that provides some idea about the above set of equations (3), and carrying out an analysis
impact of CM signal detector nonlinearity on the per- of distortion on it [10], the following distortions on the
formance of FD amplifiers, the THD of the differential second and third harmonic of Vo,dm result:
 Control of the Common-Mode Component in CMOS Signal Processing 135

1 °t3AsDAcL Table 2. Different modes to inject the CM correction signal in FD

HD2 ~ 2 LGcMLGoM, ex Vi (4a) amplifiers.
2 .d2 a2
1 Ot~ISD/tCL STRUCTURE PERFORMANCE OBSERVATIONS
HD 3 = V/2 (4b)
2 LG~MLG2M, ex A cu = GBWcu
A~M GBWD~
where ACL = g/f is the closed-loop gain, LGom,ex is
the gain of the DM feedback loop around the amplifier 1. Resistive source degeneration of
current mirro~
• g.=lSdV~-Vr).is t h e
transconduetance of
which equals to fAoo , and V/is the amplitude of the the D M amplifier
• Low g~=l~tffxV due to
input signal (vi,dm = V/COS wt). Needless to say, it is operation of M 1 in their
[~tAV resistive m o d e
ra~,er difficult to predict the harmonic distortions from • Very insufficient

(4) in an accurate way. However, as will be shown I I Acu( < <At~)

GBWc~ < <GBW~)
and
f
below, they are enough to provide a good idea about Vr v o+
• Configuration 5 (Table
D is used
the relative impact on the amplifier distortion caused
by the nonlinearity of different CMFB loops. 2, Currents injection • The same performance
can ea.~ily be achieved in
Vo+ :V~ CM and DM loops
4. Injection of the Common-Mode Correction Signal * C o n f i g u r a t i o ~ 6, 7, 8
(Table I) can be

Relying on the output magnitude proportional to Vo,cm

provided by the CM detector, different ways exist for 3. Current steering • May cattle instability in
injecting the CM correction signal into the amplifier, the CM Ic~p. C h ~ k

or in other words, different ways of merging amplifiers ~tAg~t

• Configurations 1,2,3,4
(Table I) along with a
amp1 and amp2 (figure 1). Each of them, along with gain stage are
appropriate for it
a particular sense circuit of table 1, will provide a gain • Configurations 6, 7
(Table I) can be also
and gain-bandwidth with a determined order of magni- appropriate with a
v~f al , v o , ~
tudes. Recall that for most of the applications, minimum suitable load

design specifications for CM loops usually are

LGcM ~ L G D M , ex (5a) 5. A Case Study
LGBWcM ~ LGBWDM, ex (5b)
In order to verify the above design considerations and
where LGcM and LGDM,ex were defined above, and trade-offs, a practical case study follows. To carry it out,
LGBWcM and LGBWDM,ex = fGBWDM,ex are the loop the CM output component of an FD amplifier has been
gain-bandwidth products of CM and external DM loops successively controlled by each CMFB network here
respectively. Note that low values of feedback factor presented, and then their simulated performances com-
f relax the requirements a bit of CM loop in order to pared with regard to the following figures of merit:
satisfy (5) since, as has been pointed out, this external effective conversion gain (A~gc) or linear interaction
feedback only affects the DM operation. between DM and CM loops, relative performance CM-
Table 2 illustrates the different possibilities of merg- to-DM (AcM/ADM), and harmonic distortion (THD) or
ing CM and DM amplifiers. Their relative perform- nonlinear interaction between DM and CM loops.
ances (CM to DM behavior) are also shown for each Figure 4 shows an FD high-performance folded-
strategy assuming that they are one-stage output com- cascode amplifier without CMFB. This amplifier was
pensated amplifiers. In regard to the resistive source designed to satisfy the following specifications: {At,
degeneration technique shown in table 2, the symbols GBW, SR, 49m} >-- {70 dB, 5 MHz, 8 V/#S, 70 deg}
grey and Rcm indicate the equivalent resistance seen with 6 pF and 5 V of load capacitances and total sup-
from the drain of common-drain transistors which ply voltage respectively. Obviously, these specifica-
degenerate the input and output branches of the cur- tions refer to amplifier DM behavior. According to (5)
rent mirrors respectively. So, it can be easily demon- every CM loop has been also designed trying to pro-
strated that they are given by the expressions: vide a gain and gain-bandwidth product roughly equal
R~e] = 213 Vrey- 2/3 Vr (6a) to the DM counterparts.
In order to characterize the effective conversion gain
g c 2 = 2~1 Vo,cm - 2/~1 V T (6b)
ADC, the mean value, standard deviation (a), and
which agrees with the coefficient ~l of the CM signal worst-case (WC) value have been obtained from Monte
detector 5 shown in table 1. Carlo analysis. Such analysis has been performed on
136 Duque-Carrillo

VDD and GBWcM. As a consequence of this slow and inac-

curate CM control, a very asymmetrical output swing
respect to the reference level Vref will be obtained,
which can lead to premature saturation of one of the
output nodes in some applications. As indicated in (2c),
the conversion-gain factor, in this case At3/4/3, along
with the gain ADD provides a theoretical worst-case
ADC value (WCtheo) of 17.9 dB. The discrepancy be-
tween WQheo and the simulated WC value (23.6 dB)
arises due to the loss of accuracy in the approximations
done in (2c) as a consequence of the very low gain in
S5 M 4 / / ~ ~M4:s this particular CMFB loop.

5.2. CM Control by Current Injection

Fig. 4. An FD folded-cascodeamplifier without CMFB.
75 trials with A/3 and AVT spreads of 1% and 5 mV The performance parameters of the amplifier when two
respectively. These parameters were randomly and un- injected currents act as controlling signal of the CM
correlately varied in all the transistors. Other 1% output component, are shown in table 4. To accomplish
relative variations between passive resistors were also more realistic comparison among the impacts on the
included where required. Observe that mismatches be- amplifier originated by CM loops, the dc currents in
tween bias currents have not been specifically intro- the folded-cascode amplifier were always kept constant.
duced, but they were automatically generated in the Thus, in CMFB networks based on the principle of the
simulations from the other kinds of local variations. injection of currents, before the injection, dc currents
With regard to the figures of merits AcM/ADMand were subtracted in order to maintain roughly the same
THD, perfect matched systems were assumed. All the VGs - VT voltage in amplifier transistors as with CM
simulated results have been obtained with SPICE in its loops based on different principles of operation. Com-
level 2, by using the process parameters of a standard paring it with the performance provided by resistive
CMOS technology with 2/zm feature size. Below, these source degeneration technique, it can be said that higher
results are shown along with the particular structures WCtheovalues of DM loops with CM loops based on
of the CMFB loops, which were connected to the current injection are obtained. Concretely, for the
folded-cascode amplifier of figure 4. CMFB structure 4.1, the resulting conversion-gain fac-
tor A/3/4/3 + AVT/VDSat aCCOUnts for the increase in
5.1. CM Control by Resistive Source Degeneration the simulated WC and provides a WCtheovalue of 32.7
Technique dB. This factor for networks 4.2 and 4.3 can be ap-
proximately rewritten as
Table 3 shows the folded-cascode amplifier perfor- AIa Al3 AVr
mance when its output CM component is controlled
8IB = 8# + 4VDSa------~t (7)
by degeneration of current mirrors with active resistors.
Indeed, the most remarkable lack of this very common which also demonstrates the higher sensitivity to mis-
technique resides on the low figures achieved for ACM matches in the components of these structures. However,
Table 3. Amplifierperformancewith CM controlby source degenerationof current mirrors.

Acu_ GBWcu THD

STRUCTURE A~ +IV,., @100Kltz
A~u GBW~u

III.1,
mean=ll.5 dB
ff=10.9 dB
0.08 0.025 %
WC=23.6 dB
 Control of the Common-Mode Component in CMOS Signal Processing 137

Table 4. Amplifier performance with CM control by current injection.

Acu_GBWcu THD
STRUCTURE A"~ ±IV,., @IOOKHz

IV.1.

@ ~ ' _ I

VDD mean=21.6 dB
~=8.9 dB 0.82 0.09 %
WC=35.3 dB

IV.2.

mean=7.2 dB
~=7.1 dB 0.83 0.04 %
WC=21.7 dB

IV.3. . V ~ ,v'om,IV~ ,
mean=5.5 dB
cJ=7.8 dB 0.95 0.01%
WC=18.5 dB

II~"I HI IH ["41

much more significant than the characterization of the linearity by using input devices with lower (W/L) ratios,
linear interaction ADC between CM and DM loops in however, their minimum ratios are dictated by the CM
FD amplifiers in terms of worst-case values, results, requirements.
indeed, in terms of their mean value and error distribu-
tions. As indicated by the Monte Carlo analysis, in spite 5. 3. CM Control by Current Steering
of file larger spreads between the best-case and the
theoretical worst-case ADc values in CMFB loops Table 5 illustrates the amplifier behavior when its CM
based on current injection, in practice, these spreads component is controlled by means of CMFB networks
are narrower than in resistive source degeneration based on the current steering principle. Loops 5.1 and
loops. This fact is a consequence of the higher numbers 5.2 incorporate the CM signal detector configuration
of transistors involved in the first ones. Thus, each 2 and 3 of Table 1 respectively. Just to avoid excessive
transistor has a minor impact on the performance of dc shifts, complementary structures of these CM signal
the whole circuit, and therefore, random parameter detectors were actually used in this particular case. As
deviations are averaged out. Concerning the ratio be- can be seen in Table 5, CM current steering loops pro-
tween gains and gain-bandwidths of both loops, cur- vide similar behavior to DM loops in terms of speed
rent injection technique provides a value close to one and accuracy, while the nonlinear behavior varies
as expected from the considerations of table 2. Finally, widely from a structure to another. Thus, a high ex-
the linearity of CMFB networks 4.2 and 4.3 (a3 ~ 0) cess of harmonic distortion is generated by the CMFB
originate a lower nonlinear interaction with the DM network 5.2 due to its high nonlinear coefficient, which
amplifier than structure 4.1. Loop 4.1 can improve its will be a common characteristic to every loop based
138 Duque-Carrillo

Table 5. Amplifier performance with CM control by current steering.

A cu _ GB Wcu THD
STRUCTURE A~
ADu GBWo~ +lVp.p @I00KHz

@
i Vo+ mean=8.2 dB
ts=l 1.1 dB 1.1 0.05 %
WC=21 dB

V.2,

v. q mean=20 dB
t~=9,5 dB 1.2 0.22 %
WC=33 dB

V.3.

mean=22.1 dB
~=9.6 dB 1.3 0.06 %
WC=36.2 dB

V.4.

mean=9.4 dB
~=8.5 dB 1.2 0.015 %
WC=23 dB

on the detection of the output CM component in the and therefore, rather similar standard deviation values
common-source node of a simple differential pair. The result when compared with the CMFB network 3.1.
optimization of its linearity is limited by the amplifier Again, very good agreements are achieved between the
output swing, ACM, and GBWcM required. CM loop figures of theoretical and statistical worst cases in every
5.4, which uses the CM detector 7, shows a better CM current steering loop.
nonlinear performance as could be expected from the
result of its analysis (Table 1). Regarding the figure of
merit ADC, it must be noted the wider spread achieved 5. 4. A Low-Distortion Current Steering CMFB Network
with the configuration 5.1, which, in spite of having
a high number of components in its CM detector, its Sometimes, a current mirror can be seen loading the
sensitivity (ct2) to local variations is mainly deter- differential gain stage in current steering CMFB net-
mined by the matching between the passive resistors, works [8], [11]. In such a way, one could think in
 Control of the Common-Mode Component in CMOS Signal Processing 139

imresting the increase in the CM loop gain to improve (configuration 4.3), and figure 5 showed superior per-
the linearity and, therefore, to reduce the nonlinear in- formance. They are based on current injection and cur-
teraction with the DM loop. However, the resulting con- rent steering principles and operate along with the CM
figurations are very prone to cause instability in the signal detectors 8 and 7 (table 1) respectively. On the
CM feedback loop as a consequence of the additional other hand, the more often used CM loops, which are
low-frequency pole introduced at the output node of the based on either resistive degeneration of current mir-
current mirror load, and in general these CMFB net- rors or simple differential pair CM signal detector, pro-
works should be avoided. Based on this idea but over- vided very insufficient gain and bandwidth and high
coming the above drawback, a low-distortion current excess of distortion in the DM output component also
steering loop is proposed in figure 5. Here, a diode- respectively.
connected transistor loads the output node of the mirror,
and the pole introduced is placed at a frequency given
by gm/2Cgs where gm and Cgs are its transconductance Acknowledgment
and gate-source capacitance respectively. Now, two sec-
ondary poles appear in the CM loop. Relying on the This work has been supported by C.I.C.Y.T. (Spain)
minimum CM phase margin, the position of the addi- under Grant TIC-90-1059. The author would like to
tional pole can be optimized. Thus, for a minimum CM thank Dr. Sdnchez-Sinencio of Texas A&M University
phase margin equal to the folded-cascode amplifier for his encouragement and valuable discussions.
counterpart, THD was kept below 0.007% for a 2-Vp_p
100-kHz input signal. Of course, similar behavior in
terms of gain and bandwidth are achieved with the References
CMFB loop of figure 5 with respect to the DM loop.
1. E. Sackinger and W. Guggenbuhl, '~A high-swing, high-
impedance MOS cascodecircuits," IEEEJ. Solid-State Circuits,
Vol. 25, pp. 289-298, 1990.
2. J.E Duque-Carrillo and P. Van Peteghem, "A general descrip-
tion of common-modefeedbackin fully-differentialamplifers,"
Proc. 1EEE Int. Symp. Circuits and Systems, 1990, pp.
3209-3212.
3. K.R. Lakshmiknmar, R.A. Hadaway, and M.A. Copeland,
"Characterization and modelingof mismatch in MOS transistors
for precision analog design," IEEE J. Solid-State Circuits, Vol.
21, pp. 1057-1066, 1986.

#bias 4. M. Banu, "Common-modesignal detector," U.S. Patent 4 518

870, May 21, 1985.
5. T. Choi, R.T. Kaneshiro, R.W. Brodersen, P.R. Gray, W.B. Jett,
and M. Wilcox, "High-frequencyCMOS switched-capacitor
filters for communicationsapplication" IEEEJ. Solid-State Cir-
cuits, Vol. 18, pp. 652-664, 1983.
6. A. de la Plaza and P. Morion, "Power-supplyrejection in dif-
Fig. 5. Low-distortion CM current steering loop.
ferential switched-capacitorfilters," 1EEE J. Solid-State Circuits,
Vol. 19, pp. 912-918, 1984.
7. R.A. Whatly, "Fully differential operational amplifier with DC
6. Conclusions common-modefeedback;' U.S. Patent4 573 020, Feb. 25, 1986.
8. S.M. Mallya and J.H. Nevin, "Design procedures for a fully-
Fully differential signal processing is a more and more differential folded-cascodeCMOS operational amplifier" IEEE
J. Solid-State Circuits, Vol. 24, pp. 1737-1740, 1989.
used topic. In it, an extra feedback loop (CMFB net- 9. P.W. Li, M.J. Chin, P.R. Gray, and R. Castello, '~A ratio-
work), which must have necessarily a continuous-time independent algorithmic analog-to-digitalconversiontechnique,"
nature for high frequency applications, is required to IEEE J. Solid-State Circuits, Vol. 19, pp. 828-836, 1984.
"'tame" the output CM component of FD amplifiers. i0. D.O. Pederson and K. Mayaram,Analog Integrated Circuits for
Here, an overall sight has been tried to provide the dif- Communication, chap. 2, Boston, MA: Kluwer, 1991.
11. E. Sackinger, J. Goette, and W. Guggenbuhl, '~ general rela-
ferent existing approaches for such purpose. Suitable
tionship betweenampfifierparametersand its applicationto PSRR
figures of merit to compare them have been given and improvement," IEEE Trans. Circuits Systems, VoI. 38, pp.
used. As a result, CMFB networks illustrated in table 4 1173-1181, 1991.
140 Duque-Carrillo

J. Francisco I)uque-Carrillo received the M.Sc. in electronic physics

degree from the University of Seville, Seville, Spain, and the Doc-
tor in Physics degree from the University of Extremadura, Badajoz,
Spain, in 1979 and 1984, respectively. From 1986 and 1987 he ob-
tained a NATO Fellowship which allowed him to work as a visiting
scholar at the Electrical Engineering Department of Texas A&M
University, College Station. In 1988 he was working for AT&T
Microelectronic in Madrid, Spain, and Allentown, PA. Currently,
he is with the University of Extremadura as a professor. His research
interests focus on the area of analog integrated circuit design.

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