IMPLEMENTATION OF PAFL

CIRCUIT MODEL USING

SEQUENCIAL LOGICS
AGENDA

 INRODUCTION
 AIM
 OBJECTIVES
 EXISTING DESIGNS
 PROPOSED DESIGN CIRCUITS
 RESULTS AND DISCUSSION
 CONCLUSION
ABSTRACT

 The power specification of modern portable digital circuits is severely limited. It is

very essential to improve system power performance in the flip flop networks.
 Timing elements like flip-flops are very important for the performance of digital
systems. This is due to the extremely large set up time and hold time. These are also
essential for good performance and better efficiency.
 Our design aims to initiate a low power design with 4 bit proposed PAFL D-FF and
1 bit T-FF ensuring the correct design parameters.
 These parametric criteria would suggest the design of the Flip flop would be based
on the clock gating procedure to reduce the power associated with 1 bit flip flop
ensuring the reduced power in multiple bits.
 Our design improves more than 30% of power reduction when compared to existing
design.
INTRODUCTION

 POWER minimization has become a primary concern in VLSI design. Several

conventional techniques are utilized to curb dynamic and leakage power in conventional
CMOS circuits.
 One of the most effective methods is pipelining and subsequent voltage scaling to
minimize energy dissipation at a given operating frequency.
 At high operating frequencies, however, the energy and delay overhead of pipeline
registers becomes significant and degrades overall system efficiency.
 In systems with significant switching activity, charge recovery circuits have the potential to
dissipate less energy than their pipelined, voltage-scaled CMOS counterparts. Several
charge-recovery logic styles have been proposed [1]–[5].
 Over a range of relatively low operating frequencies (a few hundred megahertz), these
charge-recovery techniques have been shown to achieve lower energy dissipation when
compared to voltage-scaled CMOS
EXISITNG MODEL USING DCCER FF

Flip flops are the examples of sequential digital circuits.

Generally in digital circuits four phase transmission gate
(FPTG) flip-flops are used.
They are very similar to the transmission gate based flip-flops
that are used conventionally.
Here we have presented two new adiabatic flip-flops which are
more power and area efficient.
These flip-flops can recover energy from their clock input
capacitance which is the basic adiabatic principle. That means,
they have an energy recovery behavior. Their storage elements
and internal nodes are powered by constant power supply.
…CONTD

 By the clock network, a significant

amount of power is dissipated too. The
basic design style separates the whole
network responsible for clocking
scheme, from the other components of
the circuit. We use a different power
supply denoted as V(clk) for the
circuit responsible for clocking and it
is used for measuring clock network
dissipated power
….CONTD

The DCCER flip-flop has their operative mode namely precharge and evaluation. In precharge
phase clock is not used but small pull-up PMOS transistors MP1 and MP2 are made operative to
charge the prechage node .

The DCCER flip-flop uses a latch which is NAND gate based. It operates in Set/Reset latch
modes.

Here the conditional capturing process is obtained by using a feedback path. This feedback path
is achieved through the output Q and also through QB and extended to the c transistors MN3 and
MN4.

These are control transistors and they help to achieve the evaluation paths too. Generally, in
energy recovery logic the clock generator circuit provides the clock continuously even when the
input signal is static that means the logical circuit is in idle state.
OBJECTIVES PROPOSED

 To implement a 10T adder or Static Energy Recovery Full Dual-FF

 To implement 10 T Positive feedback adiabatic logic (PFAL) DUAL-FF
 Implementing a conditional model charge recovery circuit using CMOS 32nm
technology
 Implement hybrid D-FF for DSP logics modelling in 32 nm technology
IMPLEMENTATION D-FF

The current design on the Flip flop design would imparts

the different circuit elements with the gates specifically
pmos and nmos which results in estimating the design of
each cascaded section of the model represented in the
current figure.

The design would provide a D-FF condition with 4 bit

memory design on each circuit where the current
switching of the gates is controlled by the input 2 on the
D-flop main. Initially the input is switched on and its
customized outputs for each stage is changed with 0000 ,
0010, 0100, and 1000
CIRCUIT 1

Similarly we have modelled and proposed the similarly

changed Dual-DFF to design a toggling model for each
values of out2 mentioned in the circuit. The purpose of
the in1 is provide stage by stage design control over the
output data ensuring the correct sequence of the data is
assured at each values of the input data given.
CIRCUIT 2

Here we have seen the current Dual-D ff design

with respect to 10 Transistor with 32 nanometer
technology at each design frame. The above
circuit aims to implement the D-FF with the two
circuits presenting the don’t care condition for the
logic design.
CIRCUIT 3

 The below circuit describes the control

is modelled with the input1 as shown
figure below. At each input values ie 0
or 1 would present a partial X values
observed at out1 resulting don’t care
condition using pull up or pull down
approach for the CMOS inverter.
 Since the PAFL circuit would provide
the design implementing the design
platform would estimate the output 0
at input 0 and clock 0 and X at clock 1.
Similarly for input 1 the clock 1 would
provide the outputs value as 1.
LAYOUTS DIAGRAM 1 and 2:
circuit1
Circuit2 90nm
32nm
 For various switching activities power dissipated by the clock and power dissipated by
the rest of the flip-flop have been estimated.
 It is clearly seen that power dissipated by the clock and power dissipation of the rest of
the circuit is less in case of sleep mode in SCCER and DCCER flip-flops as in case of
exisinting model.
 The proposed design model emhasizng a Dual D- FF with and without Don’t care
condition.
 This design has proven better results when compared with the design on the sleep mode
SCCER flip-flop has better performance. In active mode this design act as T-FF rather
than D-FF resulting better performance than DCCER flip-flop. The clock gating
scheme is implemented without any clock overload. This SCCER flip-flops can be used
in adiabatic clocking in digital systems as they have good power and delay
characteristics.