The 2018 Gan Power Electronics Roadmap: Journal of Physics D: Applied Physics

Journal of Physics D: Applied Physics
TOPICAL REVIEW • OPEN ACCESS Related content

- Gallium nitride vertical power devices on
The 2018 GaN power electronics roadmap foreign substrates: a review and outlook
Yuhao Zhang, Armin Dadgar and Tomás
Palacios
To cite this article: H Amano et al 2018 J. Phys. D: Appl. Phys. 51 163001
- Gate stack engineering for GaN lateral
power transistors
Shu Yang, Shenghou Liu, Cheng Liu et al.
- Prospects for the application of GaN

View the article online for updates and enhancements. power devices in hybrid electric vehicle
drive systems
Ming Su, Chingchi Chen and Siddharth
Rajan
Recent citations
- Monolithic integration of
enhancement/depletion-mode high
electron mobility transistors using
hydrogen plasma treatment
Ronghui Hao et al
- Simple wet-etching technology for GaN

using an electrodeless photo-assisted
electrochemical reaction with a luminous
array film as the UV source
Fumimasa Horikiri et al
- Monolithic integration of E/D-mode GaN

MIS-HEMTs on ultrathin-barrier
AlGaN/GaN heterostructure on Si
substrates
Sen Huang et al
This content was downloaded from IP address 103.78.165.178 on 04/09/2019 at 12:01

Journal of Physics D: Applied Physics
J. Phys. D: Appl. Phys. 51 (2018) 163001 (48pp) https://doi.org/10.1088/1361-6463/aaaf9d
Topical Review
The 2018 GaN power electronics roadmap

H Amano1, Y Baines2, E Beam3, Matteo Borga4 , T Bouchet2 ,
Paul R Chalker5 , M Charles2 , Kevin J Chen6 , Nadim Chowdhury7,
Rongming Chu8 , Carlo De Santi4 , Maria Merlyne De Souza9 ,
Stefaan Decoutere10 , L Di Cioccio2 , Bernd Eckardt11,
Takashi Egawa12,13 , P Fay14 , Joseph J Freedsman12 ,
L Guido15, Oliver Häberlen16 , Geoff Haynes17, Thomas Heckel11,
Dilini Hemakumara18, Peter Houston9, Jie Hu7,
Mengyuan Hua6 , Qingyun Huang19 , Alex Huang19 , Sheng Jiang9,
H Kawai20, Dan Kinzer21, Martin Kuball22 , Ashwani Kumar9,
Kean Boon Lee9 , Xu Li18, Denis Marcon10 , Martin März11,
R McCarthy23 , Gaudenzio Meneghesso4 , Matteo Meneghini4 ,
E Morvan2 , A Nakajima24 , E M S Narayanan9 , Stephen Oliver21,
Tomás Palacios7, Daniel Piedra7, M Plissonnier2, R Reddy23 , Min Sun7 ,
Iain Thayne18, A Torres2, Nicola Trivellin4 , V Unni9, Michael J Uren22 ,
Marleen Van Hove10 , David J Wallis25,26 , J Wang14 , J Xie3 ,
S Yagi20, Shu Yang27 , C Youtsey23 , Ruiyang Yu19 , Enrico Zanoni4 ,
Stefan Zeltner11 and Yuhao Zhang7
1
Nagoya University, Furo-cho, Chikusa-ku, Nagoya, 464-8601, Japan
2
CEA, LETI, L’Université Grenoble Alpes, Grenoble, France
3
Qorvo, Inc., Richardson, TX, United States of America
4
Department of Information Engineering, University of Padova, Padova, Italy
5
School of Engineering, University of Liverpool, Liverpool, United Kingdom
6
The Hong Kong University of Science and Technology, Hong Kong, People’s Republic of China
7
Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology,
Cambridge, MA, United States of America
8
HRL Laboratories, Malibu, CA, United States of America
9
Department of Electronic and Electrical Engineering, University of Sheffield, Mappin Street, Sheffield,
S1 3JD, United Kingdom
10
imec, Kapeldreef 75, 3001 Leuven, Belgium
11
Fraunhofer Institute for Integrated Systems and Device Technology, IISB, Schottkystr. 10, 91058
Erlangen, Germany
12
Research Center for Nano-Devices and Advanced Materials, Nagoya Institute of Technology, Nagoya
466 8555, Japan
13
Innovation Center for Multi-Business of Nitride Semiconductors, Nagoya Institute of Technology,
Nagoya 466 8555, Japan
14
Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN, United States of
America
15
Department of Electrical and Computer Engineering, Materials Science and Engineering,
Virginia Tech, Blacksburg, VA, United States of America
16
Infineon Technologies Austria AG, Siemensstraße 2, 9500 Villach, Austria
17
Inspirit Ventures, Ltd., Blandford Forum, United Kingdom
18
James Watt Nanofabrication Centre, University of Glasgow, Glasgow, United Kingdom
19
Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX,
United States of America
Original content from this work may be used under the terms
of the Creative Commons Attribution 3.0 licence. Any further
distribution of this work must maintain attribution to the author(s) and the title
of the work, journal citation and DOI.
1361-6463/18/163001+48$33.00 1 © 2018 IOP Publishing Ltd Printed in the UK
J. Phys. D: Appl. Phys. 51 (2018) 163001 Topical Review
20
Powdec KK 1-23-15 Wakagi-cho, Oyama City, Tochigi 323-0028, Japan
21
Navitas Semiconductor
22
Centre for Device Thermography and Reliability, University of Bristol, Bristol, United Kingdom
23
MicroLink Devices, Inc., Niles, IL, United States of America
24
National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan
25
Cambridge Centre for GaN, University of Cambridge, Cambridge, United Kingdom
26
Centre for High Frequency Engineering, University of Cardiff, Cardiff, United Kingdom
27
Zhejiang University, Hangzhou, People’s Republic of China
E-mail: [email protected] (Geoff Haynes) and [email protected]

(Maria Merlyne De Souza)
Received 16 October 2017, revised 12 February 2018

Accepted for publication 15 February 2018
Published 26 March 2018
Abstract
Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate
economic growth in a semiconductor industry that is silicon-based and currently faced with
diminishing returns of performance versus cost of investment. At a material level, its high
electric field strength and electron mobility have already shown tremendous potential for high
frequency communications and photonic applications. Advances in growth on commercially
viable large area substrates are now at the point where power conversion applications of GaN
are at the cusp of commercialisation. The future for building on the work described here in
ways driven by specific challenges emerging from entirely new markets and applications is
very exciting. This collection of GaN technology developments is therefore not itself a road
map but a valuable collection of global state-of-the-art GaN research that will inform the next
phase of the technology as market driven requirements evolve. First generation production
devices are igniting large new markets and applications that can only be achieved using the
advantages of higher speed, low specific resistivity and low saturation switching transistors.
Major investments are being made by industrial companies in a wide variety of markets
exploring the use of the technology in new circuit topologies, packaging solutions and system
architectures that are required to achieve and optimise the system advantages offered by GaN
transistors. It is this momentum that will drive priorities for the next stages of device research
gathered here.
Keywords: GaN, power circuits, GaN-on-Si
(Some figures may appear in colour only in the online journal)
Contents
Introduction 3
1. Manufacturing challenges of GaN-on-Si HEMTs in a 200 mm CMOS fab 4
2. Epitaxial lift-off of GaN and related materials for power device applications 6
3. GaN-on-Si 200 mm for power devices 8
4. Buffer design in GaN-on-Si power devices 10
5. Challenges in growth for GaN power electronics 12
6. Vertical GaN power devices 14
7. GaN insulated gate field-effect transistors 16
8. Reliability of GaN power devices: normally-on and normally-off 18
9. Plasma processing for GaN power electronic devices 21
10. Challenges to dielectric processing for E-mode GaN 23
11. Future applications, roadmap for GaN ICs 26
12. Potential of polarisation super junction technology in gallium nitride 28
13. Technological challenges in next-generation GaN-based power integrated circuits 30
14. GaN CMOS: fact or fiction? 32
15. Assessing the limits of performance of p-type devices in GaN 34
2
16. 600 V E-mode GaN power transistor technology: achievements and challenges 36
17. Potential of GaN integrated cascode transistors 38
18. Converter topologies in GaN 40
19. Fast switching with GaN and dynamic on-resistance from application view-point 42
References 44
Introduction infrastructure to support autonomous driving will create

another massive parallel requirement for efficient compact
Merlyne De Souza1 and Geoff Haynes2 power conversion.
GaN has evolved to the point where the cost of the transis-
1
University of Sheffield, Sheffield, United Kingdom tor itself is no longer considered as the key driver in system
2
Inspirit Ventures, Ltd., Blandford Forum, United Kingdom cost. The novel solutions that the technology facilitates, pro-
vide savings in both manufacturing and running costs. Focus
Silicon-based insulated gate bipolar transistors (IGBTs) and will come to bear on manufacturing parts in volume that will
superjunction MOSFETs are fundamental components of pres- finally demonstrate the predicted price learning curves and
ent day power electronic systems for the conversion, control focus attention on those research avenues that provide the
and conditioning of electrical energy, from generation to the fastest route to manufacturing maturity.
point of load. If silicon devices were to be replaced by a more First generation production devices are now available
efficient semiconductor such as GaN, compact converters with from a broad range of suppliers including Transphorm, EPC,
ultra-high density could be designed only because the break- Panasonic, Infineon, GaN Systems, Dialog and Navitas. Each
down strength and electron mobility in GaN are respectively currently represents a different combination of process and
10× and 2–5× higher. These basic material properties trans- design technology but their existence, proven performance
late into smaller devices leading to higher frequency of opera- advantages over silicon devices; reliability and manufactur-
tion, lower switching losses, and reduction in the component ability are seeing them designed into emerging applications
count and size of passives. This was demonstrated by over 100 in potentially massive new market applications. Investment
hours testing by NREL of 2 kW GaN inverters designed by in the GaN supply industry by major global companies such
the Red Electrical Devils, winners of the Google Little Box as Google, BMW and Delta Electronics underline the impor-
Challenge in 2015. Compact modules translate directly into tance of GaN devices to the automotive, information technol-
lower weight, volume and cost. Coupled with increasing con- ogy and power supply industries. It is the focus of research
cern and government commitment to global warming, there are and development in the manufacturing value chain beyond the
now strong commercial and legal pressures to accelerate adop- transistor in these new systems that will have a very strong
tion of these advantages into production systems. effect in directing the next phase of the roadmap for GaN
Applications are now emerging that have no other prac- semiconductor device technology.
tical solution than GaN. Take for example the automotive This work brings together a palette of advanced research
industry: GaN is the semiconductor of choice for power con- into GaN process developments presented by global leaders
verters throughout vehicle electronics apart from the final in GaN process and device technology that will inform solu-
drive inverter. Even here, there is now a very strong push tions to challenges driven by the specific needs of converter
to create production devices capable of switching as much and system development. Emerging demands that will feed
as 100 A at 900 V. The advent of mass adoption of electric from this work are the need to achieve 900 V breakdown in
vehicles will in turn accelerate two other major markets that applications for local 3 phase grid interface and high-speed
depend on highly efficient high-density power converters. charging for vehicles, bi-directional switching, low induct-
Charging electric cars will require intelligent switching in ance high thermal efficiency packaging and the potential to
the local power distribution grid to manage local genera- include on-chip sensing and control.
tion and storage of electrical power in order to balance the We hope you enjoy this peek into an enticing perhaps all-
load presented to the distribution grid. Simultaneously, IT GaN future!
3
1. Manufacturing challenges of GaN-on-Si HEMTs hardware changes and lowering the robot speed of some
in a 200 mm CMOS fab handling systems, the thicker and heavier GaN-on-Si wafers
can be processed in the standard imec CMOS fab. The warp
Marleen Van Hove, Denis Marcon and Stefaan Decoutere specification of 50 µm is sufficiently low to avoid chucking
issues on electrostatic chucks. Prior to the fab introduction, the
imec, Kapeldreef 75, 3001 Leuven, Belgium
200 mm GaN-on-Si wafers are tested for mechanical robust-
ness, hereby reducing the wafer breakage during processing
Status. GaN is anticipated to be a next generation power
to less than 1%. After epitaxy, Ga and Al contamination on the
semiconductor. With a higher breakdown strength, faster
wafer backside is unavoidable. Since Ga is a p-type dopant for
switching speed, higher thermal conductivity and lower on-
Si, one of the major concerns of processing GaN wafers in a
resistance (Ron), power devices based on this wide-bandgap
CMOS fab is Ga cross-contamination. The Ga and Al backside
semiconductor material can significantly outperform the tra-
contamination after epitaxy is effectively removed by an in-
ditional Si-based power chips. As such, GaN-based power
house developed HF/H2O2-based cleaning procedure, hereby
devices will play a key role in the power conversion market
reducing the contamination level of the wafer backside and
within battery chargers, smartphones, computers, servers,
bevel to below 1011 at cm−2. Moreover, imec’s e-mode pGaN
automotive, lighting systems and photovoltaics.
process flow contains (Al)GaN dry etch steps. A first step to
In absence of viable low-cost GaN bulk substrates, GaN is
dry etch the pGaN layer selectively to the AlGaN barrier layer,
grown on a variety of substrates, the most popular being sap-
and a second to recess the AlGaN barrier in the ohmic contact
phire, silicon carbide (SiC) and silicon (Si). Si substrates have
areas. Since conventional F-containing cleaning recipes of the
become attractive for GaN growth because of their larger wafer
dry etch tools can form non-volatile GaFx species (i.e. GaFx is
diameter (200 mm and higher) though the large mismatch in
not volatile below 800 °C), a Cl2-based clean that forms vola-
lattice constant and coefficient of thermal expansion (CTE)
tile GaCl3 at ~200 °C is used. This cleaning procedure effec-
imposes epitaxy challenges, especially for larger Si substrate
tively and reproducibly maintains the Ga contamination level
sizes. Moreover, GaN devices are naturally normally-on or
in the dry etch tools well below the maximum allowed level.
depletion mode (d-mode) devices, whereas, to replace com-
Finally, since Au is a rapidly diffusing contaminant in Si
mercially available Si power devices, the GaN devices should
that deteriorates the minority carrier lifetime, the GaN metal-
be normally-off or enhancement-mode (e-mode) devices.
lization schemes need to be Au-free. Because of the high
Furthermore, GaN devices should be fabricated by a low-cost,
bandgap and the absence of explicit doping of the epilayers,
reproducible and reliable production process. While e-mode
especially the development of Au-free ohmic contacts is chal-
operation can be readily achieved by adding a p-doped GaN
lenging. By using a Si/Ti/Al/Ti/TiN ohmic metal scheme and
layer under the gate, hereby lifting the conduction band at
decreasing the alloy temperature to 565 °C, the ohmic con-
equilibrium and resulting in electron depletion, the ability to
tact resistance could be lowered to 0.3 Ω · mm with excellent
manufacture GaN-on-Si power devices in existing 200 mm Si
reproducibility and uniformity.
production facilities offers further cost competitiveness to the
Si power technology.
Initially, the development of GaN-based technology Advances in science and technology to meet chal-
focused on high voltage (200 V and 650 V) power-switching lenges. Because the breakdown field of the Si substrate is
applications. The first commercial 200 V e-mode GaN devices, ten times lower compared to GaN, the breakdown voltage of
fabricated on 150 mm Si substrates, were released in 2010 and the power devices is dictated by the GaN buffer thickness.
the first 650 V commercial devices followed in 2014 (fig- In figure 1 (right) the vertical buffer breakdown voltage (at
ure 1, left). After first developing the technology on 100 mm 1 µA mm−2 leakage) is plotted versus the buffer thickness.
[1, 2], and later 150 mm wafer sizes using Au-free metalli- Straightforward extension of the 3.2 µm-thick 200 V buffer
zation schemes [3], imec has been pioneering 200 mm GaN- (red) to 5.5 µm for 650 V applications (blue) was resulting
on-Si technology with first GaN 200 V epitaxy [4] and devices in low wafer yield: the yield related to wafer breakage in the
in 2014 [5–9]. The imec 200 mm GaN-on-Si e-mode transis- mechanical screening test was reduced from 90% for 200 V
tor and diode platform was recently extended and qualified to 77% for 650 V. This issue was tackled by implementing
for 650 V applications. Today, the focus is on the technology Si substrates with high boron doping (0.01 Ω · cm resistiv-
development for higher level of integration and for 1200 V ity), hereby increasing the mechanical wafer strength, and by
applications using 200 mm CTE-matched polycrystalline AlN developing a new buffer concept with reduced thickness (4.9
substrates. µm, green) that resulted in an equally high buffer breakdown
voltage while maintaining the low buffer dispersion, and
Current and future challenges. Because of the much higher increasing the wafer yield for 200 V applications to 99% and
CTE of GaN compared to Si, the GaN in-film stress during epi- to 97% for 650 V applications.
taxial growth needs to be tuned compressive to compensate for By optimization of the cleaning and dielectric deposition
the tensile stress during cool down. The use of 1.15 mm-thick conditions, together with the field plate design, state-of-the-
200 mm Si substrates is beneficial to reduce wafer warp during art 650 V 36 mm gatewidth power devices with 2.1 V thresh-
growth and hence avoiding wafer cracking. Without significant old voltage (at maximum transconductance), 13 Ω · mm Ron
4
Figure 1. (Left) Timeline for 200 V, 650 V and 1200 V GaN-on-Si epi wafers, prototype and commercial enhancement-mode power
devices. (Right) Buffer leakage at 25 °C of imec’s 200 V (red) and 650 V (blue and green) GaN-on-Si epi wafers after full processing in the
200 mm CMOS fab.
Figure 2. (a) Transfer and (b) output characteristics of a typical 36 mm gate width 650 V e-mode power device, and (c) the dynamic Ron
device dispersion. The devices were fabricated in imec’s 200 mm CMOS fab.
and 8 A output current (figures 2(a) and (b)) were obtained on Concluding remarks. GaN technology offers faster switch-
200 mm wafer size and processed in a standard CMOS wafer ing power devices with higher breakdown voltage and lower
fab. Moreover, the devices exhibit dynamic Ron dispersion on-resistance than Si, making it an ideal material for advanced
below 20% (10 µs on, 90 µs off) up to 650 V over the full power electronic components. For cost competitiveness, GaN
temperature range from 25 °C to 150 °C (figure 2(c)). power devices are preferably fabricated on large diameter Si
For 1200 V power applications, imec is working on using substrates in existing Si CMOS fabs. Due to the large mismatch
polycrystalline AlN (poly-AlN) substrates that have a better in lattice constant and thermal expansion coefficient, the epi-
CTE-match to GaN. In this approach, a thin crystalline Si taxy of GaN on large diameter Si substrates is very challeng-
layer is transferred to a 200 mm poly-AlN substrate. This new ing. Imec has demonstrated for the first time that is possible
technology is promising to go beyond the current technol- to manufacture 200 V and 650 V GaN-on-Si e-mode devices
ogy limitations, because it is possible to grow thicker, higher in a 200 mm CMOS fab. For 1200 V applications, it is pro-
quality GaN buffers on 200 mm substrates with a standard posed to transfer the technology to 200 mm Si-on-poly-AlN
thickness of 725 µm. Imec has already demonstrated the substrates, which is CTE-matched with GaN. This sub-
CMOS-compatibility of these substrates in terms of contami- strate technology allows for thicker GaN buffers, which is
nation and wafer handling [10]. Furthermore, first high quality needed to reach 1200 V and beyond, and was also assessed
transistors have been processed illustrating the high promise to be CMOS-compatible in terms of contamination and tool
of this new approach. handling.
5
2. Epitaxial lift-off of GaN and related materials

for power device applications (a)
P Fay1, J Wang1, L Guido2, J Xie3, E Beam3, R McCarthy4,

R Reddy4 and C Youtsey4
1
Department of Electrical Engineering, University of Notre
Dame, Notre Dame, IN, United States of America
2

Virginia Tech; Department of Electrical and Computer
Engineering, Materials Science and Engineering, Blacksburg,
VA, United States of America
3
Qorvo, Inc., Richardson, TX, United States of America
4
MicroLink Devices, Inc., Niles, IL, United States of America
Status. GaN and other III-N compound semiconductors have

had an enormous impact on optoelectronics—with the wide-
spread adoption of LEDs, lasers, and solar-blind photodetec-
tors—as well as RF electronics for both consumer wireless
infrastructure and military communications and sensing. The
continuing advance of III-N electronics promises to bring this
revolution also into the power electronics space. With power
device concepts based both on extensions of conventional lat-
eral FET designs, as well as concepts based on vertical transis-
tor designs, GaN and related materials promise to dramatically Figure 3. (a) Large-area (100 mm wafer) epitaxial lift-off of GaN-
enhance the performance, efficiency, and ubiquity of sophisti- based epitaxial device layers achieved using band-gap selective
cated power management and control functions. Advances in photoelectrochemical wet etching of an InGaN [17]; (b) single-die
release of a GaN-based device using dry etching of Nb2N with
growth and substrate technologies for achieving high-quality XeF2 [13]. (a) [17] John Wiley & Sons. © 2017 WILEY-VCH
material, along with improved device designs, promise to Verlag GmbH & Co. KGaA, Weinheim.
enable continued increases in device performance. In addition,
novel processing techniques are also promising to provide Current and future challenges. Advances in power electron-
significant performance, cost, and integration improvements. ics are poised to radically alter the design and implementation
Among these processing-related advances, techniques that of electronic products and systems; ultimately, sophisticated
enable epitaxial lift-off and substrate transfer are especially power electronics and circuit topologies for enhanced effi-
attractive. Epitaxial lift-off has been demonstrated for optoelec- ciency and power-control capability could become ubiqui-
tronic applications (see e.g. [11, 12]), and offers the potential tous if the key technological and economic challenges can be
for improved light extraction, a smaller device form factor, and solved. Realization of this vision is currently constrained by
ultimately more flexible displays as well as sensors for emerg- cost, device performance, and integration challenges—all of
ing applications such as wearables. In the power application which can be addressed by epitaxial lift-off. Due to the wide
space, epitaxial lift-off can enable substantial increases in ther- diversity of potential applications there is unlikely to be a single
mal performance (through improved heat removal), electrical optimal solution; instead, we can expect different approaches
performance (through lower resistive losses and higher break- to benefit different application segments. For example, for
down voltages), economics (through more efficient materials modest voltage and current requirements for which lateral
utilization, die size reduction, and substrate reclaim and reuse), devices (e.g. MISHEMTs) provide sufficient performance
and enhanced integrability with other electronics technologies. and economic benefit, use of conventional lattice-mismatched
A range of epitaxial lift-off technologies for GaN and related substrates such as SiC, sapphire, or Si is appropriate; epitaxial
materials have been demonstrated, including selective wet lift-off can then be used to accomplish substrate transfer for
etching of ZnO layers [12], dry etching of epitaxial Nb2N lay- improved thermal or breakdown performance (see e.g. [19]),
ers by XeF2 [13], mechanical exfoliation and separation using as well as the potential for reusing high-cost substrates (e.g.
graphene or BN layers [14, 15], and band gap selective pho- SiC) [13]. For applications where high currents and material-
toelectrochemical etching based on wet-chemical etching of limited breakdown voltages are required, as well as applica-
lower-band gap materials such as InGaN [11, 16–18]. In addi- tions where economics dictates a high areal current density,
tion to the mechanism by which the lift-off occurs, epitaxial vertical device structures offer inherent advantages. How-
lift-off processes may be distinguished by whether they lift off ever, these devices also place additional demands on material
a single device (figure 3(b)) or small circuit (e.g. [11, 13]), or quality; while high dislocation densities are often tolerable
seek to lift off a larger film (figure 3(a)) either for subsequent in optoelectronic and lateral electronic nitride devices, these
processing into devices (e.g. [12, 14, 15]) or after fabrication of defects significantly compromise the performance of vertical
the devices is largely complete (e.g. [17, 18]). devices. This can be addressed by homoepitaxial devices on
6
Advances in science and technology to meet challenges. To

(a) address the challenges and fully realize the benefits of epitax-
ial lift-off as an enabling technology for high-performance,
low-cost, ubiquitous power electronics, significant techno-
logical challenges must be overcome. For material-quality
sensitive applications such as vertical devices, additional
development of lattice-matched or pseudomorphic release
layers is an important future direction. Current demonstra-
tions have been based on the use of InGaN release lay-
ers [11, 16–18]; while this approach has been successfully
demonstrated for both single-die release and lift-off of large
areas (>100 mm wafer), the lateral etch rate is modest and
the surface morphology of the N-face GaN is not yet eas-
ily controlled due to limited etch rate selectivity. Addition-
ally, the use of pseudomorphic release layers such as InGaN
have been reported to influence the mechanical behaviour of
(b) GaN released structures [20]. Development of strain-control strat-
GaN
egies or deposition of alternative release layer materials with
basal plane lattices commensurate with the GaN devices are
areas for future development and exploration. Another area
InGaN that is largely unexplored to date is that of novel packag-
InGaN
ing and bonding strategies to leverage the unique features of
devices fabricated using epitaxial lift-off. The thermal per-
formance of ultra-thin devices has been projected [18], but
experimental validation and—in particular—optimization for
Figure 4. (a) Measured current–voltage characteristics of typical
GaN vertical PN junction diodes on prime bulk GaN substrate
the unique characteristics of ultra-thin devices is an area for
and on a reclaimed substrate (i.e. after growth, lift-off, repolish, additional development. Heterogeneous integration of lifted-
and a second device growth and fabrication sequence, validating off devices with conventional electronics, and packaging of
that device performance on epi-ready prime and reclaimed/reused lifted-off devices for emerging applications such as flexible
substrates is nearly indistinguishable. (b) TEM image showing or ultra-thin form factors is another area where substantial
pseudomorphic InGaN release layer growth. [17] John Wiley &
Sons. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
additional innovation is needed. Finally, the reliability of
lifted-off devices is an important topic, but one that has not
yet been addressed due to the nascence of the technology.
bulk GaN substrates, but this in turn places more stringent
demands on the epitaxial lift-off approach to avoid the genera-
Concluding remarks. Epitaxial lift-off is an emerging
tion of dislocations. The economic benefits of epitaxial lift-off
from bulk GaN substrates are substantial, given their high cost technology that is poised to be of significant benefit to the
and small diameter. In addition to substrate reuse, thermo- developing field of III-N based devices, and in particular to
electric modelling indicates that direct bonding of lifted-off high-performance, cost-effective power electronics. The
vertical FETs to a heatsink could enable die size reduction improvements in electrical and thermal performance, eco-
by more than 50% compared to devices on bulk GaN sub- nomic benefits derived from reduced die size and bulk GaN or
strates [18]. Of the current techniques, only band gap selective SiC substrate reuse, and potential for enhanced heterogeneous
photoelectrochemical etching with pseudomorphic InGaN integration with other electronics and packaging technologies
release layers has been demonstrated to maintain fully coher- makes epitaxial lift-off appear promising for advancing power
ent single-crystal material from the bulk substrate through the electronics across a broad range of applications.
device epitaxial layers, and so may provide a unique solution
to achieving epitaxial lift-off of vertical devices on bulk GaN Acknowledgments
substrates. Reuse of bulk GaN substrates after lift-off has
recently been demonstrated with lift-off of GaN pn junctions The authors wish to acknowledge GaN substrate repolish-
(figure 4) demonstrating a pathway to improved economics; ing performed by Sumitomo Electric. The authors wish to
future efforts will be needed to fully realize the thermal and acknowledge support from the U.S. ARPA-E, Isik Kizilyalli
integration benefits. and T Heidel, program managers.
7
3. GaN-on-Si 200 mm for power devices the depolarization effect for depleting the channel beneath
the gate. However, this design suffers from a compromise
L Di Cioccio, T Bouchet, M Charles, Y Baines, E Morvan, between the threshold voltage and the sheet resistance in the
A Torres and M Plissonnier channel and so high positive threshold voltages are difficult
to achieve. This is why at LETI we are developing an alterna-
CEA, LETI, L’Université Grenoble Alpes, Grenoble, France
tive strategy, the MOSCHEMT. This architecture is a hybrid
monolithic device which essentially puts a MOS channel and
Status. The main objective in the LETI [21] power elec-
a HEMT drift layer in series. At the heart of this technology is
tronic roadmap is the miniaturization of power converters to
the MOS gate, which needs to be reliable and robust; a chal-
increase the energy efficiency of the systems while reduc-
lenge that Si and SiC have already faced in the past.
ing the cost. It is also important to improve reliability and
ensure operation at higher temperatures (300 °C), with the
Advances in science and technology to meet these
markets of automotive (EV and HEV) and motor drives for
challenges. The advances required to meet the challenges
industrial tools being targeted. To achieve these objectives
listed above can be described in five bullet points:
for power convertors from a few watts to several hundred
kW, it is essential to increase their operating frequency [22]. Simulation: to design complex architectures, capture process
GaN-on-Si power devices are capable of responding to these influence and describe device behaviour, simulations such as
requirements because GaN allows high frequency switch- TCAD [25] are of major importance. Currently, significant
ing (several MHz) and a higher power density than silicon efforts are needed to ensure simulators properly recreate the
(10 times greater), although these solutions must be imple- physics of III-N materials and devices.
mented at the system level in order to fully benefit from
Device characterisation: the JEDEC standards are not suffi-
the materials properties. Furthermore, GaN on 200 mm Si
cient to fully qualify GaN-based power devices due to restric-
enables CMOS compatible technology leading to lower cost
tive criteria. Dynamic properties and aging effects, which
and improved robustness of the processes.
show common patterns with dielectric aging, are key topics to
LETI has chosen to develop MOS Channel HEMT
be understood in order to bring GaN-on-Si products to indus-
(MOSCHEMT) GaN architecture, fabricating ‘normally-off’
trial maturity in mass markets.
devices which give functionality similar to a classic silicon
based MOS. To take full advantage of these devices, a route Device technology: as discussed above, constant improve-
towards monolithic solutions for low and mid power applica- ments are required in the epitaxy, with in particular improved
tions and a route towards system in package are promoted at defect characterization and analysis of their impact on device
LETI, figure 5, with five main axes of work: epitaxy, devices, performance. The understanding of the gate oxide trap pas-
passives, co-integration, and system architectures. Here, we sivation will also be a significant scientific and technological
will focus on the device roadmap. challenge. The whole technology has to be CMOS compat-
ible, which brings an additional constraint to GaN power
device design, and the potential of GaN on 300 mm Si has to
Current and future challenges. Adoption of GaN in the
be investigated.
industry requires high performance, high reliability devices
produced at low cost. For automotive applications, GaN tran- Thermal dissipation: the reduction in size of power devices
sistors of 1200 V–50 A and 650 V–200 A are targeted. Current when using GaN raises the challenge of thermal dissipation.
requirements are a RonS below 1 mohm · cm2, figure 6, with In order to benefit from the full potential of GaN technology,
an Rdyn of no more than 10% of the RonS, meaning low losses the power density will need to be increased, and so process
[23]. The epitaxy is expected to improve in several ways: and packaging will need to be optimised to improve thermal
firstly, a constant improvement in the buffer layers and active dissipation.
layers to decrease the dislocation density, even though this has
Switching frequency: to allow high frequency switching, co-
not been proven to be essential for high quality HEMT perfor-
integration is key. Transistors, flyback diodes, rectifiers [26]
mance, and a reduction in point defects which cause trapping;
or drivers [27] are examples of active devices that can be mon-
secondly, a vertical leakage current lower than 1 µA mm−2 at
olithically integrated to reduce parasitic elements and reach
150 °C, and thirdly improvements and optimisations in the
high performance converters.
design of the epi stack, such as integration of back barriers to
improve confinement of the free carriers in the potential well.
Of course, all this has to be implemented while maintaining Concluding remarks. The use of GaN-on-Si as a substrate for
a wafer bow <50 µm for a silicon wafer thickness of 1 mm high power transistors is becoming an increasingly common
maximum to enable the process in standard 200 mm tools [24]. choice, as an affordable large area alternative to expensive
The most developed structure to make normally-off bulk substrates. Although there are still significant challenges
GaN HEMTs is pGaN gate architecture. P-type GaN may to be overcome in order to produce high quality devices on
have a potential work function of up to 7.5 eV which makes these substrates, GaN devices will take full advantage of
pGaN, in a sense, an outstanding gate metal in addition to both the remarkable properties of GaN, and of production in
8
Figure 5. Power systems roadmap at LETI. An SOC (system on chip) route towards monolithic solutions is important for miniaturization
for low and mid power solutions. For higher voltages, an ultra-compact power module is preferred [21].
Figure 6. Specific on resistance versus breakdown voltage. Benchmark of different laboratory results versus CMOS or non CMOS
compatible technology.
CMOS compatible fabrication plants to achieve high perfor- and encourage the use of this technology. With all of these
mance and low cost devices. advances, it will surely not be long before GaN-on-Si devices
Furthermore, the development of high power integrated become a huge market as the demand for highly energy effi-
circuits on GaN on silicon wafers will further reduce costs cient convertors becomes ever greater.
9
4. Buffer design in GaN-on-Si power devices preventing cracking and yielding a flat wafer. To aid growth
uniformity, thick Si substrates (1 mm) tend to be adopted,
Michael J Uren1, David J Wallis2,3 and Martin Kuball1 which also helps to reduce the wafer breakage during process-
1 ing which has been observed for standard thickness wafers
Centre for Device Thermography and Reliability, University
(675 µm). Total epi-layer thickness as large as 8 µm can be
of Bristol, United Kingdom
2 achieved, but the challenges of wafer bow and stress become
Cambridge Centre for GaN, University of Cambridge,
more difficult to overcome. Typical dislocation densities at the
United Kingdom
3 surface of the stack, i.e. at the 2DEG, are ≈109 cm−2.
Centre for High Frequency Engineering, University of
Due to the incorporation of impurities and point defects,
Cardiff, United Kingdom
as-grown GaN is typically n-type and it has been found that it
is essential to add deep level dopants to suppress leakage. The
Status. Uptake of GaN devices for power applications
dopant of choice is carbon [28] with a density well above 1018
requires that they can be manufactured in volume at compa-
cm−3 delivering excellent isolation and breakdown voltage.
rable cost to Si components, and with validated device reli-
Carbon primarily incorporates substitutionally on the nitro-
ability. The key innovation that has made this possible is the
gen site [32]. This pins the Fermi level about 0.9 eV above
ability to grow epitaxial device quality layers of GaN and
the valence band making the GaN:C p-type, with electrical
AlGaN on 6″ or 8″ (1 1 1) Si wafers. Together with the devel-
transport being via low mobility holes rather than electrons. It
opment of Si CMOS compatible device process flows, this has
is found that the carbon doping must be spaced away from the
allowed GaN power devices to be fabricated using existing Si
active 2DEG to reduce trapping effects [33]. A key issue with
fabrication lines with Si and GaN processing occurring in par-
carbon doping is current collapse (dynamic RON) [34]. Charge
allel. This section addresses the electrical and material design
trapping occurs in the epitaxial bulk during off-state operation
of the GaN-on-Si epitaxial platform that is now being used to
when there is high drain bias. When the device is switched
realise HEMT devices for power applications.
on, trapped negative charge reduces the electron density in the
GaN HEMTs were first successfully grown on Si in the
active channel and increases the on-resistance. Some current
1990s, however the epitaxy did not have sufficient break-
commercial devices show as much as a factor of two increase
down voltage for power applications. GaN-on-SiC RF devices
following off-state bias.
used Fe doping to suppress short-channel drain leakage and
increase drain breakdown, representing the first realiza-
Advances in science and technology to meet chal-
tion that the nominally insulating GaN layer underneath the
lenges. Suppression of current collapse is key for technol-
2DEG channel is actually electrically active and needs just as
ogy uptake. The p-type nature of GaN:C means that there is
much design and optimisation as the upper barrier and chan-
a p-n junction between the 2DEG channel and the bulk of the
nel region. However, Fe doping was found to deliver insuffi-
epitaxy, meaning that the bulk can be electrically floating.
cient breakdown voltage when applied to high voltage power
Suppression requires that this floating buffer is grounded to
devices. Eventually, it was found that a combination of a com-
the active 2DEG channel preventing it from providing a back
plex strain relief buffer together with carbon doping to con-
bias, and hence, counter-intuitively, a vertical leakage path is
trol breakdown could achieve sufficient voltage handling [28].
essential. Figure 8 shows an electrical network representation
Unfortunately, there continued to be bulk trapping related
of the buffer, and simulations to show the impact of differ-
issues collectively known as dynamic RON dispersion or cur
ent leakage paths [35]. It is found that there is a trade-off
rent collapse, and their solution has only recently been dem-
between vertical leakage and current-collapse, with careful
onstrated commercially. The reasons for the wide variation in
process control of leakage paths being absolutely required.
dynamic RON performance achieved for apparently identical
Current state-of-the-art power devices are able to achieve less
carbon doped epitaxies are only now becoming understood.
than 10% change in RON in the 25 °C–150 °C temperature
range by careful leakage control [36]. Recently it has been
Current and future challenges. Key issues in epitaxial growth shown that changing the stoichiometry of the Si3N4 surface
of GaN-on-Si are the lattice and thermal expansion coeffi- passivation can change the bulk vertical leakage and con-
cient mismatches which make strain management critical. As trol the dynamic RON [37]. Further work is still required to
a result, large numbers of defects (>1010 cm−2) are gener- achieve a guaranteed simultaneous optimisation of leakage
ated, and cracking of the GaN layers can occur on cooling and current collapse.
from the growth temperatures (≈1000 °C) [29]. The epitaxial Many power switching topologies require the series con-
layer structure which has been adopted to solve these issues nection of devices. Current technologies would require a
is shown in figure 7. A nucleation layer of AlN is universally hybrid packaging approach to prevent an undesirable Si
used to initiate growth and avoid the Ga/Si eutectic that causes substrate bias being applied to the upper transistor in a half-
‘melt-back’. This is followed by a strain relief stack, where bridge configuration. New approaches to allow transistor elec-
two successful approaches have been found based on either a trical isolation are therefore required before full integration is
step-graded AlGaN layer [30], or a superlattice of AlN/GaN feasible. One approach being investigated is the use of buried
[31]. The detailed stack design is normally proprietary. These oxide layers with 200 V isolation being achieved by imec.
buffers are used to induce compressive strain during growth Operating at voltages much above 650 V will require
which counteracts the tensile strain introduced on cooling, the growth of thicker epitaxy, and that requires a solution to
10
Figure 7. (a) Schematic cross-section of the typical epitaxial layer structure used for the manufacture of GaN-on-Si HEMTs. (b) TEM
image of a GaN/AlN superlattice buffer layer and (c) a step graded AlGaN buffer layer, both on Si substrates.
reducing stress. Although single crystal GaN or AlN would be

the ideal substrates, cost and wafer size make this unlikely to
have any impact. One possible approach is the use of thermal
expansion matched substrates as an alternative to Si wafers. For
example, polycrystalline AlN wafers have been successfully
used as a growth substrate, achieving 18 µm thick epitaxial
layers.
Concluding remarks. GaN-on-Si based power transistors

(a) are already achieving impressive performance and reliability
based on the remarkable ability to grow strain-engineered,
electrically-optimised, high-quality epitaxy on low cost 6″ or
8″ Si wafers. Buffer-related trapping leading to dynamic RON
has been a serious issue, requiring a delicate balance between
leakage and performance for its suppression. This is only now
being achieved by commercial suppliers. Going significantly
beyond the current 650 V market segment to much higher
voltages will require major changes and innovation in the
substrates and epitaxy to allow thicker epitaxial layers to be
grown yet still retaining control of wafer bow.
(b)
Figure 8. (a) Schematic showing leakage and capacitive paths within
Acknowledgments
the buffer. ① to ④ indicate some of the key locations where charge
accumulates. (b) Simulated dynamic RON for different leakage paths
within the buffer. All these different behaviours are observed in This work was funded by the UK EPSRC PowerGaN project
practice. © 2017 IEEE. Reprinted, with permission from [35]. K0114471/1.
11
5. Challenges in growth for GaN power electronics 150 Thickness of GaN/AlN SLS:
AlGaN
GaN 5.0 µm
Joseph J Freedsman1 and Takashi Egawa1,2
GaN/AlN SLS
1 120
Research Center for Nano-Devices and Advanced Materials, HT-AlGaN/AlN 4.0 µm
Nagoya Institute of Technology, Nagoya 466 8555, Japan Si(111) Sub.
Wafer bowing (µm)

2
Innovation Center for Multi-Business of Nitride
Semiconductors, Nagoya Institute of Technology, Nagoya 466 90
8555, Japan
2.5 µm
Status. GaN based devices are promising for many power 60
applications such as switching functions and inverters that 1.25 µm
can save a significant amount of energy. The performance
and efficiency of these GaN power devices greatly rely on 30 : Sample without AlGaN/GaN
the epitaxial growth of GaN and related alloys. High quality
GaN epitaxial growth can be achieved by using native free- : Full structure
standing GaN substrates. However, the downside of epitaxial 0
GaN-on-GaN is it is expensive and only small-diameter GaN 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
substrates. This in turn impede the mass production of GaN Thickness of epitaxial layer (µm)
power devices at an affordable cost for commercial applica-
tions. To overcome this, the heteroepitaxial growth of GaN Figure 9. Wafer bowing as a function of total epitaxial layer
thickness of AlGaN/GaN HEMT on Si. © 2012 IEEE. Reprinted,
is carried out on foreign substrates such as silicon carbide
with permission, from [42].
(SiC), sapphire and silicon (Si). From commercial aspects,
the heteroepitaxial growth of GaN-on-Si is attractive because
in the growth of high-quality and thick GaN-on-Si. The inset
of the large-size scalability of inexpensive Si substrates. Nev-
of figure 9 shows the cross-sectional structure of AlGaN/GaN
ertheless, the areas of concern are the large differences in the
HEMT on Si using metalorganic chemical vapour deposition
physical properties between wide bandgap GaN and Si sub-
(MOCVD). High temperature growth of GaN-on-Si could
strate that often results in poor crystal quality leading to high
likely result in melt-back etching of Si substrate caused by
dislocation density, pits and cracks for GaN-on-Si. Therefore,
Ga atoms [39]. As a result, deep pits, dislocations and cracks
appropriate epitaxial growth of GaN-on-Si and subsequent
could arise, which in turn would deteriorate the device perfor-
fabrication processes are absolutely necessary for power
mance like an increase in buffer leakage, and reduced break-
device applications. For example, several switching applica-
down [40]. Therefore, the growth of high-temperature-grown
tions require lateral GaN-on-Si high-electron-mobility tran-
AlN nucleation layer (NL) is indispensable to avoid both the
sistors (HEMTs) with high breakdown voltage (BV) [38]. To
melt-back etching and deep pits. Recent studies have revealed
realize these GaN-on-Si lateral devices, we have used the met-
the influence of AlN NL on the vertical breakdown charac-
alorganic chemical vapor deposition (MOCVD) grown thick-
teristics for GaN-on-Si and the AlN NL with better surface
AlN initial layer and GaN/AlN strained layer superlattice
morphology and lower O impurity were preferred to grow
(SLS) structures. The AlGaN/GaN HEMTs grown on 8-inch
highly resistive buffers [41]. Figure 9 illustrates the typical
silicon by using similar epitaxial growth technique delivered a
relationship between wafer bowing and total epitaxial thick-
high BV of 1.6 kV. For expanding the applications to electric
ness for the AlGaN/GaN HEMT on 4-inch Si. From this cor-
and hybrid vehicles, high performance GaN power devices are
relation, it could be understood that the use of GaN/AlN SLS
required to drive high-power motors, power modules such as
is effective in controlling the bowing [42]. Subsequently, the
DC-DC converter and inverters. Typically, in these applica-
growth of SLS is essential to control the wafer bowing for
tions high-voltage GaN-on-Si vertical devices with reduced
GaN-on-Si. Additionally, thick epi layers grown by using SLS
chip area are preferred. To facilitate the fabrication process
multipairs supressed the vertical leakage and showed a verti-
of such devices, we have successfully grown thick GaN-on-Si
cal breakdown field of 2.3 MV cm−1 [43]. A high lateral BVOff
vertical structures by using conductive buffer layers compris-
of 1.4 kV was also demonstrated for AlGaN/GaN HEMT on
ing of thin-AlN initial layer and SLS. The recent advances in
Si grown with the above recommendations [44]. The recent
the hetero epitaxial GaN-on-Si are encouraging for the growth
systematic investigations and the promising results as dis-
of GaN power electronics on larger diameter Si substrates.
cussed earlier would provide substantial understanding for
the growth dynamics of epitaxial GaN typically on 8-inch Si
Current and future challenges. Despite their merits, GaN- substrates. Indeed, our AlGaN/GaN HEMT on 8-inch Si has
on-Si power devices have also associated technical challenges shown a three-terminal off-state breakdown voltage 1650 V
which need attention. Of these, the most important issue is for the gate–drain distance of 50 µm. The availability of mod-
the growth of a high-quality and thick GaN-on-Si. The large ern MOCVD reactors with multi-wafer capability and evalu-
differences in lattice constants and thermal expansion coef- ation tools suggest promising features for GaN-on-Si lateral
ficient between GaN and Si are responsible for the difficulties power devices.
12
1019 the net Nd-Na in the drift region as a function of SiH4 flow rate
Sample A Sample B
for a GaN-on-Si grown with two SLS thicknesses. As shown,
n-GaN: 1 µm n-GaN: 1 µm
the Nd-Na could be controlled for GaN-on-Si by increasing the
GaN/AlN SLS GaN/AlN SLS
3 µm 0.5 µm SLS multipairs, which is due to the reduction of dislocation
1018 AlGaN/AlN AlGaN/AlN density. The conductive buffer layers including the AlGaN/
n+-Si(111) n+-Si(111)
AlN layers and SLS are indispensable for realizing GaN-on-
Nd-Na (cm -3)
2.3 µm-thick GaN/Sapphire Si vertical devices. Therefore, a Si-doped AlN NL as thin as

SD=1.4×108 cm-2
1017 3 nm was initially deposited followed by the deposition of Si-
ED=2.0×109 cm-2
doped AlGaN and SLS. This novel fully vertical GaN-on-Si
p-n diode comprises of doped buffer layers and not involve
1016
GaN/Si (Sample B) substrate removal technology. This GaN-on-Si p-n diode has
SD=1.4×109 cm-2 ohmic contacts on the p-GaN layer and a backside of n + -Si
GaN/Si (Sample A) ED=3.5×1010 cm-2
SD=1.5×109 cm-2 substrate that showed a turn-on voltage of 3.4 V and a break-
ED=8.8×109 cm-2 down voltage of 288 V for the 1.5 µm-thick n−-GaN drift
1015 layer [47]. The BV can be further improved by increasing the
0.1 1.0 10 buffer thickness and/or by using field plate structures. These
SiH4 flow rate (sccm)
improvements in the MOCVD growth of GaN-on-Si vertical
Figure 10. Net doping concentration as a function of SiH4 flow
structures suggest their potential role in power electronics in
rate for GaN-on-Si with different SLS thickness. For comparison, near future.
the data of GaN/sapphire are also shown. Reproduced from [47]. ©
2016 The Japan Society of Applied Physics. All rights reserved. Concluding remarks. GaN-on-Si power devices are emerging
Advances in science and technology to meet chal- to play a dominant role in the next-generation power electron-
lenges. GaN-on-GaN vertical devices are expected to play ics. Significant improvements in the hetero epitaxial growth
a vital role in future high-power conversion applications as and device fabrication are indispensable for the commercial-
it can reduce the overall chip area. However, GaN substrates ization of these power devices. For the epitaxial growth of
have disadvantages such as limited wafer size and being GaN-on-Si lateral devices, we have utilized the high temper
expensive. Therefore, the realization of GaN-on-Si vertical ature AlN NL to prevent the melt back etching of Ga into Si.
devices is the upcoming challenge owing to growth and fab- It was also found that the growth of SLS is essential to control
rication difficulties. Unlike the lateral AlGaN/GaN devices, the wafer bowing for GaN-on-Si. In addition, the growth of
a deeper understanding on the growth and fabrication of SLS multipairs effectively enhanced the breakdown voltage
GaN-on-Si vertical devices is required for potential power of GaN-on-Si HEMTs. On the other hand, fully-vertical GaN-
device applications. Some researchers have demonstrated on-Si p-n diodes were demonstrated by using conductive buf-
GaN-on-Si vertical p-n diodes fabricated by wafer bonding fer layers. We have used AlN NL as thin as 3 nm and SLS
and substrate removal technology [45]. This technique could multipairs, both highly doped in order to realize fully-vertical
complicate the fabrication process and eventually lead to GaN-on-Si p-n diodes. These advancements in the MOCVD
increase in cost. Others showed GaN p-n diodes by using a growth of GaN-on-Si and device fabrication processes will
quasi-vertical structure [46]. Irrespective of these methods, a lead to the high-performance power electronics.
detailed study is required for the growth of GaN-on-Si verti-
cal structures that should complement the fabrication as well. Acknowledgment
To realize such a GaN-on-Si vertical device, (i) the doping
density (Nd-Na) in the drift region must be controlled and (ii) The authors would like to thank the Super Cluster Program of
the buffer layer should be conductive. Figure 10 represents the Japan Science and Technology Agency.
13
6. Vertical GaN power devices
Yuhao Zhang, Jie Hu, Min Sun, Daniel Piedra,

Nadim Chowdhury and Tomás Palacios
Department of Electrical Engineering and Computer Science,

Massachusetts Institute of Technology, Cambridge, MA,
United States of America
Status. Central to improving the efficiency of power electron-

ics is the availability of low-cost, efficient and reliable power
switching devices. GaN-based devices are exciting candidates
for next-generation power electronics. Currently, both lateral
and vertical structures are considered for GaN power devices.
Vertical GaN power devices have attracted significant atten- Figure 11. Overview of the main device types and voltage classes
tion recently, due to the capability of achieving high break- for the vertical GaN power devices reported in recent years.
down voltage (BV) and current levels without enlarging the
chip size, the superior reliability gained by moving the peak of avalanche capability would greatly compromise the device
electric field away from the surface into bulk devices, and the robustness when operating in inductive switching environ
easier thermal management than lateral devices [48]. ments. Although the nature of avalanche breakdown is still
Since 2010, the field of vertical GaN power devices has not fully understood in GaN devices, a key factor is believed
grown exponentially and seen numerous demonstrations of to be good edge termination technologies and a way to remove
vertical diodes and transistors (figure 11). A 3.7 kV vertical holes from the structure. In SiC power devices, successful
GaN pn diode [49] and a 1.1 kV vertical GaN Schottky bar- edge termination technologies, such as junction termination
rier diode (SBD) [50] have recently showed near-theoretical extension and field rings, was enabled by selective p-type dop-
power figure of merit. Trench metal-insulator-semiconductor ing. However, in GaN devices, the current selective area dop-
barrier Schottky diodes [51] (figure 12(a)) and junction barrier ing or selective area epitaxial regrowth technologies cannot
Schottky diodes [52] (figure 12(b)) have also been proposed to yield material of sufficiently high quality to enable defect-free
combine the good forward characteristics of SBDs (e.g. low patterned lateral pn diodes. In particular, p-type implantation
turn-on voltage) and reverse characteristics of pn diodes (e.g. and activation in GaN is far from mature. With complicated
low leakage current and high BV). activation annealing schemes, the activation ratio for accep-
Several structures have been proposed for vertical GaN tors is typically below 5%, resulting in very low concentration
transistors, with the highest BV close to 2 kV. Current aperture and mobility for the activated free holes [52].
vertical electron transistor (CAVET) combines the high con- There remain some open questions on the selection of car-
ductivity of a two-dimensional electron gas (2DEG) channel at rier channels in vertical GaN transistors to improve the device
the AlGaN/GaN heterojunction and the improved field distri- forward characteristics. The ideal channel for these devices
bution of a vertical structure [53] (figure 12(c)). The CAVET would have normally-off configuration with high carrier mobil-
is intrinsically normally-on, but a trench semi-polar gate could ity and without the need for epitaxial re-growth. Further work is
allow for normally-off operation [54] (figure 12(d)). Vertical needed for all the three channels reported so far, 2DEG channel
GaN trench MOSFETs have no 2DEG channels, but do not [53], MOS inversion layer [55] and bulk fin channel [56].
need the regrowth of AlGaN/GaN structures and are intrinsi- The commercialization of vertical GaN power devices has
cally normally-off [55] (figure 12(e)). Recently, vertical fin been hindered by the high cost of bulk GaN substrates. The
MOSFETs have been demonstrated to achieve normally-off mainstream GaN substrates are 2-inch, while 4- and 6-inch
operation without the need for p-type GaN materials or epi- GaN substrates are available very recently in small vol-
taxial regrowth [56] (figure 12(f)). umes. The wafer cost (per area) for 2-inch GaN-on-GaN is
While most vertical devices utilize expensive GaN sub- $60–$100/cm2, still much higher than the cost for 4-inch SiC
strates, it is also feasible to make vertical GaN devices on (~$8/cm2) and 8-inch GaN-on-Si (~$1/cm2). The fundamen-
low-cost Si substrates. Quasi- and fully-vertical GaN-on-Si tal challenge is how to achieve the material quality associated
vertical diodes have been demonstrated with a BV over 500 with free-standing GaN substrates, while allowing the devices
V and excellent high-temperature performance [46]. These to be transferred to alternate substrates and have the GaN sub-
devices can enable 100-fold lower substrate and epitaxial cost strates re-used to reduce cost.
than GaN-on-GaN vertical devices.
Advances in science and technology to meet chal-
Current and future challenges. In spite of the great progress, lenges. Different technological solutions can be envisioned
the full potential of vertical GaN SBDs and transistors has to address the challenges in making patterned lateral pn junc-
not been exploited yet. The BV demonstrated in these devices, tions for edge termination structures. For example, compared
with no avalanche capability reported, is still much lower to p-type ion implantation, n-type ion implantation (e.g. Si, N,
than the avalanche BV in vertical GaN pn diodes. The lack etc) and activation is much easier. Lightly-doped p-GaN edge
14
been demonstrated in CAVET [53], although much more work

is needed to study the regrown interface quality and passivate
parasitic leakage currents.
In parallel, different electrical, mechanical and chemi-
cal techniques are under development to enable devices to
be lifted off from native GaN substrates and transferred to
low-cost substrates. Successful layer transfer technology,
combined with patterned interconnections on the supporting
substrate and re-use of GaN substrates, should greatly reduce
the cost and pave the way to commercialize high-performance
vertical GaN power devices.
Another approach that can fundamentally circumvent the
cost issue of vertical GaN devices is to fabricate them on Si
substrates, which could allow for almost 100-fold lower wafer
and epitaxial cost as well as 8-inch fabrication. Recently,
GaN-on-Si vertical pn diodes with blocking capability of
500–600 V have been demonstrated [46]. Fully-vertical GaN-
on-Si power devices have also been demonstrated by differ-
ent technologies, such as layer transfer, conductive buffer
layer, and selective removal of the substrate and buffer layer.
To improve the performance of these devices, advances in
epitaxial growth technology are needed to enable thicker
GaN layers with very low background carrier concentration
(<1016 cm−3) on Si substrate.
Concluding remarks. Vertical GaN devices are key to

achieve the high currents (>100 A) and voltages (>600 V)
required by many power applications, such as electric vehicles
and renewable energy processing. Record performance near
Figure 12. Schematic of representative vertical GaN advanced the theoretical Baliga figure of merit has been demonstrated in
Schottky barrier diodes and vertical GaN transistors: (a) trench vertical GaN pn diodes, although more work is needed in ver-
MIS barrier Schottky diode, (b) junction barrier Schottky diode, (c) tical Schottky barrier diodes and transistors. Exciting research
CAVET, (d) trench CAVET, (e) trench MOSFET and (f) vertical fin
MOSFET. In this figure, ‘Diel.’ stands for dielectrics, and ‘Sub.’ for
opportunities exist in the field, especially in making patterned
substrates. pn junctions, recycling GaN substrates and developing verti-
cal GaN devices on Si substrates.
terminations has been then demonstrated by implanting donors
to compensate highly-doped p-GaN layers in vertical GaN pn Acknowledgments
diodes [49]. Patterned pn junctions have also been reported by
n-type ion implantation into epitaxially grown p-GaN regions The authors gratefully acknowledge the funding support by
[52]. Besides selective ion implantation, patterned pn junc- the ARPA-E SWITCHES program monitored by Dr T Heidel
tions can be also made by selective p-GaN regrowth to fill and Dr I Kizilyalli, and by the ONR PECASE program moni-
n-GaN trenches. The initial feasibility of this approach has tored by Dr Paul Maki.
15
7. GaN insulated gate field-effect transistors
Kevin J Chen1, Mengyuan Hua1 and Shu Yang2

1
The Hong Kong University of Science and Technology,
Hong Kong, People’s Republic of China
2
Zhejiang University, Hangzhou, People’s Republic of China
Status. GaN-based insulated gate field-effect transistors with

an insulating gate dielectric provide many desirable proper-
ties such as suppressed gate leakage and large gate voltage
swing [57]. These devices are typically in the form of metal-
insulator-semiconductor HEMT (MIS-HEMT) or MIS-FET
with the insulating dielectric on a heterojunction (e.g. AlGaN/
GaN) channel or a GaN channel, respectively, as illustrated
in figures 13(a) and (b). The MIS-HEMT was first studied
for RF/microwave power amplifier applications [58], and
then intensively investigated as a promising power switching
device. The MIS-gate transistors are especially attractive to
high-frequency power switching applications because they
can better tolerate gate voltage over-shoot that often occurs in
circuits with high slew rate.
As is the case of Si- and SiC-based MOSFETs, the gate
dielectric in GaN insulated gate FETs is required to deliver
Figure 13. Schematic cross sections of GaN-based (a) MIS-HEMT
a dielectric/III-nitride interface with low trap density, high
and (b) MIS-FET. (c) Schematic process for in situ native oxide
reliability and long lifetime under various stresses (e.g. elec- removal and surface nitridation of GaN.
trical, thermal, humidity, etc). GaN MIS-HEMTs typically
exhibit depletion-mode (D-mode) operation with a large nega- biggest challenges to GaN MIS-HEMTs and MIS-FETs [62].
tive threshold voltage (Vth) because of the presence of high- With a wide bandgap in GaN, a large energy window is avail-
density positive polarization charges in the barrier layer (e.g. able to accommodate interface and bulk trap states at shal-
AlGaN). The D-mode MIS-HEMT, with its gate (input) termi- low and deep energy levels with short and long emission time
nal seldom forward biased during circuit operation, typically constant τit. The dynamic charging/discharging processes of
exhibits less adverse effects from the gate dielectric. This is these traps could lead to VTH instability during a switching
mainly due to the presence of the barrier layer that decou- operation, and consequently affect circuit and system stability.
ples the 2DEG channel from the interface/border traps in the Unlike Si on which highly uniform and highly reli-
dielectric as long as the ‘spill-over’ of electrons toward the able thermal oxide can be prepared using high-temperature
dielectric does not occur, leading to small Vth hysteresis. Very (800 °C–1200 °C) furnaces, GaN surface becomes unstable
good gate reliability [59] has been obtained in D-mode MIS- when the ambient temperature exceeds 800 °C. In addition,
HEMTs featuring a thin gate dielectric layer (SiO2, Si3N4 or the Ga–O bonds at an oxide/III-nitride interface fundamentally
high-κ dielectrics) under relatively small forward gate bias. induce high-density gap states, except in a few very specific
Enhancement-mode (E-mode) MIS-HEMTs and MIS- crystalline oxide configurations, according to a first-principles
FETs with a positive Vth are highly desirable from the cir- calculation study [63]. Thus, removing the detrimental Ga–O
cuit application point of view for their simpler gate control bonds at the GaN surface is a critical step for obtaining low
circuitry and fail-safe operation. To fully turn on the chan- interface trap density (Dit). If oxide-based gate dielectric is
nel current, however, large positive forward gate needs to be to be used for their high dielectric constant and large band-
applied. This is when the gate dielectric is under the most gap, a non-oxide (e.g. nitride-based) interfacial layer would
demanding operational conditions (e.g. high electric field, be highly desirable.
charge injection to the dielectric and carriers leaking through Although there are many reports on E-mode GaN MIS-
the dielectric). Vth-instability (both static and dynamic) at dif- HEMTs and MIS-FETs in research literature, the commer-
ferent temperatures and bias stress conditions, and its impact cialization of these devices has been hindered by concerns
on dynamic on-resistance (RON), needs to be systematically over the gate dielectric reliability. The commonly used gate
studied and clearly understood [60, 61]. The time-dependent dielectric (SiN, SiO2 and Al2O3) is deposited by PECVD
dielectric breakdown (TDDB) is the ultimate hurdle to over- or ALD (atomic layer deposition) at relatively low temper
come before commercialization of E-mode GaN-based MIS- ature (at 300 °C–400 °C). While the low temperature helps
HEMTs and MIS-FETs. maintain GaN surface morphology, it is also the main reason
for high-density defects in the dielectric, making it difficult
Current and future challenges. Trap states at the dielectric/ for these devices to pass reliability tests and qualifications.
III-nitride interface and inside the dielectric present the High-temperature annealing only shows a moderate effect
16
MIS-HEMTs and fully MIS-FETs have both been developed

with low on-resistance, high saturation current, small Vth hys-
teresis and low dynamic on-resistance. In particular, in situ
removal of native oxide and consequent nitridation by low-
power plasma (as illustrated in figure 13(c)) prior to dielectric
deposition [65] are important techniques for producing high-
quality dielectric/GaN interface by passivating the dangling
bonds while introducing minimum gap states.
To achieve high gate dielectric reliability under large posi-
tive gate bias required for E-mode insulated gate FETs, SiNx
deposited by LPCVD (low-pressure chemical vapor deposi-
tion) has emerged as a compelling candidate as it possesses
several important benefits including large conduction band
offset with GaN (ΔEc ~ 2.3 eV), relatively high dielectric
constant (κ ~ 7) and especially the long TDDB lifetime as
a result of the low defect density achieved at high deposition
temperature (e.g. 780 °C). Implementing the LPCVD-SiNx
gate dielectric in recessed-gate E-mode MIS-HEMTs and
MIS-FETs has been more challenging since an etched GaN
surface suffers more severe degradation than an as-grown
GaN surface at high temperatures. An effective approach
to suppress such a degradation while maintaining low Dit
(1011–1012 cm−2 eV−1) has been developed using a low-
temperature PECVD-SiNx thin film as an interfacial protec-
tion layer [66], as depicted in figure 14. For a 10-year lifetime,
Figure 14. (a) Schmematic cross section of an E-mode fully
the maximum gate bias is determined to be 11 V at a failure
recessed GaN MIS-FET with interfacial protection layer. (b) High-
resolution TEM of an LPCVD-SiNx/PECVD-SiNx/GaN interface. rate of 63.2% and 9.1 V at a failure rate of 0.01%.
(c) Time to breakdown (tBD) of the LPCVD-SiNx MIS-FETs with
interfacial protection layer at forward gate stress of 18, 17, 16 and Concluding remarks. There is strong demand for GaN insu-
15 V at 25 °C. (d) Weibull plot of the electric field-dependent tBD lated gate field-effect transistors with both depletion- and
distribution. (e) Lifetime prediction with a failure rate of 63.2% and
enhancement-mode operations, as the insulated gate provides
0.01%, respectively. (f) Weibull plot of the temperature-dependent
tBD distribution. strong immunity to control voltage spikes and could be driven
with circuits very similar to those used for the mainstream Si
on enhancing the dielectric reliability. Thus, it is of critical and SiC power MOSFETs. The most critical need of a GaN
importance to develop high-temperature gate dielectric films insulated gate FET technology is a gate dielectric technique
(e.g.~ 800 °C or above) with lower defect density and longer that simultaneously delivers low interface/bulk trap density
TDDB lifetime. The biggest challenge to high-temperature and robust reliability under stringent electrical and thermal
dielectric on GaN is the degradation (via decomposition or stresses. The E-mode GaN MIS-HEMTs and MIS-FETs are
chemical reaction) of GaN surface at high temperatures. A especially challenging as they operate under large positive
possible solution could feature a low-temperature interface gate bias and the recessed-etched GaN demands better protec-
protection layer and high-temperature gate dielectric. tions during high temperature processes associated with high-
quality dielectric deposition. Combining low-temperature
Advances in science and technology to meet challenges. The interfacial layer with high-temperature gate dielectric could
first D-mode GaN MIS-HEMT was demonstrated using be a promising pathway toward reliable and stable GaN insu-
PECVD-SiO2 as the gate dielectric [58]. With MOCVD-grown lated gate FETs.
in-situ SiNx as the gate dielectric, low Dit and excellent gate
reliability are obtained [59]. At 10 years, for a 100 ppm failure
rate, a Vgs_max of ~3.1 V is extracted, which is well above the Acknowledgments
operating Vgs for a D-mode MIS-HEMT (Vgs_max = 0 V).
The first E-mode GaN MIS-HEMT was demonstrated The authors thank Dr Fu, Dr Cai and Dr Zhang in Suzhou
using PECVD-SiNx deposited on fluorine-implanted AlGaN/ Institute of Nano-tech and Nano-bionics (SINANO), Chinese
GaN heterojunction [64]. Low-damage and well-controlled Academy of Sciences for valuable discussions and techni-
dry and digital etching techniques are being developed to cal support. This work is supported in part by Hong Kong
obtain positive threshold voltage. E-mode partially recessed Innovation Technology Fund under ITS/192/14FP.
17
8. Reliability of GaN power devices: normally-on AlGaN/GaN power Schottky diodes, breakdown involved
and normally-off first the dielectric at the diode edge and then the AlGaN; as
a consequence, lifetime improves by adopting either a thicker
Enrico Zanoni, Matteo Borga, Carlo De Santi, Matteo plasma-enhanced atomic layer deposition (PEALD) SiN
Meneghini, Nicola Trivellin, Gaudenzio Meneghesso edge-termination dielectric (from 15 nm to 25 nm) or a more
robust one (25 nm in situ SiN) [72]; (iii) drain–source off-state
Department of Information Engineering, University of Padova,
catastrophic breakdown of n-on Schottky gate HEMTs, may
Padova, Italy
occur as a consequence of hole trapping and accumulation
at the source edge of the gate: trapped positive charge shifts
Status. Reliability is essential for the application of GaN
threshold voltage towards negative values and turns on the
power devices to critical electronic systems, for high-voltage
device while a high drain voltage is applied, thus resulting in
energy conversion, control of electrical engines, automotive
device burn-out [73].
electronics [67]. GaN is a robust material, capable of with-
P-gate devices (either with an ohmic or a Schottky metal
standing extremely high electric field and temperature; in
contact on top of the p-layer) are currently the most popu-
order to fully exploit its potential, deep levels effects and fail-
lar choice for n-off devices. A critical mechanism for p-gate
ure mechanisms induced by high voltage and high temper
HEMTs is the TDDB consequent to the application of a posi-
ature stress must be known in detail.
tive gate bias (figure 15, left). In the case of a rectifying contact
Several technological options are available for the fab-
rication of GaN power high electron mobility transistors on p, positive bias leads to increased electric field, potentially
(HEMTs): Schottky-gate normally-off transistors, which leading to breakdown. Time to failure decreases at increas-
have the simplest structure, are prone to higher leakage cur ing gate leakage current and consequently at higher temper
rent with respect to their insulated-gate counterpart; neverthe- ature (Ea = 0.5 eV); times to failure are Weibull-distributed.
less they can reach breakdown voltages higher than 1100 V Higher Mg doping in the p-layer reduces leakage current
and can achieve normally-off operation in conjunction with and therefore improves lifetime (figure 15, right). A possible
a Si MOS driver in cascode configuration [68]. Normally-off explanation consists in the accumulation of positive charge at
devices can be achieved using p-type AlGaN or GaN with the interface with the AlGaN, proportional to leakage current
high acceptor doping on top of the AlGaN [69]. Recessed- which, at its turn, enhances gate current and promotes further
gate metal-insulator-semiconductor devices (MISHEMT) degradation. A second hypothesis implies the formation of a
enable operation at positive gate bias without measurable gate percolation path, consequent to defects formation due to hot
current IG [70]. Normally-off operation can be achieved by carriers (collected by the gate). In this case also, times to fail-
decreasing the thickness of the AlGaN layer under the gate in ure are Weibull-distributed; a 20-year lifetime at VGS = +7.2
a recessed structure. V was demonstrated for a 200 V n-off technology [69].
The different structures can be affected by specific failure The vertical drain-substrate stack also sustains a high elec-
mechanisms. When biased in off-state at high reverse bias, tric field and is prone to time-dependent breakdown: a 200 V
Schottky-gate, normally-on HEMT were subject to a signifi- n-off technology was submitted to tests at VD-substrate in excess
cant and progressive increase of gate leakage current (several of 700 V and failed due to vertical burnout in approximately
orders of magnitude), correlated with the onset of leakage cur 2 × 104 s (figure 16(a)). As shown in figure 16(b), higher leak-
rent paths which can be detected by electroluminescence (EL) age current and temperature correspond to a shorter lifetime,
[71]. Further analysis revealed that this catastrophic increase with a decrease which is thermally activated with a 0.25 eV
of IG was time dependent, that time to failure depended on the activation energy. The maximum applicable voltage for a life-
electric field, followed a Weibull distribution, and decreased time of 20 years with 1% failure rate is about 560 V at RT,
slightly with temperature (activation energy = 0.12 eV). IG considerably higher than the operating voltage [75].
increase was attribute to the formation of a conductive per- The GaN MISHEMT represents an ideal structure for
colation path across defects [72]. This concept of GaN as normally-off power GaN electron devices since the dielectric
a ‘lossy dielectric’ was a major breakthrough for GaN reli- layer reduces significantly the gate leakage; unfortunately the
ability: it allowed the extrapolation of device lifetime using MIS structure introduces new reliability problems, related
standard time-dependent dielectric breakdown (TDDB) tests, with the stability of device threshold voltage. Large positive
and promoted the study of other GaN time-dependent failure Vth shifts (positive bias temperature instabilities) have been
mechanisms, described in the following. observed under forward gate bias conditions and attributed
to accumulation of electrons at the dielectric/III-N inter-
Current and future challenges. Time dependent breakdown face where a second electron channel forms in the so-called
effects in Schottky gate devices were due to different physical ‘spill-over’ conditions [76]. According to [76], the density of
mechanisms either related to device design or materials qual- interface states of any dielectric is currently high enough to
ity: (i) in normally-on power Schottky HEMTs with double completely deplete the 2DEG channel with a typical electron
field-plate, TDDB was found to be due to the failure of the density in the order of 1013 cm−2. Improvements therefore
insulating SiN layer between the two-dimensional electron require either a reduction of interface states or an increase of
gas (2DEG) and the first field-plate edge. Increased robust- the voltage required to induce the ‘spill-over’.
ness was achieved by changing the substrate conductivity in Negative voltage shift (NBTI), observed when nega-
order to move the 2DEG edge towards the drain [68]; (ii) in tive voltage is applied to the gate is usually less severe,
18
Figure 15. (Left) Time-dependent breakdown experiment on the p-gate of a normally-off GaN HEMT. (Right) Dependence of time to failure
on initial gate leakage current at VG = 7.5 V (and consequently on p-type doping concentration in the p-GaN layer [74]). Reprinted from [74],
Copyright 2017, with permission from Elsevier.
Figure 16. (a) Time-dependent breakdown test on drain current at VDS = 800 V. Data refer to normally-off p-GaN gate devices at RT. (b)
Time to failure dependence on the initial leakage for three drain bias levels applied during the constant voltage stress [75]. © 2017 IEEE.
Reprinted, with permission from [9].
and becomes relevant only at high temperature (activation semi-on state, and this limits the electric field across the
energy 0.37 eV, see [70] and reference therein). According to SiN/AlGaN stack.
[70], NBTI is due to detrapping of states at the SiN/AlGaN
interface; authors in [77] have formulated a unified model Advances in science and technology to meet chal-
for positive bias temperature instability (PBTI) and NBTI, lenges. Schottky-gate and MISHEMT n-on devices for
which implies electron trapping/detrapping in pre-existing cascode configuration and p-gate n-off devices are gaining
oxide traps that form a defect band very close to the GaN/ maturity; time-dependent breakdown effects can be evalu-
insulator interface. NBTI can reduce the threshold voltage ated using standard, well-established testing methods; meth-
of n-off devices, thus thinning the safety margin in off-state. ods for long-term thermal stability assessment still have to
Conversely, NBTI does not represent a critical problem for be developed and consolidated into standards. Some issues
n-on devices: under cascode operation, the on/off state is remain, concerning gate leakage, hot electron degradation,
controlled by the Si MOSFET; moreover, due to the leakage instantaneous breakdown. Since the electric field plays a key
current of the Si MOSFET, the HEMT is always in slight role in the reported degradations and failures, it is important
19
to develop solutions in order to reduce its impact on the reli- stack consists in the removal of the silicon substrate removal,
ability issues. The regions/interfaces where the electric field which, however, involves some processing complications.
reaches its maximum value often represent the weakest point
of the device due to several effects: (i) the inverse piezoelectric Concluding remarks. This chapter has reviewed the
effect could bring to a catastrophic failure due to the lattice reliability of n-on and n-off GaN power HEMTs, with par
damage; (ii) hot electrons gain energy thanks to the high elec- ticular emphasis on time-dependent breakdown mechanisms
tric field in the pinch-off region; (iii) it has been shown that and NBTI/PBTI effects. The results described here have been
the p-gate failures are related to the electric field peak along obtained by means of on-wafer short-term (<100 h) tests.
the gate edge. Both preventing the building up of high electric Knowledge on the long-term reliability of these devices is
field and growing high quality materials that can withstand being developed only recently, thanks also to cooperative
the electrical stress are ways to improve the reliability of the projects such as POWERBASE and InRel-Npower, which
devices. The quality of the passivation layer has been shown promise to achieve full maturity for GaN power technologies
to be crucial to improve both the lifetime and the robustness, in the 650–1200 V range.
and the optimization of the materials quality is needed.
Also, the process is important and could be improved, since
the etching treatment could damage the passivation layer at Acknowledgments
the gate edge, exactly where the electric field peaks in a for-
ward gate bias condition. The work has been partially supported by Office of Naval
Concerning n-off MISHEMTs, stabilization of threshold Research project ONR N000141410647 ‘GaN HEMT reli-
voltage remains an open issue, which requires in-depth physi- ability physics: from failure mechanisms to testing methods,
cal characterization of surface and interface properties and of test structures and acceleration laws’, under the supervision
dielectric materials. of Dr Paul Maki. This project has received funding from the
Since one of the targets is to increase the operating voltage Electronic Component Systems for European Leadership
over 1000 V, it is important to focus on the drain-to-substrate Joint Undertaking under grant agreement POWERBASE
stack. In order to reduce the vertical leakage, the transition No. 662133. This Joint Undertaking received support from
layers must be optimized and engineered, avoiding the defects the European Union’s Horizon 2020 research and inno-
to behave like conductive paths between the silicon substrate vation programme and Austria, Belgium, Germany, Italy,
and the drain. It is worth noticing that these paths are the Netherlands, Norway, Slovakia, Spain, United Kingdom.
starting point which leads to the formation of the conductive This article reflects only the authors’ view and the JU is not
percolation path leading to a TDDB behavior. Nevertheless, responsible for any use that may be made of the informa-
electric field peaks within the structure can also lead to tion it contains. This research work was partly supported by
reliability issues; smoothing the electric field at the hetero- H2020 Project INREL-NPOWER, project ID: 720527. Work
interfaces will results in a higher breakdown voltage of the partially supported by the Italian Ministry of Foreign Affairs
vertical stack. In particular, it has been shown that this type of and International Cooperation, ‘Direzione Generale per la
failure occurs within the silicon (substrate), which is the mat Promozione del Sistema Paese’, through the Italy-Japan bilat-
erial with the lower breakdown field. A possible solution that eral project ‘MAGYGAN’ between the University of Padova
increases considerably the breakdown voltage of the vertical and Nagoya University (Professor Hiroshi Amano).
20
9. Plasma processing for GaN power electronic and reduced thermal budget (contact resistance of 0.5 Ohm
devices mm was achieved in [78] at a contact anneal temperature of
550 °C using a SiCl4-based chemistry). Driving down the
Xu Li, Dilini Hemakumara and Iain Thayne thermal budget to below 500 °C opens up new opportunities
for ‘gate first’ approaches to device realisation which may be
James Watt Nanofabrication Centre, University of Glasgow,
important in improving the stability of the gate/semiconductor
Glasgow, United Kingdom
interface.
Status. To significantly impact the marketplace of energy
Plasma processing in the gate–drain region. As described
efficient power switching, GaN-based transistors must be
in [79], passivation of the gate–drain region using low pres
produced in high volumes at low cost. Adopting silicon-
sure chemical vapour deposition (LPCVD) of SiNx with opti-
based substrates and silicon-like manufacturing approaches
mal conditions had a strong effect on both current collapse
enables production using legacy 150 mm and 200 mm wafer
and leakage currents. This is a high temperature (850 °C)
facilities driving cost efficiencies. Standard silicon manu-
process. A key property of the LPCVD-SiNx films in this
facturing approaches rely heavily on plasma processing for
study was the stress. Recently, the use of stress control in
etching semiconductors and deposition of dielectrics and
room temperature deposited inductively coupled plasma-
metals. These procedures need to be migrated to GaN-based
CVD (ICP-CVD) SiNx films for surface passivation was also
materials and optimised to minimise process induced damage
shown to reduce significantly leakage currents [80], therefore
of the semiconductor layers. These can present as reductions
a key challenge at this time is to understand the underlying
in channel carrier concentration and mobility and therefore
physical mechanisms that govern the leakage current and cur
increased on-resistance, as well as hysteretic effects due to
rent collapse phenomena.
the formation of charge trapping states which can influence
dynamic response.
Plasma processing in the gate stack. As mentioned above,
As shown in figure 17(a), there are three areas where
the incorporation of a gate dielectric is important to reduc-
plasma processing as part of device manufacture can have a
ing the gate leakage current in GaN transistors and allows
significant effect.
for a larger gate voltage swing, which is particularly impor-
1—in the source–drain regions, controlled etching into the tant for normally-off devices. As reported in [84], controlling
semiconductor to the same relative position compared to the properties of the GaN surface, in this case by removing
the device channel offers a generic solution as described a SiN capping layer deposited as the final stage of the wafer
in [78] irrespective of the thickness of the AlGaN barrier growth using an SF6 plasma etch immediately prior to atomic
layer of the device. layer deposition of an Al2O3, resulted in a 4× reduction in
2—in the gate–drain region, effective passivation of the semi- hysteresis to 60 mV for GaN MOS-capacitors. This work
conductor surface is vital to minimise leakage current also reported the impact of the introduction of TiN into the
and current collapse. A variety of dielectrics are being gate stack, which resulted in a 35% increase in accumulation
actively used and demonstrated encouraging performance capacitance. Understanding of the origin of these effects will
[79, 80] with further work required to fully understand the be vital to further device optimisation.
interaction between the dielectric and the semiconductor.
3—in the gate stack, a dielectric introduced between the gate Advances in science and technology to meet chal-
metal and the semiconductor (figure 17(b)) can suppress lenges. Understanding the role and impact of plasma-based
gate leakage current. Subjecting the semiconductor to a processing will be vital to further optimising and improving
fluorine plasma (figure 17(c)) has been shown to be effec- the efficiency of GaN power device operation in terms of static
tive in shifting positive the device threshold voltage [81], and dynamic on-resistance, current collapse, leakage currents
important for normally-off device operation. There can and threshold voltage control. Control of the semiconduc-
be issues with long term reliability of this approach how- tor surface, both mechanically and chemically, is a key. This
ever. An alternate is to perform a gate recess etch prior can best be addressed by understanding and correlating the
to gate dielectric and metal deposition (figure 17(d))— properties of the semiconductor surface and its interface with
controlling the etch depth to control threshold voltage dielectrics and/or metals with transistor performance. Com-
requires the use of low damage plasma based atomic bining plasma processing equipment so that an etched wafer
layer etching approaches, such as those described in can be transferred directly into a dielectric or metal deposition
[82]. Wafer scale and wafer to wafer uniformity of these tool is an important technological advance. This ‘clustered’
etching approaches still need to be confirmed. approach to wafer processing is relatively standard in the
mainstream silicon industry—research needs to be undertaken
Current and future challenges. to validate such approaches for GaN-based materials and
Plasma processing in the source–drain region. As devices for power electronics applications. A cluster tool such
reported in [77, 83], plasma etching of the semiconductor lay- as that shown in figure 18 is already proving highly insightful
ers in the source–drain region before contact metal deposi- in this regard. In addition to combined process chambers, the
tion results in reduced contact resistance (0.18 Ohm mm was cluster tool shown in figure 18 also has an in situ scanning
obtained in [83] using ‘patterned’ Cl2-based plasma etching), Auger capability. Clustered plasma process and metrology
21
Figure 17. (a) Schematic of a generic GaN-on-silicon power

transistor. Key areas for device optimisation using plasma
Figure 18. Views of clustered plasma process chambers. A central
processing are 1—recessed ohmic contacts for low resistance, high
robot handler allows movements of wafers between reactive ion
field compatible source–drain contacts; 2—the gate–drain region to
etch, atomic layer deposition and chemical vapour deposition
mitigate leakage current and dynamic on-resistance issues; 3—the
chambers without atmospheric exposure. Also clustered is a
gate stack to control threshold voltage and minimise gate leakage
scanning Auger microscope to enable in-situ mid-process surface
current with minimal hysteretic effects. (b), (c) and (d) Specific
analysis.
gate stack solutions. (b) Has a gate dielectric deposited on the GaN
surface; (c) has a gate dielectric above a fluorine plasma treated
region to tune threshold voltage; (d) has a recessed gate prior to
dielectric deposition. optimising device performance. Having a profound and fun-
damental understanding of the impact of plasma processing
engines are going to be the key to unlocking the full potential on the GaN surface is therefore an imperative to ultimate GaN
of plasma processing for GaN power electronics. power device realisation.
Concluding remarks. Plasma processing is a vital element in Acknowledgments

the manufacture of GaN power electronics as, based on its
use in the mainstream silicon industry, only plasma process- This work was undertaken as part of the UK Engineering
ing offers reproducible wafer scale and wafer to wafer etch- and Physical Sciences Research Council ‘PowerGaN’ project
ing and dielectric and metal deposition. Arguably, the GaN (EP/K014471/1), ‘Silicon Compatible GaN Power Electronics,
surface is one of the most process sensitive in the electron- PowerGaN’; and with support from Oxford Instruments
ics industry, so its control at a chemical level is key to fully Plasma Technology Ltd.
22
10. Challenges to dielectric processing

for E-mode GaN
Paul R Chalker
School of Engineering, University of Liverpool,

United Kingdom
Status. The growth of ultrathin dielectric layers into GaN-

based devices incorporating metal-insulator-semiconductor
(MIS) structures has been extensively investigated as a method
of minimising gate leakage currents, which are lost through
the gate by electron tunnelling, leading to poorer power effi-
ciency and electrical noise. For normally-off, enhancement
mode devices, low off-currents are necessary to reduce the
static power consumption and ensure fail-safe operation. The
incorporation of various oxide or nitride dielectric materials
into GaN-based heterostructures has been explored previously
using a range of conversion (e.g. oxidation or wet chemical
methods) and chemical (e.g. CVD or ALD) or physical vapour
(e.g. sputtering or evaporation) growth processes. Regardless
of the dielectric or fabrication process used, the discontinuity
(see figure 19) at the resulting insulator-semiconductor inter-
face gives rise to electrically active interface trap states. These
can influence device performance, by acting as remote impurity
scattering centres that can either lower the carrier mobility (µ) Figure 19. Cross section TEM of the gate MIS structure in a
[85] or influence the threshold voltage (Vth) [86]. The insulator GaN-based MISHEMT. The inset shows a high resolution dark field
itself may also contain deleterious intrinsic charge traps. Fur- image indicating the disruption of atomic lattice structure in the
GaN cap adjacent to the Al2O3 dielectric layer.
thermore, the insulator will have valence band and conduction
band offsets with respect to the III-nitride (e.g. GaN, AlGaN, situ fluorine-doping during ALD Al2O3 deposition, we reported
InAlN etc.) which will influence the carrier confinement prop- the control of Vth in enhancement-mode AlGaN/GaN MIS-
erties in the semiconductor [87]. Despite these issues, both HFETS [90]. When compared to the undoped dielectric, the
depletion-mode and enhancement-mode insulated-gate GaN- F-doping caused positive threshold voltage shift (see figure 20)
based transistors have been realised through the development and a reduction of positive fixed charge in the gate oxide.
of surface pre-treatments; dielectric film deposition processes; A dielectric is exploited in recessed gate MIS-HEMT, to sup-
and post-deposition heat treatments [88]. press gate leakage current and increase the on-state gate swing.
However, in the case of E-mode MIS-HEMTs, Vth hysteresis
Current and future challenges. The integration of insulted gate can be caused by large positive gate voltages due to 2DEG
dielectric with III–N semiconductors continues to represent a entering the deep trap states at the oxide/III-nitride interface.
significant hurdle to be overcome before E-mode MIS transis- A demonstration of how this effect can be mitigated is through
tors can reach maturity. The dynamic charging of deep traps the application of an Al2O3/AlN gate stack insulator [91]. The
at the dielectric-semiconductor interface is associated with Vth insertion of a 2 nm thin plasma enhanced ALD AlN interfa-
instability and long term reliability of the material system under cial passivation layer yielded a device with a Vth of +1.5 V,
electrical stress is uncertain. To begin to address some of these a current density of 420 mA mm−1 and an OFF-state break-
issues, gate dielectrics have been explored in the fabrication down of 600 V with low drain leakage of 1.7 µA mm−1.
of E-mode MIS GaN-based devices. Two of the approaches The preceding discussion has focused on n-type (2DEG)
explored to date include: (1) fluorine-doping which is used to channel MIS E-mode devices, however the realisation of
passivate or neutralise positive charges at the semiconductor p-type (2DHG) devices has received less attention to date. A
surface or in the dielectric itself; or (2) by recessing the gate significant advance, in this respect, has been the demonstration
by selectively etching the barrier layer in the region under the of complementary metal–oxide–semiconductor (CMOS) GaN
gate electrode. One example of F-doping via, CF4-plasma treat- field-effect-transistor technology [92]. This landmark achieve-
ment in the gate region of an AlGaN/GaN high-electron-mobil- ment is considered in more detail elsewhere in this roadmap. In
ity transistor (HEMT) [89]. Exposure to the plasma implants the context of the dielectric employed, an MOCVD AlN/SiN
F− ions into the AlGaN barrier and underlying GaN-channel. dielectric stack was exploited as the gate oxide for both NMOS
After application of an ALD Al2O3 gate-dielectric, the F-doped (µe—300 cm2 V−1 s−1) and PMOS (µh—20 cm2 V−1 s−1)
semiconductor acts as a source of fluorine that diffuses into an transistors. The devices were used to demonstrate a functional
Al2O3 dielectric compensating its intrinsic positive charge. It inverter integrated circuit.
was reported that the Vth increases with gate dielectric thick- Significant advances have been made in the integration of
ness, exceeding 3.5 V for gate dielectrics 25 nm thick. Using in gate dielectrics into III-N transistors, with the main purpose
23
Figure 20. Effect of F-doping in Al2O3 in E-mode MOS capacitors. (a) Reduction in CV hysteresis. (b) Influence of forming gas annealing
on fixed charge density. Effect of F-doping in Al2O3 in E-mode MISHFETs. (c) ID and IG versus VGS for 20 nm Al2O3 and F:Al2O3. (d) ID
versus VDS for 20 nm Al2O3 gate oxide with VGS from −4 V to +6 V in 2 V steps. (e) ID against VDS for 20 nm F:Al2O3 gate oxide with VGS.
(f) Mean, variance, and standard deviation (σ) of VTH for 15 of each type of MISHFET.
of minimising leakage currents in normally-off devices. A non-planar substrates comprising of a mixture of materials. The
variety of dielectric materials have been assessed, using dif- strategies for preparing III-nitride semiconductor (e.g. GaN,
ferent deposition processes, but the main focused has been AlGaN, AlInN etc) surfaces for subsequent dielectric deposi-
on SiO2, SiNx and Al2O3. The continuing challenges for tion will continue further development for both NMOS and
E-mode MIS devices are: (1) the minimisation of charge PMOS technologies. Where these are combined on the same
trap densities at the insulator/semiconductor interface across wafer for nitride-based circuits will add process complexity.
the range of barrier and channel III-nitride materials; (2) The solution to this problem will have to involve removal or
minimisation of the effect charging–discharging of trap conversion of any unwanted native contamination at the semi-
states which gives rise to Vth instability; (3) minimisation conductor surface. Ideally the semiconductor surface would be
of the influence of bulk and border traps within the insulator atomically planar after preparation. Various wet and dry (e.g.
dielectric itself which may impair the long term gate reli- thermal and plasma) processes have been explored to passiv-
ability and performance; (4) the development of processes ate and protect the semiconductor. It seems likely that future
and materials matched to the thermal budget of the device strategies may rely more on capping the semiconductor wafer
manufacture and the longer term in-field operating environ in situ at the end the III-nitride growth process to mitigate the
ment; (5) lastly addressing issues (1)–(4) in the context of problems associated with post-growth environmental exposure.
PMOS E-mode devices [93, 94]. Obvious candidates for this would be AlN- or SiN-based mat
erials, but could include others. Alternatively, advanced strate-
Advances in science and technology to meet challenges. The gies for the dielectric deposition process (e.g. ALD MOCVD
challenges of processing dielectrics for E-mode GaN MIS-based PECVD, LPCVD or some physical vapour deposition method),
device technology are comparable to those encountered over would involve an in situ preparation step. As an example, one
the last two decades in the field of silicon CMOS. Fundamen- prospect might be the introduction of an atomic layer etching
tally, the processing of dielectrics requires atomic-scale control (ALE) step to remove unwanted native oxide/contamination.
over the preparation of the semiconductor surface, followed by ALE could be applied to remove disordered gallium oxide/alu-
assembly of the insulator with sub-nanometre precision over minium oxide residue, prior to the ALD of a ‘dielectric-quality’
24
ALD layer. To realise this, further research would be required to high frequencies. It is foreseeable that the development of
develop ALE chemistries for the group-III oxides and nitrides. gate dielectrics will be tuned to meet three overarching chal-
In addition to surface pre-treatments, there is clearly scope lenges. Firstly, at the materials level, the dielectric stack will
for the development of improved dielectrics. Alternatives to mitigate the effects of detrimental traps or defects within
the existing candidates, future developments might target mul- the dielectric and at the nitride semiconductor-dielectric
tilayer dielectric stacks to target the overall gate capacitance, interface, with negligible gate-leakage and maximum resist
whilst enhancing resistance to gate-leakage. Multilayer gate ance to high-voltage electrical breakdown. Secondly, at
stack might also be exploited to engineer band alignments to the manufacturing stage, processing technologies will be
both the underlying semiconductor and the gate contact mat required incorporate the dielectric into increasingly complex
erial. Current research has identified the use of fluorine- or device architectures within the bounds of thermal budget.
hydrogen-‘doping’ in Al2O3 or SiNx, as a method of ‘defect Thirdly, the development of dielectrics will be driven by the
engineering’ to neutralise or passivate traps in dielectric mat operational issues of life-time and reliability in the extreme
erials. There is clear scope for basic materials research to take environments experienced by GaN-based device technology.
this defect engineering further to enhance the electrical prop-
erties of gate dielectrics. Acknowledgments
Concluding remarks. The incorporation of MIS structures The author acknowledges financial support from the UK
within E-mode GaN transistors offers a range of device design Engineering and Physics Sciences Research Council (EPSRC)
freedoms to realise monolithic GaN power IC, with reduced under EP/K014471/1 (Silicon Compatible GaN Power
parasitic inductance and more efficient power switching at Electronics).
25
11. Future applications, roadmap for GaN ICs charging, and protection features (e.g. shoot-through preven-
tion, UVLO, etc.) into a complete half-bridge power IC. Now,
Dan Kinzer and Stephen Oliver PWM ICs need simply to generate two, low current, ground-
referenced digital signals and the half-bridge GaN power IC
Navitas Semiconductor
completes this ubiquitous building block (see figure 21).
Since the 1990s, when Si-based junction-isolation (JI)
Status.
level-shifting techniques were introduced, power designers
The power GaN progression. With GaN already established
have searched for higher-efficiency and higher-frequency
as a leading material for LED/opto applications and for RF
methods. Hybrid level-shifter techniques, e.g. capacitive- or
amplifiers, this wide band-gap material emerged as an inter-
inductive-coupling, have been introduced but the disparate
esting academic option for discrete power devices around
semiconductor technologies used, plus complex assembly
the turn of the century. Today, discrete GaN power devices
techniques meant large and expensive modules. The 650 V
have been qualified to JEDEC standards from 80 to 650 V,
GaN power IC enables the true, next-generation, monolithic-
using technology that has advanced from complex, costly and
integration approach and results in a level-shifter which has
slow ‘cascoded d-mode’ implementations in highly-inductive
10 × lower loss than Si and 3 × lower than the best-in-class
through-hole packaging, to true single-die, e-mode devices in
hybrids.
SMT formats [94]. However, significant system factors still
exist which restrict practical switching speeds, negate the per-
Advances in science and technology to meet challenges.
formance advantages of GaN and, as a result, have slowed
Real-world applications. GaN is a low-loss, fast-switching
market adoption.
material and enables a range of new high-frequency topolo-
The answer to this problem is derived from the lateral
gies to move from academic to commercial applications. Com-
structure of GaN itself. A two-dimensional electron gas with
mercial devices now have blocking voltage ranging from 40
AlGaN/GaN heterojunction gives very high mobility in the
V to 1200 V. Generational improvements are driving RDS(ON)
channel and drain drift region, so resistance is much reduced
and device capacitances lower, but still far from a theoretical
compared to both Si and SiC. Circa 2009, early GaN power IC
limit. For high voltage devices, RDS(ON) scales approximately
technology was published from university research [95]. The
as (LGD)2. Drain-drift length is still 5× larger than the limit for
ability to integrate multiple power switches on a single chip
650 V devices, which means a 10× improvement in transis-
is a big advantage for GaN power ICs. Isolating substrates
tor area for a specific resistance value is possible and can be
began with sapphire and silicon carbide, though it was clear
expected over the next 10 years.
that an ability to grow GaN onto Si substrates enabled a cost
The easy-to-use GaN power IC building block now
structure and an ability to use existing large-diameter wafer
becomes the core enabler for high frequency, soft-switching
fabs that would be a big cost and capacity advantage. Since
topologies such as active clamp flyback (ACF), critical con-
Si is conductive, this introduces an additional challenge, of
duction mode (CrCM) and totem-pole power factor correc-
handling the substrate potential, and the way that it interacts
tion (PFC) and LLC DC-DC circuits to enter mainstream
with the power device.
markets [98–100]. Expect more system-enhancing and appli-
cation specific features to be added to the power ICs, which
Current and future challenges—the GaN power IC. All- will improve timing control, fault detection and feedback, and
GaN™ is the industry’s first GaN power IC Process Design light-load loss reduction.
Kit (PDK), and allows the monolithic integration of 650 V In parallel, new magnetic materials are being developed
GaN IC circuits (drive, logic) with GaN FETs [96]. This pro- and released to production with high-efficiency operation
prietary PDK is remarkable given the restricted device-level up to 5 MHz. Multi-MHz DSP controllers are available for
tool-set, e.g. no p-channel devices are available. This mono- higher power applications and new high-frequency, cost-
lithic integration is impractical using vertical GaN, d-mode effective ASICs are being introduced to enable adoption in
GaN or SiC technologies. price-sensitive markets such as smartphone and laptop charg-
For high-frequency operation, the most critical achieve- ers. Soft-switching circuits in the 5–10 MHz range frequency
ment has been the monolithic integration of GaN driver and with simultaneous increase in efficiency deliver cost-effective,
GaN FET. In discrete implementations, the exposed GaN increased power density [101].
gate is vulnerable to noise and potentially damaging voltage Practical examples of soft-switching topologies today are
spikes. Even when the GaN FET is included in a co-packaged, shown below in figure 22. Note that the mechanical construc-
multi-chip module, the impedance between Si driver output tion/assembly techniques used are industry-standard, and
and GaN FET gate leads to losses and potentially unstable readily-available at low cost. The 65 W solution operates at
operation. Only a monolithic solution delivers the required ~400 kHz, while the 150 W circuit operates at 1 MHz.
speed, efficiency and robustness [97]. From the driver inte- The same GaN power ICs may be applied in high-power,
gration, we can then consider ‘higher-order’ functions of multi-kW applications, with one example being a 3.2 kW, 1
the power IC such as inclusion of logic, start-up protection, MHz, AC-48 V converter prototype with 65 W/in3 power den-
dV/dt control, dV/dt robustness, and ESD to create full-func- sity [102]. Here, the single devices are paralleled to achieve
tion GaN power ICs. Another major step is the combination lower RDS(ON) and interleaving techniques are used for the
of two FETs plus all associated drive, level-shift, bootstrap Totem-Pole PFC and LLC sections.
26
Figure 21. 650 V GaN power ICs: (a) single, (b) half-bridge, (c) package types, dimensions (Navitas Semiconductor).
Figure 22. Examples of AC-DC converters using GaN power ICs; (a) 65 W active clamp flyback at 300 kHz using commercial control
ASIC and half-bridge GaN power IC, 94.5% peak efficiency at full load, 1.5 W cc−1 (24.6 W/in3) uncased power density (Navitas
Semiconductor), and b) 150 W Totem-Pole PFC plus LLC at 1 MHz using single GaN power ICs, >95% peak efficiency at full load,
3.7 W cc−1 (60 W/in3) uncased power density. DSP controller not shown (courtesy of CPES, Virginia Polytechnic).
Concluding remarks. magnetics and integration lead to major steps in efficiency,

Major accomplishments, major opportunities. The last 20 density and system cost-reductions. The power revolution of
years have seen GaN’s progression from RF to power discrete the late 1970s [103] will finally repeat today, 40 years later.
and now to the first generation of AllGaN power ICs. This has
enabled advanced, soft-switching topologies to enter the com- Acknowledgments
mercial marketplace. Next-generation monolithic integration
(e.g. advanced I/O features, over-current and over-temperature The authors wish to thank Dr F C Lee (CPES, Virginia
protection) will enable even higher levels of efficiency, power Polytechnic) and Dr A Q Huang (FREEDM Systems Center,
density and reduced system cost. Today, we see the simulta- North Carolina State University) for their pioneering MHz
neous ‘perfect storm’ of new devices, new topologies, new application work with GaN power ICs.
27
12. Potential of polarisation super junction the semiconductor surface and the field plates. Realizing such
technology in gallium nitride high voltage devices also requires sophisticated processing
capability for formation of precise field modulating plates.
E M S Narayanan1, V Unni1, A Nakajima2, H Amano3, S Yagi4 An alternative solution for manufacturing low-cost high-volt
and H Kawai4 age GaN power switching devices, which can overcome some
1
University of Sheffield, Sheffield, United Kingdom of the above-mentioned challenges is the polarisation super
2
National Institute of Advanced Industrial Science and junction (PSJ) technology, which is described in the next sec-
Technology, Tsukuba, Japan tion. This technology is also a highly promising candidate for
3
Nagoya University, Furo-cho, Chikusa-ku, Nagoya, the fully GaN based power ICs.
464-8601, Japan
4
Powdec KK 1-23-15 Wakagi-cho, Oyama city, Tochigi Advances in science and technology to meet chal-
323-0028, Japan lenges. In 2006, a polarisation junction (PJ) concept was
proposed based on the charge compensation of positive and
Status. Amongst many semiconductors, silicon carbide negative polarisation charges at heterointerfaces of a GaN/
(SiC), gallium nitride (GaN) and diamond can offer signifi- AlGaN/GaN structure [107]. This was followed by the suc-
cant system level benefits and have the potential to meet the cessful demonstration of GaN double heterostructures,
anticipated power densities by 2025 [104]. GaN offers similar grown along the (0 0 0 1) crystal axis, where high density
performance benefits to SiC, but with a greater potential for positive and negative polarisation charges coexist at the
cost-reduction as well as higher frequency. A price advantage AlGaN(0 0 0 1̄)/GaN(0 0 0 1) interface with accumulated 2D
over SiC is also possible because GaN power devices can be electron gas (2DEG) and 2D hole gas (2DHG) accumulated
grown on substrates that are larger and less expensive than SiC. at the GaN(0 0 0 1̄)/AlGaN(0 0 0 1) interface respectively, as
Since the first report of high density two-dimensional (2D) shown in figure 23 (left) and figure 23 (middle) which has
electron gas in 1991 [105] and high electron mobility transis- since enabled a polarisation super junction (PSJ) technol-
tors in 1993 [106], GaN has gained traction and now discrete ogy [108]. Like the superjunction in Si, PSJ enables linear
GaN transistors are emerging as commercial products. Their scaling of breakdown voltage with increase in thickness or
performance is however limited to about 1/5 of their poten- length of the drift region and with performances beyond that
tial capability by slower external silicon gate driver circuits of 1-D 4-H silicon carbide limit, as shown in figure 23 (right).
required to control them. Si circuits have a limited operating Over the past few years, high performance diodes, transis-
temperature range and inherently efficient GaN devices are tors as well bidirectional switches have been demonstrated
forced to slow down, leading to failure and severe derating of [109, 110]. Enhancement-mode PSJ-HEMTs have also been
efficiency. The dual (Si & GaN) technology approach impacts reported with most recent results of large (4 × 6 mm2) and
cost deleteriously. By monolithically integrating control cir- small devices made on sapphire substrates showing with
cuits with power devices on a single GaN technology plat- breakdown voltages beyond 3 kV [111]. Moreover, due to
form the efficiency can be greatly increased, and cost reduced. the effective lateral charge balance and field distribution,
Moreover, because of the difficulty in obtaining p-channel these devices fabricated on a sapphire substrate show no cur
devices, integrated circuits (ICs) thus far demonstrated are rent collapse. One of the key attributes of the PSJ technology
made of n-channel devices. is that it is viable to make both NMOS as well as PMOS
circuits, and CMOS inverter operation of a monolithic P-
Current and future challenges. In GaN-on-Si technology, and N-channel MOSFETs has been demonstrated on this
the breakdown voltage is primarily determined by the GaN platform [112]. This technology also paves way for bidirec-
buffer and therefore thick buffer and transition layers are tional switches with integrated diodes. This device is well
necessary to sustain high voltage, which make the wafers suited for a variety of applications and for solid state circuit
more susceptible to bowing and crack generation. The inher- breaker because, PSJ offers the possibility of realising much
ent tensile stress due to mismatch in lattice constants and lower saturation currents than conventional HFETs [108],
coefficients of thermal expansion in such structures can also while maintaining ultra-low on-state resistance. Thus, PSJ
compromise the reliability of devices. Lack of avalanche technology can pave the way for high power density mono-
capability or non-destructive breakdown behaviour necessi- lithic integration of various devices for a variety of applica-
tates over-rating the device breakdown voltage for a given tions, as shown in figure 24.
application. Moreover, there is a significant level of defects Most recently, the PSJ concept has been extended to
in layers and understanding of these defects and their rela- vertical GaN technologies and is termed as vertical PSJ

tionship with device reliability is necessary. The conventional (VIPSJ) with predicted benefits of 2 orders of magnitude
GaN technology uses metal field plates. However, the dis- reduction in specific on-state resistance in comparison to SiC
tribution of the electric field is not uniform, which impacts at 1 kV rating [113].
breakdown voltage along with rendering such devices to be
sensitive to current collapse during high voltage switching. Concluding remarks. There are several scientific, technolog-
The field distribution is also highly sensitive to changes in ical and manufacturing challenges that need to be addressed
charges accumulated in the insulators sandwiched between before GaN power semiconductor devices can be considered
28
Figure 23. (Left) Double heterostructure in GaN [108]; (middle) measured 2DEG and 2DHG through Hall effect measurements; (right)
variation of measured specific on-state resistance with breakdown voltage of PSJ-HFETs against calculated unipolar 1D material limits
of silicon, SiC and GaN [111]. (Left) Reproduced from [108]. © 2010 The Japan Society of Applied Physics. All rights reserved. (Right)
[111] John Wiley & Sons. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Figure 24. Proposed PSJ platform for monolithic power integrated circuits. Please note that the substrate is not specified. However, thin
sapphire is the most cost-effective option because of the use of uniform thickness of 1 µm u-GaN buffer layers to serve for both low as well
as high voltage devices and provide full electrical isolation (critical requirement for monolithic integration).
mainstream. It is also becoming apparent that a transition from Acknowledgments

the general scheme of manufacturing power conversion cir-
cuits using discrete devices to that of a fully integrated power The authors thank Royal Society of London, British Academy
system-on-chip is anticipated to be a prerequisite to fully har- and Royal Academy of Engineering under the Newton
ness the high-frequency power switching benefits of GaN. To International Fellowship scheme since 2009 and EPSRC.
conclude, GaN PSJ technology will be instrumental in shap- Nakajima also acknowledges the support from New Energy and
ing a viable and a new era of an integrated power electronics Industrial Technology Development Organisation (NEDO),
for ultra-high-power density converters. Japan for their support through project No. 11B06003d.
29
13. Technological challenges in next-generation

GaN-based power integrated circuits
Akira Nakajima
National Institute of AIST, Japan
Status. Si-based lateral power devices have been widely uti-

lized in high-frequency and low-power converters for ratings
of up to several hundred watts [114]. On the other hand, GaN-
based heterojunction field-effect transistors (HFETs) utilizing
polarization-induced 2D electron gas (2DEG) are emerging
components for such high-frequency converters. GaN-based
discrete devices up to 650 V rating are commercially available
now. The development of GaN growth technology on conduc-
tive Si substrates has largely contributed to the improvement
in the device performance and decrease in cost [43]. As a next Figure 25. Schematic cross section of monolithic half-bridge
step, towards achieving high intrinsic switching capability circuit on conductive Si substrate.
of GaN devices, monolithic integration of GaN-based con-
verter circuits will be necessary. Area-specific on-resistances
of GaN-HFETs are already two orders of magnitude smaller
than those of Si-based lateral power devices. Owing to this
significant footprint reduction, high output powers of up to
several kilowatts can be expected in GaN-based monolithic
converters. In this article, two technological challenges are
addressed: the ‘crosstalk effect’ and ‘heat dissipation’ in next-
generation ultra-high-frequency monolithic power integrated
circuits (ICs). These issues are quantitatively discussed using
simple analytical models.
Current and future challenges. As an example of GaN power

ICs, if an integrated half-bridge circuit on a conductive Si sub-
strate as shown in figure 25 is assumed with the following
parameters: voltage rating of the GaN devices are 600 V, input
voltage VIN is 400 V, 2DEG density Ns has a conventional
value of 1013 cm−2, and dielectric constant ε of the GaN-based
epilayer is 9.0 ε0. Figure 26. Calculated heat densities of GaN chip depending on
output frequency under hard switching condition.
Firstly, the ‘crosstalk effect’ is discussed. In discrete GaN
devices, the substrate potential is shorted with the source elec- speed is sufficiently high, power loss of the hard-switching
trode. The conductive Si substrate acts as a back-side field circuit (figure 25) reaches the minimum value. Under the min-
plate contributing to the suppression of current collapse. imum loss condition, the heat density HD of the GaN chip can
However, in an IC, it induces a significant increase in the on- be expressed as
resistance of the high-side transistor [115]. This is because the
HD = Qoss VIN f /A = qNs VIN f ,
(2)
2DEG of the high-side transistor interacts with the substrate
potential through the GaN epilayer capacitance Cepi. During where Qoss is the output charge of each GaN transistor and f is
the on-state of the high-side transistor, the input voltage VIN the the output pulse-width modulation frequency. Equation (2)
is directly applied to Cepi, inducing a 2DEG density reduction implies that a charge Qoss is supplied from the voltage source
ΔNs: VIN during every switching period, and the energy is consumed
as joule heat in the GaN chip. Figure 26 shows the heat den-
q∆Ns = Cepi VIN /A = εVIN /tepi ,
(1) sity calculated using equation (2). Although high-frequency
where q is the electron charge, A is the GaN device area, and operation is expected in hard-switched GaN monolithic con-
tepi is the GaN-based epilayer thickness grown over silicon verters, the estimated heat density is unacceptably high. For
substrate. If we consider a 2DEG density reduction of 10% example, it is 6.4 kW cm−2 at 10 MHz.
(i.e. 10% on-resistance increase), the calculated tepi is 20 µm.
In comparison with a GaN-based epilayer in conventional dis- Advances in science and technology to meet challenges. The
crete devices (3–5 µm), power IC applications require an epi- substrate material for the growth of GaN-based layers is a
layer which is thicker by five times. key element of power ICs. Because conductive Si substrates
Next, the issue of ‘heat dissipation’ challenges are dis- induce the crosstalk effect, novel platform substrates are
cussed under hard switching condition. When the gate drive required for next-generation ICs, especially for high-voltage
30
and high-frequency applications. GaN-on-silicon-on-insu- SiC substrates have been widely used in RF applications and
lator (SOI) technologies are a promising solution which can are also emerging candidates in power converter applications.
enable CMOS compatibility in the GaN device fabrication Finally, GaN-on-diamond technology might be the ultimate
process [116, 117]. The contribution of the back-side field solution to the heat dissipation issue because diamond has the
plate effect is also obtained through substrate contact from highest thermal conductivity [119–121].
the front side [117]. However, a several-µm-thick SiO2 buried
layer will be required to sustain 600 V or more. The thermal Concluding remarks. In next-generation GaN-based power
conductivity of SiO2 is two orders of magnitude smaller than ICs, device isolation technologies are a key challenge, espe-
that of Si. Therefore, heat dissipation from integrated GaN cially in high-voltage applications. GaN-on-SOI and GaN-
devices on an SOI substrate will be big challenge. Further- on-sapphire technologies are promising candidates from this
more, GaN power device technologies on insulator sapphire perspective. In addition, thermal management is a key issue.
substrates are equally promising candidates [92, 118] because Area-specific on-resistance has been a major benchmark
they yield high-quality GaN crystals. However, on such insu- parameter of GaN-HFETs. In addition, the minimization of
lator substrates, current collapse must be eliminated without area-specific ‘thermal-resistance’ will be a key strategy in
the support of the back-side field plate effect. Effective lateral GaN-based IC development. Therefore, GaN device technolo-
electric field management strategies will be necessary, such as gies utilizing high-thermal-conductivity substrates such as
polarization superjunction technology [118]. SiC and diamond are also emerging as platform substrates for
In addition, other emerging candidates must be consid- GaN power ICs. However, on any platform, potential advan-
ered. Because the thermal conductivity of SiC is three times tages in performance and cost should be considered from the
higher than that of Si, GaN technologies on highly resistive system level viewpoint.
31
14. GaN CMOS: fact or fiction?
Rongming Chu
HRL Laboratories, Malibu, CA, United States of America
Status. GaN power transistors have demonstrated unprec-

edented switching speed [122]. At high switching speed, para-
sitic inductance in the power loop as well as in the drive loop
causes large voltage overshoot [123]. In current practice, the
GaN switch is often intentionally slowed down to avoid cata-
strophic failure and additional power consumption induced
by the voltage overshoot [124]. To take full advantage of the
high-speed GaN switch, one need to eliminate the parasitic Figure 27. Schematic showing the concept of monolithic GaN
inductance by monolithically integrating power switches and power IC with the power stage and the gate drive stage integrated
on the same chip.
their gate drivers. The gate driver typically uses a Totem-Pole
topology with a pair of complementary N-type and P-type hole mobility, low mobile hole concentration, and poor ohmic
transistors. The complementary transistors eliminate static contacts. The off-state leakage is attributed to impurity con-
power consumption. GaN CMOS technology is needed to tamination at the regrowth interface.
realize monolithic GaN power IC integrating high-voltage
GaN transistors with low-voltage N- and P-type GaN transis- Advances in science and technology to meet challenges.
tors on the same chip. Figure 28 shows device structure, IV curves, and on-resistance
The monolithic GaN power IC, as shown in figure 27, mini- component breakdown of a P-type GaN transistor reported
mizes interconnect parasitic between power switches and gate in [92]. Inefficient P-type doping is the primary challenge
drives. Reduction of interconnect parasitic enables efficient responsible for the low current and the high on-resistance. Mg,
power switching at high frequencies. At high frequencies, with an activation energy as high as 0.2 eV in GaN, is used as
the size of passive components can be drastically reduced. the acceptor. High dopant activation energy leads to low con-
Reduction of interconnect parasitic also enables active concentration of mobile holes even at high doping level, therefore
trol of switching trajectory with minimal time delay. Active high contact resistance and high access resistance. Advance
control of switching trajectory mitigates device stress and in P-type doping technique, e.g. polarization-assisted doping
improves the reliability. The monolithic GaN power IC ena- [130], has the potential of overcoming the doping challenge.
bles modular architecture where a number of power switch- Low hole mobility is another important factor responsible for
ing unit cells, e.g. half bridge, can be stacked in parallel and the high on-resistance. Low hole mobility is caused by severe
in series to scale the current and voltage handling capability. impurity scattering, interface scattering under the gate insula-
The monolithic GaN power IC enables cost reduction by cut- tor, and large hole effective mass. In addition to enhancing
ting the assembly and packaging cost, as well as by using the doping efficiency, improvement of insulator-semiconductor
modular architecture consisting of standardized switching interface is important for achieving better hole mobility and
unit cells. lower channel resistance. Strain engineering may increase the
population of light holes, thereby improving the hole mobil-
Current and future challenges. N-type GaN high- and low- ity. In addition to improving hole density and mobility, reduc-
voltage transistors are readily available. Difficulty in making or eliminating the spacings between gate and source/drain
ing P-type GaN transistor and integrating it with the N-type electrodes can effectively improve the on-resistance.
transistor has been the major obstacle for realizing the GaN Improvement of epitaxy regrowth process is needed to
CMOS technology. There have been a few early studies on eliminate the off-state leakage current shown in figure 28.
P-type GaN transistors [125–128], an attempt to integrate P- P-type transistors fabricated on P-type only wafers did not
and N-type Schottky gate GaN transistors [129], and lately a show this off-state leakage. The off-state leakage is attrib-
demonstration of a working GaN CMOS IC inverter [92]. The uted to Si contamination commonly observed at the regrowth
GaN CMOS demonstration was achieved through selective interface. The source of the Si contamination can be volatile
area regrowth of P-type GaN transistor structure on a wafer organic silicon compound in the air ambient. A regrowth pro-
with N-type GaN transistor epitaxy structure. Significant cess avoiding such contamination is needed to integrate high-
improvement of the GaN CMOS technology is needed to meet performance P- and N-type transistors.
the performance requirement of the monolithic power IC. Comprehensive study of gate dielectric in P-type transis-
Specifically, there are two major challenges to be addressed. tors is also needed to ensure stable threshold voltage, and
One challenge is the low output current, or high on-resistance, facilitate scaling to smaller gate lengths.
of the P-type transistor. The other challenge is the off-state
leakage current of the P-type transistor when integrated with Concluding remarks. Monolithic power IC based on the GaN
the N-type transistor. The low output current results from poor CMOS technology is essential for realizing and maximizing
32
Figure 28. Cross-section schematic, output IV characteristics, and on-resistance component breakdown of the P-type GaN transistor
reported in [92]. 5X reduction of on-resistance is achievable at low risk with optimized device design/process.
the performance/cost potential of GaN power electronics. fiction. Improvement of P-type doping and selective area
Early work on GaN N/P-type transistors and GaN CMOS regrowth is important for realizing high-performance GaN
technology has proved that the GaN CMOS is a fact, not a CMOS technology for monolithic power IC applications.
33
15. Assessing the limits of performance of p-type

devices in GaN
Ashwani Kumar and Maria Merlyne De Souza
University of Sheffield, United Kingdom
Status. P-type devices are required for integration of

CMOS gate drivers and power devices to enable high fre-
quency, high efficiency convertor systems on a chip in GaN.
A D-mode p-channel HFET in GaN, utilising a low density
(1 × 1011 cm2) polarization induced two dimensional hole gas
(2DHG) as carrier was first demonstrated by Zimmermann
et al in 2004 [126]. It is more difficult to realise a normally-
off (E-mode) operation, with negative threshold voltage Vth ,
since the 2DHG under the gate has to be depleted at zero gate
bias. A recessed gate [131], and/or reduction of polarization
charge via adjustment of the mole fractions [132] have been
amongst techniques explored for E-mode operation, follow-
ing logically from similar progression in n-type devices in
Figure 29. (a) On-current versus threshold voltage, and (b) on-off
GaN. However, these techniques are not easily transferrable,
current ratio versus threshold voltage characteristics of the state-of-
primarily because unlike a 2DEG in GaN, achieving a high the-art p-channel HFETs reported to date.
density 2DHG is a challenge, and reported mobility of holes
in a 2DHG, ranges no more than 6–43 cm2 V s−1 at room
temperature [126, 132].
Current and future challenges. The main challenge for a

p-type MOSHFET in GaN is achieving a high threshold
voltage |Vth | to prevent false turn-on in PMIC applications,
while maintaining a high |ION | and |ION /IOFF | ratio. Achiev-
ing a |Vth | of |−2.0| V is not feasible by etching alone, as it
requires the thicknesses of the oxide and GaN channel layer
to be reduced to undesirably small values (∼ 5 nm ) [133]. On Figure 30. Schematic of p-type MOSHFETs with (a) an AlGaN
the other hand, achieving an E-mode operation by reducing cap and (b) a bias applied to the 2DEG.
the polarization charge via a reduction in the Al mole fraction
leads to reduction in the density of both 2DHG and 2DEG, simultaneously, it is possible to tune the polarization and the
not only reducing the |ION | in p-type devices but also dete- bandgap of the barrier layer, independently, to some extent.
riorating the performance of n-type devices on the same plat-
form. Figures 29(a) and (b) depict the on-current |ION | and Advances in science and technology to meet challenges. A
on-off current ratio |ION /IOFF | with threshold voltage |Vth | of higher |ION | requires a high density of 2DHG, nevertheless,
experimental p-channel HFETs reported in [92, 127, 131, 132, for an overall lower parasitic resistance, as well as high on/off
134], highlighting the degradation of |ION | as the device turns current ratio, requires a localised depletion of the 2DHG under
from D-mode to E-mode while |ION /IOFF | ratios improve with the gate, so as to not affect the access regions. This can be
increasingly negative |Vth |. Except for the work of Chu [92] achieved via an AlGaN cap between the oxide and GaN chan-
and Li et al [127], which do not include an underlying 2DEG nel layers [136], where the barrier separating the 2DHG from
beneath the 2DHG, the activities can be summarised into two the 2DEG can be either AlGaN or InAlGaN. As shown previ-
main barrier-layer platforms, ternary AlGaN and quaternary ously, for the device in figure 30(a), the additional polarisa-
InAlGaN, both of which possess an inherent polarisation tion charge introduced by the AlGaN cap not only depletes the
superjunction [135] that is eminently useful for management 2DHG under the gate, but also minimises the trade-off between
of the peak electric field distribution and reliability of GaN |ION | and |Vth | [133]. However, this approach demands a selec-
power devices. The best performing E-mode p-type device tive epitaxial regrowth of the AlGaN cap layer. F igure 30(b)
by gate recess so far, reported by Hahn et al [132], resulted shows an alternate heterostructure, where in addition to the
in an on-current |ION | of ∼ 9 mA mm−1 at a Vth of −1.3 V recessed gate, the 2DEG is biased via an additional base con-
and an on/off current ratio of ∼ 107. In quaternary barriers, tact [134], thus acting as a secondary gate for the 2DHG. By
increasing the Al mole fraction leads to an increase in nega- applying a positive bias to the base contact VB, the density of
tive polarization charge, higher bandgap, and a smaller lattice 2DHG can be reduced locally, without affecting other devices
constant, while increasing the In mole fraction has the oppo- on the platform. In both the device structures (figures 30(a)
site effect. Hence, by adjusting both Al and In mole fractions and (b)), a 2DEG lying parallel beneath the 2DHG separated
34
by an AlGaN/InAlGaN barrier contributes an additional para- tailoring the valence band structure in GaN, for example by
sitic capacitance which can be offset by increasing the barrier the application of stress to lower the effective mass of holes
thickness. or introduction of positive ions directly in the gate oxide to
Advancements in the growth of gate oxide are necessary to deplete the hole gas underneath.
control and lower the impact of trap states at the oxide/AlGaN
cap and oxide/GaN interfaces while at the same time lower the Concluding remarks. P-type devices in GaN are necessary
gate leakage current, for a reliable and replicable operation of in the long run to harness the full potential that GaN tech-
these devices. The MOCVD growth of Mg doped p-GaN layer nology has to offer in achieving high efficiency power con-
currently suffers from, large activation energy (120–200 meV) version. Despite the poor mobility of holes and challenges
of Mg dopants and memory effect [137], which leads to poor associated with Mg dopant, techniques to circumvent or limit
hole density in p-GaN and a broader doping profile. Moreover, their impact exist, although still in their infancy. More work is
during the epitaxial growth at high temperature, Mg ions can required for demonstrating their reliable operation and manu-
diffuse into the GaN layer underneath, thus contributing to the facturability at low cost.
leakage current and affecting the minimum channel thickness
that can be achieved in manufacture. Therefore, novel doping
techniques are required to obtain p-GaN layers with high hole Acknowledgments
density and sharper doping profile.
Other possibilities to boost the performance of p-type We acknowledge partial support of ENIAC-JU grant E2SG in
devices in GaN include, improving the hole mobility by the first year of studies for Ashwani Kumar.
35
16. 600 V E-mode GaN power transistor technology: power level operating at 350 kHz without sacrificing peak
achievements and challenges efficiency of 98.4% demonstrate high density of 170 W/in3
[144]. For hard switching applications the relevant figure-of-
Oliver Häberlen merit is the energy stored in the output capacitance (Eoss) and
here recent developments in Si SJ devices have raised the bar
Infineon Technologies Austria AG, Siemensstraße 2, 9500
significantly so that as of today only E-mode GaN can out-
Villach, Austria
perform Si. In combination with the lack of reverse recovery
charge that enables the use of GaN devices in half bridge con-
Status. Since the first confirmation of a 2DEG at the AlGaN/
figurations new and simpler topologies like full bridge totem
GaN interface in 1992 and the first availability of GaN-on-
pole are possible.
SiC radio frequency power transistors in 1998, nitride semi-
conductor hetero structure electron devices now constitute a
hundred million dollar market for RF power. As regards power Current and future challenges. One of the biggest challenges
conversion applications, GaN-on-Si high voltage power tran- to release power GaN devices to the market has for sure been
sistors have been in development stage for the past decade their reliability. The hetero epitaxial growth of the GaN buf-
with initial focus on depletion mode devices, due to the inher- fer on silicon wafers unavoidably leads to lattice misfit dislo-
ent nature of the 2DEG. However, most power electronic cations and other growth defects. At the same time, present
applications demand for enhancement mode devices. The first lateral GaN devices differ from the established silicon power
high voltage solution released to market in 2015 by Trans- devices in many aspects as they are based on hetero junc-
Phorm [138] is based on a cascode configuration of a low tions, differences in spontaneous polarizations and bulk/sur-
voltage Si-MOSFET in series connection with a high voltage face donors to generate the 2DEG instead of p and n dopings.
GaN MIS-HEMT to solve that issue. Following the progress The qualification of those devices therefore cannot solely rely
of enhancement mode devices based on a p doped GaN gate on established silicon procedures (e.g. according to JEDEC
module for low voltage GaN power transistors from EPC Solid State Technology Association, former Joint Electron
[139], we now see the first fully industrial qualified 600 V Device Engineering Council) but must take into consideration
true enhancement mode (E-mode) GaN power transistors on the new possible failure modes and physics together with the
the market from Panasonic and Infineon [140, 141]. These corresponding lifetime models and application profiles to
E-mode GaN power transistors are based on a fully recessed determine appropriate qualification tests and durations. It is
gate module with subsequent regrowth of a second AlGaN bar- also essential to derive appropriate screening tests based on
rier with pGaN (see figure 31) on top for an excellent control intrinsic and extrinsic lifetime models to achieve the needed
of the threshold voltage independent of the drift layer carrier low field failure rates of 1 fit or less. Passing all those quali-
density [142]. pGaN is also used at the drain region as drain fication procedures still does not guarantee stable long term
extension which improves the dynamic on state resistance to behaviour in the application. Long term testing of the devices
well below 10% even at high temperatures of 150 °C and at under real application conditions with no fails is a first neces-
a full rated drain voltage of 600 V down with delay times as sary step, but only application testing with accelerated condi-
short as few hundreds of ns from blocking mode to settled tions (e.g. higher temperatures, bus voltages, peak currents)
on state resistance measurement. At the same time, this drain and testing to failure allows extraction of life time models and
sided pGaN region (see figure 31) also improves the robust- hence failure rates in real life [145]. As a joint effort by the
ness of the device to the required levels for hard switching major semiconductor companies involved in GaN, a working
applications [140]. The devices are offered in surface mount group for the standardization of GaN qualification under the
device packages allowing for designs with low loop induc- framework of JEDEC has been recently established to address
tances including top side cooled variants for enabling 3 kW many of the before mentioned aspects [146].
converters without need for paralleled devices (see figure 31).
Recently, it has been demonstrated that the gate module even Advances in science and technology to meet challenges. For
allows for a >10 µs short circuit robustness at full bus volt further advancing the reliability of GaN devices it is important
age of 400 V when driven properly [143]. The technology has to further deepen the understanding of defects and their rela-
been implemented in a volume silicon power fab with a very tion to device behaviour and device reliability. This comprises
high degree of equipment sharing with standard silicon pro- e.g. the understanding of point defects including their elec-
cesses to achieve economy of scale. tronic structure mainly in the various parts of the AlN/AlGaN/
When comparing Infineon’s CoolGaN™ technology to the GaN buffer, channel and barrier layers and how those defects
state-of-the-art silicon super junction devices (Si SJ) as well as are influenced by the growth conditions of the material and
other wide band gap technologies on the market (see table 1), the selection of possible advanced substrates. In order to pos-
we see that all WBG technologies offer roughly the same order sibly achieve future enhancement mode devices based on MIS
of magnitude improvement in output charge QOSS and reverse gate structures with low leakage currents and a wide range of
recovery charge QRR per RDSON. However, only E-mode GaN threshold voltages and gate drive voltages a big step in under-
offers at the same time one order of magnitude of gate charge standing on how to reduce the interface defect density of gate
QG improvement which makes it the perfect device for high dielectrics on top of GaN and how to improve channel mobil-
frequency resonant switching. Resonant converters with 3 kW ity is needed.
36
Table 1. Benchmark of state-of-the-art high voltage power transistors. © 2017 IEEE. Reprinted, with permission, from [94].
Rating RDSON RDSON * QOSS RDSON * QRR RDSON * EOSS RDSON * QG

Device (V) (mΩ) (mΩ µC) (mΩ µC) (mΩ * µJ) (mΩ nC)
Si Super Junctiona 600 57 22.6 32.5 440 3820
GaN eModeb 600 55 2.2 0 350 320
GaN Cascodec 600 52 3.8 7.1 730 1460
GaN Direct Drived 600 70 4.1 0 530 n.a.
SiC DMOSe 900 65 4.5 8.5 570 1950
SiC TMOSf 650 60 3.8 3.3 540 3480
a
Infineon CoolMOS™ IPP60R070CFD7 Datasheet. b Infineon CoolGaN™ preliminary values (QRR is exclusive of QOSS). c TransPhorm Cascode
TPH3205WS datasheet. d TI Direct Drive LMG3410 datasheet. e Wolfspeed C3M0065090J datasheet. f Rohm SCT3060AL datasheet (QRR is at 300V).
All values given typically at 25 °C incl. package.
Figure 31. (a) 600 V E-mode GaN cell concept with through recessed first AlGaN barrier and regrown thin second AlGaN barrier with
pGaN enhancement mode gate, (b) GaN-on-Si wafer with enlarged unit cell and schematic of AlGaN/GaN hetero junction forming the
2DEG, (c) top side cooled SMD package: top view and schematic with wire bonds. (a) © 2017 IEEE. Reprinted, with permission, from [94].
An important mid to long term challenge for GaN tech- have been established according to the needs of the new mat
nology to enable broader market penetration is approach- erial system and taking into consideration typical industrial
ing cost parity per same RDSON compared to silicon devices application profiles targeting field failure rates below 1 fit.
like CoolMOS™. This will be driven on the one hand side by The new devices offer customers the degree of freedom to
reducing the cost per die area through increasing economy of either boost the power conversion efficiency to unprece-
scale and increased yield with rising volume and the introduc- dented levels of 99% and beyond or to significantly increase
tion of 200 mm wafer diameter for GaN-on-Si during the next the power density of their converters without compromising
few years as well as the step to 300 mm within the next dec- the efficiency.
ade. On the other hand, we will see further die shrinks through
better exploration of the material limits e.g. by increased mat Acknowledgments
erial quality allowing for shorter drift regions through higher
electric fields as well as advanced drift region engineering This project has received funding from the Electronic
(improved field plates, graded 2DEG density, etc.) allowing Component Systems for European Leadership Joint
for higher carrier densities without compromising reliability. Undertaking under grant agreement No. 662133. This Joint
Undertaking receives support from the European Union’s
Horizon 2020 research and innovation programme and
Concluding remarks. After GaN-on-SiC RF power devices
Austria, Belgium, Germany, Italy, Netherlands, Norway,
reached a multi hundred million dollar market volume, and
Slovakia, Spain, United Kingdom.
after a decade of intense research and development of GaN-
on-Si power technology, fully industrial qualified 600 V true
enhancement mode GaN power devices are finally entering
the market. Qualification procedures and screening methods
37
17. Potential of GaN integrated cascode transistors gate [151], GaN MOSFETs [152] and p-AlGaN gate [153]
remains low, typically less than 2 V. This presents an issue for
Kean Boon Lee, Sheng Jiang and Peter Houston gate driving as un-intended turn-on may occur with a voltage
ringing effect as a result of CdV/dt coupling from the drain to
Department of Electronic and Electrical Engineering,
the gate.
University of Sheffield, Mappin Street, Sheffield, S1 3JD,
United Kingdom
Advances in science and technology to meet challenges. The
Status. AlGaN/GaN high electron mobility transistors switching losses in a field effect transistor are partly deter-
(HEMTs) are poised to replace Si MOSFETs for high fre- mined by the current through the resistive loss-generating
quency power switching applications up to 600 V. Enhance- channel during the charging/discharging processes [154] and
ment mode (E-mode) operation with a positive threshold hence depend on the speed of charging and discharging the
voltage (VTH) ⩾ 3 V is desirable for circuitry protection and Miller capacitance (Miller effect) at high voltages. The latter
safety purposes but GaN HEMTs are naturally depletion mode depends on the load current-to-gate drive current ratio. On the
(D-mode) devices. Cascode devices with low voltage E-mode other hand, the discharging of the charge stored in the output
Si MOSFETs and high voltage D-mode GaN HEMTs offer an capacitance of the cascode device is not limited by the gate
excellent solution to the E-mode operation issue using exist- drive current during turn-on as shown in figure 32(a). Dur-
ing gate drivers. In addition, the cascode structure can lead ing turn-off, the cascode connection utilises the load current
to improved switching speed and reduced switching losses to charge the output capacitance and a faster turn-off time
compared to an equivalent discrete transistor [147]. Here, we can be achieved for the same gate drive capability. The GaN-
discuss the challenges faced by cascode devices as well as based integrated cascode transistor is an excellent candidate
the potential of integrated cascode structures to achieve high to exploit these switching advantages without the additional
switching frequency. parasitic inductance. In our recent work using F treatment
technology to achieve E-mode in the integrated cascode GaN
Current and future challenges. Despite the promising per- transistor (VTH = +2 V) (figure 33), we demonstrated a reduc-
formance of commercial 600 V hybrid GaN plus Si cascode tion in turn-on and turn-off energy losses of 21% and 35%,
transistors [148], several issues hinder their switching perfor- respectively in comparison to a discrete GaN E-mode transis-
mance. Firstly, additional package connections in the hybrid tor under 200 V hard switching conditions [155]. The immedi-
cascode lead to increased parasitic inductances which can ate challenge is to achieve a reliable E-mode technology with
cause excessive ringing and limit the operating frequency VTH greater than +2 V.
[149]. This presents major challenges to packaging design. In Matching of intrinsic capacitances between E-mode and
addition, the intrinsic capacitance mismatch between the Si D-mode devices in the cascode connection is critical to con-
and GaN transistors and the body diode in the Si MOSFET trol the off-state operating voltage of the E-mode device.
can result in additional switching losses when the Si device is For hybrid cascodes, adding an external capacitor in par-
driven into avalanche mode during turn-off [150]. allel with drain–source of E-mode Si MOSFETs has been
Monolithically integration of E-mode and D-mode GaN proposed to provide this matching and prevent the Si device
devices in the cascode configuration, on the other hand, will running into avalanche [150], but at the expense of addi-
mitigate the parasitic inductances and the ‘slower’ Si device tional package inductances. For GaN integrated cascode
issues in the hybrid GaN plus Si cascode devices. However, transistors, different field plate structures in E-mode and
VTH of the reported E-mode GaN devices using various tech- D-mode devices can be employed to achieve capacitance
niques such as fluorine (F) treatment on the barrier under the matching. In addition, with the lack of a body diode in the
38
Figure 32. Charging and discharging paths of the output capacitance in the cascode device during (a) turn-on and (b) turn-off processes.
Figure 33. Device structure of GaN integrated cascode transistors.
low voltage GaN E-mode device, the integrated cascode E-mode and the mismatch of D-mode and E-mode devices to
devices have the option to trade the off-state operating volt realise the full potential of integrated GaN cascode HEMTs.
age of the E-mode part for a faster switching speed, without
the avalanche loss.
Acknowledgments
Concluding remarks. Monolithically integrated GaN cascode The authors acknowledge financial support from the UK
HEMTs open up new opportunities to achieve high efficiency Engineering and Physics Sciences Research Council (EPSRC)
power devices in the MHz range. It is however necessary to under EP/K014471/1 (Silicon Compatible GaN Power
overcome both problems with the magnitude of VTH of the Electronics).
39
18. Converter topologies in GaN loss and the size of the passive components. The optim
ization of the switching frequency is an important
Qingyun Huang, Ruiyang Yu and Alex Huang research topic.
2. Selection between hard switching and soft switching:
Department of Electrical and Computer Engineering, Univer
constant frequency hard switching modulation has low
sity of Texas at Austin, Austin, TX, United States of America
control complexity and high reliability, while the size of
the passive components is large. Variable frequency soft
Status. The commercialization of 600 V GaN power devices,
switching techniques can reduce the size of the passive
including the cascode-based FETs and the enhancement
components due to the high frequency. However, the
mode FETs, has enabled large scale R&D effort in academia
control complexity is significantly increased due to the
and industry [156] to evaluate the impact on converter design
variable frequency operation. The selection between hard
and performance. Compared with the best 600 V Si super-
switching and soft switching is a challenge.
junction (SJ) MOSFET, the input figure of merit (Ron · Ciss)
3. The reduction of the differential mode (DM) filter size
of 600 V GaN FET has been improved by about 20 times,
for soft-switched topologies: soft-switched topologies,
the output figure of merit (Ron · Coss) has been improved by
such as the TCM totem-pole PFC and the TCM inverter,
about five times while the reverse recovery figure of merit
have large input current ripples. It is still challenging to
(Ron · Qrr) has been improved by more than 40 times [156].
dramatically reduce the DM filter size even the frequency
These revolutionary improvements make GaN devices ideal
is high.
for high efficiency and high density power supply design,
4. New converter topologies in GaN: to take full advantage
especially for applications where the DC link voltage is
of the GaN device, developing new topologies and new
around 400 V. Many converter topologies exist that can take
power delivery architecture is a needed new challenge
advantages of the improved device performance by directly
replacing Si SJ MOSFETs with GaN FETs, operating at the
same switching frequency or at an increased frequency. Exam- Advances in science and technology to meet challenges. The
ple topologies include the active-clamped flyback converter progresses in addressing and investigating the previously
for universal AC/DC adapter which can use GaN devices in mentioned challenges are:
the primary side [157]; the soft-switched isolated DC/DC
1. The optimization of the switching frequency: the
converters, such as LLC resonant converter, phase-shift-full-
optimization of the switching frequency depends on

bridge (PSFB), dual-active-bridge (DAB), etc, which use the
the requirements of the application. For applications
GaN devices in the primary side or both sides [158]. Many
focusing on the high efficiency, lower frequency is pre-
designs explore the ability to push the switching frequency
ferred. For the applications requiring high density, such
to much higher value than the Si-based ones, achieving ultra-
as the Google Little Box challenge, higher frequency is
high efficiency and density. Some topologies are rarely used
preferred.
in the past, limited by the severe reverse recovery issue such
2. Selection between hard switching and soft switching:
as large Qrr and high recovery di/dt in the Si SJ MOSFET.
due to the elimination of the turn on loss, the zero-
However, by using the GaN devices where the reverse recov-
voltage-switching (ZVS) converters can realize high
ery Qrr is pretty much zero due to the absence of any minority
switching frequency. Thus, the size of all the passive
carrier injection, some of these topologies become feasible
components, especially the EMI filters, can be reduced.
and have demonstrated extraordinary performance. Exam-
In addition, the slower dv/dt of the ZVS converters also
ples include the 99% efficient totem-pole PFC, full-bridge
reduce the EMI noises. The soft-switched converters
(FB) photovoltaic (PV) inverter and the 98.8% efficient hard-
have demonstrated ultra-high density, over 145 W/
switching isolated full-bridge converter [102, 159–161]. In
inch3, on the totem-pole PFC and FB PV inverter [102,
addition to the circuits, improved modulations also make the
159, 161].
same topologies perform even better. The continuous conduc-
3. The reduction of the DM filter size for soft-switched
tion mode (CCM) totem-pole power factor corrector (PFC)
topologies: multiphase interleaved soft-switched topolo-
and FB PV inverter work with hard switching and constant
gies can solve this challenge [162]. The interleaving
frequency, typically only in the range of 50–100 kHz. How-
technologies significantly reduce the current ripples. The
ever, the triangular current mode (TCM) totem-pole PFC and
DM filter size is optimized, too.
FB PV inverter can work with soft switching and variable
4. New converter topologies in GaN: the upcoming
frequency in the range of 100 kHz–3 MHz [102, 159, 161].
GaN-based AC switch could enable a number of new
With these GaN-based topologies, the efficiency and the
high-performance topologies. The resonant converter
power density are significantly improved compared with the
with GaN AC switch not only realizes high efficiency,
Si-based solutions.
but also achieves the wide input and wide output voltage
conversion [163]. A new single stage solution, the iso-
Current and future challenges. The main challenges for the
lated AC/DC DAB converter with GaN AC switches on
GaN based converter topologies are:
the primary side, can be used for on-board charger and
1. The optimization of the switching frequency: the battery system with significantly improving the system
switching frequency determines the frequency related efficiency [164].
40
Table 2. Benchmark of the state of the art GaN-based converters.
Frequency Efficiency Power density

65 W active-clamp Flyback Charger [157] 1 MHz 93.0% (full load) 25 W/inch3
2.4 kW FB isolated DC/DC [160] 50 kHz 98.6% (full load) 116 W/inch3
1 kW TCM two-phase totem-pole PFC [159] 4 MHz (max) 98.7% (full load) 220 W/inch3 (no bulky capacitors)
2 kW multiphase TCM FB PV inverter [161] 35–240 kHz 95.4% (CEC) 150 W/inch3
Concluding remarks. The GaN-based converters have dem- innovation and the optimization of the converter topologies
onstrated extraordinary performance. As shown in table 2, the in GaN, the density and efficiency will be further improved.
power density and the efficiency have been improved signifi- Even though the cost of the devices is increased, the high den-
cantly based on these benchmark GaN converters. With the sity and efficiency will reduce the system cost in the future.
41
19. Fast switching with GaN and dynamic shows the highest dynamic on-resistance with a ratio of
on-resistance from application view-point rds,on (t1)/Rds,on,typ = 4.3 while it decreases to 2.5 after 300
µs. For example, the turn on time of a DC/DC converter
Thomas Heckel, Stefan Zeltner, Bernd Eckardt operating at a moderate switching frequency of 100 kHz
and Martin März and a duty cycle of 50% is only 5 µs. This results in an
effective on-resistance of 4.2 · Rds,on,typ for the system
Fraunhofer Institute for Integrated Systems and Device
design and therefore in higher losses and lower efficiency.
Technology, IISB, Germany
The influence of this issue becomes even worse when the
switching frequency is increased.
Status. GaN semiconductors have gained popularity in GHz
3. Reverse conduction capability: in half-bridge configura-
applications, while power electronic applications are still in
tion, reverse conduction capability is required for negative
the early stages of development. The focus of this section is
drain currents. Though there is no intrinsic body-diode in
the application of GaN devices for power electronics with
GaN transistors, current can flow from source to drain.
device breakdown voltages from 400 V up to 900 V. Applica-
However, the source–drain-voltage drop vsd increases
tions of GaN transistors include uni- and bidirectional DC/DC
with decreasing gate–source-voltage vgs. This is valid for
and AC/DC converters, inverters for high-speed motor drives
all commercially GaN transistors known to the authors.
as well as inductive heating and wireless power transmission
For example, for some GaN transistors, the forward
(figure 34). High system efficiencies and power densities are
voltage drop vsd is 8 V or higher, when the gate is kept in
the main requirements for these applications. This is enabled
the off state with vgs = −5 V.
by low conduction and low switching losses from a semicon-
4. Parasitics, packaging, controllability and EMI: in general,
ductor point of view. GaN transistors allow both aspects. Low
the influence of parasitic inductances and capacitances
conduction losses are achieved by GaN transistors with low
is the same as with Si and SiC circuits. This situation
area-related on-resistance compared to silicon (Si) and silicon
worsens for GaN transistors due to tighter gate voltage
carbide (SiC) counterparts. Low switching losses are achieved
margins compared to Si and SiC devices which can lead
by fast switching between the on- and off state. GaN transis-
to device destruction and phase leg short circuits. In gen-
tors show a purely capacitive behaviour due to their unipolar
eral, fast switching semiconductors enable higher power
device characteristic, while Si- and SiC-MOSFETs lack from
densities, but require additional filters for electromagnetic
reverse recovery charge due to intrinsic bipolar body diodes
interference (EMI), also.
[165]. Regarding the switching speed of the drain–source-
5. Reliability issues and countermeasures are discussed in
voltage, 5–20 V ns−1 is considered as ‘fast’ for Si devices.
section 8.
Slew rates are typically limited to the range of 1–16 V ns−1
in motor drive applications [166]. In contrast, optimized SiC
and GaN circuits allow up to 200 V ns−1 and 500 V ns−1, Advances in science and technology to meet challenges. The
respectively [167, 168]. The possibility of ultra-fast switching progresses in addressing and investigating the challenges from
exceeds the boundary conditions of most applications. How- the preceding subsection are:
ever, operating two 600 V transistors in half-bridge configura-
1. Normally-off characteristic: this challenge must be
tion for e.g. hard-switching bidirectional DC/DC converters,
solved at the level of the device technology. Alternatively,
Si-MOSFETs are not suitable due to their bipolar body diode.
a cascode circuit with normally-off behaviour can be real-
SiC-MOSFETs with orders of magnitude lower reverse recov-
ized by using a normally-on high-voltage GaN transistor
ery charge are suitable, but higher system efficiency can be
and a normally-off low-voltage Si transistor. However,
achieved with unipolar GaN-transistors.
recent studies have shown that the switching speed of cas-
codes is barely adjustable without additional components
Current and future challenges. The main challenges for GaN
inside the cascode [171]. The necessity of an additional
transistors in power electronic applications are: Si transistor for the cascode is another disadvantage of
1. Normally-off characteristic: system developers require the cascode compared to normally-off GaN transistors.
normally-off devices because of safety reasons, while the All commercial GaN transistors at the time of this study
realization of normally-off device characteristics is still a show normally-off behaviour by intrinsic normally-off
main research topic (section 8). characteristic or cascode configuration.
2. Dynamic on-resistance: some GaN transistors show 2. Dynamic on-resistance: as can be seen in figure 35, the
dynamic on-resistance. After turn-on, their on-resistance GaN transistor #3 shows no dynamic on-resistance for
rds,on is higher than the static value Rds,on,typ and decays the full time scale. The manufacturer applies an additional
over time until it reaches the static value Rds,on,typ. The p-GaN-layer to provide the injection of holes from the
main reason is a physical phenomenon called ‘trapping’ drain and dynamic on-resistance can be prevented suc-
due to high electric-field strengths in the off-state, when cessfully [172]. However, other manufacturers still face
the blocking voltage is applied (drain–source-voltage is the challenge of the dynamic on-resistance which is also
e.g. 400 V) [169, 170]. Figure 35 shows a comparison indicated by significantly increased scientific activities
of three devices from different manufacturers. GaN #1 regarding this topic.
42
Figure 34. (a) Demonstrator of 20 W inductive power transmission

for high-speed rotating applications (top) and corresponding Figure 35. Measurement of the on-resistance of three GaN
matchbox-sized GaN power electronics (bottom) [173]. (b) transistors from different manufacturers. The drain–source voltage
Demonstrator of 6 kW on-board charger for electric vehicles with in the off-state is kept at 50% of the drain–source breakdown
3 kW l−1 power density (top) and power electronics setup (bottom) voltage for 20 s.
[174]. (b) Reproduced with permission from [174].
The issues discussed in this section will diminish with further
research similar to the advances with Si and SiC devices in the
3. Reverse conduction capability: the high forward voltage last 70 and 20 years, respectively.
drop in reverse conduction mode of GaN transistors
can be avoided by using synchronous rectification. This
means to turn the GaN transistor on shortly after the cur Acknowledgments
rent has commutated to the transistor in reverse direction.
In contrast to a diode, the transistor has to be turned off This contribution was supported by the Bavarian Ministry of
before the complementary transistor of the half-bridge Economic Affairs and Media, Energy and Technology as a part
turns on. Otherwise, phase leg short circuits may occur of the Bavarian project ‘Leistungszentrum Elektroniksysteme
which lead to immediate destruction of both switches. (LZE)’ and by the German Federal Ministry of Education and
In this case, special protection circuits are necessary. Research (BMBF) through grant ‘ZuGaNG’ FKZ: 16ES0084.
Additionally, the adaption of the dead-time between the
half-bridge switching actions helps to increase the effi-
ciency even more. ORCID iDs
4. Parasitics, packaging, controllability and EMI: integration
Matteo Borga https://orcid.org/0000-0003-3087-6612
of GaN transistors and gate drivers within one package
T Bouchet https://orcid.org/0000-0003-2723-1602
will minimize the effects of parasitic circuit elements.
Paul R Chalker https://orcid.org/0000-0002-2295-6332
The next step is to integrate GaN transistors and drivers
M Charles https://orcid.org/0000-0003-0668-8865
within one chip which has already been demonstrated. To
Kevin J Chen https://orcid.org/0000-0002-0659-2022
gain the most advantage for power electronic systems,
Rongming Chu https://orcid.org/0000-0003-3262-5120
the integration of GaN transistor, gate drivers, auxiliary
Carlo De Santi https://orcid.org/0000-0001-6064-077X
circuits and DC link filters within one device will allow
Maria Merlyne De Souza https://orcid.org/0000-0002-
minimum parasitic circuit inductance and high switching
7804-7154
speeds. The EMI can also be improved by the enclosure
Stefaan Decoutere https://orcid.org/0000-0001-6632-6239
on low footprint as well as novel active filters.
L Di Cioccio https://orcid.org/0000-0002-9327-7118
Takashi Egawa https://orcid.org/0000-0002-0335-0044
Concluding remarks. GaN transistors have evolved dramati- P Fay https://orcid.org/0000-0003-1239-4978
cally in the last ten years and enable power electronic sys- Joseph J Freedsman https://orcid.org/0000-0002-1819-7900
tems with highest efficiencies due to their unipolar device Oliver Häberlen https://orcid.org/0000-0002-9102-1071
characteristic and low area-specific on-resistance (figure 35). Mengyuan Hua https://orcid.org/0000-0003-3016-1588
43
Qingyun Huang https://orcid.org/0000-0002-5498-9841 [14] Bayram C, Kim J, Cheng C, Ott J, Reuter K, Bedell S,
Alex Huang https://orcid.org/0000-0003-3427-0335 Sadana D, Park H and Dimitrakopoulos C 2015 Vertical
thinking in blue light emitting diodes: GaN on graphene
Martin Kuball https://orcid.org/0000-0003-3070-1070
technology Oxide-Based Mater. Devices VI 9364 93641C
Kean Boon Lee https://orcid.org/0000-0002-5374-2767 [15] Ayari T, Sundaram S, Li X, El Gmili Y, Voss P, Salvestrini J
Denis Marcon https://orcid.org/0000-0002-2211-9198 and Ougazzaden A 2016 Wafer-scale controlled exfoliation
R McCarthy https://orcid.org/0000-0002-3184-0286 of metal organize vapor phase epitaxy grown InGaN/
Gaudenzio Meneghesso https://orcid.org/0000-0002-6715- GaN multi quantum well structures using low-tack two-
dimensional layered h-BN Appl. Phys. Lett. 108 171106
4827
[16] Stonas A, MacDonald N, Turner K, DenBaars S and Hu E
Matteo Meneghini https://orcid.org/0000-0003-2421-505X 2001 Photoelectrochemical undercut etching for fabrication
E Morvan https://orcid.org/0000-0001-6880-3174 of GaN microelectromechanical systems J. Vac. Sci.
A Nakajima https://orcid.org/0000-0002-7307-9763 Technol. B 19 2838
E M S Narayanan https://orcid.org/0000-0001-6832-1300 [17] Youtsey C et al 2017 Wafer-scale epitaxial lift-off of GaN
using bandgap-selective photoenhanced wet etching Phys.
R Reddy https://orcid.org/0000-0002-1309-9797
Status Solidi b 254 1600774
Min Sun https://orcid.org/0000-0003-4858-8264 [18] Wang J, Youtsey C, McCarthy R, Reddy R, Allen N, Guido L,
Nicola Trivellin https://orcid.org/0000-0002-0916-1877 Xie J, Beam E and Fay P 2017 Thin-film GaN Schottky
Michael J Uren https://orcid.org/0000-0002-8842-0426 diodes formed by epitaxial lift-off Appl. Phys. Lett.
Marleen Van Hove https://orcid.org/0000-0002-9409-7178 110 173503
[19] Hiroki M, Kumakura K and Yamamoto H Efficient heat
David J Wallis https://orcid.org/0000-0002-0475-7583
dissipation in AlGaN/GaN high electron mobility transistors
J Wang https://orcid.org/0000-0002-4126-8543 by substrate-transfer technique Phys. Status Solidi a 214
J Xie https://orcid.org/0000-0001-6144-5714 1600845
Shu Yang https://orcid.org/0000-0002-4526-9535 Lu B and Palacios T 2010 High breakdown (>1500 V)
C Youtsey https://orcid.org/0000-0001-7804-241X AlGaN/GaN HEMTs by substrate-transfer technology
IEEE Electron Device Lett. 31 951
Riuyang Yu https://orcid.org/0000-0002-4409-8092
[20] Ramesh P, Krishnamoorthy S, Rajan S and Washington G
Enrico Zanoni https://orcid.org/0000-0001-7349-9656 2014 Energy band engineering for photoelectrochemical
etching of GaN/InGaN heterostructures Appl. Phys. Lett.
104 243503
References
[21] Bouchet T 2018 GaN/Si a new era of energy conversion: road
map and demonstrators APEC 2018 (San Antonio, TX)
[1] Visalli D, Van Hove M, Derluyn J, Degroote S, Leys M, [22] Morita T, Tamura S, Anda Y, Ishida M, Uemoto Y, Ueda T,
Cheng K, Germain M and Borghs G 2009 Japan. J. Appl. Tanaka T and Ueda D 2011 99.3% efficiency of three-phase
Phys. 48 04C101 inverter for motor drive using GaN-based gate injection
[2] Srivastava P et al 2011 IEEE Electron Device Lett. 32 30–2 transistors IEEE Applied Power Electronics Conf. Expo
[3] Van Hove M, Kang X, Stoffels S, Wellekens D, Ronchi N, p 481
Venegas R, Geens K and Decoutere S 2013 IEEE Trans. [23] Di Cioccio L et al 2017 From epitaxy to converters topologies
Electron Devices 60 3071–8 what issues for 200 mm GaN/Si? IEDM 2017
[4] Cheng K et al 2012 Appl. Phys. Express 5 011002 [24] Marchand H, Whao L, Zhang N, Moran B, Coffie R,
[5] De Jaeger B, Van Hove M, Wellekens D, Kang X, Liang H, Mishra U K, Speck J S and DenBaars S P 2001
Mannaert G, Geens K and Decoutere S 2012 IEEE 24th Int. Metalorganic chemical vapor deposition of GaN on
Symp. Power Semiconductor and ICs pp 49–52 Si(1 1 1): stress control and application to field-effect
[6] Marcon D, De Jaeger B, Halder S, Vranckx N, Mannaert G, transistors J. Appl. Phys. 89 7846
Van Hove M and Decoutere S 2013 IEEE Trans. Semicond. [25] Jaud M-A, Baines Y, Charles M, Morvan E, Scheiblin P,
Manuf. 26 361–7 Torres A, Plissionnier M and Barbé J-C 2017 TCAD for
[7] Lenci S, De Jaeger B, Carbonell L, Hu J, Mannaert G, gate stack optimization in pGaN gate HEMT devices
Wellekens D, You S, Bakeroot B and Decoutere S 2013 SISPAD (Kamakura) pp 113–6
IEEE Electron Device Lett. 34 1035–7 [26] Baines Y, Buckley J, Biscarrat J, Garnier G, Charles M,
[8] Marcon D et al 2015 Proc. SPIE 9363 936311 Vandendaele W, Gillot C and Plissonnier M 2017 Coherent
[9] Marcon D, Saripalli Y N and Decoutere S 2015 Proc. IEEE tunneling in an AlGaN/AlN/GaN heterojunction captured
Int. Electron Devices Meeting pp 414–7 through an analogy with a MOS contact Sci Rep. 7 8177
[10] Geens K, Van Hove M, Li X, Zhao M, Šatka A, Vincze A [27] Grezaud R, Ayel F, Chapel A and Bergogne D 2016 Wide
and Decoutere S 2017 Proc. 41th Worskshop Compound band gap power transistors gate driver cutting edge bloc
Semiconductor Devices and Integrated Circuits pp 97–8 functions CIPS pp 1–6
[11] Hwang D, Yonkee B, Addin B, Farrell R, Nakamura S, Speck J [28] Kato S, Satoh Y, Sasaki H, Masayuki I and Yoshida S 2007
and DenBaars S 2016 Photoelectrochemical liftoff of LEDs C-doped GaN buffer layers with high breakdown voltages
grown on freestanding c-plane GaN substrates Opt. Express for high-power operation AlGaN/GaN HFETs on 4-in Si
24 22875–80 substrates by MOVPE J. Cryst. Growth 298 831–4
[12] Rajan A et al 2016 Wafer-scale epitaxial lift-off of [29] Zhu D, Wallis D J and Humphreys C J 2013 Prospects of
optoelectronic grade GaN from a GaN substrate using III-nitride optoelectronics grown on Si Rep. Prog. Phys.
a sacrificial ZnO interlayer J. Phys. D: Appl. Phys. 76 106501
49 315105 [30] Weeks T W, Piner E L, Gehrke T and Linthicum K J 2003
[13] Meyer D, Downey B, Katzer D, Nepal N, Wheeler V, Gallium nitride materials and methods USA Patent US
Hardy M, Anderson T and Storm D 2016 Epitaxial lift- 6,617,060 B2
off and transfer of III-N materials and devices from SiC [31] Ikeda N, Niiyama Y, Kambayashi H, Sato Y, Nomura T,
substrates IEEE Trans. Semicond. Manuf. 29 384 Kato S and Yoshida S 2010 GaN power transistors on
44
si substrates for switching applications Proc. IEEE barrier diodes with high-mobility drift layers on low-
98 1151–61 dislocation-density GaN substrates Appl. Phys. Express
[32] Lyons J L, Janotti A and Van de Walle C G 2014 Effects of 3 081001
carbon on the electrical and optical properties of InN, GaN, [51] Zhang Y, Sun M, Liu Z, Piedra D, Pan M, Gao X, Lin Y,
and AlN Phys. Rev. B 89 035204 Zubair A, Yu L and Palacios T 2016 Novel GaN trench MIS
[33] Bahat-Treidel E, Brunner F, Hilt O, Cho E, Wurfl J and barrier Schottky rectifiers with implanted field rings IEEE
Trankle G 2010 AlGaN/GaN/GaN:C back-barrier HFETs Int. Electron Devices Meeting pp 10.2.1–4
with breakdown voltage of over 1 kV and low RON x A [52] Zhang Y et al 2017 Vertical GaN junction barrier Schottky
IEEE Trans. Electron Devices 57 3050–8 rectifiers by selective ion implantation IEEE Electron
[34] Wuerfl J, Hilt O, Bahat-Treidel E, Zhytnytska R, Kotara P, Device Lett. 38 1097–100
Brunner F, Krueger O and Weyers M 2013 Techniques [53] Yeluri R, Lu J, Hurni C A, Browne D A, Chowdhury S,
towards GaN power transistors with improved high voltage Keller S, Speck J S and Mishra U K 2015 Design,
dynamic switching properties IEDM 2013 pp 6.1.1–4 fabrication, and performance analysis of GaN vertical
[35] Uren M J, Karboyan S, Chatterjee I, Pooth A, Moens P, electron transistors with a buried p/n junction Appl. Phys.
Banerjee A and Kuball M 2017 ‘Leaky dielectric’ model Lett. 106 183502
for the suppression of dynamic RON in carbon-doped [54] Shibata D, Kajitani R, Ogawa M, Tanaka K, Tamura S,
AlGaN/GaN HEMTs IEEE Trans. Electron Devices Hatsuda T, Ishida M and Ueda T 2016 1.7 kV/1.0 mΩcm2
64 2826–34 normally-off vertical GaN transistor on GaN substrate with
[36] Moens P et al 2017 Negative dynamic RON in AlGaN/GaN regrown p-GaN/AlGaN/GaN semipolar gate structure
power devices ISPSD (Sapporo, Japan) pp 97–100 IEEE Int. Electron Devices Meeting pp 10.1.1–4
[37] Waller W M, Gajda M, Pandey S, Donkers J J T M, Calton D, [55] Oka T, Ueno Y, Ina T and Hasegawa K 2014 Vertical
Croon J, Šonský J, Uren M J and Kuball M 2017 Control GaN-based trench metal oxide semiconductor field-
of buffer-induced current collapse in AlGaN/GaN HEMTs effect transistors on a free-standing GaN substrate
using SiNx deposition IEEE Trans. Electron Devices with blocking voltage of 1.6 kV Appl. Phys. Express
64 4044–9 7 021002
[38] www.transphormusa.com/products/ [56] Sun M, Zhang Y, Gao X and Palacios T 2017 High-
[39] Ishikawa H, Zhao G-Y, Nakada N, Egawa T, Jimbo T and performance GaN vertical fin power transistors on
Umeno M 1999 GaN on Si substrate with AlGaN/AlN bulk GaN substrates IEEE Electron Device Lett.
intermediate layer Japan. J. Appl. Phys. 38 L492–4 38 509–12
[40] Selvaraj S L, Suzue T and Egawa T 2009 Influence of deep [57] Chen K J, Yang S, Liu S, Liu C and Hua M 2016 Toward
pits on the breakdown of metalorganic chemical vapor reliable MIS- and MOS-gate structures for GaN lateral
deposition grown AlGaN/GaN high electron mobility power devices Phys. Status Solidi a 213 861
transistors on silicon Appl. Phys. Exp. 2 111005 [58] Khan M A, Simin G, Yang J, Zhang J P, Koudymov A,
[41] Freedsman J J, Watanabe A, Yamaoka Y, Kubo T and Shur M S, Gaska R, Hu X and Tarakji A 2003 Insulating
Egawa T 2015 Influence of AlN nucleation layer on vertical gate III-N heterostructure field-effect transistors for high-
breakdown characteristics for GaN-on-Si Phys. Status power microwave and switching applications IEEE Trans.
Solidi a 213 424–8 Microw. Theory Tech. 51 624
[42] Egawa T 2012 Heteroepitaxial growth and power electronics [59] Moens P et al 2014 An industrial process for 650V rated GaN-
using AlGaN/GaN HEMT on Si Proc. Int. Electron Devices on-Si power devices using in-situ SiN as a gate dielectric
Meeting pp 613–6 Proc. 26th Int. Symp. Power Semicond. Devices and ICs
[43] Rowena I B, Selvaraj S L and Egawa T 2011 Buffer thickness vol 374
contribution to suppress vertical leakage current with high [60] Lagger P, Reiner M, Pogany D and Ostermaier C 2014
breakdown field (2.3 MV/cm) for GaN on Si IEEE Electron Comprehensive study of the complex dynamics of forward
Device Lett. 32 1534–6 bias-induced threshold voltage drifts in GaN based MIS-
[44] Selvaraj S L, Watanabe A, Wakejima A and Egawa T 2012 HEMTs by stress/recovery experiments IEEE Trans.
1.4-kV Breakdown voltage for AlGaN/GaN high-electron- Electron Devices 61 1022
mobility transistors on silicon substrate IEEE Electron [61] Yang S, Lu Y, Wang H, Liu S, Liu C and Chen K J 2016
Device Lett. 33 1375–7 Dynamic gate stress-induced VTH shift and its impact on
[45] Zou X, Zhang X, Lu X, Tang C W and Lau K M 2016 Fully dynamic RON in GaN MIS-HEMTs IEEE Elec. Dev. Lett.
vertical GaN p-i-n diodes using GaN-on-Si epilayers 37 157
IEEE Electron Device Lett. 37 636–9 [62] Yatabe Z, Asubar J T and Hashizume T 2016 Insulated gate
[46] Zhang Y, Piedra D, Sun M, Hennig J, Dadgar A, Yu L and and surface passivation structures for GaN-based power
Palacios T 2017 High-performance quasi-and fully-vertical transistors J. Phys. D: Appl. Phys. 49 393001
GaN-on-Si pn diodes IEEE Electron Device Lett. 38 248–51 [63] Miao M S, Weber J R and de Walle C G V 2010 Oxidation and
[47] Mase S, Urayama Y, Hamada T, Freedsman J J and Egawa T the origin of the two-dimensional electron gas in AlGaN/
2016 Novel fully vertical GaN p-n diode on Si substrate GaN heterostructures J. Appl. Phys. 107 123713
grown by metalorganic chemical vapor deposition Appl. [64] Wang R, Cai Y, Tang C-W, Lau K M and Chen K J 2006
Phys. Exp. 9 111005 Enhancement-mode Si3N4/AlGaN/GaN MISHFETs IEEE
[48] Zhang Y, Sun M, Liu Z, Piedra D, Lee H-S, Gao F, Electron Device Lett. 27 793
Fujishima T and Palacios T 2013 Electrothermal simulation [65] Yang S, Tang Z, Wong K-Y, Lin Y-S, Liu C, Lu Y, Huang S
and thermal performance study of GaN vertical and lateral and Chen K J 2013 High-quality interface in Al2O3/GaN/
power transistors IEEE Trans. Electron Devices 60 2224–30 AlGaN/GaN MIS structures with in situ pre-gate plasma
[49] Kizilyalli I C, Edwards A P, Aktas O, Prunty T and Bour D nitridation IEEE Electron Device Lett. 34 1497
2015 Vertical power p-n diodes based on bulk GaN IEEE [66] Hua M, Zhang Z, Wei J, Lei J, Tang G, Fu K, Cai Y, Zhang B
Trans. Electron Devices 62 414–22 and Chen K J 2016 Integration of LPCVD-SiNx gate
[50] Saitoh Y, Sumiyoshi K, Okada M, Horii T, Miyazaki T, dielectric with recessed-gate E-mode GaN MIS-FETs:
Shiomi H, Ueno M, Katayama K, Kiyama M and toward high performance, high stability and long TDDB
Nakamura T 2010 Extremely low on-resistance and high lifetime Int. Electron Device Meeting (San Francisco, CA,
breakdown voltage observed in vertical GaN Schottky USA, 5–7 December 2016)
45
[67] Meneghini M et al 2017 Reliability and failure analysis in [82] Li X, Floros K, Cho S J, Guiney I, Moran D and Thayne I G
power GaN-HEMTs: an overview IEEE Int. Reliability 2016 An atomic layer etch process based on a cycled
Physics Symp. (IRPS) (Monterey, CA) pp 3B-2.1–8 procedure of chlorination in Cl2 and argon plasma removal
[68] Rossetto I, Meneghini M, Pandey S, Gajda M, Hurkx G A, of chlorines for GaN based device fabrication Proc. 8th
Croon J A, Šonský J, Meneghesso G and Zanoni E 2017 Int. Symp. Advanced Plasma Science and its Applications
Field-related failure of GaN-on-Si HEMTs; dependence for Nitrides and Nanomaterials
on device geometry and passivation IEEE Trans. Electron [83] Chong W, Meng-Di Z, Yun-Long H, Xue-Feng Z, Xiao-
Devices 64 73 Xiao W, Wei M, Xiao-Hua M, Jin-Cheng Z and Yue H
[69] Meneghini M et al 2017 Degradation of GaN-HEMTs with 2017 Optimisation of ohmic contact for AlGaNGaN
p-GaN gate: dependence on temperature and on geometry HEMT by introducing patterned etching in ohmic area
IEEE Int. Reliability Physics Symp. (IRPS) (Monterey, CA) Solid-State Electron. 129 114–9
pp 4B5.1–5 [84] Hemakumara D, Li X, Cho S J, Floros K, Guiney I,
[70] Dalcanale S, Meneghini M, Tajalli A, Rossetto I, Ruzzarin M, Moran D, Humphreys C, O’Mahoney A, Knoops H
Zanoni E, Meneghesso G, Moens P, Banerjee A and and Thayne I 2017 The impact on GaN MOS capacitor
Vandeweghe S 2017 GaN-based MIS-HEMTs: impact of performance on in-situ processing in a clustered ALD/ICP/
cascode-mode high temperature source current stress on RIE Tool Proc. Int. Conf. on Atomic Layer Deposition
NBTI shift IEEE Int. Reliability Physics Symp. (IRPS) [85] Hung T, Esposto M and Rajan S 2011 Appl. Phys. Lett.
(Monterey, CA) pp 4B-1.1–5 99 162104
[71] Marcon D et al 2010 A comprehensive reliability investigation [86] Hung T-H, Park P S, Krishnamoorthy S, Nath D N and
of the voltage, temperature and device geometry Rajan S 2014 IEEE Electron Device Lett. 35 312
dependence of the gate degradation on state-of-the-art [87] Robertson J and Falabretti B 2006 J. Appl. Phys. 100 014111
GaN-on-Si HEMTs IEEE Int. Electron Devices Meeting [88] Eller B S, Yang J and Nemanich R J 2013 J. Vac. Sci.
(IEDM) (San Francisco, CA) pp 472–5 Technol. A 31 050807
[72] Hu J et al 2017 Time-dependent breakdown mechanisms and [89] Zhang Y, Sun M, Joglekar S J, Fujishima T and Palacios T
reliability improvement in edge terminated AlGaN/GaN 2013 Appl. Phys. Lett. 103 033524
Schottky diodes under HTRB tests IEEE Electron Device [90] Roberts J W, Chalker P R, Lee K B, Houston P A, Cho S J,
Lett. 38 371–4 Thayne I G, Guiney I, Wallis D and Humphreys C J 2016
[73] Meneghini M, Cibin G, Hurkx G A M, Ivo P, Šonský J, Appl. Phys. Lett. 108 072901
Croon J A, Meneghesso G and Zanoni E 2014 Off-state [91] Hsieh T-E, Chang E Y, Song Y-Z, Lin Y-C, Wang H-C,
degradation of AlGaN/GaN power HEMTs: experimental Liu S-C, Salahuddin S and Hu C C 2014 IEEE Electron
demonstration of time-dependent drain-source breakdown Device Lett. 35 732
IEEE Trans. Electron Devices 61 1987–92 [92] Chu R, Cao Y, Chen M, Li R and Zehnder D 2016 An
[74] Rossetto I, Meneghini M, Canato E, Barbato M, Stoffels S, experimental demonstration of GaN CMOS technology
Posthuma N, Decoutere S, Tallarico A N, Meneghesso G IEEE Electron Device Lett. 37 269–71
and Zanoni E 2017 Field- and current-driven degradation of [93] Kumar A and De Souza M M 2016 IEDM16-180
GaN-based power HEMTs with p-GaN gate: dependence on [94] Chen K J, Häberlen O, Lidow A, Tsai C L, Ueda T,
Mg-doping level Microelectron. Reliab. 76–7 298–303 Uemoto Y and Wu Y 2017 GaN-on-Si power technology:
[75] Borga M, Meneghini M, Rossetto I, Stoffels S, Posthuma N, devices and applications IEEE Trans. Electron Devices
van Hove M, Marcon D, Decoutere S, Meneghesso G 64 779–95
and Zanoni E 2017 Evidence of time-dependent vertical [95] Kinzer D 2017 GaN Power IC technology: past, present, and
breakdown in GaN-on-SI HEMTs IEEE Trans. Electron future, plenary 29th ISPSD 2017
Devices 64 3616–21 [96] Kinzer D 2016 Breaking speed limits with GaN Power
[76] Lagger P et al 2014 Role of the dielectric for the charging ICs Keynote APEC 2016 (www.navitassemi.com/
dynamics of the dielectric/barrier interface in AlGaN/ white-papers-articles/)
GaN based metal-insulator-semiconductor structures under [97] Oliver S and Giandalia M 2016 Next-generation
forward gate bias stress Appl. Phys. Lett. 105 033512 GaN isolators/level-shifters for high frequency,
[77] Guo A and del Alamo J A 2017 Unified mechanism for high efficiency power conversion PSMA Industry
positive and negative bias temperature instability in GaN Session, APEC 2016 (www.navitassemi.com/
MOSFETs IEEE Trans. Electron Devices 64 2142–7 white-papers-articles/)
[78] Li X, Floros K, Ternent G, Al-Khalidi A, Wasige E and [98] Huang X, Feng J, Du W, Lee F C and Li Q 2017 Design
Thayne I G 2015 Effect of SiH4 inductively coupled plasma consideration of MHz active clamp flyback converter with
surface treatment on low temperature and low resistance GaN devices for low power adapter application APEC
ohmic contacts for AlGaN/GaN-based power device 2017
Proc. 7th Int. Symp. on Advanced Plasma Science and its [99] Xue L and Zhang J 2017 Active clamp flyback using GaN
Applications for Nitrides and Nanomaterials power IC for power adapter applications APEC 2017
[79] Waller W M, Gajda M, Pandey S, Donkers J J T M, Calton D, [100] Ribarich T and Oliver S 2017 State-of-the-art GaN power
Croon J, Karboyan S, Sonsky J, Uren M J and Kuball M IC-based 150 W AC-DC adapter PCIM 2017
2017 Impact of silicon nitride stoichiometry on the [101] Sheridan G 2016 Speed drives performance Keynote,
effectiveness of AlGaN/GaN HEMT field plates IEEE 4th IEEE WiPDA (www.navitassemi.com/
Trans. Electron Devices 64 1197–202 white-papers-articles/)
[80] Cho S J, Li X, Guiney I, Floros K, Moran D A J, [102] Huang Q, Yu R, Huang A Q and Yu W 2017 Adaptive zero-
Hemakumara D, Wallis D J, Humphreys C and Thayne I G voltage-switching control and hybrid current control
2017 Low leakage currents in AlGaN/GaN high electron for high efficiency GaN-based MHz totem-pole PFC
mobility transistors by employing a high stress ICP-CVD rectifier 2017 IEEE Applied Power Electronics Conf. and
SiNx surface passivation Proc. UK Semiconductors Exposition (Tampa, FL) pp 1763–70
[81] Zaidi Z H, Lee K B, Guiney I, Qian H, Jiang S, Wallis D J, [103] Oliver S, Xue L and Huang P 2017 From science fiction to
Humphreys C J and Houston P A 2015 Enhancement industry fact: GaN power ICs enable the new revolution
mode operation in AlInN/GaN (MIS)HEMTs on Si in power electronics Bodo’s Power Systems December
substrates using a fluorine implant Semicond. Sci. Technol. 2017 (http://www.bodospower.com/restricted/downloads/
30 105007 bp_2017_12.pdf)
46
[104] Ohashi H and Omura I 2013 IEEE Trans. Electron Devices [127] Li G, Wang R, Song B, Verma J, Cao Y, Ganguly S, Verma A,
60 528–34 Guo J, Xing H G and Jena D 2013 Polarization-induced
[105] Khan M A et al 1991 Appl. Phys. Lett. 58 526 GaN-on-insulator E/D mode p-channel heterostructure
[106] Khan M A et al 1993 Appl. Phys. Lett. 63 1214 FETs IEEE Electron Device Lett. 34 852–4
[107] Nakajima A et al 2006 Appl. Phys. Lett. 89 193501 [128] Hahn H, Reuters B, Pooth A, Noculak A, Kalisch H and
[108] Nakajima A et al 2010 Appl. Phys. Express 3 121004 Vescan A 2013 First small-signal data of GaN-based
[109] Nakajima A et al 2011 IEEE Electron Device Lett. 32 54 p-channel heterostructure field effect transistors Japan. J.
[110] Unni V et al 2014 Proc. Int. Symp. Power Semiconductor Appl. Phys. 52 128001
Devices and ICs pp 245–8 [129] Hahn H, Reuters B, Kotzea S, Lukens G, Geipel S, Kalisch H
[111] Kawai H et al 2017 Phys. Status Solidi 214 1600834 and Vescan A 2014 First monolithic integration of
[112] Nakajima A et al 2017 IET Power Electron. submitted GaN-based enhancement mode n-channel and p-channel
[113] Unni V and Sankara Narayanan E M 2017 Japan. J. Appl. heterostructure field effect transistors 72nd Annual Device
Phys. 56 04CG02 Research Conf. (IEEE) pp 259–60
[114] Disney D, Letavic T, Trajkovic T, Terashima T and [130] Simon J, Protasenko V, Lian C, Xing H and Jena D 2010
Nakagawa A 2017 High-voltage integrated circuits: Polarization-induced hole doping in wide–band-gap
history, state of the art, and future prospects IEEE Trans. uniaxial semiconductor heterostructures Science
Electron Devices 64 659–73 327 60–4
[115] Unni V, Kawai H and Narayanan E M S 2014 Crosstalk [131] Hahn H, Reuters B, Pooth A, Hollander B, Heuken M,
in monolithic GaN-on-silicon power electronic devices Kalisch H and Vescan A 2013 P-channel enhancement
Microelectron. Reliab. 54 2242–7 and depletion mode GaN-based HFETs with
[116] Jiang Q, Liu C, Lu Y and Chen K J 2013 1.4 kV AlGaN/GaN quaternary backbarriers IEEE Trans. Electron Devices
HEMTs on a GaN-on-SOI platform IEEE Electron Device 60 3005–11
Lett. 34 357–9 [132] Reuters B, Hahn H, Pooth A, Hollander B, Breuer U,
[117] Li X, Hove M V, Zhao M, Geens K, Lempinen V-P, Heuken M, Kalisch H and Vescan A 2014 Fabrication
Sormunen J, Groeseneken G and Decoutere S 2017 of p-channel heterostructure field effect transistors with
200 V enhancement-mode p-GaN HEMTs fabricated polarization-induced two-dimensional hole gases at
on 200 mm GaN-on-SOI with trench isolation for monolithic metal—polar GaN/AlInGaN interfaces J. Phys. D: Appl.
integration IEEE Electron Device Lett. 38 918–21 Phys. 47 175103
[118] Nakajima A, Menon K G, Dhyani M H, Sumida Y, Kawai H [133] Kumar A and De Souza M M 2016 Extending the bounds of
and Narayanan E M S 2012 GaN-based bidirectional super performance in E-mode p-channel GaN MOSHFETs IEEE
HFETs using polarization junction concept on insulator Int. Electron Devices Meeting (IEEE) pp 7.4.1–4
substrate Proc. ISPSD (Bruges, Belgium) pp 256–8 [134] Nakajima A, Kubota S, Kayanuma R, Tsutsui K,
[119] Hirama K, Taniyasu Y and Kasu M 2011 AlGaN/GaN high- Kakushima K, Wakabayashi H, Iwai H, Nishizawa S and
electron mobility transistors with low thermal resistance Ohashi H 2016 Monolithic integration of GaN-based
grown on single-crystal diamond (1 1 1) substrates by normally-off P- and N-channel MOSFETs 13th Int.
metalorganic vapor-phase epitaxy Appl. Phys. Lett. Seminar on Power Semiconductors
98 162112 [135] Nakajima A, Sumida Y, Dhyani M H, Kawai H and
[120] Dumka D C, Chou T M, Jimenez J L, Fanning D M, Narayanan E M 2011 GaN-based super heterojunction
Francis D, Faili F, Ejeckam F, Bernardoni M, field effect transistors using the polarization junction
Pomeroy J W and Kuball M 2013 Electrical and thermal concept IEEE Electron Device Lett. 32 542–4
performance of AlGaN/GaN HEMTs on diamond [136] Kub F J, Anderson T J, Koehler A D and Hobart K D 2015
substrate for RF applications Proc. IEEE CSICS pp 1–4 Inverted p-channel III-nitride field effect transistor with
[121] Baltynov T, Unni V and Narayanan E M S 2016 The world’s hole carriers in the channel US Patent No. 9,275,998
first high voltage GaN-on-Diamond power semiconductor [137] Han J et al 1999 Growth and fabrication of GaN/AlGaN
devices Solid-State Electron. 125 111–7 heterojunction bipolar transistor Appl. Phys. Lett.
[122] Chu R et al 2013 Normally-off GaN-on-Si transistors 74 2702
enabling nanosecond power switching at one kilowatt 71st [138] Kikkawa T et al 2015 IEEE Int. Reliability Physics Symp.
Annual Device Research Conf. (23–26 June 2013) pp 6C.1.1–6
pp 199–200 [139] Lidow A 2010 Int. Conf. Integrated Power Electronics
[123] Luo F, Chen Z, Xue L, Mattavelli P, Boroyevich D and Systems p 14.3
Hughes B 2014 Design considerations for GaN HEMT [140] Kaneko S 2015 Int. Symp. Power Semiconductor Devices &
multichip halfbridge module for high-frequency power ICs pp 41–4
converters 29th Annual IEEE Applied Power Electronics [141] Tanaka K et al 2017 IEEE Int. Reliability Physics Symp.
Conf. and Exposition (16–20 March 2014) pp 537–44 pp 4B.2.1–10
[124] Hughes B, Lazar J, Hulsey S, Musni M, Zehnder D, [142] Okita H et al 2016 Int. Symp. Power Semiconductor Devices
Garrido A, Khanna R, Chu R, Khalil S and Boutros K & ICs pp 23–6
2014 Normally-off GaN-on-Si multi-chip module boost [143] Oeder T et al 2017 Int. Symp. Power Semiconductor Devices
converter with 96% efficiency and low gate and drain & ICs pp 211–4
overshoot 29th Annual IEEE Applied Power Electronics [144] Amirahmadi A et al 2017 Applied Power Electronics Conf.
Conf. and Exposition (16–20 March 2014) pp 484–7 and Exposition pp 350–4
[125] Shatalov M, Simin G, Jianping Z, Adivarahan V, [145] Sleik R et al 2016 Applied Power Electronics Conf. and
Koudymov A, Pachipulusu R and Asif Khan M 2002 GaN/ Exposition pp 759–65
AlGaN p-channel inverted heterostructure JFET [146] JEDEC Committee JC-70 Wide Bandgap Power Electronic
IEEE Electron Device Lett. 23 452–4 Conversion Semiconductors (www.jedec.org/committees/
[126] Zimmermann T, Neuburger M, Kunze M, Daumiller I, jc-70)
Denisenko A, Dadgar A, Krost A and Kohn E 2004 [147] Alonso A R, Diaz M F, Lamar D G, Azpeitia M A P,
P-channel InGaN-HFET structure based on polarization Hernando M M and Sebastian J 2014 IEEE Trans. Power
doping IEEE Electron Device Lett. 25 450–2 Electron. 29 2428
47
[148] TPH3208PS Datasheet www.transphormusa.com/ [164] Jauch F and Biela J 2016 Combined phase-shift and
document/650v-cascode-gan-fet-tph3208p/ (Accessed: 28 frequency modulation of a dual-active-bridge AC–DC
June 2017) converter with PFC IEEE Trans. Power Electron.
[149] Liu Z, Huang X, Lee F C and Li Q 2014 IEEE Trans. Power 31 8387–97
Electron. 29 1977 [165] Wang Z, Ouyang J, Zhang J, Wu X and Sheng K 2014
[150] Huang X, Du W, Lee F C, Li Q and Liu Z 2016 IEEE Trans. Analysis on reverse recovery characteristic of SiC
Power Electron. 31 593 MOSFET intrinsic diode IEEE Energy Conversion
[151] Cai Y, Zhou Y G, Lau K M and Chen K J 2006 IEEE Trans. Congress and Exposition (Pittsburgh, PA) pp 2832–7
Electron Devices 53 2207 [166] Oswald N, Anthony P, McNeill N and Stark B H 2014
[152] Wei J, Liu S, Li B, Tang X, Lu Y, Liu C, Hua M, Zhang Z, An experimental investigation of the tradeoff between
Tang G and Chen K J 2015 IEEE Electron Devices Lett. switching losses and EMI generation with hard-switched
36 1287 All-Si, Si-SiC, and All-SiC device combinations IEEE
[153] Uemoto Y, Hikita M, Ueno H, Matsuo H, Ishida H, Trans. Power Electron 29 2393–407
Yanagihara M, Ueda T, Tanaka T and Ueda D 2007 IEEE [167] Kolar J 2015 Approaches to overcome the Google/IEEE
Trans. Electron Devices 54 3393 little-box challenges IEEE Int. Telecommunications
[154] Xiong Y, Sun S, Jia P, Shea H and Shen Z J 2009 IEEE Energy Conf. (Osaka, Japan)
Trans. Power Electron. 24 525 [168] Kreutzer O and Heckel Tand Maerz M 2016 Using SiC
[155] Jiang S, Lee K B, Guiney I, Miaja P F, Zaidi Z H, Qian H, MOSFET’s full potential—switching faster than
Wallis D J, Forsyth A J, Humphreys C J and Houston P A 200 kV/μs Mater. Sci. Forum 858 880–4
2017 IEEE Trans. Power Electron. 32 8743 [169] Wang H, Wei J, Xie R, Liu C, Tang G and Chen K J 2017
[156] Huang A Q 2016 Wide bandgap (WBG) power devices and Maximizing the performance of 650-V p-GaN gate
their impacts on power delivery systems IEEE Int. Electron HEMTs: dynamic RON characterization and circuit
Devices Meeting (San Francisco, CA) pp 20.1.1–4 design considerations IEEE Trans. Power Electron.
[157] Huang X, Feng J, Du W, Lee F C and Li Q 2016 Design 32 5539–49
consideration of MHz active clamp flyback converter with [170] Meneghesso G, Verzellesi G, Pierobon R, Rampazzo F,
GaN devices for low power adapter application 2016 IEEE Chini A, Canali C and Zanoni E 2004 Surface-related
Applied Power Electronics Conf. and Exposition drain current dispersion effects in AlGaN-GaN HEMTs
(Long Beach, CA) pp 2334–41 IEEE Trans. Electron Devices 51 1554–61
[158] Hu B et al 2016 Device loss comparison of GaN device [171] Endruschat A, Heckel T, Reiner R, Waltereit P, Quay R,
based LLC, dual active bridge and phase shift quasi Ambacher O, Maerz M, Eckardt B and Frey L 2016
switched capacitor circuit IEEE Energy Conversion Slew rate control of a 600 V 55 mΩ GaN cascode 2016
Congress and Exposition (Milwaukee, WI) pp 1–7 IEEE 4th Workshop Wide Bandgap Power Devices and
[159] Liu Z, Lee F C, Li Q and Yang Y 2016 Design of GaN-based Applications (Fayetteville, AR) pp 334–9
MHz totem-pole PFC rectifier IEEE J. Emerg. Sel. Top. [172] Tanaka K et al 2015 Suppression of current collapse by hole
Power Electron 4 799–807 injection from drain in a normally-off GaN-based hybrid-
[160] Ramachandran M and Nymand R 2016 Experimental drain-embedded gate injection transistor Appl. Phys. Lett.
demonstration of a 98.8% efficient isolated DC-DC GaN 107 163502
converter IEEE Trans. Ind. Electron. 64 9104–13 [173] Ditze S, Endruschat A, Schriefer T, Rosskopf A and
[161] Bomboir O, Bleus P, Milstein F, Joannès T, Stassain P, Heckel T 2016 Inductive power transfer system with
Geuzaine C, Emmerechts C, Frebel F and Laurent P 2016 a rotary transformer for contactless energy transfer on
Technical approach document of red electrical devils by rotating applications 2016 IEEE Int. Symp. Circuits and
CE + T Google Little Box Challenge Systems (Montreal, QC) pp 1622–5
[162] Liu Z, Huang Z, Lee F C and Li Q 2016 Digital-based [174] Zeltner S, Endres S, Sessler C, Eckardt B and Morita T
interleaving control for GaN-based MHz CRM totem-pole 2017 6 kW bidirectional, insulated on-board charger
PFC IEEE J. Emerg. Sel. Top. Power Electron. 4 808–14 with normally-off GaN gate injection transistors
[163] LaBella T, Yu W, Lai J S, Senesky M and Anderson D 2014 PCIM Europe 2016; Int. Exhibition and Conf.
A bidirectional-switch-based wide-input range high- Power Electronics, Intelligent Motion, Renewable
efficiency isolated resonant converter for photovoltaic Energy and Energy Management (Nuremberg,
applications IEEE Trans. Power Electron. 29 3473–84 Germany)
48

The 2018 Gan Power Electronics Roadmap: Journal of Physics D: Applied Physics

Uploaded by

Copyright:

Available Formats

The 2018 Gan Power Electronics Roadmap: Journal of Physics D: Applied Physics

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

The 2018 Gan Power Electronics Roadmap: Journal of Physics D: Applied Physics

Uploaded by

Copyright:

Available Formats

Journal of Physics D: Applied Physics

TOPICAL REVIEW • OPEN ACCESS Related content

- Prospects for the application of GaN

- Simple wet-etching technology for GaN

- Monolithic integration of E/D-mode GaN

This content was downloaded from IP address 103.78.165.178 on 04/09/2019 at 12:01

J. Phys. D: Appl. Phys. 51 (2018) 163001 (48pp) https://doi.org/10.1088/1361-6463/aaaf9d

The 2018 GaN power electronics roadmap

E-mail: [email protected] (Geoff Haynes) and [email protected]

Received 16 October 2017, revised 12 February 2018

Keywords: GaN, power circuits, GaN-on-Si

(Some figures may appear in colour only in the online journal)

Introduction infrastructure to support autonomous driving will create

2. Epitaxial lift-off of GaN and related materials

P Fay1, J Wang1, L Guido2, J Xie3, E Beam3, R McCarthy4,

Status. GaN and other III-N compound semiconductors have

Advances in science and technology to meet challenges. To

reducing stress. Although single crystal GaN or AlN would be

Concluding remarks. GaN-on-Si based power transistors

Wafer bowing (µm)

2.3 µm-thick GaN/Sapphire Si vertical devices. Therefore, a Si-doped AlN NL as thin as

6. Vertical GaN power devices

Yuhao Zhang, Jie Hu, Min Sun, Daniel Piedra,

Department of Electrical Engineering and Computer Science,

Status. Central to improving the efficiency of power electron-

been demonstrated in CAVET [53], although much more work

Concluding remarks. Vertical GaN devices are key to

7. GaN insulated gate field-effect transistors

Kevin J Chen1, Mengyuan Hua1 and Shu Yang2

Status. GaN-based insulated gate field-effect transistors with

MIS-HEMTs and fully MIS-FETs have both been developed

Figure 17. (a) Schematic of a generic GaN-on-silicon power

Concluding remarks. Plasma processing is a vital element in Acknowledgments

10. Challenges to dielectric processing

School of Engineering, University of Liverpool,

Status. The growth of ultrathin dielectric layers into GaN-

Concluding remarks. magnetics and integration lead to major steps in efficiency,

mainstream. It is also becoming apparent that a transition from Acknowledgments

13. Technological challenges in next-generation

National Institute of AIST, Japan

Status. Si-based lateral power devices have been widely uti-

Current and future challenges. As an example of GaN power

14. GaN CMOS: fact or fiction?

HRL Laboratories, Malibu, CA, United States of America

Status. GaN power transistors have demonstrated unprec-

15. Assessing the limits of performance of p-type

Ashwani Kumar and Maria Merlyne De Souza

University of Sheffield, United Kingdom

Status. P-type devices are required for integration of

Current and future challenges. The main challenge for a

Rating RDSON RDSON * QOSS RDSON * QRR RDSON * EOSS RDSON * QG

Figure 33. Device structure of GaN integrated cascode transistors.

Table 2. Benchmark of the state of the art GaN-based converters.

Frequency Efficiency Power density

Figure 34. (a) Demonstrator of 20 W inductive power transmission

You might also like