FPGA Implementation of Sine and Cosine Value Generators Using Cordic Algorithm For Satellite Attitude Determination and Calculators
FPGA Implementation of Sine and Cosine Value Generators Using Cordic Algorithm For Satellite Attitude Determination and Calculators
FPGA Implementation of Sine and Cosine Value Generators Using Cordic Algorithm For Satellite Attitude Determination and Calculators
stored, the lookup table can be big or small, but clearly, the Therefore, the angle for which we want to know the sine and
smaller the lookup table, more is the error involved. The cosine value can be obtained by simply rotating the point to
problem with a bigger lookup table is that it requires more the target angle. The rotation can be in a single step or a series
memory and memory is expensive. Moreover the size of the of small steps which may be either clock wise or anti-
Lookup table increases exponentially with the increase in the clockwise.
precision of the angle. Though this approach provides fast The rotation of a point in two dimensional space can be
results it is very expensive to implement. given by the rotation matrix which is:
C. Cordic Algorithm
x ' x cos θ − sin θ
CORDIC is an acronym for Coordinate Rotation Digital = (2)
Computer introduced by Jack E. Volder [1]. It is an iterative y ' y sin θ cos θ
algorithm capable of calculating trigonometric and various
other functions. In this algorithm with the help of an This matrix operation can be expressed by mathematical
adder/subtractor, a small look up table and a shifter the operations as follows:
trigonometric functions can be calculated very easily. The x ' = x cos θ − y sin θ (3)
advantage that Cordic offers over other algorithms is that it y ' = y cos θ + x sin θ (4)
does not require multiplication or division blocks, instead it
works only with a shifter, adder/subtractor and a small lookup
Therefore, in each iteration the coordinates are rotated and in
table. This reduces the hardware requirement drastically and
the i+1th rotation coordinates are given by:
provides reasonably good speed.
xi +1 = xi cos θ i +1 − yi sin θ i +1 (5)
The main constraint in System on chip design is the amount yi +1 = yi cos θ i +1 + xi sin θ i +1 (6)
of on chip memory and this constraint is equally valid in
System on chip prototyping using programmable logic [6]. Now if we divide by cos θ i +1 we get:
Hence using Cordic Algorithm we can minimize the memory xi +1
requirements. = xi − yi tan θ i +1 (7)
cos θi +1
III. MATHEMATICAL BASIS OF CORDIC ALGORITHM yi +1
= yi + xi tan θ i +1 (8)
There are two forms of the Cordic Algorithm - Vectoring cos θi +1
and Rotation mode. In vectoring mode, the coordinates (x0,y0)
are rotated until y0 converges to zero. In the rotation mode the Therefore,
coordinates (x0,y0) are initially aligned with the x- axis and
xi +1 = cos θ i +1 ( xi − yi tan θ i +1 ) (9)
they are rotated by an angle of θ i every cycle until it reaches
the target angle or close to the target angle. yi +1 = cos θ i +1 ( yi + xi tan θ i +1 ) (10)
For the Architecture proposed we have used the rotation
mode to calculate sine and cosine values. Now if tan θi +1 is restricted to ±2− i , then the
Suppose that we have a point on a unit circle then by Fig 1.
multiplication is converted into an arithmetic right shift.
we can conclude that the coordinates can be given
by (cos θ ,sin θ ) where θ is the angle made by the line Therefore we have:
joining the point and the center with the x-axis.
tan θ i +1 = ±2− i (11)
y - axis
θi +1 = tan −1 (±2 − i )
(cos θ ,sin θ )
Now taking Cosine of θi +1 we get:
cos(θi +1 ) = cos(tan −1 (±2− i )) (12)
−1 1
As cos(tan ( x )) =
x - axis 1 + x2
We have,
1
cos(tan −1 (±2−1 )) = = Ki
1 + 2 −2i (13)
Now we can write (9) and (10) as:
Fig 1. A point on unit circle rotated by an angle θ xi +1 = K i ( xi − yi d i 2 − i ) (14)
−i
yi +1 = K i ( yi + xi di 2 ) (15)
3
d i gives the direction of rotation and d i = ±1 . If d i is clock cycle. Also a control unit is used for coordinating the
activities and finally a lookup table is used for storing the
positive it means direction of rotation is anti clockwise and if values.
it is negative it means direction of rotation is clockwise.
Multiplication with Ki can be avoided by considering it as
a multiplication factor for all the iterations. Therefore, for n
iterations K is given by the product of every Ki .
K = K 0 * K1 * K 2 *.....* K15 = 0.6073
Hence, it is possible to break our rotations into many steps,
each of decreasing size and have each step such that tan θ is
1
a power of . This would allow us the multiplication by
2
tan θ operation to be substituted by a simple bit shift
operation.
VI. RESULTS
TABLE II
All of the modules were written in VHDL and the simulation XILINX FPGA IMPLEMENTATION RESULTS
was done on Altera's Quartus II 9.0 as well as Xilinx ISE 12.1
for 16 iterations, 16 bit system. Finally the design was Parameter Used Percentage
implemented on Altera's FPGA EP2C35F672C6 of Cyclone II
No. of Slices 157 8
family and Xilinx's xc3s200-5ft256. The implementation
results on Altera's FPGA are given in the table below: No. of Slice Flip Flops 110 2
No. of 4 input Lookup Tables 299 7
TABLE I
ALTERA FPGA IMPLEMENTATION RESULTS
No. of GCLKS 2 25
The Device utilization summary for the work done in [10] for
Parameter Used Available
the Area optimization is:
Logic Elements 417 33216
TABLE III
Dedicated Logic Registers 55 33216 RESULTS FOR WORK DONE IN [10]
Total Memory Bits 272 483840
Parameter Used Percentage
The time taken for the Computation of Sine and Cosine No. of Slices 1075 55
values was 400ns. No. of Slice Flip Flops 570 14
A program was written in C++ for the calculation of sine No. of 4 input Lookup Tables 1737 44
and cosine for the same no of iterations. On executing the No. of GCLKS 1 12
program on a 2GHZ T7300 processor, it was found that the
time taken to compute the sine and cosine value was 11ms. Though the work done in [10] offers much higher speed but
Therefore our approach is 27500 times faster than the software at the same time it also takes up much more area, but for
approach. systems such as calculator where the chip count has to be
Also a graph was plotted using Matlab for the error in sine reduced we have to go for an approach which takes least
and cosine values obtained for different angles. The graph is amount of area. Moreover for calculators, it is not an issue
given below : even if the time taken to compute these values is in
microseconds since human beings do not respond that fast.
VII. CONCLUSION
Therefore an architecture of iterative Cordic is presented for
systems such as calculator and Satellite Attitude
determination. For Calculators it provides a very area efficient
system as well as accurate results and for the Satellite Attitude
determination systems it gives results as fast as 27500 times
than the traditional software approach. Implementation results
on Altera's EP2C35F672C6 of Cyclone II family and Xilinx's
xc3s200-5ft256 are presented. Finally our work has been
compared with the work done in [9] and [10].
VIII. REFERENCES