Lyla B Das

CHAPTER 1
THE ARCHITECTURE OF 8086
OBJECTIVES
In this chapter you will learn
• The internal architecture of the 8086

• The registers of 8086 and their specific functions.
• The operation of the flags of 8086
• Memory segmentation technique used by the x86 family
• How to perform memory address calculations
• The different addressing modes of 8086
We will start our learning of the x86 family of microprocessors, by understanding the
architecture of the 8086 ,on which is based the architecture of the whole family.
1.1 INTERNAL BLOCK DIAGRAM OF THE 8086

Fig 1.1 a Internal block diagram of the 8086 (simplified model)
The 8086 processor is a 16 bit processor internally as well as externally –which means
that its data bus width as well as the bit size of its internal data registers is 16 .Thus it
can access an external source 16 bits at a time through its data bus. . But it also has the
capability to access and work on 8 bit (byte) data.
As the first step in understanding the architecture of the 8086 ,let us examine the internal
block diagram of the 8086 . Fig 1-1a shows the simplified block diagram and Fig 1-1b
show the detailed one . Go through the simplified one first .Though not specifically
shown in the block diagram ,it is to be noted that all actions in the processor are
synchronized by a system clock ,which provides the basic timing .There is a control unit
which provides the control signals for the overall functioning of the processor.
We see that the internal block diagram has been partitioned into two logical units
,namely the Bus Interface Unit (BIU) and the Execution Unit .
They interact directly with each other through the internal bus ,but perform separately
as two units with well defined functions for each unit. Let us explore the internal
configuration of these units, one by one.
1.2 THE EXECUTION UNIT
It contains the arithmetic and logic unit ,the control unit ,an internal bus ,plus a few
registers. Let us get a bird’s eye view of the EU starting with the register set.
Why Registers?
All processors have internal registers ,which is actually on-chip RAM.
Some are program visible ,while others are not directly visible to programmers.
The more the number of program visible registers ,the better it is for the programmer
.This is because internal registers are used as temporary storage for operands ,and if the
operand is already in a register ,it takes less time for execution of the associated
instruction. Such registers are called general purpose or scratch pad registers .
But registers constitute on chip RAM ,which is costly.

Also ,more the number of registers, more are the number of bits required to identify and
address a particular register. This can cause an increase in the length of opcodes in
modes involving registers. . Thus the number of registers a processor can have is a trade
off between a number of conflicting factors..
Fig 1.1b Internal Block diagram of the 8086 (detailed)
Register Set of 8086

Let us see how the register set of 8086 has been organized.
The 8086 has data registers, address registers segment registers and also a flag registers.
We will first examine the registers in the Execution Unit.
Fig 1.2 Register model of the 8086
1.2.1 The Scratch Pad Registers
They are called so as they are used for temporary storage ,just as we jot down a few
things temporarily in a scratch pad.
As shown in Fig1.2,,the 8086 has four 16 bit general purpose registers labeled as
AX,BX, CX and DX. Each of these registers can also be used as two separate and
exclusive 8 bit registers also .i.e AX has two parts AH and AL , where H and L stands
for the high and low portions respectively When used as 8 bit registers , AH and AL are
separate ,but they can be concatenated to form the 16 bit register AX. Similar is the case
for the registers BX ,CX and DX. Each register ,while being general purpose ,has
specialized uses as well .As such ,let us understand these features clearly,
AX
This is a 16 bit data register ,but can also be used as two unrelated 8 bit registers AH and
AL . AL/AX is sometimes called the accumulator ,but the relevance of the accumulator
is less for 8086 compared to the earlier 8085 in which one operand is implied to be in the
A register for many instructions.However , for the 8086 ,only for certain specialized
instructions is the AL or AX register implied to contain one of the operands .In most
other instructions ,the source and destination must be specifically mentioned in the
instruction. (The destination is the register or memory location in which the result of any
operation is to be put )
BX,CX and DX
These are the other working registers of the 8086 ,which means that temporary data
storage ,arithmetic calculations ,data manipulation etc can be done with these registers
.They also can be used as 8 bit or 16 bit registers as mentioned earlier . Still, each of them
has special functions .
Base register BX is frequently used as an address register in many based addressing
modes. Counting register CX is used as a counter in many instructions .
Data register DX is used in I/O instructions as a pointer to data by storing the address of
the I/O port . .Also, multiply and divide operations involving large numbers assume DX
and AX as a pair.
Pointer and Index Registers

SP,BP ,SI and DI are address registers, and can be used only as 16 bit registers.
They are very important in programming ,as they facilitate the use of various addressing
modes.
BP and SP
They are the Base pointer and Stack pointer respectively .
SP always points to the top of the stack ,while BP can point to any location in the stack .
(We will discuss the concept of the stack shortly).Thus normally ,whenever we refer to
data referred to by BP and SP , it is implied that we are talking about data in the stack.
SI and DI
These are Index registers ,labeled as Source Index and Destination Index respectively
They function as address registers in various addressing modes ,but they have a
specialized function as being the default registers in string instructions .
1.2.2 FLAG REGISTER
It is a 16 bit register ,of which 7 bits are unused .Out of the remaining bits , 6 bits are
used as conditional flags .The others are control .flags.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

U U U U OF DF IF TF SF ZF U AF U PF U CF
U=unused
CONDITIONAL FLAGS CONTROL FLAGS
OF= Overflow flag DF= Direction Flag
SF= Sign Flag IF= Interrupt Flag
ZF= Zero Flag TF= Trap Flag
AF= Auxiliary carry Flag
PF= Parity Flag
CF= Carry Flag
Fig 1-3 : 8086 Flag register
A conditional flag is a single bit flip flop which is set or reset according to the result of
an arithmetic or logic operation .
The conditional flags available are the Carry (CF), Zero (ZF) ,parity (PF) ,overflow
(OF)and the sign flag(SF). Since conditional flags are an important ingredient in
computation using assembly language ,we will not defer our discussion on them.
Carry flag (CF)

The carry flag (CF)gets set if there is a carry out from the most significant bit during a
calculation. For example ,when 8 bit addition causes the result to be greater than 8 bits
,there is a carry out from the MSB (D7),which causes this flag to be set . For 16 bit
operations , the carry will be from bit D15, and CF will be set.
Zero Flag(ZF)
When the result of an arithmetic or logic operation is zero ,the Zero flag gets set .For
example ,if we keep on decrementing the contents of a register (say ,the CX register
which is used as a count), it will finally become zero . At this instant ,the zero flag gets
set i.e. ZF=1. Another case is when two numbers are compared .Comparison is achieved
by subtraction .If the numbers compared are equal ,the zero flag is set (ZF=1) indicating
equality of the operands.
Parity Flag (PF)
The setting of this flag indicates the presence of an even number of bits in the least
significant byte (lower 8 bits) of the destination.
For example ,after a particular arithmetic or logic operation ,if the destination contains
the number 11100111 ,the parity flag is set to indicate even parity. Even if the operation
is on 16 bit data, only the parity of the lower 8 bits is verified. This flag does not find
much applications in current programming practices.
Sign Flag(SF)
After an arithmetic or logic operation ,if the result contains a negative number ,the sign
flag is set .In essence ,it contains the MSB of the result ,which can be interpreted as the
sign bit in signed arithmetic operations.
Auxiliary Carry Flag(AF)

This flag functions similar to the Carry flag ,except that the overflow is from bit D3 into
D4. It thus indicates a carry out from the lower 4 bits . The need for this flag is for the
Decimal Adjust instruction important in BCD number calculations. There are no other
instructions that directly test the state of this flag and no conditional branching associated
with this flag .
Overflow Flag(OF)
This flag is set under one of the following conditions
i) there is an overflow into the MSB (8th or 16th bit) from the bit of lower
significance, but no carry out from the MSB
ii) there is a carry out from the MSB ,but no carry into the MSB.
This flag indicates the that the result of a signed number operation is too large , causing
the higher order bit to overflow into the sign bit ,thus changing the sign bit .
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Example 1-1
Find the status of the flags CF ,SF, AF after the following instructions are executed
MOV AL,35H
ADD AL,0CEH
Solution:
The format of a MOV instruction is MOV destination ,source .
In the above two instructions ,a number 35H is first moved to AL .In the next line ,0CEH
is added to AL .The sum will be in AL ,the destination register .
35 H 0011 0101 +
+ CE H 1100 1110
103 H 1 0000 0011
After computation ,AL will contain 0000 0011 and

.
CF=1 since there is a carry out from D7.
SF=0 since the sign bit (MSB) of the 8 bit destination is 0
AF=1 ,since there is an overflow from D3 to D4.
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Example 1-2
Show the effect of the following instructions on the CF,ZF and OF bits of the flag
register.
MOV BX,45ECH
ADD BX,7723H
Solution:
This is the case of 16 bit addition
45EC H 0100 0101 1110 1100
+ 7723 H 0111 0111 0010 0011
BD0F H 1011 1101 0000 1111
The sum will be in BX which is the destination register.

CF= 0 since there is no carry out from D15
ZF=0 since the destination is not zero
OF=1 since there is an overflow into the MSB D15
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Example 1-3
Assuming we are adding signed 8 bit numbers , how is the result of the following
addition to be interpreted?
MOV AL,125
ADD AL,75
Solution:
Both operands here are decimal numbers
This program causes AL to be loaded with +125 and then +75 to be added to AL .The
result is to be in AL.
Signed numbers consider the MSB as the sign bit .With 8 bits ,the maximum range of
signed numbers -128 to +127 .
When adding the given signed numbers,
+125 0111 1101
+75 0100 1011
+200 1100 1000
There has been an overflow from D6 to D7 (i.e to the MSB). In this case we find OF=1
.The sum is interpreted as a negative number with value of the sign bit =1 .
The setting of the OF flag indicates that the magnitude of the result has caused an
inversion of the sign bit ,indicating a mistake .This interpretation is done ,because the
maximum range of signed positive numbers is only +127 for 8 bit representation.
Incidentally the Sign Flag is also set (SF=1)
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Control Flags:
Besides the conditional flags ,there are three control flags namely the Trap flag ,
Direction flag and Interrupt flag .The control flags have to be deliberately set or reset
according to the requirements of the program,.
The Trap flag (TF) is set to perform step by step execution ,during debugging .
The Interrupt Flag (IF) is set to enable interrupts.
The Direction flag (DF) is used in string operations .
Details of the functioning of these flags will be discussed in later chapters.
Arithmetic Logic Unit
It is the part of a computer that performs all arithmetic and logic computations. The ALU
is the most important unit of the processor .Instructions which are fetched and decoded,
are executed in the ALU. Thus the ALU has direct access to the general purpose
registers and flags.
1.3 BUS INTERFACE UNIT

This unit is responsible for address calculations ,pre-fetching instructions for the queue
and sequencing instructions one by one .. Let us examine each function .
1.3.1 THE INSTRUCTION QUEUE
Instructions are found in memory ,from where they are fetched and decoded as and when
they need to be executed .But in 8086,there is a queue which fetches instructions ahead
of the execution time and places them in a six byte first in first out (FIFO) queue. This
pre-fetching is done when the buses are free i.e. not being used for the execution of the
current instruction .
The advantage of pre-fetching is that when a particular instruction is to be executed, there
is a good chance of finding it in the queue(which is on-chip), rather than having to go to
memory to fetch it . But the queue will have to be emptied in the event of a branch
instruction ,i.e. when the next instruction to be executed is not the next one in the
sequence. After this ,the queue needs to be re-loaded from the new ‘branch’ .address.
This pre-fetching belongs to a class of ideas called pipelining ,which means that both
execution and fetching take place at the same time. i.e, while the execution of one
instruction is going on ,the fetching of another one can be done.
Pipelining greatly speeds up processing.
1.3.2 MEMORY SEGMENTATION
The 8086 has a 20 bit address bus , but let us remember that we have not seen any 20 bit
registers so far . .It is understandable that the general purpose registers are used as 16 bit
or 8 bit registers ,as this is the way data is organized. But we see that all the address
registers also are 16 bit . An ingenuous idea called segmentation has been used to take
care of this situation. A segment is just an area in memory . Thus the total memory size
can be considered to be divided into segments of various sizes . The idea of dividing
memory this way is called segmentation
In memory ,data is stored as bytes. Each byte has a specific address.
With 20 address lines ,the memory that can be addressed is 220 bytes. This will amount
to 1,048,576 bytes (1 Megabyte). Thus the 8086 can access a physical memory with
addresses ranging from 00000H to FFFFFH .A 20 bit physical address is to be placed
on the address bus to access any location in memory.
Memory as a whole is considered to have four different types of segments
labeled as data, code ,stack and extra. One idea of segmentation is to keep data and code
separately . Thus the code segment contains code only . Data is stored in the data segment
,and the extra segment is just another type of data segment used in a special way.
The stack segment is an area of memory which functions and is accessed differently
from the other three segments
.
1.3.2.1 Segment Registers
Each of these segments is addressed by an address stored in corresponding segment
registers .These registers are all 16 bit in size .Each register stores the base address of
the corresponding segment .A base address is the starting address of a segment .But
since the segment registers cannot store 20 bits (of the base address) ,they store only the
upper 16 bits. The least significant nibble is implied to be zero.
How is a 20 bit physical address obtained if there are only 16 bit registers?
The 20 bit address of a byte is called its physical address .But it is specified as a logical
address which is in the form of two 16 bit numbers in the format base address: offset
See the following figure ,as a typical example .
22236H Addressed Byte

-
-
Physical Address -
=22220H+ -
0016H -
------------- - OFFSET = 0016 H
22236 H BYTE- 2
----------- -
Base addres
BYTE 1
Base address 2220H BYTE 0 2222 H DS Register
Fig 1-3 Calculation of a physical address from the logical address

We consider that a data byte is stored in a data segment ,whose base address is 22220H
.Then the data segment register (DS) will contain the number 2222H . The data at any
location within this segment is referenced by an offset(displacement) with respect to the
base address . Thus if a data at location a has a logical address specified as
2220H:0016H ,the number 0016H is the offset or displacement with respect to the base
address .For physical address calculation ,the BIU appends the segment register content
with four binary zeros(or one hex zero) on the right . The physical address is thus
calculated as
22220H
+ 0016H
22236H
BASE ADDRESS
SS
A0000H
ES
90000H
SEGMENT REGISTERS
A000H SS
70000H DS 9000H ES
7000H DS
5000 H CS
CS
50000H
Fig 1-4 Segment Registers and Corresponding segments
Similar is the case for the other segments . All offsets are limited to 16 bits which
means that the maximum size possible for a segment is only 216 which is 65,536 bytes
or 64K bytes. We can conclude that every memory reference by the 8086 will use one of
the segment registers (i.e., DS, ES, SS, or CS, ) which is combined with an offset
(usually given in the instruction) to determine the physical address being accessed.
A data byte has the logical address of the form DS: offset
1.3.2.2 The Code Segment and the Instruction Pointer

The code segment is the area of memory where code alone is stored . The offsets within
the code segment are referenced using the Instruction Pointer(IP) which is a 16 bit
register .The IP sequences the instructions ,and always points to the next instruction to
be executed. Whenever an instruction byte has to be fetched from memory ,the bus
interface unit(BIU ) performs the address calculation using the contents of CS register
and the IP. This 20 bit address is then placed on the address bus and the instruction byte
is fetched. Thus the logical address for an instruction bye is of the form CS:IP
1.3.2.3 The Stack Segment and the Stack Pointer
The stack is an area of memory which is used in a special way . Data is generally pushed
in and popped out of the stack . The stack of the 8086 is a Last in First out ( LIFO )stack
,which means that the last data that was pushed in ,is the first one that can be popped out
.This also means that data can only be taken out or put in only from the top of the stack,
But the s‘ stack top’ changes as data is put in or taken out.
There is a 16 bit register called Stack Pointer which points to the top f the stack .
The stack segment is like any other segment ,and the upper 16 bits of its base address is
available is the SS register. A stack address of the form 4466H: 0122H means that the SS
register contains 4466 H, the stack pointer (SP)contains the number 0122H , and the
physical address of the top of the stack is 44660H+0122H =44782H
Address of the
top of stack 44782H Byte 0122 H SP
Byte
Byte
-
-
-
-
-
-
Base Address 44660H - 4466H SS
Fig : 1.5 Stack and physical address of the top of stack
The stack is used mostly to keep aside address and data temporarily , when a subprogram
is called . This will be taken back when the subprogram ends .The 8086 has a stack which
grows downwards(i.e. to lower memory addresses ) . This means that each push
instruction causes the SP to be decremented (by two for 8086) , and data is pushed deeper
downwards into the stack segment .We will discuss the operation of the stack in more
detail in Chapter 4.
Even though ,a stack is usually accessed only from the top ,the 8086 has another register
named BP (base pointer) which is used to reference data anywhere within the stack .
Thus the format SS:BP is also a logical address. This has certain interesting
applications.
1.3.2.4 The Data Segment and Extra Segment

Both these segments store data ,but in certain special cases (string instructions) ,it may be
necessary to list them separately . There is an Extra Segment ( ES )register to store the
upper 16 bits of the base address of the extra segment
The offset within the data segment is also termed as an ‘effective address’. The
effective address calculation depends on the mode of addressing .We will discuss this
very soon.
SEGMENT OFFSET REGISTERS FUNCTION

CS IP Address of the next instruction
DS BX ,DI ,SI Address of data
SS SP , BP Addresses in the stack
ES BX,DI ,SI Address of destination data
(for string instructions )
Table 1-1: Segments and corresponding registers used for specifying offsets
Table 1.1 shows the segment registers and the corresponding registers for offsets
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Example 1-4
The content of DS is 345BH . The amount of data that is to be stored in the data segment
is 12K bytes . Where in memory ,will this segment be located?
Solution:
DS contains the number 345BH.
This number corresponds to the upper 4 hex digits of the starting (base address)of the
data segment .
The base address of the segment is 345B0H .
The last address will have an offset of 12K from the base address .
1K =1024 bytes
12 K=12 x1024 =12228=3000H
The last address of the segment =345B0H +3000H=375B0H
Hence the data segment occupies the memory addresses from 345B0H to 375B0H.
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Example 1.5
The contents of the following segment registers are as given
CS =1111H ,DS =3333H ,SS=2526H
IP =1232H ,SP =1100H ,offset in data segment =0020H
Calculate the corresponding physical addresses for the addressed byte in a)CS b)SS and
c)DS.
Solution:
a)The base address of CS is 1110H .
The address of the next instruction to be executed is referenced by CS and IP .
which is given by 11110H + 1232H =12342H
b)The current top of the stack is referenced by SS and SP .The base address of the stack
segment is 25260H .The corresponding physical address is 25260H +1100H =26350H
c)The data that needs to be accessed is given by DS and the offset .The base address of
the data segment is 33330H .The physical address of this data is calculated as
33330H+0020H =33350H
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Segmentation-General Concerns
1. Segments begin at paragraph boundaries ,where a paragraph is 16 bytes.

i.e. Base addresses are divisible by 16 (because the lowest nibble of all base
addresses are to be zero).
2 Segments can overlap with a new segment starting every 16 bytes. This also
means that there can be more than one logical address for the same memory
location. (physical address) For example, 0000:0100, 0001:00F0, and 0010:0000
all refer to physical address 00100H.
3 We can have segments with the same base address ,but the offsets within the
segment will have to be taken care of to prevent overwriting of data .
For example ,in string operations ,we might use the same segment as the
data and extra segments. This is achieved by loading the same number in the ES
and DS registers.
4. A segment can have a maximum size of 64 K .
5 . A program need not have all four segments ,but it will have at least the code
segment ,
6.. The addresses used in instructions are called logical addresses which are
translated by the BIU to physical addresses.
Advantages of Segmentation
1. It allows all address registers to have the same size as the data registers(16 bit) ,
while allowing the use of 20 bit physical addresses.
2. All addresses in memory are re-locatable . This means that any program or data
can be loaded in any address in memory .A re-locatable program is one which
can be placed in any area of memory and executed without change. Data is also
re-locatable. Changing the base address of the corresponding segment is the only
action we need to perform, in order to re-locate .. All addresses within the
program are relative to the base address, as they are of the form Base address:
offset .All processors in the x86 family have this kind of segmentation . The
higher order processors have protection also added to this structure.
Memory Organization
We have seen that data is stored in memory as bytes . Each byte location has an address .
If a word (two bytes) is to be stored ,two locations of consecutive addresses are needed .
Consider that the number 34E6H is to stored . Then 34H is stored in one location and
E6H is in the next location .Intel’s processors use what is termed the little endian format
which means the lower byte is stored in the lower address and the upper byte in the
higher address .Thus if the above word has an address of 60088H , the storage is as
shown in the fig
ADDRESS DATA
60088H E6H
60089H 34H
Fig: Little endian format
This is in contrast to certain other processors (like Motorola) which uses the big endian
format.
(The origin of the word ‘endian’ is supposed to be from Gulliver’s travels ,referring to a
controversy about whether an egg should be broken at the little end or big end)
Since the data in this case is a word ,two memory locations with two addresses have to be
used to access it .The hardware connection between the processor and memory is
designed in such a way that both these locations are accessed and a word (16 bits) access
is obtained, even though only one logical address is mentioned in the instruction.
1.4 ADDRESSING MODES
For computations in assembly language ,we need an opcode and operands .

Opcode stands for operation code–i.e the code which specifies the operation
to be performed . Opcodes operate on data which are then called the operands.
In the 8086, an instruction can have either one, or two operands (not more). For example ,
an addition operation needs two operands ,while a shift operation operates on a single
operand .
The way in which operands are specified in an assembly language instruction is called its
addressing mode . ,Let us attempt to get a clear understanding of the different
addressing modes allowed for this processor .
We will use the MOV instruction for understanding these modes. .This has the format
MOV destination , source
which causes the source data to be copied into the destination.
The basic assumptions in this context are
i) The operands can be in registers, in memory ,or may be in the instruction
itself . But the 8086 does not have an addressing mode in which both
operands are in memory locations
ii) In the case of two operands, one of them can be in memory ,but the other will
have to be placed in a register .
iii) Data types should match –ie. the source and destination should both be either
bytes or words
1) Register Addressing
Here both the source and destination are registers .No memory access is involved See the
following instructions
MOV AL, AH ; copy the content of AH to AL
MOV CH, BL ;copy the content of BL to CH
MOV SI, BX ;copy the content of BX to SI
MOV ES,AX ;copy the content of AX to ES
Note that the first two are byte operations ,while the other two are word operations.
MOV AX,BL ;gives an error as AX is 16 bit and BL is 8 bit
MOV BL,AX ;gives an error for the same reasons
2) Immediate Addressing
In this mode ,the source will be a constant data
MOV AL, 45H ;copy 45H to AL
MOV BX, 34E3H ;move the hex number 34E3H to BX
MOV CL.’Q’ ;move the ASCII value of Q to CL
MOV PRICE,40 ;move the hex number 40 to the memory
;location with label PRICE
MOV NUMS, 0FC6H ;move the hex number 0FC6H to the memory
; location NUMS
Segment registers are not allowed to use this mode of addressing.
MOV DS,2300H ;gives an error as DS is a segment register
3) Direct Addressing
Here either the source or the destination will be a memory address
MOV AX,[2345H] ;move the word in location 2345H into AX
MOV [1089H],AL ;the byte in AL is moved to location 1086H
It is to be remembered that the addresses in the instructions are offsets within the data
segment (i.e the logical address) . We need to know the content of DS to calculate the
physical address . The size of the registers indicate the size of the operand . Hence ,in the
first instruction ,a data word is referred to ,while in the second ,a data byte is moved.
The square brackets are necessary to indicate that the number is an address and not data .
However , we may use labels for addresses ,and re-write the above two instructions
MOV AX , PRICE
MOV COST,AL
We must then ensure that the referred items have been defined earlier with these labels.
We will see this aspect later
4) Register Indirect Addressing

In this mode , the address of the data is held in a register .The register acts as a pointer to
the data ..The registers must be enclosed in square brackets to indicate that they function
as pointers .We also use the term effective address for the address of the operand . For
this mode of addressing, the address registers allowed are BX,SI and DI.
EA= { [BX] / [DI] /[SI]}
MOV AL,[BX] ; move into AL the content of the location whose

; address is in BX
MOV [SI], CL ; move the content of CL to the address pointed by SI
MOV [DI],AX ;move the content of AX to the address pointed by DI
In the third instruction , AX contains two bytes . Hence the content of AL will be moved
to the address pointed by DI . The content of AH will be moved to the address [DI+1]
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Example 1.6
Show the location of data in memory, after the execution of each of these instructions , if
the content of registers are as given
DS= 1112H , AX= EE78H and BX=3400H
i) MOV [0422H], AL
ii) MOV [0424H],AX
iii) MOV [BX] ,AX
Solution:
i)This is a case of direct addressing . The destination is a memory location which is
specified directly in the instruction. AL contains 78H (lower byte of AX)
DS =1112H
Data segment base address is 11120H
The offset in the instruction is 0422H
Physical address is 11120H +
0422H
11542H
After the instruction execution ,the content of the addressed location is as shown
PHYSICAL CONTENT
ADDRESS
11542H 78H
ii)This is also a case of direct addressing . The physical address is calculated as

11120 H+
04224 H
11544 H
However since AX contains two bytes of data , the lower byte (AL) is stored in the
address 11544H and the higher byte (AH) in the next address (recollect the ‘little endian’
concept)
PHYSICAL CONTENT
ADDRESS
11544H 78H
11545H EEH
iii)This is a case of register indirect addressing . BX is a pointer to the address 3400H

,which is an offset .The corresponding physical address is
11120 H +
3400 H
14520 H
The content of AX is moved to this address .Hence the corresponding memory will be
as shown
PHYSICAL CONTENT
ADDRESS
14520H 78H
14521H EEH
5) Register relative addressing

In relative addressing mode , a number or displacement is part of the effective address .
EA ={[BX] /[DI] /[SI] /[BP]} + 8 bit or 16 bit displacement
MOV CL ,10[BX] ; move the content of the address specified by adding the
; content of BX and 10.
Thus the effective address is [BX+10 ].
Once the effective address is computed, the physical address is calculated as the sum of
the segment base address and the effective address.
The displacement can be a 16 bit signed/unsigned number or an 8 bit sign extended
number. But the displacement should not be so large as to make the effective address go
beyond the range of the maximum size of a segment .
The above instruction can also be written as
MOV CL,[BX+10]
MOV CL,[BX]+10 or
MOV CL,[BX][10] or
MOV CL ,PRICE [BX]
In the last case , PRICE has to be defined earlier as a displacement of 10.
6) Based Indexed Mode
In this mode ,an index register and a base register together carry the effective address .
The content of these two registers are added and called the effective address.
MOV AL,[BX][SI] ;move the content of the effective address pointed
; by [BX] and [SI] into AL
The effective address is obtained by adding the content of BX and SI .Since the
destination register is an 8 bit register , this is a byte operation.
The following is a word operation as the source register CX is 16 bit in size.
MOV [BX][DI],CX ;move the content of CX to the effective address
; pointed by [BX] and [SI]
7) Relative Based Indexed Mode

This is the case when the ‘effective address ‘ is specified with a base register ,an index
register as well as a displacement . The ‘effective address is the sum of the two registers
and the displacement .
For example ,the following use the relative based indexed mode of addressing
MOV DL ,5[BX][DI] ;EA =5 +BX +DI
MOV 5[BP][SI], AX ;EA =5+BP +SI
MOV CL ,COST[BX[[SI] ;EA=COST +BX +SI
; COST has to be defined as a displacement earlier
------------------------------------------------------------------------------------------------------------
Example 1.7
Find the address of physical memory for the following instructions if the content of
the required registers are as given below
SS =2344 H, DS =4022H , BX =0200H ,BP=1402H ,SI=4442H
i) MOV CL,1234H[SI]
ii) MOV AL,5[SI[[BP]
Solution:
i) MOV CL,1234H[SI]
This is a case of register relative addressing .The effective address is obtained from
the instruction, to be the sum of the displacement and SI
Effective address =1234H +
4442H
5676H
The segment base address is obtained from DS to be 40220H
The physical address is the sum of the segment base address and the effective
address. i.e. 40220H +
5676H
45896H
ii) MOV AL,5[SI[[BP]
This is a case of relative based indexed mode .The effective address is calculated as
the sum of the displacement and the contents of the registers SI and BP .
Effective address = 0005 H +
4442 H
1402 H
5849 H
The physical address is the sum of the segment base address and the effective
address . In this case ,as BP is one of the address registers ,the segment referred is
the stack segment
Physical address is 23440 H (base address of the stack segment)
+ 5849 H
28C89 H
------------------------------------------------------------------------------------------------------------
Sl No Addressing mode Effective address Segment

1 Direct offset DS
2 Register indirect [BX] DS
[SI] DS
[DI] DS
3 Register relative Disp+ [BX] DS
Disp + [SI] DS
Disp + [DI] DS
Disp + [BP] SS
6 Based Indexed [BX] +[SI] DS

[BX]+DI] DS
[BP]+[SI] SS
[BP]+ [DI] SS
7 Relative Based Indexed Disp+ [BX][SI] DS
Disp+ [BX]DI] DS
Disp+ [BP][SI] SS
Disp +[BP]DI] SS
Table 1-2 : Effective address and referred segments for various memory based
addressing modes
Note that BP cannot be used without a displacement. See it being used in ‘register
relative’ mode but not in register indirect mode.
Segment Override
Table 1-2 shows the default segments to be used in the various memory based addressing
modes. However this can be overridden by a segment override prefix .i.e.. We can use
segments other than those specified in the table .The format of this override prefix is
shown below.
MOV AL , ES: [BX] overrides the fact that an instruction of this sort implies that the
data segment is to be used . Here it says that ES is to be used instead .Hence physical
address calculations use the content of the CS register as the base address.
Other examples are
MOV DS: [BP+7], BL ;DS to be used instead of SS
MOV AX, CS:[BX ] ;CS to be used instead of DS
Key points of this chapter
• The architecture of 8086 is representative of the architecture of all the members of the
x86 family .
• The data bus width of 8086 is 16 ,and internal registers also have the same bit size.
• The internal block diagram shows two units named the ‘execution unit’ and the ‘bus
interface unit’ with well defined and separate functions.
• The BIU and EU communicate through the internal bus .Both have a common timing
and control unit.
• The execution unit takes care of computations ,and thus it contains the necessary
registers and flags.
• The conditional flags are set or reset according to the result of certain arithmetic/logic
operations
• The 8086 has 20 address lines which means it can access 1 MByte of memory.
• Memory is segmented into four types of segments .
• Code and data are kept in separate segments.
• The upper 16 bits of the base address of any segment is available in the
corresponding segment registers.
• The stack segment is a type of segment which grows downwards as data is pushed
into it.
• The BIU converts the logical addresses to physical addresses.
• Segmentation makes data and code to be re-locatable.
• The addressing mode dictates where operands are available.
• 8086 follows the ‘little endian’ scheme of data storage in memory.
QUIZ
1. Name the 8 bit registers of 8086.

2. What is meant by saying that the 8086 is a 16 bit processor?
3. Which are the first and last memory addresses that an 8086 can address?
4. Which unit (EU or BIU) is responsible for performing arithmetic calculations?
5. .How will it be helpful for a processor if it has a large number of internal
registers?
6. What are the minus points regarding the presence of too many scratch pad
registers.?
7. Which are the registers catering to string instructions?
8. What is meant by a LIFO stack?
9. What is the difference in operation between the carry flag and the overflow flag?
10. Which register is frequently used as a counter?
11. Where in memory is program code located?
12. BP is a register which refers to the extra segment .True or False?
13. BP cannot be used without a displacement .True or False?
14. What is meant by the term ‘program relocation’?
15. What happens to the pre-fetch queue when a branch instruction is encountered?
16. What is the format of a logical address?
17. If the physical address of a byte is 12345H ,suggest three logical addresses that it
can have?
18. Which is the default segment when IP is used?
19. Can we have segments with size less than 64K?
20. Write an example instruction which contains a segment override prefix.
EXERCISE
1. Find the content of the destination and the status of the carry flag (CF) and zero
flag (ZF) after the execution of the following set of instructions
a) MOV AL,09H
ADD AL,CFH
b) MOV BX,0876H
MOV AX,0034H
ADD BX,AX
c)MOV AL,0FFH
ADD AL,01
2. Add the numbers 100 and 89 using the following instructions

MOV AL,100
ADD AL,89
Which of the conditional flags are set and why?
3. Show the binary number that will be available in AL after the execution of each
of the following instructions?
a)MOV AL ,’C’ b) MOV AL,25 c)MOV AL,34H
4. Find the physical address of the top of the stack if SS =0777H ,and SP =1234H .
5. If IP contains the number 0034H ,and CS= 5555H ,where will the next instruction
be fetched from?
6. If CS contains the number 0FC2H ,and the volume of code is 2400 bytes ,which
is the last address in this code segment?
7. Write the addressing mode of the following instructions .
a) MOV [4560H],AX
b) ADD BL,89H
c) ADD BX,[DI]
d) MOV 6[BP][DI],AL
e) MOV CX,[BP+9]
f) ADD CL,BL
8 Find the physical address of the memory locations referred in the following
instructions if DS=0223H , DI =0CCCH ,SI =1234H .
a) MOV [DI], AL
b) MOV [SI][56H] ,BL
9.Which segments will be accessed in the following cases?
g) MOV [6][BX],CX
h) MOV [BP]+4,CL
i) PUSH AX
j) MOV CS:[BX] ,DL
k) MOV AL,ES:[45H]
10 The memory addresses starting from the logical address 0124H: 0056H store
the numbers 0978H ,CE45H ,45H and 7809H in consecutive locations
Draw a diagram showing the physical address and the corresponding data stored .
CHAPTER 2
PROGRAMMING CONCEPTS –I
OBJECTIVES

• The working principle of an assembler
• The various assemblers available for x86
• The features and use of a popular assembler
• To write programs using simplified memory models
• To write programs using the full segment definition
• To understand the techniques of instruction design for 8086
A. ASSEMBLY LANGUAGE PROGRAMMING
In chapter 0 ,we have seen why assembly language is very important .To code efficiently
in assembly language for a particular processor ,the prerequisites are a good knowledge
of the internal architecture of the processor and addressing modes ,which means that
understanding the contents of chapter 1 is absolutely necessary .
When we want to write and execute an ALP ,we first type it using an editor .Then we
assemble link and run it .There are many assembly language program development tools
available for each of these actions .We shall examine them one by one .
2.1 The Assembly Process

The way an assembler is designed depends heavily on the internal organization of the
processor for which it is used.. Architectural features such as memory word size, number
formats, internal character codes, index registers, and general purpose registers affect the
way assemblers are written and the way an assembler handles instructions and directives.
In assembly language programming ,coding is done in symbolic language (called

mnemonics) . The word mnemonic comes from a Greek word meaning pertaining to
memory; it is a memory aid. The mnemonic specifies the operation to be done
We need a software called an assembler which translates this symbolic language to
machine code which the processor will understand .As such ,we guess that this
‘translation’ is indeed the main task of the assembler .
Let us first get an idea of the assembly process. An interesting definition for an
assembler is that it is a translator that translates source instructions( in symbolic
language) into target instructions (in machine language), on a one to one basis. The point
is that each source instruction is translated to exactly one target instruction. This is indeed
the main task of the translator. But an assembler is more than just a translator . It is an
important program development tool ,the quality of which can affect the ease of
programming . Since assembly language programming is more prone to errors (than
HLLs) ,the assembler should be good enough to give appropriate error messages to the
programmer and guide every step of his programming .
2.1.1 Features of assemblers
When code is written in assembly language ,it is easy if we can use labels (names) for
memory locations. All constants and variables are given names so that they can be
referenced by name . Managing and utilizing these labels (called symbols) efficiently
reflects on the quality of an assembler .
Assemblers that support macros are called Macro Assemblers .A Macro is a name given
to a sequence of instruction lines . Once a macro is defined , its name may be used in
place of this set of lines .In the assembly process, each macro is replaced by the text lines
.Thus a macro seems to the programmer to be like a mnemonic ,and he can use it as
frequently as he wants ,without incurring any of the overheads that a procedure or
function may cause.
The use of macros can help to make programs structured.
2.1.2 Instructions and Directives

An assembly language program contains pseudo –instructions (directives) along with
instructions .Instructions get translated to machine codes ,but directives don’t . i.e.
Instructions produce executable code ,but directives don’t. They direct the assembler to
perform in certain ways that we would like it to .The directives perform as ‘help’ for the
assembler for deciding certain other aspects of the assembly process.
Thus the assembler takes our source code (which is our program containing instructions
and directives) and converts it into object code which contains the machine code. The
object file is the one that will be loaded into memory and executed as many times as
necessary
2.1.3 The Forward Reference Problem
A typical line in a program could be
BEGIN : MOV AX , COST ; move the content of the location COST to AX
In this example, BEGIN is a label, which corresponds to the address at which this line
of code is stored . MOV is a mnemonic. This instruction means that the content of COST
is to be moved to register AX . COST is a label (for a memory location) which acts as
one operand in this two operand instruction .A label when defined is called a symbol . A
symbol can only be defined once but it can be used many times.
There will be a memory address corresponding to all symbols. In this instruction, the
other operand is AX . The text coming after ‘;’ is a comment .
All current assemblers allow the use of labels , rather than numeric addresses of memory
locations . But finally, the assembler must translate these labels to memory addresses .As
such, an important issue that an assembler will have to sort out is what is called the
‘forward reference problem’ .
See the code below
BEGIN : MOV AX , BX
JMP AGAIN
---------------
----------------
-
-
-
AGAIN: ----------
As the assembler reads the second line of this program ,an undefined label AGAIN is
encountered .The assembler has no knowledge of it as yet ,but the value of the symbol
AGAIN is needed before it can be defined .This is also called the future symbol problem
or the problem of unresolved references .
This problem is solved in various ways depending of the type of the assembler .
There are many types of assemblers-one pass , two pass and multi pass assemblers .Each
pass optimizes the assembly process.
2.1.4 Two Pass Assemblers

Two pass assemblers are the commonest, so let us discuss those. A pass implies ‘a
reading’ of the code from beginning to end .
A two pass assembler does two passes over the source file ( the second pass will be over
a file generated in the first pass ). In the first pass all it does is looks for label definitions
and inserts them in the symbol table after assigning them addresses. Modern assemblers
keep more information in their symbol table which allows them to resolve addresses in a
single pass. Known addresses (backward references) are immediately resolved. Unknown
addresses (forward references) are “back-filled” once they are resolved
Memory is allocated sequentially ,and a ‘location counter’ is incremented at each
step .At the end of this pass , the symbol table should contain definitions of all the labels
used in the program .This means that during the first pass, the only duty of the assembler
is assigning memory addresses to labels.
In pass 2 , the actual translation of assembly code to machine code is done .
Errors are also reported after this . The assembly process produces a ‘re-locatable ‘ object
file . This object file can be loaded anywhere in memory ,when the program is to be
executed .A ‘loader ‘ is a program which does this . Please note that loading can be done
anywhere in memory and that it is not necessary to load it at the same location each time
the program execution is done .
2.2 ASSEMBLERS FOR x86
Assembly language is specific to a particular processor .As such ,we should concern
ourselves with assemblers for the x86 family of processors ,which includes the whole set
from 8086 to Pentium . A large set of assemblers are available ,but the code running on
one assembler will not run on another .Another matter to be taken care of is the OS under
which it can run.
A86 was the first assembler to appear on the scene .It could run only under DOS .Now
there are assemblers which run under DOS ,Windows and Linux .
The names of a few popular assemblers are NASM ,FASM ,MASM ,TASM and HLA.
FASM and NASM can run under all these three OSes.
Two of the very popular assemblers are TASM and MASM. TASM is Borland’s Turbo
Assembler ,while MASM is Microsoft’s Macro Assembler . It is found that code written
on TASM runs on MASM ,though the reverse is need not be true
Both of them run under DOS and Windows, which means they can use 16 bit and 32 bit
coding .Both of them are classified as High level Assemblers which mean that we can use
high level control structures (IF, WHILE, REPEAT….UNTIL etc.) which makes
programming easy .
HLA is another assembler which uses high level control structures ,high level data types
and High level procedure calls .
2.2.1 Why MASM ?
For programs in this book ,we will choose MASM because it is one of the best
assemblers and also because of its popularity . A popular assembler gives us the chance
to get easy access to references and material . Also MASM has many constructs and
features which makes ALP easy and fun for beginners
Another reason is that the documentation available for it is very good . MASM was a
commercial product for a very long time ,and is a sort of industry standard. Microsoft has
written considerable documentation for this assembler and many third parties have
written assembly language reference manuals for MASM. The versions of MASM 6.0
and above have a lot more features (aimed at simplification in writing code )than
previous versions .
Incidentally ,MASM is a proprietary product of Microsoft. We will now use the 16 bit
version which runs under DOS ,because we can use DOS and BIOS interrupts in this
version . . There is a 32 bit version which runs under Windows This is freely available on
the net (The 32 bit version does not allow the use of DOS and BIOS interrupts) . In later
chapters, we will use MASM32 for the 32 bit x86 processors This approach gives a very
good understanding of assembly language in general . The DOS version used for
programs in this book is MASM 6.14.These programs will run in all versions of MASM
from 6.0 upwards.
2.2.2 ASSEMBLY LANGUAGE PROGRAMMING

Now that we have understood the assembly process and have decided the assembler to
use ,let us get into the nitty gritty of programming .
The steps involved are
i) Write the code with the help of an editor . We can have an editor within
MASM or can use notepad or wordpad . Save it as filename.asm in the BIN
directory of MASM. Note that instructions, directives and labels are not case
sensitive.
ii) Open the DOS command window and go to the directory containing
MASM. From this ,go to the BIN directory
ii) Assemble the code . Syntax errors (if any) will be reported at this stage
This will generate the object file with the name filename.obj .Other files are
also generated and we can opt to view them .(list file ,configuration file etc)
Details of these are given in Appendix A.
iii) Link the object file . The linking involves combining separately assembled
modules into one executable file ( filename.exe)
iv) Run the exe file .This will cause the program to be loaded in memory and
executed .
v) The results of execution will be in memory or in registers .If we want to view
it on our display unit ,we will have to use special codes for it (this will be
discussed later). Otherwise ,we can examine the memory and register contents
using the debugger . The debugger has all the commands needed to do this ,
and the full set of commands is detailed in Appendix A.
2.3 Memory Models

To write programs ,we know we have to define segments, which means that the segment
registers must be initialized . This will take us to the conventional full segment model
.However versions of MASM 6.0 and above have incorporated certain short cuts which
help to make programming simple .These are called the dot models.They have the format
. MODEL MODEL NAME

The different models tell the assembler how to use segments and to provide sufficient
space for the object code . The simplest of these are the tiny model and the small model.
We will start with these models . The tiny model is used when code ,data and stack will
all fit into one segment with a maximum size of 64K . The small model can have one
data segment and one code segment each of which has a maximum size of 64K.
2.3.1 The Tiny Model
Let us now write a program using the tiny model.

-----------------------------------------------------------------------------------------------------------
Example 2.1
.MODEL TINY ;choose single segment model
.CODE ;start of code segment
.STARTUP ;start of program
MOV AL,67H ;move 67H to AL
MOV BL,45H ;move 45H to BL
ADD AL,BL ;add BL to AL
MOV DL,AL ;copy AL to DL
.EXIT ;exit to DOS

END ;program end
----------------------------------------------------------------------------------------------------------------
Let us enter this code using an editor and save it as tinym.asm in the BIN directory of
MASM6.14. Open the DOS command window .Go to the directory MASM 6.14/BIN .
In the BIN directory , assemble and link the file use the command ml tinym.asm .
Example 2.2 shows the DOS command window corresponding to this .The ml command
causes assembling and linking to be done at one go . .
Now to get the list file , type the command ml/Fl tinym.asm .The list file will be saved
in the BIN directory as tinym.lst
(More commands and options are available in Appendix A)
Earlier versions of MASM required two steps for the same actions.
To assemble , the command was masm filename.asm
Linking required the command link filename .obj
The list file was obtained by using masm/l filename.asm
Examples 2.2 shows the DOS command window as we do assembling and linking .
Example 2.3 shows the list file .
Note: If you think this part is taxing , rush through these topics fast and come back
to it after you have learned more aspects of programming and are ready to do
programming using this assembler.
________________________________________________________________
Example 2.2
C:\masm6.14\BIN>ml tinym.asm
Microsoft (R) Macro Assembler Version 6.14.8444
Copyright (C) Microsoft Corp 1981-1997. All rights reserved.
Assembling: tinym.asm
Microsoft (R) Segmented Executable Linker Version 5.60.339 Dec 5 1994

Copyright (C) Microsoft Corp 1984-1993. All rights reserved.
Object Modules [.obj]: tinym.obj /t

Run File [tinym.com]: "tinym.com"
List File [nul.map]: NUL
Libraries [.lib]:
Definitions File [nul.def]:
_________________________________________________________________________
Example 2.3
Microsoft (R) Macro Assembler Version 6.14.8444

tinym.asm Page 1 - 1

0000 .CODE ;start of code segment
0100 B0 67 MOV AL,67H ;move 67H to AL
0102 B3 45 MOV BL,45H ;move 45H to BL
0104 02 C3 ADD AL,BL ;add BL to AL
0106 8A D0 MOV DL,AL ;copy AL to DL
.EXIT ;exit to DOS

END ;assembler to stop reading
--------------------------------------------------------------
Example 2.3 shows the listing corresponding to our tinym program.
( Only a part of the list file is shown here. See Appendix A for the additional details.)
A lot of information can be obtained just by looking at the list file .The list file is one of
the outputs obtained in the assembly process .
Examine Example 2.3
We see first the details of the version of MASM that is used.
The complete assembly language program along with the comments that we had typed in
, is seen next.. On the left hand side, we see the offsets within the code segment in which
the code is saved .These offsets have been generated by the assembler .We also find the
opcodes corresponding to each instruction.
For example in the first line which is
0100H is the offset in the code segment where the first instruction is stored ,and B0 67 is
the opcode of MOV AL,67H . If we add a directive .listall , the list file is changed as
shown in Example 2.4
------------------------------------------------------------------------------------------------------------
Example 2.4
.MODEL TINY
0000 .CODE
.STARTUP
0100 *@Startup:
.listall

0102 B3 45 MOV BL,45H ;move 45H to BL
0104 02 C3 ADD AL,BL ;add BL to AL
0106 8A D0 MOV DL,AL ;copy AL to DL
.EXIT ;return to DOS

0108 B4 4C * mov
ah, 04Ch
010A CD 21 * 021h int
END
----------------------------------------------------------------------
.Listall has listed the instructions corresponding to .EXIT
.EXIT is a shortcut which is actually transformed to two instructions
MOV AH,4CH
INT 21H
These two instructions terminate program execution and bring control back to DOS.
END is a directive .It tells the assembler to stop reading ,as there are no instructions
beyond this . The .STARTUP command is available only is versions of MASM 6.0 and
above .It is a shortcut ,whereby segment registers get initialized automatically ,which
means that programmers need not write instructions for that .
Now let us use the debugger to get more information about these aspects .
The debugger allows us to view memory and registers, along with various other functions
(See Appendix A)
To enter the debugger ,type debug tinym.com .
We get an underscore as the prompt.
On typing ‘r’, we can see the contents of the registers ,before execution of the program .
Now type ‘u’, which is the command for unassembling.
Unassembling is the reverse of assembling. It gets the mnemonics back from the
machine codes.
Example 2-5 gives the result of these two commands
---------------------------------------------------------------------------------------------------------
Example 2.5
C:\masm6.14\BIN>debug tinym.com
-r
AX=0000 BX=0000 CX=010C DX=0000 SP=0000 BP=0000 SI=0000 DI=0000
DS=13AD ES=13AD SS=13BD CS=13BD IP=0100 NV UP EI PL NZ NA PO NC
13BD:0100 B067 MOV AL,67
-u
13BD:0100 B067 MOV AL,67
13BD:0102 B345 MOV BL,45
13BD:0104 02C3 ADD AL,BL
13BD:0106 8AD0 MOV DL,AL
13BD:0108 B44C MOV AH,4C
13BD:010A CD21 INT 21
-------------------------------------------------------------------------------------------------
The r command gives us the content of the registers, before the execution of the
instruction MOV AL,67H .
We find that the content of the CS register is CS=13BD.
On typing the ‘u’ command ,, we find that the logical address of the first instruction is
13BD:0100 . The value of CS need not be the same every time the program is loaded into
memory .This is because of the fact that object file generated by the assembler is
re-locatable.
2.3.2COM and EXE files

For this program ,there is only one segment ,which is the code segment .The run file
generated for the tiny model is a Command( .com )file ,rather than an Executable( .exe)
file .This can be seen in Example 2.2 .in the line
Run File [tinym.com]: "tinym.com"
Later ,it will be seen that run files will be obtained as ‘executable ‘ with .exe as the
extension . But the tiny model always assembles to be a com file .This is the special case
,when we need a compacted form of data and code ,all fitting into just 64K size for
memory efficiency . Other models which we will see later ,all assemble to .exe files .
Quantifying the features of COM files :
i) Size is limited to 64K
ii) Only one segment ,which is the code segment
iii) Data is defined in this code segment
iv) Code starts at offset 0100 H ,just after the PSP (program prefix segment ) of
DOS
v) Smaller file compared to exe files ,because it does not have the 512 byte
header block
From the examples 2.2 to 2,5 , we see the tactics of running and analyzing a single
segment assembly language program running on MASM.
Now , see the listing corresponding to another program which uses the tiny model .
---------------------------------------------------------------------
Example 2.6

0100 8B C8 MOV CX,AX ;copy contents of AX to CX

0102 8B C2 MOV AX,DX ;copy contents of DX to AX
0104 8A C3 MOV AL,BL ;copy contents of BL to AL
0106 8A E1 MOV AH,CL ;copy contents of CL to AH
0108 8A F2 MOV DH,DL ;copy contents of DL to DH
010A 8E DA MOV DS,DX ;copy contents of DX to DS
010C 8E D3 MOV SS,BX ;copy contents of BX to SS
.EXIT ;exit to DOS

END ;end of program
--------------------------------------------------------------------
Example 2,6 shows a sequence of instructions that copy various data between 16 and 8
bit registers. The act of moving data from one register to another changes only the
destination register ,never the source.
-------------------------------------------------------------------------------------------------------
Example 2.7

0100 B8 0000 MOV AX,0 ;place 0000 into AX
0103 B0 43 MOV AL,'C' ;place ‘C’ into AL
0105 B9 5674 MOV CX,05674H ;place 5674H into CX
0108 B2 2D MOV DL,45 ;place 45 (decimal) into DL
010A B6 45 MOV DH,45H ;place 45H into DH
.EXIT ;exit to DOS
END ;end of program
--------------------------------------------------------------------
Example 2.7 shows various assembly language instructions that use
immediate addressing .Only 8 bit data can be placed into an 8 bit register . AL,DL and
DH are 8 bit registers.16 bit data can be copied to 16 bit registers. Though in the editor
,the second instruction was written as MOV AL,'C' , the assembler translates ASCII 'C'
to its hex equivalent 43H. All data written in memory will be in the hex format (i.e. the
compressed form of binary representation).Thus the decimal 45 is found to 2D H in the
listing .
Important note: A data (byte ,word or longer) starting with the hex characters
A,B,C,D,E or F must be preceded by a 0 .Otherwise the assembler will give an error .
.i.e. MOV AL, EFH gives an assembly error .It must re-written as
MOV AL,0EFH
Similarly MOV BX,C456H is wrong .Rewrite it as MOV BX,0C456H
2.3.3 Definition of data types
Before we go on to using a two segment memory model ,we need to understand a few
directives of the assembler which define and describe different kinds of data.
Data which is used in a program can be bytes or words or of greater length .We have to
define data and assign labels to their corresponding addresses . Assigning labels eases
the programmer’s burden as he does not have to concern himself with numerical values
.The location counter in the assembler keeps on incrementing as labels are
encountered.
Defining data implies allocating space for data . Data is defined accordingly using
directives . Thus DB defines data byte ,while DW defines data word. This is the
traditional way of defining data . The newer versions of MASM (6.0 and higher)allow the
use of the directive BYTE for DB ,and WORD for DW ..
Table 2.1 shows the definitions of data of different lengths.
Definition Traditional Directive New Directive

Byte DB BYTE
Word DW WORD
Double word DD DWORD

Quad word DQ QWORD
Ten bytes DT TBYTE
Table 2.1 : Data definitions used by MASM

------------------------------------------------------------------------------------------------------
Example 2.8
.MODEL TINY
0000 .CODE
0000 50 NUM1 DB 50H ;place 50H into NUM1
0001 210A NUM2 DW 210AH ;place 210AH into NUM2
0003 0789 NUM3 DW 0789H ;place 0789H into NUM3
.STARTUP
0100 A0 0000 R MOV AL,NUM1 ;move NUM1 to AL

0103 8B 1E 0001 R MOV BX,NUM2 ;move NUM2 into BX
0107 8B C8 MOV CX,AX ;copy AX to CX
0109 8B 1E 0003 R MOV BX,NUM3 ;move NUM3 into BX
.EXIT
END
------------------------------------------------------------------
Example 2.8 shows data being placed in the code segment itself .i.e. In the tiny model ,
we can have data and code in the same segment ,with the restriction is that the size of the
segment should not exceed 64Kbytes. NUM1 ,NUM2 and NUM3 are locations which
store data . NUM1 is a byte location ,while NUM2 and NUM3 are word locations.
2.3.4 The small model

Now we are in a position to write a program using the small model , which has one data
segment and one code segment .Example 2.9 shows the same program as in Ex 2-8
,except that a separate data segment is used to store the data.
---------------------------------------------------------------------------------------------------------
Example 2.9a
.MODEL SMALL ;choose small model

0000 .DATA ;start data segment
0000 50 NUM1 DB 50H

0001 210A NUM2 DW 210AH
0003 0789 NUM3 DW 0789H
0000 .CODE ;start code segment

0017 A0 0000 R MOV AL,NUM1

001A 8B 1E 0001 R MOV BX,NUM2
001E 8B C8 MOV CX,AX
0020 8B 1E 0003 R MOV BX,NUM3
.EXIT
END
-------------------------------------------------------------------
The salient points of this program listing are
i) The word R on code lines with addresses says that the addresses are
re-locatable. This can be observed in the listing of Example 2.8 as well.
iii) In the data segment ,data locations have been given labels . Data will
be stored at offsets as shown in fig below (recollect the little endian
concept.
LABELS OFFSET DATA(H)

NUM3+1 0004 07
NUM3 0003 89
NUM2+1 0002 21
NUM2 0001 0A
NUM1 0000 50
Fig 2.1 Data segment with labels and offsets corresponding to Example 2.9
Now let us see the same program listing with the .LISTALL directive inserted before
the startup directive .This will show the conversion of .STARTUP and .EXIT to a
number of instructions of 8086 . What is to be noted is that the startup directive
corresponds to instructions necessary to initialize the segment registers (except CS ,which
is done by the OS alone.)Compare this to Example 2-11. But if all this confuses you
,leave it aside for the time being and come back to it when you become more proficient in
assembly language programming,
-----------------------------------------------------------------------------------------------------------
Example 2-9b
.MODEL SMALL ;choose small model

0000 50 NUM1 DB 50H

0001 210A NUM2 DW 210AH
0003 0789 NUM3 DW 0789H
.LISTALL
0000 *@Startup:
0000 BA ---- R * mov dx, DGROUP
0003 8E DA * mov ds, dx
0005 8C D3 * mov bx, ss
0007 2B DA * sub bx, dx
0009 D1 E3 * shl bx, 001h
000B D1 E3 * shl bx, 001h
000D D1 E3 * shl bx, 001h
000F D1 E3 * shl bx, 001h
0011 FA * cli
0012 8E D2 * mov ss, dx
0014 03 E3 * add sp, bx
0016 FB * sti
0017 A0 0000 R MOV AL,NUM1

001A 8B 1E 0001 R MOV BX,NUM2
001E 8B C8 MOV CX,AX
0020 8B 1E 0003 R MOV BX,NUM3
.EXIT
0024 B4 4C * mov ah, 04Ch
0026 CD 21 * int 021h
END
---------------------------------------------------------------------------------------------------------
2.3.5 The DUP Directive
This directive is used to replicate a given number of characters. For example ,we may
want to fill up a number of locations in the data segment with the same word or byte .
NUMS DB 10 DUP(0) fills up with 0s the 10 byte locations starting with the label
NUMS.
STARS DB 5 DUP(‘#’) fills up 5 byte locations starting at location STARS,
with the ASCII value of the character # .
BLANK DB 10DUP(?) reserves 10 byte spaces starting from location with the label
BLANK ,but these are not initialized ,which implies that whatever data is there will
remain .We can overwrite these locations with new data when we choose to .
WRDS DW 4 DUP(FF0FH) fills up 4 word locations with the word FF0FH.
2.3.6The EQU Directive
This directive allows us to equate names to constants .The assembler just replaces the
names by the values mentioned .Examples are
TEMP EQU 34
PRICE EQU 199
----------------------------------------------------------------------------------------------------------
Example 2.10
.MODEL SMALL
0000 .DATA
0000 45 ONE DB 45H
0001 00 TWO DB ?
0000 .CODE
.STARTUP
= 0025 FACTR EQU 25H
0017 A0 0000 R MOV AL,ONE ;copy ONE to AL

001A 04 25 ADD AL,FACTR ;add FACTR to AL
001C A2 0001 R MOV TWO,AL ;move the sum to TWO
.EXIT
END
----------------------------------------------------------------------
Example 2.10 shows the use of the EQU directive . From the list file, we see that the
label FACTR is replaced by 25H when the program is being executed.
2.3.6 The ORG Directive

ORG is a directive which means ‘origin’. In the context of assembly language
programming, it can change the location of storage of data or code in memory –i.e. the
programmer gets the freedom to decide the offset of data/code when it is stored. The
format is ORG d16 ,where d16 means a 16 bit displacement.
Let us try out the usage of this directive.
----------------------------------------------------------------------------------------------------------
Example 2-12a
.MODEL SMALL
.DATA
ORG 0010H ;origin to be at 0010H

NUMS DB 20H,40H
ORG 0030H ;origin to be at 0030H
NUMS1 DW 8907H,0FDH
.CODE
.STARTUP
ORG 000AH ;org is a directive
MOV AL,NUMS ;this is an instruction
MOV BL,NUMS+1 ;this is an instruction
ORG 0020H ;org is a directive
MOV DX,NUMS1 ;this is an instruction
.EXIT
END
-----------------------------------------------------------------------------------------------------------
Example 2-12b
.MODEL SMALL
0000 .DATA
ORG 0010H
0010 20 40 NUMS DB 20H,40H
ORG 0030H
0030 8907 00FD NUMS1 DW 8907H,0FDH
0000 .CODE
.STARTUP
ORG 000AH
000A A0 0010 R MOV AL,NUMS

000D 8A 1E 0011 R MOV BL,NUMS+1
ORG 0020H
0020 8B 16 0030 R MOV DX,NUMS1
.EXIT
END
--------------------------------------------------------------------------------------------------------
Example 2-12 b is the list file corresponding to the program in Example 2-12a.
Compare it to any of the list files seen earlier . Now neither the data or code segments
start at the default offset of 0000. The data and code coming after the ORG statements
have offsets as specified in the ORG directive . It has thus left out a lot of space in both
the data and code segments.
2.3.7 Other Models
These are other models available to be used according to our requirements. See the table
below to get an idea of those models and their specifications.
Sl Name How many code segments? How many data segments?

No
1 Tiny 1 Nil
2 Small 1 ,max size 64K 1 ,max size 64K
3 Medium Any number ,any size 1 ,max size 64K
4 Compact 1 ,max size 64K Any number ,any size
5 Large Any number ,any size Any number ,any size
6 Huge Any number ,any size Any number ,any size
Table 2.2 The different memory models used by MASM
There is another model called the flat model ,which uses 32 bit addressing and
unsegmented memory and is used in the protected mode.
From the above ,it is clear that all the models are not for 8086 alone,but are the features
of MASM which caters to the whole x86 family.
2.3.8 Full Segment Definition

Now let us see the traditional model of MASM. In the simplified memory model ,it is
left to the loader to initialize the segment registers .In the traditional model ,we use
directives to define segments ,and instructions to initialize the segment registers .This is
called the Full Segment definition. The CS and SS registers are automatically initialized
by the loader ,but the DS and ES (if the extra segment is being used) will have to be
initialized by the programmer .
Let us re-write Example 2.9 using the full segment definition.
-----------------------------------------------------------------------------------------------------------
Example 2-11
DAT SEGMENT ;start the data segment

NUM1 DB 50H
NUM2 DW 210AH
NUM3 DW 0789H
DAT ENDS ;end the data segment
COD SEGMENT ;start the code segment
ASSUME CS:COD.DS:DAT
MOV AX,DAT ; move DAT to AX
MOV DS,AX ; copy AX to DS
MOV AL,NUM1
MOV BX,NUM2
MOV CX,AX
MOV BX,NUM3
MOV AH,4CH
INT 21H
COD ENDS ;end the code segment
END ;end of program
--------------------------------------------------------------
The salient features of this model are :
i) The data segment has been given a name DAT . The data within the segment
is enclosed between the SEGMENT and ENDS directives which are similar to
parentheses for a segment .
ii) Similarly ,the code segment is named COD and the contents of this segment
also have been enclosed between the same directives
iii) The DS register has been initialized by the first two instructions. DS cannot
use immediate addressing .Hence DAT, which corresponds to a number has
to be loaded to AX (or any other16 bit register)and then transferred to DS.
iv)
The value of DAT is loaded into DS . This means that DAT corresponds to
the base address of the data segment .But only when the loader loads this
program in memory ,will the actual base address (i.e. the upper 16 bits of the
base address) be loaded into the CS register. At this point ,the assembler just
recognizes the ‘reference’ to a segment named DAT.
iv) The CS register need not be initialized in the program .This is done by the
loader by default.
v) The program is terminated by using the DOS INT 21H with function
number 4CH
(DOS function calls will be discussed in detail later)
vi) ASSUME is a directive which relates each segment to its segment register,
by specifying the name .
However ,the simplified dot models will be used throughout this text book ,except when
special reasons call for the use of the full segment definition. In older versions of MASM
,before the advent of the .startup directive , segment registers had to be initialized with
the instructions as below .
MOV AX ,@DATA
MOV DS, AX
where .DATA is used at the start of the data segment .
2.3.9 General rules for writing assembly language
Now let us summarize the general format for an assembly language line with an example
.
---------------------------------------------------------------------------------------------------------
Example 2-12
LABEL OPCODE OPERAND COMMENT
NUM1 DB 56H ;define NUM1 as a byte of 56H

NUM2 DW 0557AH ;define NUM2 as a word of 0557H
START: MOV BL,NUM1 ;copy NUM1 into BL

MOV AL,BL ;copy BL into AL
-------------------------------------------------------------------------------------------------------------------------------
An assembly language line has four fields namely ,label ,opcode ,operand and comment.
A label is positioned at the left of a line and is the symbol for the memory address which
stores that line of information .There are certain rules regarding labels that are allowed
under MASM.
i) All labels should begin with a letter or the special characters @,$ , _ and ? .
ii)A label can have 1 to 31 characters which may be digits ,letters in upper or lower
case or the special characters at (@),dollar($) , underscore (_) ,dot(.) or question mark(?)
iii)No reserved words of MASM may be used
iv)Each label must be unique .
The second field is the opcode or instruction field . The third is the operand field ,and the
last is the comment field which starts with a semicolon.
The usage of comments is advised for making programs more readable ..
2.4 INSTRUCTION DESIGN
Upto now ,we were discussing assemblers ,the best assemblers available and how to run
our programs using assemblers and other program development tools. Now ,let us go a bit
deeper into the core of the processor and investigate the process of how machine codes
have been designed . In doing so ,we will realize why the assembly process is a ‘one to
one’ process.
2.4.1 Manual Coding
Another idea to think of is the possibility of doing manual or hand coding, as it is called
–i.e. taking an assembly instruction ,looking up or finding out its machine code and
feeding it directly to the processor .Why not ? It looks quite feasible ,doesn’t it ?.Actually
it is , but very soon it becomes obvious that it is too cumbersome to think of
programming as fun.
During the time that the 8085 was a popular processor ,hand coding was the rule rather
than the exception .This was because 8085 had a limited instruction set and a look up
table was sufficient for hand coding . The scenario has changed with the 8086 , which
has more registers and more instructions –but the most notable fact is that it has many
,many more modes of addressing -which implies that each instruction can be expressed
in too many modes to facilitate the use of a look up a table . With the more advanced
of the x86 processors coming to the scene ,the difficulty has multiplied many fold .As
such ,we will conclude that using a standard and good assembler is the best solution .
However ,it will be very instructive and informative to understand how and why a
particular mnemonic has been converted to a particular code .
Let us understand the underlying principles of the Instruction set architecture of 8086 .
2.4.1 Instruction Set Architecture(ISA)
The following statement gives an almost appropriate definition of what is meant by ISA.
An instruction set, or instruction set architecture (ISA), is defined as the part of computer
architecture related to programming, including the native data types, instructions,
registers, addressing modes, memory architecture, interrupt and exception handling, and
external I/O. An ISA includes a specification of the set of opcodes (machine
language),i.e. the native commands implemented by a particular CPU design.
It must be noted that processors with the same ISAs need not have the same internal
designs(microarchitectures) –they only need to share a common instruction set .That is
why we find that AMD64 and P64 have the same ISA but they are not the same internally
. The ISA is an interface between a higher level language and the machine language .
2.4.2 Instruction set design of 8086
Now let us get to the 8086 processor ,which is a CISC processor .One feature of
CISC is that its instruction size varies –i.e. all instructions do not have the same size .
8086 has instruction size varying from one byte to five bytes. This makes the
processes of assembly, disassembly and instruction decoding complicated because the
instruction length needs to be calculated for each instruction. An instruction should have
the complete information for fetching and executing an instruction . It should thus have
the following information.
i Opcode corresponding to the operation to be carried out

i. Size of the operands
ii. Addressing mode of each operand mentioning one or more of the following :
a) General purpose register
b) Value of an immediate operand
c) Address of operand
d) Base register
e) Index register
f) Combination of a base and index register
g) Displacement in combination with base/index/ [base+index] registers
See the general format of the first three bytes of the instruction.
i)
PREFIXES
(OPTIONAL)
ii)
OPCODE D W
(6 bits) (1 (1
bit) bit)
iii)
MOD REG R/M
(2 bits) (3 bits) (3 bits)
Fig 2.2 Format of three bytes of an instruction
PREFIX:
This is an optional byte and need to be used only to change the operation. e.g. segment
override prefix
FIRST BYTE:
This is considered to be the first byte of an instruction .
In this byte ,there is the operation code(opcode) which is 6 bytes long .This is the code
which defines the operation to be carried out. The other two bits are the D and W bits.
W (1 bit)- operand size .W=1 ,means word operand ;W=0 means byte operand.
D (1 bit) –Direction bit .D=1 means register is destination ;D=0 means register is source.
SECOND BYTE:
MOD (2 bit)- Register bits
REG (3 bit) –the identifying code of the register used .
R/M (3 bits) – Specifying a register or memory operand.
The MOD and R/M bits together specify the addressing mode of the instruction.
Note : All instructions need not have the W and D bits. In such cases, the size of the
operand is implicit ,and the direction is irrelevant .
2.4.3 Designing a code
The design of a code requires more information than has been presented so far.
We need the identifying codes of the registers, obviously .
Each 16 bit and 8 bit register has a unique code .These codes are given in Table 2.3 and
2.4 . In addition , a table showing the MOD and R/M bits corresponding to various
combinations of addressing modes is also given . Using these ,code design will be quite
simple. We also need the Intel manual for the opcodes and formats of instructions .This
is given in Appendix B.
REG W=0 W=1

000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI
Table 2.3 : Codes of general purpose registers
SEGMENT CODE
REGS
ES 00
CS 01
SS 10
DS 11
Table 2.4 : Codes of Segment Registers
MOD
R/M 00 01 10 11
W=0 W=1
000 (BX) +(SI) (BX) +(SI) + d8 (BX) +(SI) + d16 AL AX
001 (BX) +(DI) (BX) +(DI) + d8 (BX) +(DI) + d16 CL CX
010 (BP) +(SI) (BP) +(SI) + d8 (BP) +(SI) + d16 DL DX
011 (BP) +(DI) (BP) +(DI) + d8 (BP) +(DI) + d16 BL BX
100 (SI) (SI) + d8 (SI) + d16 AH SP
101 (DI) (DI) + d8 (DI) + d16 CH BP
110 d16 (direct address) (BP) + d8 (BP)+ d16 DH SI
111 (BX) (BX) + d8 (BX) + d16 BH DI
MEMORY MODE REGISTER MODE
d8 and d16 are 8 bit and 16 bit displacement respectively
Table 2.5: Codes pertaining to addressing modes –MOD and R/M bit patterns
With the help of the above tables, let us try designing a code for a few simple
instructions .
i)MOV AX,BX
Coming to our task ,first look in the Intel manual for the opcode of MOV ,with the
specification of ‘Register /Memory to /from Register . It is seen to be 100010. This will
correspond to the first 6 bits of the first byte .
W=1,as the operand is a word.
The direction bit D has to be defined . In this case ,both the source and destination are
registers . Let us view it as a word being moved to AX .i. e, register AX is thus the
destination. Hence D=1 .Then we must use the code of AX in the register field of the
second byte . The first byte is
OPCODE D W
1 0 0 0 1 0 1 1
Fig : 2.3a Byte 1
To design the second byte ,first look in Table 2.5 for the MOD and R/M bits. We find
that the MOD bits are 11 (last column of the table) for register addressing , the reg bits
are 011 for AX (from Table 2.3) and the R/M bits are treated as the ‘second register’
field .Here ,the second register is BX ,the code of which is 011 (Table 2.5,4th row). Thus
the second byte is
MOD REG R/M

1 1 0 0 0 0 1 1
FIG 2.3 b Byte 2
There is no other information needed in coding this instruction .This is a two byte
instruction with the code 8B C3 H .
ii) ADD BL,CL
OPCODE D W
0 0 0 0 0 0 1 0
Fig 2.4a Byte1
MOD REG R/M

1 1 0 1 1 0 0 1
Fig 2.4b Byte 2

The opcode of ADD with the specification of ‘Register/Memory with Register to either’
is 00000 . W=0 since it is a byte transfer. D=1 considering BL as the destination register.
For the second byte , MOD =11 .Register code for BL is 011, R/M bits corresponding to
CL is 001. The code thus is 02 D9 H.
iii)MOV CX, 0213H

This is an instruction in the immediate mode .Two bytes are necessary for the immediate
data ,which is 16 bit Now let us took at Intel’s manuals on the format of MOV in the
immediate mode ‘to register’. .It shows
1011 W Reg data data if W=1
Fig 2.5 Format of a MOV instruction in the immediate mode
Here W=1 ,Reg (CX) =001

Hence the coding of this instruction is 1011 1001 as the first byte followed by the word
data in the liitle endian scheme as 13 02 H
The complete instruction is B9 13 02H.
iv)MOV DX,[23CDH]
OPCODE D W
1 0 0 0 1 0 1 1
Fig 2.6a Byte 1
MOD REG R/M

0 0 0 1 0 1 1 0
Fig 2.6b Byte 2
The first byte is 8BH .The second byte has MOD =00 (Column 2 in Table 2.5 ) and
R/M bits are 110 (corresponding to direct addressing in Table 2.5).Thus the second byte
is 16H .This is followed by the direct address in little endian form.
The four byte machine code is 8B 16 CD 23 H
v)MOV [BX],DH
OPCODE D W
1 0 0 0 1 0 0 0
Fig 2.7a Byte 1
MOD REG R/M

0 0 1 1 0 1 1 1
Fig 2.7b Byte 2
For the second byte ,MOD =00 corresponding to [BX]. The register bits are 110 for DH
,and R/M =111 from Table 2.5. Thus the instruction code is 88 37H.
vi) MOV AL,[SI[BX]

OPCODE D W
1 0 0 0 1 0 1 0
Fig 2.8a Byte 1
MOD REG R/M

0 0 0 0 0 0 0 0
Fig 2.8 b Byte 2
By following the same procedure as discussed for the previous instructions, the code for
this is 8A 00 H.
vii) ADD AX,53H[SI][BX]
OPCODE D W
0 0 0 0 0 0 1 1
Fig 2.9 a Byte 1
MOD REG R/M

0 1 0 0 0 0 0 0
Fig 2.9b Byte 2
The third byte of the instruction is 53H ,being the 8 bit displacement given in the
instruction. Thus the code is 03 40 53 H.
Segment override prefix
viii)MOV CS: [BX],DH

The segment override prefix is a byte with the format 001XX110. In place of XX,the
code of the segment register which overrides the default segment ,has to be inserted .
For the above instruction ,the prefix byte is 00101110 ,using the code of CS which is 01
(Table 2.4 ). We have already coded the instruction MOV [BX],DH .
Appending the prefix to it ,the three byte code is now 2E 88 37 H.
Now, to confirm if the ‘hand coding’ we have done is correct, let us put it all in a
program and examine the list file .Example 2.13a is the .program and 2.13 b is the
unassembled file from the debugger which contains the assembly code as well as the
machine code.. On checking it, we find that our hand coding indeed agrees with the
assembler’s coding .
-----------------------------------------------------------------------------------------------------------
Example 2.13a
.MODEL SMALL
.DATA
ORG 23CDH
DAT DW 0000
.CODE
.STARTUP
MOV AX,BX
ADD BL,CL
MOV CX,0213H
MOV DX,DAT
MOV [BX],DH
MOV AL,[SI][BX]
ADD AX,53H[SI][BX]
MOV CS:[BX],DH
MOV AX,CS:[BX]
.EXIT
END
Example 2.13b
0B56:0017 8BC3 MOV AX,BX
0B56:0019 02D9 ADD BL,CL
0B56:001B B91302 MOV CX,0213
0B56:001E 8B16CD23 MOV DX,[23CD]
0B56:0022 8837 MOV [BX],DH
0B56:0024 8A00 MOV AL,[BX+SI]
0B56:0026 034053 ADD AX,[BX+SI+53]
0B56:0029 2E CS:
0B56:002A 8837 MOV [BX],DH
In the debugger ,the unassembled instructions are shown above, with the
addresses(offsets within the code segments) of the instructions also shown.
For example, in the line
0B56:0019 02D9 ADD BL,CL
0B56 is the CS value ,0019 is the offset of the instruction , and 02D9H is the machine
code of the instruction ADD BL,CL .
Note how the address of the next instruction depends on the size(number of bytes) of the
current instruction .
--------------------------------------------------------------------------------------------------------
Now ,that we have the procedure of coding for a few instructions , it can be concluded
that manual coding is an alternative in the absence of an assembler ,but it is not a good
practice to rely on it . Using a good assembler is recommended for fast and efficient use
of assembly code.. But knowing the methodology of coding does help us to get an idea of
the way data ,registers and instructions are handled by the processor
Note: All the instructions we have coded in this section are at least two bytes in length.
But there are some instructions that have only one byte –Examples are STI (set interrupt
flag),CLD (clear direction flag)etc .Try to find out why they are only one byte long.
Key Points of this chapter
• An assembler is a software that translates assembly language into machine code

on a one to one basis.
• Assemblers convert labels to memory addresses.
• An assembly language program contains instructions and directives-the former
produces executable code but the latter only gives directions to the assembler
• For an assembler, having to know the memory address corresponding to a label
that has not yet been defined is called the ‘forward reference’ problem.
• Assemblers can be one pass, two pass or multipass. Each pass refines the
optimality of the assembly process.
• A number of assemblers are available for x86,of which MASM is currently one of
the most popular ones.
• MASM 6.14 and MASM32 are used in this book.
• The tiny model is a memory model which is compact ,and allows only one
segment. The run file generated herein is a com file.
• The small model needs a data segment as well. It generates an exe file as the run
file.
• Data types have to be defines as bytes, words etc ,before labels are used for data.
• Programs can also be written using the conventional ‘full segment definition’.
• Hand coding of instructions is possible if all the information pertaining to
instruction formats ,mode, register codes ,opcodes etc are available .
QUIZ
1. The translation from assembly code to machine code is a one to one
process ,but the translation from a high level language to machine code is
not so .Explain why.
2. List the steps involved in converting source code to executable code ,using
an assembler and other program development tools.
3. What are the roles of the linker and loader in the generation of the run
file?
4. How is a com file different from an exe file?
5. ‘The assembled code is re-locatable’. What is the implication of this
statement?
6. Why is that a .com program has the origin at 0100H?
7. Is MASM a high level assembler (HLA)? Comment.
8. How does a debugger help in the programming process?
9. What exactly does the .EXIT statement do?
10. List the rules regarding labels that can be used in MASM.
EXERCISE
1) Using the tiny model ,write a program that does the following.
a) Moves 1020H to AX,056H to BL and C76H to CX.
b) Copies the content of AX to DS ,the content of BH to AH ,and the content
of CX to DX.
2) Write a program to copy 25 to AL, ‘S’ to BL and ‘*’ to CL . Then move these
to AH,BH and CH respectively.
3) Using the small model, store the bytes 56H and FCH , and words 0978H and
CFD4H in the data segment.
4) Store three bytes and four words in the data segment. Copy one byte and one
Word of these to appropriate registers.
5) Using the small model , write a program which incorporates the following
addressing modes.
a) register mode
b) immediate mode
c) register indirect mode..
6) Write a program which adds a constant correction factor to a temperature that is
stored in the data segment .The corrected temperature should be stored in a new
location in memory.
7) Using the DUP directive allocate space for 10 data words, 5 double words and 2
quadwords in the data segment . Also fill the next 12 spaces with 0, the next 10
spaces with ‘$’ and the next space with ‘S’.
8) Using the full segment definition , write a program to add the content of two
words which are in memory , and store the sum in a third address.
9) Design the machine codes for the following instructions
i. XOR AL,AL
ii. AND AX,BX
iii. OR AL,BL
iv. MOV DS,AX
10) Find the machine codes for the instructions
i. SUB AL,[5676H]
ii. CMP AX, 0CDE2H
iii. CMP 34H[DI][BX],DL
iv ADD CX,[SI]
CHAPTER 3
PROGRAMMING CONCEPTS-II
OBJECTIVES
• Ideas on good programming practices

• A few important DOS functions and how to use them in programs
• A part of the instruction set of 8086
• To use data transfer instructions in different modes of addressing
• The concept and importance of branch instructions
• To use unconditional and conditional branch instructions
• To use the arithmetic instructions catering to unsigned numbers
• To use the multiply and divide instructions for interesting applications
• The use of logical ,shift and rotate instructions of the 8086
3.1 Approaches to Programming
We are now in a position to feel that we have understood to a small extent ,the tools
needed for programming (in this case assembly programming) .But before getting down
to the actual coding process ,it might be worthwhile to spend some time trying to
understand the various approaches to be used in programming . These ideas apply to all
levels of programming -i.e. whether we use high level languages or assembly level
languages .
One common argument is whether programming is an art or a skill . To say that it is an
art implies that good programmers are born ,not made . This may be partly true ,because
it is seen that some people have a natural flair for programming .But this applies to
almost every ability we might have .Even if programming skill is an inborn ability , one
has to polish it and practice this craft to become good at it .There is no other way but
hard work to become an expert .
Coming to the other side of the argument that programming is a skill -then also ,the same
rules apply . The craft of programming has to learned with sound basics - we should
develop our thought processes to become good problem solvers . For every problem
,there is more than one way of solving it .Finding the optimal solution depends to a great
extent on how much we have learned to build castles in the air -where these castles are
the solutions to our problems .
Let us conclude that just anyone can become a reasonably good programmer , by getting
a good grasp of the basics and following it up with keen studying and continuous
practice.
There are various approaches to solve a programming problem .One is called the top
down approach. This approach tends to look at the problem as one whole functional
block .The solution to the problem is planned , after the whole problem is thoroughly
understood . This functional block is then broken down to smaller blocks ,whose
functions are to be defined along the way .
The other approach is the bottoms up approach . Here the basic functional blocks which
are available or can be clearly defined ,are joined together to get the bigger module .Thus
small function blocks are integrated to form the top level entity .
Both these approaches have their advantages and disadvantages. Depending on the type
of problem at hand , the methodology has to be decided.
Now ,a tip and advice before getting started-
Something that is to be avoided is to jump to 'coding' as soon as a problem is presented .

What this means is that, we must first build the solution to our problem ,optionally in our
mind -but the best way is to write a pseudocode or draw a flow chart before writing the
actual code .In this way , our thought processes lead us to the algorithm to use . As we
become more familiar with programming ,we may gradually avoid pseudocodes or flow
charts for small programs , but use them for the more complex ones .
In this book ,only the coding part is done -it is left to the student to visualize or write the
algorithm ,as he chooses .
Assembly programming tips

From the previous chapter ,you might have got an insight into assembly programming
using MASM . Now we are in a position to get a better idea of the instruction set of
8086, in a phased manner .
In chapter 2 , a few programs were run ,but we did not have any mechanism to display
the outputs .There was also no mechanism to take in data through the keyboard i.e.
interactive programming could not be done There we used the debugger to access
memory and view registers in order to verify if our results are as they should be . For
entering data , we were supposed to store it in the data part of the segment being used .
For a programmer , this approach seems cumbersome . Interactive programming is
definitely been more fun and instructive. What is the way for this?
Let us see what it is.
What is DOS?
We are now in the computer age when our learning of computers starts with using the
latest version of Windows . But that was not so in the beginning of computer evolution .A
number of operating systems were tried ,tested and discarded before the graphical
interface that Windows is ,came to common use . DOS was a very popular OS many
years ago , is still used and is very useful too .
DOS stands for Disk Operating Systems which could be an acronym for any OS ,but
it is most often used as a shorthand for MS-DOS (Microsoft disk operating system).
Originally developed by Microsoft for IBM, MS-DOS was the standard operating system
for IBM-compatible personal computers.
The initial versions of DOS were very simple and resembled another operating system
called CP/M. Subsequent versions have became increasingly sophisticated as they
incorporated features of minicomputer operating systems. However, DOS is still a 16-bit
operating system and does not support multiple users or multitasking .
DOS is considered insufficient for many of the graphical operations that we use
our computers for ,but all Windows have a strong dependency on DOS . So newer and
newer versions of DOS are inbuilt in all Windows OS . DOS is considered to be a
software which can control hardware directly .It is this aspect of DOS which will prompt
us to DOS and BIOS interrupts in this book . A few basic commands of DOS are given
in Appendix A . They will help you to get started on MASM 6.14 .
3.1.2 BIOS and DOS function calls

Until now , we were viewing the 8086 processor as being connected only to
memory .i.e. physical memory which is RAM .But in reality ,the processor is also
connected to various input and output devices .For example ,the PC has the keyboard
and mouse as input devices .The video monitor is an output device . As programmers
,we would like to input data into the processor using the key board and get the results
displayed on the video monitor . To do this , we need to have some way of accessing
these I/O devices ,which contain a lot of extra hardware . Luckily, there is some ready
made software available to handle this problem ,and they come in the form of functions
written to access Input and Output devices. The word BIOS may seem familiar . BIOS
(Basic Input Output System)consists of a set of functions written for this purpose
.Besides this ,there is another set of functions called DOS functions or DOS interrupts .
They are part of the DOS operating system. They are functions written for accessing
input and output devices, which are called in the form of software interrupts .We have
seen one such DOS interrupt which is the one that the .EXIT statement gets translated to .
i.e.
MOV AH ,4CH
INT 21H
In this , 4CH is the function number which has to be loaded into the AH register before
calling the interrupt with type number 21H .This function caused exiting the program
and returning to the DOS prompt.
In Chapter 8,we will see the logic of interrupts and their way of functioning . But in
this chapter, we will use a few DOS interrupts to aid us in the process of programming .
Using these simple DOS interrupts will help us get the feel of programming as we are
able to use the available input and output devices interactively. We will see that
assembly language programming can be fun In this chapter ,a few DOS function calls
will be introduced. BIOS interrupts will be used in later chapters.
3.1.3 Using DOS function Calls
We will start with three important function calls ,all of which are of interrupt type 21H
i)Read the keyboard with echo
MOV AH ,01
INT 21H
This call exits with the ASCII value of the key pressed ,being available in AL .
The key pressed is also echoed on the screen .
ii)Read Keyboard without echo
MOV AH ,08
INT 21H
This call exits with the ASCII value of the key pressed being available in AL .
The key pressed is not echoed on the screen
iii)Write a character to the standard display unit.

For this ,the ASCII value of the character to be displayed should be in DL.
MOV DL ,S’
MOV AH ,02
INT 21H
With this ,the character S is displayed on the video screen
iv) Display a character string on the standard display unit
The logical address DS:DX should point to the beginning of the string .
This is to be followed by the following instructions
MOV AH ,09
INT 21H
3.1.4 The Instruction set of 8086
The instruction set of the 8086 is reasonably large .Besides, each instruction can be used
in various addressing modes making the whole set larger . Knowing all the instructions
,their format and their features is a key factor in becoming an expert programmer .
Let us list out the general features of instructions which will become clearer as they are
explicitly earned.
i)Most instructions have two operands i.e. the destination and the source .
These can be registers or memory operands .But both operands cannot be
memory operands. Some instructions can also use immediate data as the source
operand.
iii) Certain instructions have only one operand mentioned which is either the
destination or the source . These can be register or memory operands ,but not
immediate data.
iv) There are instructions which have no operands explicitly mentioned in the
instructions .In that case ,some register is implicit in the usage of these
instructions.
To learn the instruction set ,the approach will to be list instructions based on their
functionality , learn their format and function, and then write a few programs using them.
3.2 Data transfer Instructions.
The list below ( Table 3.1)gives all the data transfer instructions of 8086 ,except the
input and output instructions ,which will be introduced in Chapter 5.
Sl Instruction format Function performed Flags

No affected
1 MOV dest,src Copy the contents of the source to None
(Move) the destination
2 LEA reg16,memory Load the offset of specified memory None
(Load Effective Address) location in the (16 bit)register
3 XCHG dest,src Exchange the contents of the None
(Exchange) destination and source
4 PUSH source Transfer one word from source to the None
(Push) stack top (SS:SP).
5 POP destination Transfers word at the current stack None
(Pop) top (SS:SP) to the destination .
6 LDS reg16,memory Load far pointer to DS and reg.. None
(Load to DS and register)
7 LES reg16,memory Load far pointer to ES and register . None
(Loads to ES and register)
8 LAHF Copy bits 0-7 of the flag register into None
(Load AH with flags) AH.
9 SAHF Transfer bits 0-7 of AH into the flag None
(Store AH with flags) register.
10 PUSHF Transfers the flag register onto the None
(Push flags) stack
11 POPF Pop word from stack into the flag None
(Pop flags) register
12 XLAT Replaces the byte in AL with byte None
(Translate) from a user table addressed by BX.
Table 3.1: List of 8086 data transfer instructions with format and function
A few of these instructions will be discussed in detail and used in programs here. The rest
will be used in later chapters.
3.2.1 MOV -Move

Usage : MOV destination ,source
This instruction causes the source content to be copied to the destination.(copying does
not change the contents of the source).
Remember that the data types of source and destination should match –both should be
either bytes or words.
Examples
MOV AX,CX ;copy CX to AX –this is a word operation
MOV AL,AH ; copy AH to AL –this is a byte operation
MOV AX,[BX] ;copy into AX the data in the address pointed by BX
MOV COST,DX ;copy the word in DX to the location labeled COST
. The use of the MOV instruction in the register and immediate addressing modes was
covered in Chapter 2 .Hence we will use MOV in other modes of addressing now.
Example 3-1
.MODEL SMALL ;select small model

.DATA ;start data segment
COSTP DB 67H ;store cost price
SELLP DB ? ;space for selling price
.CODE ;start code segment
.STARTUP ;start program
PROFIT EQU 25H ;define the profit
MOV AL,COSTP ;move COSTP to AL

ADD AL,PROFIT ;add PROFIT to AL
MOV SELLP,AL ;store the sum in SELLP
.EXIT ;exit to DOS

END ;end of program
Example 3.1 shows the use of the MOV instruction in the direct mode of addressing .
This mode uses a memory location as one operand . Here two memory locations labeled
COSTP and SELLP have been defined in the data segment .COSTP has a data byte
stored in it ,but SELLP is only allocated space for later storage .The first MOV
instruction gets the data byte in COSTP into AL. After adding a pre-defined constant
PROFIT to it ,the sum in AL is stored in SELLP .Both MOV instructions use direct
addressing . At this stage , you need to remember that the assembler will do the
conversion of the labels to memory addresses.
Example 3.2
.MODEL SMALL ; select small model

0000 .DATA ; start data segment
0000 10 20 30 40 50 ARRAY DB 10H,20H,30H,40H,50H

; setup array
0000 .CODE ; start code segment
0017 BF 0000 MOV DI,0 ;load DI with 0

001A 8A 85 0000 R MOV AL,ARRAY[DI] ;get first element in AL
001E 04 07 ADD AL,07H ;add 07 to it
0020 BF 0005 MOV DI,05H ;add 5 to DI
0023 88 85 0000 R MOV ARRAY[DI],AL ;move sum to memory
.EXIT ;exit to DOS

END ;end of program
Example 3.2 shows the list file of a program which uses the MOV instruction in the
register relative addressing mode. Let us analyze the program The data segment is first
initialized with 5 bytes .The address of the first location is labeled as ARRAY ..DI is
used to address the element numbers .With DI=0 ,the first element is accessed ,and with
DI=5 ,the sixth element is accessed. Then the effective address (EA) is [ARRAY+DI] .
When DI=0, the instruction MOV AL,ARRAY[DI] ,transfers the data in the first memory
location to AL. To this , 07 is added. With DI=5, ARRAY[DI] becomes the effective
address of the sixth location in memory . Then MOV ARRAY[DI], AL stores the sum
in memory .
.The displacement for the relative mode is the value of the label ARRAY . From the list
file ,it is seen the offset corresponding to ARRAY is 0000..
Since ARRAY is the address of the first location in the data segment ,the data segment
will look like this ,after the program is executed. The sum will be in the location
ARRAY+5 .
EA CONTENT
ARRAY+5 17H
ARRAY+4 50H
ARRAY+3 40H
ARRAY+2 30H
ARRAY+1 20H
ARRAY +0 10H
Example 3.3
0000 34 87 56 05 07 ARRAY DB 34H,87H,56H,05H,07H
;setup array
0017 BB 0000 R MOV BX,OFFSET ARRAY ;address ARRAY

001A BF 0000 MOV DI,0 ;load DI with 0
001D 8A 01 MOV AL,[BX+DI] ;get first data
001F 04 35 ADD AL,35H ;add 35H to it
0021 BF 0005 MOV DI,05 ;address new location
0024 88 01 MOV [BX+DI],AL ;move sum here
.EXIT ;exit to DOS

END ;end program
Example 3.3 is the list file of a program that performs the same function as the previous
example ,but uses the based indexed mode of addressing .i.e. the effective address is the
sum of a base register and an index register . The instruction MOV BX, OFFSET
ARRAY causes the offset of ARRAY (which is 0000 as seen from the list file)to be
loaded into BX .Thus BX now is a pointer to the location labeled as ARRAY .But to
point to each element one by one ,another register DI is also used. With DI=0 ,the
instruction MOV AL, [BX+DI] causes the data in the first location to be copied to AL.
With DI=5 ,[BX+DI] accesses the sixth location in the data segment .
3.2.2 LEA –Load Effective address

Usage: LEA reg16, memory
This instruction causes the offset of the specified memory location to be loaded in the
indicated register.
Examples
LEA SI,COSTP ;load the offset of memory location COSTP in SI
LEA BX, ARRAY ;load the offset of memory location ARRAY in BX
You may have noticed that the above is a replacement for the instruction
MOV BX, OFFSET ARRAY used in Example 3.3 .
Now let us use this instruction in an interesting application.

We would like to display two character strings on two lines on the video monitor . It
was discussed in Section 3.1.2 that DOS function calls are needed for this . The following
is the list file for the program which does this.
Example 3.4(a)
.MODEL SMALL
0000 .DATA
0000 48 45 4C 4C 4F 24 MESG1 DB "HELLO$"
0006 0A 0D 49 20 41 4D MESG2 DB 0AH,0DH,"I AM SAM$"
20 53 41 4D 24
0000 .CODE
.STARTUP
0017 8D 16 0000 R LEA DX,MESG1 ;load offset of MESG1 in DX

001B B4 09 MOV AH,09H ;DOS function number for
001D CD 21 INT 21H ; displaying a string
001F 8D 16 0006 R LEA DX,MESG2 ;load offset of MESG2 in DX

0023 B4 09 MOV AH,09H
0025 CD 21 INT 21H
.EXIT
END
Example 3.4(b)
HELLO
I AM SAM
C:\masm6.14\BIN>
Now let us analyze the program that does this ,the listing of which is shown in Example
3.4(a).
In the data segment ,two messages are stored at offsets with labels MESG1 and MESG2
.The character strings are enclosed in double quotes and terminated by the $ sign .This
sign is mandatory to end a character string which is to be printed on the display device ..
Notice that the listing in Ex 3.4a shows the corresponding ASCII values for each
character of the string. There is an ASCII value for ‘space’ which comes between each
word of the second message-i.e. I AM SAM . It is seen to be ‘20H’ . Note that’24H’is the
ASCII value of $ and it is seen at the end of both strings.
On the second line , we also see two characters 0AH and 0DH .These are the ASCII
values for line feed(which advances the cursor to the next line) and carriage return (sets
cursor to the left position of screen).These are necessary for printing to occur on the
second line, starting from the left.
To print the first message ,DX points to the offset MESG1 This is done by using the LEA
instruction ,which loads the offset of MESG1 in DX.. Then the DOS function with
number 09 is called .Similarly for the second message ,DX should point to the offset of
MESG2.
The two messages as they are printed on the command window is seen in Example
3.4(b). The .EXIT command causes control to return to DOS prompt
3.2.3 .XLAT -Translate a byte in AL

Usage : XLAT
This instruction translates a byte in AL with a byte from a lookup table in memory .
XLAT is an instruction which can handle look up tables and access data depending on the
value of the pointing number. There should be one-to-one relationship between the
number and the data in the table .Before using XLAT ,the look up table must be in
memory and the offset of the table must be in BX
Requirements : load into BX ,the offset of the look up table .

Then use XLAT
Then into AL ,load the number which will extract the required data .Refer Table …
For example if you want to get the ASCII value of 5, load AL=5 .It will get the sixth
entry from the table .
Number ASCII
0 ‘0’
1 ‘1’
2 ‘2’
3 ‘3’
4 ‘4’
5 ‘5’
6 ‘6’
7 ‘7’
8 ‘8’
9 ‘9’
Table ….: look up table for decimal to ASCII conversion.
See the above look up table which relates a decimal number to its ASCII value .
The ASCII ‘0’,’1’ ,’2’ etc have numerical values 30H,31H ,32H etc .Refer to the
ASCII table in Section 0-....
Example 3.5
The following program gets into the memory location starting from VALUES , the
ASCII values of 1,3,5,4,0….in that order. The look up table is stored in the array named
ASC.
.MODEL SMALL
.DATA
ASC DB '0','1','2','3','4','5','6','7'
NUM DB 1,3,5,4,0
VAL DB ?
.CODE
.STARTUP
LEA BX,ASC ; let BX point to offset of the table
LEA SI,NUM ; let SI point to NUM
LEA DI,VAL ;let DI point to VAL
MOV CX,5 ;CX=5
AGN: MOV AL,[SI] ; move the content of NUM to AL
XLAT ;translate
MOV [DI],AL ; move translated value from AL to VAL
INC SI ; increment the pointer to NUM
INC DI ;increment the pointer to VAL
LOOP AGN ;repeat until CX=0
.EXIT
END
XLAT is equivalent to the following instructions

MOV AX,0
MOV SI,0
MOV AL,[BX+SI]
SI or DI will be okay for showing the equivalence
Try using XLAT for various look up tables

e.g.i) an integer and its square.
iii) an integer and its cube
ii) a BCD number and it seven segment code
iii) a key and its ASCII or seven segment code
3.2.4 PUSH and POP
Usage : PUSH source

POP destination
For the 8086 ,only 16 bit data can be pushed and popped.
Note : CS is not a valid destination for POP.
Examples:
PUSH BX ; save the contents of BX to stack
PUSH [BX ] ;save to stack the contents of the word pointed
;by BX
PUSH DS ; save to stack the contents of the segment
; register DS
PUSH COSTP ;save to stack the contents of the word
;location COSTP
POP CX ;load the contents of the stack top to CX
POP [SI] ;load the contents of the stack top to the
;memory location pointed by SI
The PUSH and POP instructions are relevant only for the stack segment .
So scroll down and read about the operation of the stack before attempting to
understand the PUSH and POP instructions.
The stack is a region of temporary storage .When a subprogram is called ,the register
contents of the main program at that point of time and the current value of IP and CS are
pushed onto the stack ,and retrieved on returning from the sub program .These things are
done automatically as part of a CALL instruction .Besides this ,a programmer can opt to
store in stack temporarily the values of some registers ,so that he can use those registers
for other computations . He can get back the previous values of these registers ,after he
completes his current computation . These operations are accomplished by the PUSH and
POP instructions.
3.2.3.1 OPERATION OF THE STACK
The 8086 ,as mentioned in Chapter 1 , uses a Last in First out(LIFO)stack . A stack is
an area of memory , in which the lowest address is the base address of the segment .The
upper 16 bits of this base address will be in the SS register .The highest address will be in
the SP register –or rather ,the SP will contain the offset of the highest address with
respect to the base address .This is why it is called the TOP of STACK . For example, if
the stack is defined from addresses 20000H to 203E8H , SS=2000H and
SP=03E8H,.This stack then has a size of 3E8H bytes or 1000 bytes.
In the 8086 ,only a word (16 bits ) can be pushed on to stack . A push thus causes two
memory locations to be accessed .
The operation of the stack is different from normal memory operations. It is a push-down
memory . i.e. For the value of SP mentioned above ,let us say ,the PUSH BX instruction
is to be executed . Let BX=CC99H. .Recollect that SP=03E8H.
The operation of pushing is as follows SP is first decremented by two . The new data
will be put in addresses (offsets ) 03E7H (SP-1) and 03E6H(SP-2), adhering to the
‘ little endian’ concept i.e. the higher byte of BX will be the higher address (03E7H) and
the lower byte in the lower address (03E6H).The new value of SP will be 03E6H . This
shows that new data to be pushed onto the stack will be pushed in the lower two
addresses with respect to the current stack top. Always ,the stack top (SP) has the offset
corresponding to the last byte that was pushed in .
BX
CC 99
CONTENTS ADDRESS OF
OF STACK STACK TOP
-- 03E8H SP BEFORE
THE PUSH
CC 03E7H
99 03E6H SP AFTER THE
PUSH
---- 03E5H
--- 03E4H
Fig 3.1 PUSH operation in a stack
The reverse will be the case after a POP operation. Assume a POP CX operation at a
time when the SP value is 0312H . The content of the stack will be loaded into the CX
register. ,and SP is incremented by two.
CONTENTS ADDRESS OF
OF STACK STACK TOP
-- 0314H SP AFTER
THE POP
0E 0313H
67 0312H SP BEFORE
THE POP
---- 0311H
--- 03E10H
CX
0E 67
Fig 3.2 :POP operation in a stack
3.2.3.2 DEFINING A STACK

Now ,how will we use the stack in programming?
Obviously we have to define the stack size ,base address of segment ,stack top etc . If we
are using the tiny segment ,this is done for by DOS –but in other memory models ,we
will have to do it ourselves ..In case we don’t , a warning ‘No stack segment’ will
appear on assembling .This can be ignored if the stack size is less than 128 bytes
.Otherwise , the stack that gets defined by DOS may erase the PSP (program segment
prefix) and cause the system to crash .
Example 3.5 a
.MODEL SMALL
.STACK 400H ;specify stack size
Example 3.5b
STACKSEG SEGMENT STACK
DW 200H (?)
STACKSEG ENDS
Example 3.5 shows two ways of defining a stack. Ex 3.5a uses the simplified memory
model and it specifies the size of the stack as 400 bytes .Ex 3.5 b uses the full segment
definition .200 data words are to be set aside as stack ,as per this definition. Here, both
definitions create stacks of the same size.
Example 3.6
Explain what is done in this program .Assume SP =0310H ,when the stack was initialized
.MODEL SMALL
.STACK 300H
.CODE
.STARTUP
MOV AX,4567H
MOV BX,0ACEH
PUSH AX
PUSH BX
POP AX
POP BX
.EXIT
END
Solution:
This program defines a stack of 300 bytes by the use of the stack directive
The program first loads two numbers in AX and BX. These numbers are pushed into
stack using the PUSH operations . Then comes the POP operations .What we need to
remember is that popping occurs in the reverse direction. What is pushed in last will be
popped out first .The last PUSH was PUSH BX ..It is obvious then that by the POP AX
operation ,the content of AX is replaced by the content of BX .Similarly the second POP
causes BX to get the content of AX. Thus this program exchanges the content of these
two registers , using the stack as a temporary data storage area. After execution the
contents of the registers are: BX=4567H and AX=0ACEH .
Note: Exchanging register contents is not really an application for the stack .We can
exchange these register contents easily by using the instruction XCHG AX,BX
But this program shows the relationship between POP and PUSH operations.
3.3 BRANCH INSTRUCTIONS
Branch instructions are very important ,because they carry on them the full power of a
computer . Branching can be conditional or unconditional .Unconditional branching
becomes necessary when looping back or forward is done infinitely ,like when we use
software to generate a square wave continuously .But most of the time , conditional
branching is what may be more important . Taking decisions based on the result of a
computation is what gives computers their power and versatility . Most instructions that
we will use subsequently become meaningful only when conditional branching is used.
In this chapter ,we will discuss only the jump and loop instructions .Other branching
instructions like call and return will be discussed in Chapter 4.
We will start with the jump instruction.
3.3.1 JMP -Jump
Usage: JMP destination
The destination is a memory location ,which can be expressed in different ways as will
be discussed presently .The jump destination is frequently referred to as ‘target’ as well.
A jump instruction breaks the normal sequence of program execution ,and takes control
to a different location in the code segment .
MOV…..
ADD,-----
JMP AGAIN
………..
--------
-
-
------------
AGAIN: ……..
Figure 3.3 : Control flow using the jump instruction

There are many ways and restrictions in specifying the target value ,and based on this
,we can have different types of jumps . Fig 3.3 above could be a typical scenario. When
the ADD instruction is being executed , IP(Instruction Pointer) points to the next
instruction which is an unconditional JMP instruction .On decoding the JMP instruction
,the EU(Execution Unit) realizes that the next instruction should be taken from the
location with label AGAIN . It is obvious then , that the IP content must be changed in
such a way that a new sequence is to be followed .
The salient points regarding jump are :
i) The jump location may be in the same code segment ,in which case it a near
jump. For a near jump ,the value of CS remains the same ,but the value of IP
will change. This also called an intrasegment (within segment) jump.
ii) The jump location may be in a different code segment –then it is called a far
jump .In this case , both CS and IP will have to take on new values. This is an
inter-segment (between segments) jump.
iii) The label of the destination address should be followed by a colon.
iv) Jumping can be backward or forward in the program sequence
v) Jumping can be unconditional .Then the format of the jump instruction is
JMP label ,where label is the address of the destination
vi) Besides unconditional jumps, there are a number of conditional jumps
available .The conditions are based on the state of the flags which get affected
by arithmetic or logic instructions.
3.3.1.1 The Near Jump

In the direct mode of addressing ,the near jump has the format JMP label where the
label is the address of a memory location.
The destination can be a 16 bit signed number ,which means that range of jumping is
within +/- 32K bytes . . In direct jump ,the jump location is a signed displacement from
the current value of IP to the destination address. i.e. the assembler calculates this
displacement ,and adds it to the current IP value .Thus the jump address is relative or
rather ,re-locatable .For a forward jump ,this displacement will be positive ,while for a
backward jump ,this will be negative It uses three bytes as instruction size –one byte for
the opcode ,and two bytes for the 16 bit destination offset.
OPCODE OFFSET LOW OFFSET HIGH
NEW IP =CURRENT IP + OFFSET (16 bit)
Fig 3.4 : Format of the near jump instruction
3.3.1.2 The Short Jump

The short jump is a special case of a near jump with the format JMP destination . , For
short jumps ,the displacement must be an 8 bit signed number ,which means that the
jump destination can only be -128 or +127 bytes displaced from the current value of IP.
A directive SHORT can be used if we are sure that our jump destination is within the
above specified range This instruction is two bytes long .-i.e. one byte for the opcode and
one byte for the destination offset.
OPCODE OFFSET
Fig :Format of the short jump instruction
Now let us see an address calculation for a short jump instruction
EXAMPLE 3.7
0000 B4 01 BEGIN: MOV AH,01
0002 CD 21 INT 21H
0004 8A D0 MOV DL,AL
0006 EB 07 JMP SHORT THERE
----------------------------------------
--------------,skipped instructions>---
----------------------------------------
000F 80 C2 02 THERE: ADD DL,02
0012 B4 02 MOV AH,02
0014 CD 21 INT 21H
0016 EB E8 JMP SHORT BEGIN
Example 3.7 shows how ‘short’ jump instructions pass control from one part of the
program to another.
0006 EB 07 JMP SHORT THERE
See the above line which is taken from the list file of the corresponding program. It
shows the address (0006) at which this instruction is stored .The opcode of this direct
JUMP instruction is EB and the ‘displacement’ is 07.
During the time that this instruction is decoded, the IP value is 0008 (address of the
next instruction) . At the beginning of the first pass ,the assembler reserves one byte
space in memory for the address of THERE. The assembler knows that only one byte is
required for THERE , because of the directive SHORT. .Otherwise it would have
reserved two bytes space ,as for a general near jump. If the address of the next
instruction (0008) is added to the sign extended displacement (0007) of the jump
instruction(this displacement is calculated by the assembler) ,the address of THERE is at
location 0008H + 0007H = 000FH . Thus control branches to location 000FH.
Now see the other direct jump instruction in the program
0016 EB E8 JMP SHORT BEGIN
The opcode is EB and the displacement is E8. JMP BEGIN is seen to be a backward
jump as BEGIN is a label appearing much before this instruction line.
The assembler calculates this displacement (which is negative) and add this displacement
to the value of IP at that point of the instruction sequence. Then it jumps to the
destination BEGIN. In this case the negative displacement is E8H .When JMP SHORT
BEGIN is executed ,the IP content will be 0018H . For jumping to BEGIN, the address
calculation is 0018+FFE8=0000 ,which is the address of the instruction with the BEGIN
label .Note that the negative number E8H ,when used in 16 bit calculations ,has to be
sign extended. So E8H is FFE8H in 16 bit sign extended form.
Now let us write and run a fun program using an unconditional jump instruction.
Example 3.8 is a simple program named UPLOW which uses DOS interrupts to enter a
character from a key board . If this character is an upper case alphabet ,it converts it to
lower case . The ASCII character table shows that a lower case character can be obtained
by adding 20H to the upper case code .i.e. The ASCII of ‘A’ is 41H and that of ‘ a’ is
61H ,and so on .
Example 3.8a
.MODEL TINY
.CODE
.STARTUP
START: MOV AH,01H ;AH=01
INT 21H ;enter a key
ADD AL,20H ;add 20H to it
MOV DL,AL ;move the sum to DL
MOV AH,02 ;AH=02
INT 21H ; use this function to display
MOV DL,0AH ;0AH is the ASCII for newline
MOV AH,02H ;display a new line
INT 21H
JMP START ;go to start to repeat
.EXIT
END
Example 3.8b
C:\masm6.14\BIN>UPLOW
Aa
Bb
Cc
Dd
Ee
Ff
Gg
Hh
^C
C:\masm6.14\BIN>
INT 21H with function number 01 is used to enter a key .Then 20H is added to the
ASCII value of the key ,and this is displayed in the same line . To get further displays on
separate lines ,the ASCII character 0AH is displayed .Remember that 0AH corresponds
to ‘newline’. The JMP START instruction is used to repeat this whole sequence
indefinitely .Since there is no stopping condition for this loop ,we have to use the ’ctrl c’
combination of the key board to terminate the program . The displayed output is shown
in example 3.8b ,Note that ,for any key input other than an upper case character ,the
output is some random character.
3.3.3 Other forms of the unconditional jump instruction
There are other modes of addressing for the near jump .

i) JMP reg16
This is called an indirect jump .The 16 bit register contains the destination address
(offset).This jump is not a relative jump .IP gets replaced by the value in the register .
Example
JMP BX ;jump to the destination address in BX .Make IP=BX
JMP SI ;jump to the destination address in SI .Make IP=SI
ii) JMP [reg 16]

This is like a double indirect jump .The register points to an address which contains the
jump location .
Example
JMP [SI] ;jump to the address which is stored in the memory location pointed
;by SI
If SI =0670H , the destination address is taken from the data segment at locations 0670H
and 0671H. IP is replaced by the value at these addresses.
3.3.1.4 CONDITIONAL JUMPS
Conditional jumps are the best part of the idea of control transfer .They change the
sequence of program execution based on the result of a computation which causes flag
bits to be set or reset .However ,there is one case (JCXZ) where a register content is
checked.
Note: All conditional jumps are short jumps
.
Usage : J(condition) destination
Table 3.1 contain the jumps used for unsigned data ,and those directly testing flags and
registers.
Sl Mnemonic What it means Condition tested

No
1 JA Jump if Above CF=0 and ZF=0
2 JAE Jump if Above or Equal CF=0
3 JB Jump if Below CF=1

4 JBE Jump if Below or Equal CF=1 or ZF=1
5 JC Jump if Carry CF=1

6 JCXZ Jump if CX Zero CX=0
7 JE Jump if Equal ZF=1
8 JNA Jump if Not Above CF=1 or ZF=1
9 JNAE Jump if Not Above or CF=1
Equal
10 JNB Jump if Not Below CF=0
11 JNBE Jump if Not Below nor CF=0 and ZF=0
Equal
12 JNC Jump if No Carry CF=0
13 JNE Jump if Not Equal ZF=0
14 JNP Jump if No Parity PF=0
15 JNZ Jump if Not Zero ZF=0
16 JP Jump if Parity PF=1
17 JPE Jump if Parity Even PF=1
18 JPO Jump if Parity Odd PF=0
19 JZ Jump if Zero ZF=1
.
Table 3.2 List of conditional jump instructions which cater to unsigned arithmetic
and which directly address flags or registers
Note
i) Certain mnemonics are equivalent–For example ,JZ and JE mean the same as
they test the same flags. So also JC and JB , JP and JPE etc. More can be
identified from the list.
ii) JCXZ tests the CX register but other Jump instructions test conditional flags
only.
iii)There is another set of conditional jump instructions which are specially meant
for signed arithmetic .The list of those instructions and their usage will be dealt
with, in Chapter 4.
We will use a few of the conditional jumps in the forthcoming examples.
3.3.1.5 FAR JUMP

A far jump is an intersegment jump ,which means that the destination address is in a
different code segment .
This will be a five byte instruction ,the first byte being the opcode ,the second and third
the new value of IP ,and the fourth and fifth the new values of CS.
OPCODE IP LOW IP HIGH CS LOW CS HIGH
Fig 3.6: Format of the far jump instruction

To specify that a jump is to a different code segment , a far pointer can be used in the
format
JMP FAR PTR AGAIN ;PTR stands for ‘pointer’
Defining an address as external and then using a jump to this address is also possible .
These ideas will be discussed in Chapter 5.
3.3.2 The LOOP instruction

Usage : LOOP label
There is a very useful and frequently used instruction called LOOP .This combines jump
with a counter .The register CX is assigned to decrement every time LOOP executes.
When CX=0 ,the looping is exited.
MOV CX,N
MORE: ……..
--------
…………
………..
LOOP MORE
……………….
…………………
Initially CX is loaded with a number ,which we call ‘count’. See the above program
sequence. What is to be understood here is that ,the sequence of instructions up to the line
containing the LOOP instruction ,will execute once .Then, when the LOOP instruction is
encountered ,CX is decremented and then tested .If CX is found to be equal to zero,
looping is exited and the next instruction in the sequence is taken up .If CX!=0 , control
returns to the label MORE .
LOOP can be combined with other conditions ,to make it a conditional instruction.
LOOPNE/ LOOPNZ , LOOPE/LOOPZ etc can be used. These instructions test the zero
flag ,as well as the value of CX
Example 3-9 shows the use of an unconditional LOOP instruction.
In this program , three arrays have been declared in the data segment .Corresponding
bytes from the first two arrays are to be added and the sum is to be saved in the third
array . To point to the data items in the three arrays ,three registers are used . Data is
accessed using register indirect addressing .After one round of these actions ,the pointer
registers are incremented using the INC instruction .This instruction adds 1 to the
registers . This sequence of operations is repeated six times ,by using the LOOP
instruction .Once CX=0 ,the loop is exited ,and the program ends.
Example 3.9a
.MODEL SMALL
.DATA
NUMS1 DB 45H,67H,89H,65H,34H,23H
NUMS2 DB 09,09,12H,13H,08,02
NUMS3 DB 6 DUP(0)
.CODE
.STARTUP
LEA BX,NUMS1 ;use BX to point to NUMS1

LEA SI,NUMS2 ;use SI to point to NUMS2
LEA DI,NUMS3 ;use DI to point to nUMS3
MOV CX,06 ;CX=6
REPEA: MOV AL,[BX] ;take into AL data from the array NUMS1
ADD AL,[SI] ;add to AL the data in array NUMS2
MOV [DI],AL ;save the sum in the third array
INC BX ; increment pointer
INC SI ; increment pointer
INC DI ; increment pointer
LOOP REPEA ;repeat the sequence until CX=0
.EXIT
END
This problem can be done with less number of address registers if ‘register relative
mode’ of addressing is used .See Example 3.9b.Here only the register BX is used .Its
content is added to different addresses so as to access the three different arrays.
Example 3.9b
.MODEL SMALL
.DATA
NUMS1 DB 45H,67H,89H,65H,34H,23H
NUMS2 DB 09,09,12H,13H,08,02
NUMS3 DB 6 DUP(0)
.CODE
.STARTUP
MOV CX,6
MOV BX,0
REPEA: MOV AL,NUMS1[BX] ;point to the first array
ADD AL, NUMS2[BX] ;add numbers of the second array
MOV NUMS3[BX] ,AL ;save in the third array
INC BX
LOOP REPEA ;repeat until CX-0
.EXIT
END
Now ,we will digress to the discussion of arithmetic instructions ,but you can see that
branch instructions in various forms will be continued to be used.
3.4 ARITHMETIC INSTRUCTIONS

The complete list of arithmetic instructions is given in Table 3.3. Instructions from 1 to 9
will be discussed in detail and used in this chapter .The rest will be dealt with , in Chapter
4 for signed number arithmetic.
Note
i) In the list ,dest means destination and src means source.
After an operation ,the result is available in the destination.
iii) As mentioned earlier ,the destination and source may be both registers or a
memory location and a register. The source can
be immediate data, unless explicitly mentioned (for certain instructions)that
immediate mode of addressing is not allowed.
iv) Flags are affected by most of the arithmetic instructions, In certain cases ,all
flags are affected ,but some flags are undefined .The --- notation for the
corresponding flags is used in such cases meaning ‘undefined’.(in the table)
iii) In certain cases ,flags are not affected .This is specified by ‘none’
No Instruction Format FUNCTION PERFORMED FLAGS AFFECTED

1 ADD dest,src Add dest and src AF CF OF PF SF ZF
2 ADC dest,src Add dest ,src and CF AF CF OF PF SF ZF

3 INC dest Add 1 to the destination AF -- OF PF SF ZF
4 SUB dest,src Subtract src from dest AF CF OF PF SF ZF
5 SBB dest,src Subtract source and CF from dest AF CF OF PF SF ZF
6 DEC dest Subtract 1 from dest AF --- OF PF SF ZF
7 CMP dest ,src Subtracts source from destination and AF CF OF PF SF ZF
updates the flags but does not save result.
Only flags are affected
8 MUL src Unsigned Multiply --- CF OF -- --- ---
9 DIV src Unsigned binary divide -- -- --- --- --- --
10 CBW Convert byte to word None
11 CWD Convert word to double word None
12 DAA Decimal Adjust for Addition- AF CF -- PF SF ZF
13 DAS Decimal Adjust for Subtraction. AF CF -- PF SF ZF
14 NEG dest Two's Complement Negation AF CF OF PF SF ZF

15 IMUL src Signed Multiply --- CF OF -- --- ---
16 IDIV src Signed Integer Division -- -- --- --- --- --
17 AAA ASCII Adjust for Addition AF CF -- --- --- --
18 AAS ASCII Adjust for Subtraction AF CF --- --- -- --
19 AAM ASCII Adjust for Multiplication --- --- PF SF ZF
20 AAD ASCII Adjust for Division SF -- -- PF --- ZF
Table 3.3 : Full set of arithmetic instructions
FLAG CONTROL INSTRUCTIONS
There are certain instructions which can be used to set/reset flags .This is very relevant
in the case of control flags like direction flag ,interrupt flag etc . But there is one
conditional flag which can be set /reset using instructions ,and that is the carry flag. The
relevant instructions for it are:
i) CLC -Clear carry
ii) STC -Set Carry
iii) CMC -Complement carry
Now we will see the format and usage of some of the important and commonly used
arithmetic instructions.
3.4.1 ADDITION INSTRUCTIONS
1)ADD -Add
Usage: ADD destination ,source
This instructions adds the destination and source and puts the sum in the destination. All
conditional flags get affected.
Examples
ADD AH,AL ;add AL to AH ,sum in AH
ADD AL, COSTP ;add the byte in COSTP to AL ,sum in AL
ADD BX,0987H ;add the number 987H to BX ,sum in BX
ADD CX ,[BX ] ;add the word in the location pointed by BX to CX
;sum in CX
2) ADC –Add with carry
Usage: ADC destination ,source
This instruction adds CF and source to the destination ,and puts the sum in the
destination. There are three operands ,of which the third is the carry . All conditional
flags get affected
Examples
ADC AH,0 ; AH=AH+0+CF
ADC [BX],AL ;add the byte pointed by BX with AL, and CF .
;put sum in the location pointed by BX
ADC AX,[BX][SI] ;add to AX , CF and the word with EA=BX+SI
;sum in AX
3)INC -Increment
Usage: INC destination
This instruction adds 1 to the destination . All conditional flags except the carry flag
get affected.
INC BX ;add 1 to the content of BX
INC [BX] ;add 1 to the content of the memory location pointed by BX
INC AH ;add 1 to the content of AH
The PTR directive

This is a convenient point to introduce the PTR (pointer) directive .When the size of
the operand is not implicit in the instruction ,a pointer is used to indicate whether the
operand is a byte ,word ,or doubleword.. For example ,see the instruction
INC [BX]
Here BX is a pointer to a location whose content is to be incremented .It is not clear
whether the data being pointed to ,is a byte or word or dword .To make it clear ,it will be
helpful to modify the instruction as
INC BYTE PTR [BX] ;byte pointer
or INC WORD PTR [BX] ;word pointer
or INC DWORD PTR [BX] ;double word pointer
as the case may be . We will encounter various instances where this pointer is used.
Example 3.10
The following is a program which adds two bytes stored in memory . The sum of the
bytes is likely to be greater than FFH. Hence a word space needs to be allocated for the
sum.
.MODEL SMALL
.DATA
NUMS DB 95H ,0FCH ;store the two bytes
SUM DW ? ;allocate a word space for the sum
.CODE
.STARTUP
MOV AX,0 ;AX=0
CLC ;clear the carry flag
MOV AL,NUMS ;move the first number to AL
ADD AL,NUMS+1 ;add the second number to AL
ADC AH,0 ;add AH and CF and 0
MOV SUM,AX ;the sum in AX is moved to memory
.EXIT
END
First AX is loaded with 0.Observe how a byte addition causes a result to be a word .The
sum of two bytes which are added to AL is too large to fit in AL. Hence it generates a
carry .The next instruction adds CF ,0 and AH which contains a 0. So we find that the
carry bit is accommodated in AH .Thus AH-AL i.e. AX contains the sum which is a
word.
Example 3-11 adds 10 bytes stored in memory . The sum of these ten bytes will not fit
into a byte location .So a word location is allocated for the sum .It must also be noted
that the sum will definitely fit into a word location .[ If there are ten bytes ,the maximum
number possible for the sum of ten bytes is only 255 x10 =2550 ,which is less than
65,536 the maximum decimal number that a word can hold]
Example 3.11
.MODEL SMALL
.DATA
NUMS DB 245,178,190,167,56,178,250,89,150,235
SUM DW 0
.CODE
.STARTUP
CLC ;clear the carry flag
LEA BX,NUMS ;BX to point to the numbers
MOV CX,10 ;move the count to CX
MOV AX,0 ;make AX=0
REPEA: ADD AL,[BX] ;add the numbers ,sum in AX
ADC AH,0 ;add the carries into AH
INC BX ;increment the pointer
LOOP REPEA ;repeat if CX is not equal to 0
MOV SUM,AX ;store AX in SUM
.EXIT
END
The above is a simple program which gives a lot of information .

For one thing ,note that data is written in the decimal form ,and not as hexadecimal bytes
.But if the list file is checked, it will show that the data is converted to hexadecimal
format (in the machine code part of the listing)
The program uses the LOOP instruction to carry out cumulative addition . CX is used as
a counter, which decrements with each addition .The first ADD instruction adds two
bytes .It is possible that a carry is generated out of this addition This carry is added to AH
,the other operand of which is 0 .Thus the sum of the carries of the ten addition
operations will be in AH ,which will form the upper byte of the sum .This sum is thus
available as a word in AX which is saved in the word location SUM. It is important to
clear the carry flag before using the ADC instruction ,to avoid the possibility of any
residual carry leading to a wrong result.
Example 3.12 is an interesting program which adds two double words .A doubleword is
two words long .i.e 4 bytes long .
Example 3-12
.MODEL SMALL
.DATA
LONGNUM1 DD 0F8FC6768H ;first double word data
LONGNUM2 DD 0C6EF2109H ;second double word data
SUM DD 0 ;sum
SUMC DB 0 ;space for carry out
.CODE
.STARTUP
LEA SI,LONGNUM1 ;SI as pointer to first operand
LEA DI,LONGNUM2 ;DI as pointer to second operand
LEA BX,SUM ;DX as pointer to the sum
CLC ; clear carry
MOV CX,2 ; CX to count the number of words
REPEA: MOV AX,[SI] ;move to AX the first word
ADC AX,[DI] ;add the second operand and carry
MOV[BX],AX ;the lower word of result stored
INC SI ;increment SI twice to point to
INC SI ;next word operand
INC DI ; increment DI twice to point to
INC DI ;second word operand
INC BX ;increment BX twice to point to
INC BX ;second word of the sum
LOOP REPEA ;go back if CX is not 0
MOV DL,0 ;make DL=00
ADC DL,0 ;add the carry to DL
MOV SUMC,DL ;move the carry to SUMC
.EXIT
END
There are a number of notable features for this program .

Let us list out these features.
i) The double words are stored in two DD locations named LONGNUM1 and
LONGNUM2 . They will be stored in the little endian format.
ii) The sum of two doublewords can be more than a double word. This can be
accommodated as a carry ,added to a register ,and can be stored in memory
as the uppermost byte of the sum. Three registers are used as pointers to each
double word .However ,addition can be done only as words ,as the maximum
size of an operand is only 16 bits (called a word), for the 8086.. Hence, first
the lower order words of the two double words are added .There is a
possibility of a carry due to this addition ,which may have to be added to the
upper word.
Since addition is looped, the ADC instruction is used so as to accommodate
the addition of the carry .
iii) The address pointers have to be incremented by 2 to point to the upper word
of the double word .The INC instruction is preferred over the ADD
instruction ,as it does not affect the carry flag .It is important to preserve
the carry bit out of the second word operation . This final carry is added to
DL (which is first ensured to be 0).
The numbers used herein are two double words whose sum is a double word ,
plus a byte (01 BFEB 8871H)
iv) The memory locations and the corresponding data ,after program execution
is as shown(assuming the origin of the data segment is 0000)
v) The three arrays in memory can be accessed by using ‘register relative
addressing ‘ as is Example 3-9b. Try to see if it gives any advantage in terms
of reducing the number of instructions/registers used.
OFFSETS IN DATA
MEMORY
000C 01 SUMC
000B BF
000A EB
0009 88
0008 71 SUM
0007 C6
0006 EF
0005 21
0004 09 LONGNUM2
0003 F8
0002 FC
0001 67
0000 68
LONGNUM1
Table: 3.4 Relevant portion of the data segment after the execution of Example
3.12
3.4.2 SUBTRACTION
1)SUB -subtract
Usage : SUB destination ,source
This instructions subtracts the source from the destination .The result is in the
destination. All conditional flags are affected
Examples
SUB AX,BX ;subtract BX from AX
SUB AL,[BX] ;subtract the byte pointed by BX from AL
SUB COST[SI], CX ;subtract CX from the word with EA=COST+SI
SUB AX,8956H ;subtract 8596H from AX
SUB CL,BYTE PTR [SI] ; subtract from CL the byte pointed by SI
2) SBB –subtract with borrow

Usage: SBB destination ,source
This instruction subtracts the source and the carry flag from the destination .
All conditional flags are affected .
SBB CH,7 ;subtract from CH 7 and CF –result in CH
SBB AX,]BP+2] ;subtract from AX ,the word pointed by [BP+2]
;Since BP is used ,the data is taken from the
; stack segment .The result is put in AX
3) DEC -decrement
Usage : DEC destination
This instruction subtracts 1 from the destination
All conditional flags except the carry flag ,are affected.
DEC CL ; subtract 1 from CL

DEC WORD PTR [SI] ;subtract 1 from the word pointed by SI
DEC BYTE PTR NUMB[BX] ;subtract 1 from the byte pointed by the
;effective address NUMB+BX
Example 13 .13
Explain what occurs on execution of the following instructions
MOV CL,0B5H
SUB CL,0FCH
Solution
B5 H 181 1011 0101 -
- FC H - 252 1111 1100
B9 H -71 1011 1001
This is a subtraction of a bigger number from a smaller number .Hence the carry flag is
set to indicate that a borrow has been used in the subtraction. The difference is -71
(decimal),which is represented as B9H which is the two’s complement representation of
decimal -71.. The carry flag is set in indicate that the subtraction has used a borrow .The
sign flag is set to indicate that the MSB of the result is 1 ,which ,in this case is interpreted
to be a negative number.
Now Let us use the SUB instruction in an interesting example .
Division is an operation which can be achieved by repeated subtraction .Many early
microprocessors (8085 ,for example) had no divide instruction. The 8086 ,however has a
divide instruction .But here ,let us use repeated subtraction to divide say ,100 by 9 . We
know that the quotient is 11 (0BH) and the remainder is 1 .
Example 3.14
.MODEL SMALL
.DATA
QUOTIENT DB 0
REMAINDER DB 0
.CODE
.STARTUP
MOV AL,100 ;copy dividend to AL
MOV CL,0 ;CL ,the quotient register=0
REPEA: SUB AL,9 ;subtract 9 from 100
JC OVER ;stop when CF =1
INC CL ; increment CL if CF is not set
JMP REPEA ;repeat subtraction if CF is not set
OVER: ADD AL,9 ;add 9 to AL to get remainder
MOV REMAINDER,AL ;store remainder
MOV QUOTIENT,CL ;store quotient
.EXIT
END
The steps of the program are as follows

i) Subtract 9 from 100 repeatedly until a negative number is obtained .In the
program ,start with AL=100 .When AL becomes negative ,the carry flag will
be set (due to borrow) .This is the stopping condition for subtraction.
ii) In this problem , after subtracting 9 from 100 eleven times , AL will contain
01 . One more subtraction will cause the content of AL to become -8 (F8H
in 2’s complement form) . The carry flag is found to be set ,and further
subtraction is stopped.
iii) To get the remainder, add 9 (the divisor ) to AL . We get 1 .This is the
remainder
iv) Every time a subtraction is performed unhindered ,increment a count in CL.
This will give the quotient .
v) The quotient and remainder are stored in their allocated space in the data
segment .
The SBB instruction can be used in instances when multibyte subtraction is done .For
example ,to subtract two double words or quad words, SBB will have to be used ,just as
ADC is used (Example 3.12)for multibyte addition.
We have seen so far, addition and subtraction operations using numbers in the
hexadecimal (essentially binary) format .But numbers are also represented in other
formats like BCD ,ASCII etc . There are special like instructions like DAA and DAS that
cater to BCD numbers ,and instructions like AAA, AAS etc which cater to ASCII
operations .In Section 4.4.2 , these instructions will be used in arithmetic calculations
using such numbers.
3.4.3 COMPARE INSTRUCTION

CMP –Compare
Usage : CMP destination ,source
This instruction compares the two operands ,causes the conditional flags to be affected
,but neither the destination nor the source changes . Comparison is done by a subtraction
operation ,and the flags are set/reset according to the result of this .But only two flags
really matter –they are the Zero flag and the Carry flag .
Consider the instruction CMP destination ,source .The condition of the flags will be as
shown in Table 3.5
If CF ZF
destination > source 0 0
destination < source 1 0
destination =source 0 1
Table 3.5 –Flag settings after a compare instruction
It is thus obvious that following up a compare instruction with a JNC/JC or JNZ/JZ will
do the trick .
If the instruction is ,say CMP AL,BL the way to picture it is -
If AL> BL , CF is reset
if AL< BL ,CF is set
if AL= BL , ZF is set.
If two unsigned numbers are to be compared ,it will be clearer if we use JA/JB as the
mnemonic following the compare instruction ,instead of JC or JNC . This will make it
easier to comprehend the meaning of the result of the comparison ,.
If we want to compare AX and BX we could think of it as :
Jump to target if AX is above BX .The instructions to use will be
CMP AX.BX
JA Target
Similarly ,when testing for equality ,we could use JE/LNE instead of JZ/JNZ .Now ,let
us write a few programs illustrating the use of the compare instruction.
These tips are only for enhancing the readability of the program .
Example 3-15
Two unsigned words are stored in the data segment in locations WORD1 and WORD2
.The program compares the two numbers and displays a message stating which number is
bigger.
.MODEL SMALL
.DATA
WORD1 DW ------- ;store the first number
WORD2 DW ------ ;store the second number
MES1 DB "WORD1 IS BIGGER$" ;first message string
MES2 DB "WORD2 IS BIGGER$" ;second message string
.CODE
.STARTUP
MOV AX,WORD1 ;copy WORD1 to AX

CMP AX,WORD2 ;compare AX with WORD2
JB SECOND ;If AX < WORD2 ,go to SECOND
LEA DX,MES1 ;point DX to MES1
JMP DISP ;jump to DISP
SECOND: LEA DX,MES2 ;point DX to MES2
DISP: MOV AH,09 ;AH=09 for string display
INT 21H ;DOS function INT21H is called
.EXIT
END
This is a very simple program in which the WORD1 is brought into AX .It is then
compared with WORD2 . The jump (JB) instruction following the comparison, directs
control to the appropriate message . Recall that DOS function call with AH=09 will
display a string on the console.
Note : To run this program , actual data will have to be written in the data segment at
locations WORD1 and WORD2
Example 3.16 finds the biggest of 10 bytes stored in memory ..

Example 3.16
.MODEL SMALL
.DATA
NUMS DB 56H,38H,09H,98H,99H,0C7H,07H,0BCH,0CH,0ECH
BIGGEST DB ? ;store the biggest number
.CODE
.STARTUP
LEA BX,NUMS ;BX is the pointer to the array

MOV CL,0AH ;CL acts as the counter
MOV AL,0 ;AL=0
REPEA: CMP AL,[BX] ;compare each number with AL
JAE AGAIN ;if AL is above or equal, jump
MOV AL,[BX] ;if below, bigger no. to be in AL
AGAIN: INC BX ;increment pointer
DEC CL ;decrement counter
JNZ REPEA ;repeat the sequence if count!=0
MOV BIGGEST,AL ; the biggest number will be in AL
;store it in the location BIGGEST
.EXIT
END
The logic of this program is as follows .

i) The numbers are stored as an array in memory named NUMS . BX is used as
a pointer to this array.
ii) CL contains the count of the numbers(here CL=0AH)
iii) Initially AL = 0.
iv) AL is compared with each number . If AL is not above or equal to the
number in the array , the bigger number is brought to AL.
v) If AL is above the number in the array ,the content of AL is retained as it is.
vi) This is one round of comparison. Then the pointer (BX) is incremented and
count (CL) is decremented.
vii) When the count reaches zero ,ZF is set and the looping is terminated because
of using the JNZ mnemonic.
viii) The biggest number is now in AL which is stored in memory in the space
allocated for it
Example 3.17 is another an interesting program ,which searches a character string for
the presence of a particular character ,and displays appropriate messages.
Example 3-17
.MODEL SMALL
.DATA
STRIN DB "HOWAREYOUMYBOY" ;string of characters
LEN DW 0EH
MESG1 DB 0AH,0DH,"CHARACTER FOUND$"
MESG2 DB 0AH,0DH,"CHARACTER NOT FOUND$"
.CODE
.STARTUP
LEA BX,STRIN ;BX to point to the string
MOV CX,LEN ;copy the string length to CX
MOV AH,01 ; DOS function call for

INT 21H ;character input with echo
;the entered character is in AL
REPEA: CMP [BX],AL ; compare AL with string bytes
JE FOUND ;if equality is found , display
;appropriate message
INC BX ; point to the next byte in array
LOOP REPEA ;if count is not 0,repeat
LEA DX,MESG2 ; character not found ,go to MESG2
JMP DISP
FOUND: LEA DX,MESG1 ;display MESG1
DISP: MOV AH,09 ;DOS function call for display
INT 21H ;of string
.EXIT
END
A character string is a stored in location labeled STRIN .The length of this string is
specified in a word location named LEN . The character whose presence (or absence) we
want to check for , is entered through the keyboard using the DOS function call with
AH=01 . This character is compared with each of the characters in the string .Once
equality is found ,the comparing loop is exited and MES1 is displayed . Otherwise
MES2 is displayed ,after all the characters in the array have been compared .
Note that both the messages (MESG1 and MESG2) are preceded by the newline (0AH
) and carriage return (0DH )characters .This is to ensure that the display is obtained in a
different line ,after the input character (i.e. the one that is entered through the keyboard)
is echoed on the screen.
3.4.4 UNSIGNED MULTIPLICATION
MUL -Multiply
Usage :MUL source
This instruction multiplies a number in AL or AX by the source (where the source can be
a register or a memory location ,but not an immediate number).
All the conditional flags are affected ,but only the CF and ZF are defined as meaningful
for the result. The destination depends on the size of the operand.
There are two ways of performing multiplication .
i) Byte by byte
In this ,one of the operands must be in the AL register ,and the source can be a byte in
a register or memory location. The product (a word) will be in AX .
For example
MUL BL ;multiply BL by AL –product in AX
MUL BYTE PTR[SI] ;multiply the byte pointed by SI, by AL –product in AX
MUL BIG ;multiply the content of BIG by AL –product in AX
ii) Word by word

In this ,one of the operands must be in the AX register ,and the source can be a word
in a register or memory location. The product will be in DX and AX ,with the upper word
in DX.
For example
MUL CX ;multiply CX by AX –product in DX and AX
MUL WORD PTR [DI] ;multiply the word pointed by DI with AX –
;product in DX and AX
iii) Word by byte
This is only a special case of the word x word multiplication .The byte must be extended
to be a word .by making the upper byte to be 0. If the byte is in AL ,extend it to be a word
by making the content of AH to be zero. Thus AX now contains one of the operands.
Flags Affected
For the multiply instruction ,all conditional flags are affected ,but only the carry (CF)
and overflow(OF) flags have any significance . They will be set or reset according to the
size of the product .Recall that a byte x byte multiplication can produce a result of a word
size .But if the operands are small, the product itself is only a byte, and needs only the
AL register for the product. .In that case ,both the carry and overflow flags are found
cleared ,but if the product occupies a word size ,both these flags are set (CF=1,OF=1).
This concept can be extended to the word x word multiplication as well .We can
summarize that if the product has a size equal to the size of the operands ,both these flags
are reset .i.e. CF=0,OF=0 .However ,if the product is large enough to occupy the registers
assigned for it, these flags are set i.e. CF=1,ZF=1. See this multiplication.
MOV AL 78H
MOV CL ,0F9H
MUL CL
This program segment will cause the product to be 74B8H .Thus the result of the
multiplication is AX =74B8H ,CF =1 and OF=1.
However if the program segment is
MOV AL,13H
MOV CL ,09H
MUL CL
The result is AX=00ABH ,CF=0 and OF=0 .
In example 3-18, two bytes stored in the data segment are multiplied .The result of
multiplication is available in AX ,which is then moved to the location PROD , a word
location .
Example 3.18
.MODEL SMALL
.DATA
MULT DB 0AH ;multiplier
MULP DB 0F6H ;multiplicand
PROD DW ? ;space allocated for product
.CODE
.STARTUP
MOV AL,MULP ;move the multiplicand to AL
MUL MULT ;multiply with the multiplicand
MOV PROD,AX ;product moved from AX to memory
.EXIT
END
Now let use the multiply instruction in a more complex application

Example 3.19 is a program to find the factorial of a number N.
For 8086 , the maximum size of an operand for multiplication ,is only a word .This places
a limitation on the value of N that can be used . It can be verified that N is to be less than
9 ,for the program to give the correct result. In this program ,the value of N should be
entered from the keyboard ,remembering that N is to be less than 9. Since any value that
is entered from the keyboard is in ASCII form ,30H is subtracted from it ,to get the
binary value of N to be used in the computation.
Example 3-19
.MODEL SMALL
.DATA
FACT DW 0 ;space allocated for the factorial
.CODE
.STARTUP
MOV AH,01
INT 21H ;enter N from the keyboard
SUB AL,30H ;convert ASCII to binary
MOV AH,0 ;convert N in AL to a word in AX
MOV BX,AX ;move it to BX
MOV AX,1 ;AX=1 ,to start the iteration
CMP BX,0 ;compare BX (=N)to 0
JZ FINAL ;if N=0 ,jump to find 0!
REPEA: MUL BX ;for N not 0, multiply with AX
DEC BX ;decrement BX
CMP BX,0 ;compare with 0
JNE REPEA ;repeat if BX is not 0
FINAL: MOV FACT,AX ; AX=1 ,hence 0!=1
.EXIT
END
The computation is done iteratively . First AX =1 .The value of N is copied to BX .For

N=0 , the factorial is 1 .For this case ,the content of AX is transferred to the location
FACT and corresponds to 0!..If N is not zero ,then it is multiplied with AX. BX is
decremented and cumulatively multiplied with the product in AX. .As N becomes higher
, N! increases steeply ,and only for numbers upto 8 ,will the factorial fit into a word
location .Further multiplication becomes impossible because one of the operands has a
size greater than a word. The value of N! is finally stored in the memory location labeled
FACT.
3.4.5 UNSIGNED DIVISION

DIV -Divide
Usage: DIV source
This instruction divides AX or DX –AX by the source ,where the source can be a register
or a memory location ,but not an immediate number. All the conditional flags are
affected ,but undefined –hence they don’t give any interpretation or information about
the result.
The destination depends on the size of the operand .There are two ways of performing
division
i) Divide a word by a byte .
Here ,the dividend must be a word placed in AX and the source must be a byte . The
result of division causes AL to contain the quotient ,and AH to contain the remainder.
Example
DIV BL ;divide AX by the byte in BL
DIV BYTE PTR [BX] ; divide the word in AX by the byte pointed by BX
DIV DIG ; divide the word in AX by the byte in DIG
See this division

MOV AX, 0C678H
MOV CL ,0F9H
This program segment will cause AH (remainder) =0CH and AL (quotient) = CCH
Dividing a byte by a byte
This is just a special case of a division of a word by a byte.
In this case ,convert the dividend byte to a word by loading the dividend in AL and 0 in
AH .Thus AX will be the word that acts as the dividend.
ii)Divide a double word by a word.

In this case ,the dividend has to be in AX and DX (the upper word in DX).
The divisor should be a word . The result of this division causes the quotient to be in AX
and the remainder to be in DX.
Examples
DIV BX ;divide the dword in DX-AX by the word in BX
DIV WORD PTR [SI] ;divide the dword in DX-AX by the word pointed
;by SI
DIV ANGLE ; divide the dword in DX-AX by the word in ANGLE
Dividing a word by a word
Similar to the previous case ,if we want a word by word division ,extend the word in AX
to be a double word by loading 0 in DX to get the dividend to be a double word in AX
and DX.
Divide by Zero Error
For division ,if the divisor is zero ,the quotient becomes undefined In attempting such a
division ,the 8086 will exit from this program and generate an interrupt .This state is said
to a ‘divide by zero error ‘.An interrupt generated by an error ,is termed an exception.
But division by zero is not the only condition to cause such an error . If the quotient
register is too small to accommodate the quotient ,then also this happens .For example ,if
the dividend is a large number and the divisor is very small ,such a condition is possible .
MOV AX,09876H
MOV CL,25H
DIV CL
The above program segment will give a quotient of 41E H ,which obviously cannot
be accommodated in AL . If this problem had been foreseen , the solution would be to
convert the dividend to a double word, and the divisor to a word. .Then the quotient will
be in AX ,which will be big enough for it ..When such an error occurs ,program
execution is aborted and the assembler displays the message ‘divide overflow error’.
EXAMPLE 3-20
.MODEL SMALL
.DATA
FIRST DB 89H
SECOND DB 0CAH
AVG DB ?
.CODE
.STARTUP
MOV AL,FIRST ;copy FIRST to AL
MOV AH,0 ;zero-extend
MOV BL,SECOND ;copy SECOND to BL
MOV BH,0 ;zero-extend
ADD AX,BX ;add the zero extended words
MOV CL,02 ;load divisor to CL
DIV CL ;divide AX by CL
MOV AVG,AL ;save quotient to AVG
.EXIT
END
Example 3-20 gives a complete program for finding the average of two bytes stored in
memory locations labeled FIRST and SECOND .These are copied to registers AL and BL
and zero extended to convert them to words. Addition of the numbers is then done as
words. This sum ,which is the dividend is in the AX register. The divisor 2 is copied to
the CL register. After division ,the quotient is available in AL and the remainder in AH
.For this problem ,only the quotient is important ,and this is saved to location AVG.
Now we will see a very useful and interesting application of the division operation.
This program converts a 16 bit hexadecimal number to decimal and displays the decimal
number on the console after converting it to ASCII form.
To see the logic of this program ,let us take a number ,say ,246 .
i) Divide this by 10 to get a quotient of 24 and a remainder of 6 .Push
the remainder on to the stack .
ii) Next ,divide the quotient again by 10 to get 2 as the quotient and 4 as
remainder .Push this remainder also on to the stack.
iii) One more division causes the quotient to be zero .This is the stopping
condition in the division loop..
iv) The number of division operations done is counted along with all these
steps. Now pop out the remainders from the stack .This will be in the
reverse order of the push operations .Thus 2 will be popped out first
and 6 last .This can be displayed in this order.
v) For displaying ,each digit must be converted to its corresponding
ASCII .This is done by adding 30H to each digit .
Now ,examine Example 3.21 the program that does the conversion of any 16 bit
hexadecimal number to decimal and then displays it. Here, the hexadecimal number is
placed in the data segment. Note that the division here is accomplished as a double word
by word division.
Example 3.21
.MODEL SMALL
.DATA
NUM DW 0CEF6H ;the hexadecimal number
COUNT DB 0 ;count of the number of divisions done
.CODE
.STARTUP
MOV AX,NUM ;get the hex number into AX

MOV DX,0 ;DX=0 ,thus DX-AX is the dividend
MOV CX ,10 ; the divisor 10 is loaded into CX
REPEA: DIV CX ; divide by CX
PUSH DX ;the remainder in DX is pushed to stack
MOV DX,0 ;DX=0 again to get the dividend in DX-AX
INC COUNT ;increment the count
CMP AX,0 ;check if the quotient (in AL) is zero
JNE REPEA ;if AL is not zero ,repeat the division
DISP: POP DX ;pop out the remainders for displaying

ADD DL,30H ;add 30H to convert to ASCII
MOV AH,02 ;DOS function call for displaying
INT 21H ;a character
DEC COUNT ;decrement the count
JNZ DISP ;if count=0 ,it means all remainders
;have been popped out
.EXIT
END
3.5 LOGICAL INSTRUCTIONS
Table 3.6 gives the complete list of logical instructions and the function performed
Instruction format Function Performed Flags affected

1 AND dest,src Logical AND of the two operands CF OF PF SF ZF
returning the result in the destination (AF undefined)
2 OR dest,src Logical inclusive OR of the two CF OF PF SF ZF
operands returning the result in the (AF undefined)
destination
3 XOR dest ,src Performs a bitwise exclusive OR of the CF OF PF SF ZF
operands returning the result in the (AF undefined)
destination
4 NOT dest Inverts the bits of the "dest" operand None
forming the one’s complement.
5 TEST dest,src Performs a logical AND of the two CF OF PF SF ZF
operands updating the flags register (AF undefined)
without saving the result.
Table 3.6 : List of Logical instructions and functions performed by them
Example 3-22
Find the result and the state of the FLAGS CF,ZF and OF due to the following
instructions.
Given AX =008CH ,BX =345EH , CX=67EBH
II) AND BL,CL
III) OR AH,BH
IV) XOR AL,CH
V) TEST AH,BL
Solution:
i) AND BL,AL
BL= 5E H 0101 1110

CL= EB H 1110 1011
4A H 0100 1010
After this operation , BL contains 4AH . CF=0,OF=0,ZF=0
ii) OR AH,BH
AH = 00 0000 0000
BH = 34H 0011 0100
34H 0011 0100
After this operation , AH=34H .CF=0,OF=0,ZF=0
iii) XOR AL,CH

AL = 8C H 1000 1100
CH = 67 H 0110 0111
EBH 1110 1011
After this operation, AL=EBH, CF=0,OF=0,ZF=0
i) TEST AH,BL
AH = 00 0000 0000
BL = 5EH 0101 1110
After this operation ,the ZF =1 ,OF=0,CF=0
MASKING
There is a word ‘masking ‘ associated with the AND operation .Masking is used to select
the part of a word or a byte needed ,while making the unwanted bits to be zero
For example ,observe the value in AL after the following instructions are executed.
MOV AL, 78 H
AND AL ,0F H
This gives AL=07H in the AL register .The upper nibble of 78 H has been masked.
As another example ,see below where 16 bit data is ANDed with 0FFFH ,so as to mask
the upper 4 bits., This is a particular case when only 12 bits of this data are needed .
MOV AX, ,9876H

AND AX,0FFFH
AX now has a content of 0876H
TYPICAL APPLICATIONS OF LOGICAL INSTRUCTIONS

Now ,let us use these logical instructions in some simple applications
AND
To convert an ASCII number to a binary number ,mask the number with 0FH
MOV AH,01 ;get in the number through the keyboard
INT 21H
AND AL,0FH ;mask the upper nibble
OR
To convert an 8 bit binary number (from 0 to 9) to ASCII , OR it with 30H
MOV AL ,9 ;AL=09
OR AL,30H ;AL=39H
XOR
To clear a register ,use XOR
XOR BL,BL ;BL=0
TEST
To test whether a bit is set or not use the TEST instruction .
TEST BL,01H
This tests whether bit D0 of BL is 1 or not .If the bit under test is reset ,the AND
operation corresponding to the TEST operations causes ZF to be set.(ZF=1)
TEST CX,8000H
This tests whether D15 of CX is set or not . .The result of this that ZF=0 as D15=1.
3.5 SHIFT AND ROTATE INSTRUCTIONS
Sl Instruction format Function Performed Flags affected

No
1 SHL dest ,count Shift Logical Left by ‘count ‘ bits CF OF PF SF ZF (AF
undefined)
2 SAL dest,count Shift Arithmetic Left by ‘count’ bits CF OF PF SF ZF (AF
undefined)
3 SHR dest,count Shift logical right by ‘count’ bits. CF OF PF SF ZF (AF
undefined)
4 SAR dest,count Shift Arithmetic Right by ‘count’ CF OF PF SF ZF (AF
bits undefined)
5 RCL dest,count Rotate Through Carry Left by CF OF
‘count’ bits.
6 RCR dest,count Rotate Through Carry Right by CF OF
‘count’ bits
7 ROL dest,count Rotate Left by ‘count’ bits CF OF
8 ROR dest,count Rotate Right. By ‘count’ bits CF OF
Table 3.7 List of the shift and rotate instructions .
3.5.1 SHIFT
i) Shift instructions do arithmetic or logical shifting
ii) They also shift right or left .
iii)Arithmetic shift is used for signed number operations ,while logical shift caters
to unsigned numbers.
iv)Shifting right causes a divide by 2 ,for each bit position shifted, while shifting
left corresponds to a multiplication by 2.
v)The count means the number of bit positions ,by which shifting is to be done.
vi)If the count >1, load it in CL ,otherwise use ‘1’ in the immediate mode.
1)SAL/SHL -Shift left Arithmetic/Shift left logical

Usage: SAL/SHL dest,count
This instruction Shifts the destination left by "count" bits and zeroes are shifted in to fill
the vacant positions on the right. The Carry Flag contains the last bit shifted out. .Because
a ‘0’ is shifted in from the right side .Left shift ‘logical’ and ‘arithmetic’ perform the
same operation and hence the mnemonic SAL or SHL can be used interchangeably
Modifies Flags: CF OF PF SF ZF (AF undefined)
Fig
Examples
SHL BX,1 ;shift left logical by one position ,the word in BX

SAL AL,CL ;shift left arithmetic AL by the count specified in CL
SHL DATA2 ,CL ;;shift left logical the content of memory DATA2
; by the count specified in CL
SHL BYTE PTR [BX][DI] ,1 ;shift left (logical)once ,the byte with EA=BX+DI
SAL WORD PTR [DI],CL ;shift left (arithmetic)the word pointed by DI ,by the
;count specified in CL
Example 3-23shows a program segment for finding the weight of the modulo-2 sum of
two numbers.. Modulo-2 sum essentially is finding the positions in which the two
numbers are different – which is an XOR operation. The weight of a number is the
number of 1s in it .
In this problem , the modulo-2 sum is found by XORing the two numbers in AL and BL.
The result of this is then shifted left .The bit shifted out will be in the carry flag On
checking the carry bit ,if it is found to be 1, the register CH is incremented .Along with
this ,the register CL is decremented .CL contains the length of the operand . Here CL=8.
At the end of the program ,we get the ‘weight’ of the modulo-2 sum of AL and BL in
CH. For the numbers used in this program ,CH=6 is the result.
Example 3.23
.MODEL TINY
.CODE
.STARTUP
MOV AL,89H ;move first number to AL
MOV BL,0F7H ;move second number to BL
XOR AL,BL ;EX-OR the two numbers
MOV CL,8 ;CL=8
BACK: SHL AL,1 ;shift left AL once
JNC REPEA ;repeat if there is no carry
INC CH ;increment CH if there is a carry
REPEA: DEC CL ;decrement count
JNZ BACK ;repeat the shifting until CL=0
.EXIT
END
2) SHR –shift right logical

Usage:SHR dest,count
This instruction shifts the destination right by ‘count’ bits and fills with zeroes the vacant
positions on the left. The Carry Flag contains the last bit shifted out.
Modifies Flags: CF OF PF SF ZF (AF undefined)
Fig
Examples
SHR DX,1 ;shift right by one position ,the word in DX

SHR WORD PTR [SI]THERE ,CL ;shift right the word with EA=THERE+SI ,by
;the count specified in CL
SHR CH ,CL ;shift right the content of CH ,by the count in CL
SHR BYTE PTR [BP]ISI] ,1 ;shift right by one the byte pointed by EA=BP+SI
Example 3.24 shows an example of a shift operation. When a decimal number is

represented as a 4 bit binary nibble ,and these nibbles are packed in a byte ,it is called
packed BCD representation for example the packed BCD representation of 56 is 0101
0110 . Unpacking it means separating it as two bytes 0000 0101 and 0000 0110.
Example 3.24
Convert a packed BCD byte to two unpacked bytes.
Solution:
.MODEL TINY
.CODE
.STARTUP
MOV AL,95H ;copy the packed BCD byte to AL
MOV BL,AL ;copy the same byte to BL
AND AL,0FH ;mask the upper nibble of AL
AND BL,0F0H ;mask the lower nibble of BL
MOV CL,04 ;move a count of 4 into CL
SHR BL,CL ;shift BL right 4 times
.EXIT
END
In this problem, a packed BCD byte is in AL.

It is to be unpacked and placed in two registers. The operand is AL .Keep a copy of it in
BL too . For unpacking ,fist the upper nibble of AL is masked . This gives one unpacked
BCD byte. This is now in AL Next ,the lower nibble of BL is masked ,and the result is
shifted right 4 times to bring the upper nibble data to the lower nibble position.
Now ,the two unpacked bytes are available in AL and BL.
Note : The operation and practical use of the SAR instruction will be discussed in
Section 4.7.4 ,where signed number arithmetic is dealt with .
3.5.2 ROTATE INSTRUCTIONS

Rotate instructions have the same format as the shift instructions .There are two types of
rotate – rotate through carry or without taking the carry bit as a part of the rotate act.
ROL – Rotate Left

Usage: ROL dest, count
This instruction rotates the bits in the destination to the left "count" times with all data
pushed out at the left re-entering on the right. The Carry Flag will contain the value of
the last bit rotated out.
Modifies Flags: CF OF
Examples
ROL SI, CL ;rotate left the word in SI ,by the count in CL
ROL BYTE PTR [DI][BX],1 ;rotate left the byte pointed by EA=[DI+BX] once
ROR - Rotate Right

Usage: ROR dest,count
This instruction rotates the bits in the destination to the right ‘count’ times with all data
pushed out at the right side re-entering on the left. The Carry Flag will contain the value
of the last bit rotated out.
Examples
ROR AL,1 ;rotate right once the byte in AL
ROR DX,CL ;rotate right the word in DX the count in CL
Let us examine what Example 3.25 will do.
Example 3-25
.MODEL TINY
.CODE
.STARTUP
MOV BX,5634H
MOV CL,8
ROL BX,CL
MOV AL,0C6H
MOV CL,4
ROR AL,CL
.EXIT
END
In the first instance ,there is a 16 bit register BX which contains the value 5634H..By
using ROL ,and rotating 8 times the value in BX changes to 3456H. .Similarly with
AL=C6H , using ROR with a count of 4 ,Al will have the new value of 6C H. Thus we
can switch exchange nibbles or bytes using the rotate instructions with the appropriate
count in CL . Note that ,for this application ,it does not matter if ROL or ROR is used.
It is easy to check that Example 3-24 can be re-written replacing the SHR instruction
with either the ROL or ROR instruction.
RCL - Rotate Through Carry Left

Usage: RCL dest, count
This instructions causes the left most bit (LSB) to enter the carry flag ,and the CF enters
through the left end(MSB) Thus ,due to one shift operation ,the MSB enters the CF ,and
the CF gets into the LSB position.
Examples
RCL BL,CL ; rotate left through carry , BL ,by the count in CL
RCL CX,1 ; rotate left through carry the word in CX once
RCR - Rotate Through Carry Right
Usage: RCR dest, count
This instructions causes the right most bit (MSB) to enter the carry flag ,and the CF
enters through the left end(MSB) Thus ,due to one shift operation ,the LSB enters the CF
,and the CF gets into the MSB position.
Examples
RCR BYTE PTR [SI] ,1 ;rotate right through carry ,the byte pointed by SI,once
RCR WORD PTR [DI][BX],CL ;rotate right through carry the word pointed by
EA=SI+BX ,by the count specified in CL
Example 3.26
Find the values in the destination for each line of this program segment.
STC
MOV AX,5485H
RCR AL,1
MOV CL,03
RCL AX,CL
MOV CL,05
ROR AX,CL
ROL AX,1
Solution:
Instructions Result after execution
STC CF=1
MOV AX,5485H AX=0101 0100 1000 0101
RCR AL,1 AL=1100 0010
MOV CL,03 CL=03
RCL AX,CL AX=1010 0110 0001 0101
MOV CL,05 CL=5
ROR AX,CL AX=1010 1101 0011 0000
ROL AX,1 AX=0101 1010 0110 0001
Key Points of this chapter
• BIOS and DOS function calls facilitate the use of input and output devices in
programming, making it interactive and more fun.
• The instruction set of 8086 can be divided into groups based on functionality.
• MOV is the most frequently used instruction and it is part of the data transfer
group.
• LEA is an instruction that copies the offset of a memory address to a 16 bit
register. It can be used to make the register be a pointer to an array of data items
in memory.
• PUSH and POP can be used only with the stack segment
• The SS register contains the upper 16 bits of the lowest (base) address in the stack
segment. SP contains the offset (with respect to the base address ) of the highest
address in the stack.
• Branch instructions cause the program sequence to change.
• JUMP is an important branch instruction which can be far or near ,and
unconditional or conditional.
• Jumps using the direct mode of addressing are re-locatable and ‘relative’.
• LOOP is a jump instruction which causes branching as well as decrementing a
count in CX. A LOOP instruction can be conditional ,as well.
• There are 20 arithmetic instructions for 8086 ,of which a few specifically cater to
signed numbers, a few to BCD numbers ,and a few to ASCII numbers.
• The ADC(Add with carry) and SBB (Subtract with borrow) instructions find use
in multibyte additions and subtractions.
• The INC and DEC instructions do not affect the carry flag.
• The CMP (Compare) instruction subtracts the source from the destination
and sets/resets flags ,but neither the source nor the destination is altered.
• MUL is the mnemonic for unsigned multiplication .For a byte by byte
multiplication ,one operand is implied to be in AL and the product in AX. For a
word by word multiplication , one operand is to be in AX and the product will be
in DX-AX.
• DIV is the mnemonic for unsigned division. For a word by byte division ,the
dividend is to be in AX .After division ,the quotient will in AL ,and the remainder
in AH .For a double word by word division ,the dividend is to be in DX-AX
.Then the quotient will be in AX and the remainder in DX.
• If the quotient is too large to fit in the register assigned for it , a ‘divide by zero’
error will be generated.
• The logical instructions of 8086 are AND,OR,XOR,NOT and TEST.
• The TEST instruction does logical ANDing ,but only the flags are affected.
• Shifting of a data can be done left or right ,and also by as many positions as
required.
• Arithmetic shifting is meaningful for signed numbers , while logical shifting
pertains to unsigned arithmetic.
• Rotation can be done left or right and can be direct or through the carry flag.
QUIZ
1. Distinguish between the top-down and bottoms-up approach in programming.
2. What is the use of DOS function calls in assembly programming?
3. How many operands do each of the following instructions have?
a. ADD ii) ADC iii) INC
4. Which conditional flag is not affected by the DEC instruction?
5. If AX=5600H and BX=0C07H ,find the contents of CX and DX after the
following three sets of instructions.
i) PUSH AX ii) PUSH AX iii) PUSH BX
PUSH BX PUSH BX PUSH AX
POP CX POP DX POP CX
POP DX POP CX POP DX
6. Why is the stack pointer called the TOP OF STACK?
7. Distinguish between a near and a far jump.
8. Specify two ways of specifying an unconditional jump in the indirect mode of
addressing.
9. Why does the far jump have five bytes of instruction length?
10. Name a conditional jump instruction that does not test a conditional flag.
11. What are the conditions under which a LOOPZ instruction exits looping?
12. What does the instruction STC do?
13. Can the ADD instruction use CS as a destination?
14. The instruction INC [SI] seems ambiguous .Why? How can the ambiguity be
corrected?
15. What does the instruction CMP AX,BX do?
16. What is the role of OF and CF in multiplication?
17. What happens if the DIV instruction is used for a dividend of 1938H and divisor
of 05?
18. What is meant by masking? Give an example of how it is used?
19. How can multiplication and division be achieved by shift operations?
20. What is the difference between the instructions RCL and ROL?
EXERCISE
1) Write a program to print on two separate lines ,the messages ‘Hi, folks’
and ‘I am Samantha’.
2) Enter a character through the keyboard without echoing it on the video monitor.
Compare it with a number stored in memory and display the message ‘EQUAL’
or ‘NOT EQUAL’ as the case may be.
3) Display each character of the word PRADO on a separate line.
4) Enter ‘N’ characters through the keyboard without echo. Save it in memory as an
array .Then display it as a character string.
5) Indicate what is wrong (if anything is wrong) with each of these instructions.
i. MOV CX,DL
ii. ADD DATA1,0978H
iii. MOV BYTE PTR [SI][BX],DX
iv. MOV 045FH,AX
v. MOV [DX],AL
vi. MOV [SI][CX],AX
vii. MOV DS,3453H
6) Write a program that adds two quad words and stores the result in memory.
7) Write a program that subtracts two double words and stores the result in memory.
8) Find the status of the CF and ZF flags after the execution of the following sets of
instructions.
i) MOV AX,9078H
CMP AX,0C089H
ii) XOR AL,AL
iii) MOV AL,29H
CMP AL,0
9) Find the biggest number in an array of i) bytes ii) words. Display the biggest
number in each case ,as a decimal number.
10) There are 10 unsigned bytes stored in memory .Arrange these bytes in i)
ascending and ii) descending order.
11) Find the average of 20 bytes stored in memory .Display the average as a decimal
number.
12) Add the sum of the first 20 natural numbers .Display the sum.
13) Write a program that counts the number of 1s in a binary number.
14) Write a program to add two N x N matrices.
15) Find the number of times a particular character is present in a character string
stored in memory.
CHAPTER 4
PROGRAMMING CONCEPTS-III
OBJECTIVES
• To use string instructions for various applications

• The concept and use of procedures and call instructions
• To distinguish macros from procedures and learn to write and use macros
• To write programs to convert between the commonly used number formats
• Signed number arithmetic using 8086 instructions
• To write programs using the high level language constructs of MASM
4.1 String Instructions

The 8086 has a set of instructions for handling blocks of data in the form of bytes or
words. They are called ‘ string’ instructions . A string is an array of data of the same type
–like ,for example, a character string ,byte string and so on .Table 4.1 gives the list of
string instructions/prefixes which are used in string manipulations. The usefulness of
string instructions can be seen when data in blocks in memory has to be moved, searched
, compared etc..
Consider the case of 100(say) words or bytes in a particular memory area that is to be
moved to another memory area .This can very well be done using pointer registers and
looping using a counter . But, this whole process can be, sort of, automated with less
number of instructions ,if we use string instructions. Similarly, we may need to
compare two blocks of data for equality ,or search a data block for a particular data
.In all these cases ,string instructions make our task easier and our code shorter.
But before using these instructions, we have to include a few initialization steps in our
code.
Pre-requisites for using string instructions
i. Two segments are to be defined i.e. the data segment and the extra segment. This
means that the corresponding segment registers DS and ES have to be initialized
and used. The data segment is the source segment and the extra segment is the
destination segment.
ii. The DI register and SI registers should act as pointers to the data segment and
extra segment respectively.. This means that, initially, SI should contain the
address (offset) of the first location of the data segment .Similarly , DI should
contain the address(offset) of the first location of the extra segment.
iii. There is a control flag called the direction flag which is used exclusively for
string operations .Its purpose is that in string operations, if the flag is set, the
pointer registers get automatically decremented and if reset, the reverse occurs
.So whenever string instructions are being used, the direction flag (DF)should be
set or reset depending on the direction the addresses are to be modified after each
operation
iv. The counter CX should be loaded with the count of the number of operations
required.
Sl Instruction format Function Performed Flags affected

No
1 MOVSB/MOVSW Move byte or word stringNone
2 CMPSB/CMPSW Compare byte or word string
AF CF OF PF SF
ZF
3 SCANSB/SCANSW Scan byte or word string AF CF OF PF SF
ZF
4 LODSB/LODSW Load byte or word string None
5 STOSB/STOSW Store byte or word string None
6 CLD Clear direction flag DF
7 STD Set direction flag DF
8 REP(Prefix for a string Repeat execution of string None
instruction) instructions while CX is not 0
9 REPE/REPZ (Prefix for a Repeat execution of string None
string instruction) instructions while CX is not 0
and while Zero flag is set
10 REPNE/REPNZ(Prefix for Repeat execution of string None
a string instruction) instructions while CX is not 0
and while Zero flag is not
set
Note In string instructions ‘SB’ stands for ‘string byte ‘ and ‘SW’ for ‘string word’
Table 4.1 List of instructions/prefixes used in string operations
.
4.1.1 The MOVS instruction
Example 4-1 shows the use of the string instruction MOVSB with the necessary pre-
requisites incorporated .Let us examine how this has been done.
The problem in hand is to transfer 10 bytes (the character ‘*’) from an area of memory
designated as DATA1 to an area named DATA2. Thus the source has to be the data
segment ,and the destination the extra segment. .How do we incorporate. the extra
segment?
If we use the full segment model ,we can define two segments i.e.-the data
segment(DAT) and the extra segment (EXTR) .See how it is done. When both the
segments registers are defined, the segments get defined. Then the program instructions
cause the data in the data segment to be copied to the extra segment. Example 4-1a uses
the full segment model for this.
Example 4-1a
DAT SEGMENT
DAT1 DB 10 DUP('*') ;store ‘*’ in 10 locations
DAT ENDS
EXTR SEGMENT
DAT2 DB 10 DUP(0) ;allocate 10 locations
EXTR ENDS
COD SEGMENT
ASSUME CS:COD,DS:DAT,ES:EXTR
MOV AX,DAT
MOV DS,AX ;initialize the DS register
MOV AX,EXTR
MOV ES,AX ;initialize the ES register
LEA SI,DAT1 ; point SI to Source

LEA DI,DAT2 ; point DI to destination
MOV CX,10 ; load count in CX
CLD ; clear Direction flag
REP MOVSB ; move the byte string
MOV AH,4CH ;AH=4CH to return to DOS
INT 21H
COD ENDS
END
In Example 4-1a , two segments DAT and EXTR are defined ,and two segment
registers are initialized –i.e. DS and ES. The addresses SI and DI point to the source data
and destination data addresses and DF is cleared for auto incrementing the pointer
registers.
Now let us do the same program using the simplified model. The small model can have
only one data segment ,so how can we have an ‘extra segment’? The solution is to have
both data areas in the data segment itself ,but after the data segment is defined, copy
the value of DS into ES –this makes the assembler believe that the extra segment is
available-though it is the same as the data segment. In this example ,the destination data
area is chosen to be at org 0200H .This is done just to space the source and destination
data areas and is not mandatory. Thus the first pre-requisite of having both the data and
extra segments is satisfied.
Next, the SI register is made to point to the address DATA1 and the DI register to
DATA2 . Then the counter register is loaded with 10 ,the count of data transfer
operations required . The instruction CLD is used to clear the direction flag(DF). This
causes the value of SI and DI to be incremented after each move operation. Here the
data is in the form of bytes. Hence SI and DI are incremented only by one each time .The
string instruction used here is MOVSB (prefixed by REP).This causes the data in the
location pointed by SI to be moved to the location pointed by DI. After each such move
operation , two actions occur. One is that CX decrements by 1,and the other is that the
pointer registers are incremented. This sequence continues until CX=0. Example 4-1 a
and b illustrate these steps.
Example 4-1b

DAT1 DB 10 DUP('*') ;store ‘*’ in 10 locations
ORG 0200H ;define destination area
DAT2 DB 10 DUP(?) ;set aside 10 locations
.CODE
.STARTUP
MOV AX,DS ; move DS into AX
MOV ES,AX ; move AX to ES
LEA SI,DAT1 ; point SI to Source
LEA DI,DAT2 ; point DI to destination
MOV CX,10 ; load count in CX
CLD ; clear Direction flag
REP MOVSB ; move the byte string
.EXIT
END
For the above program ,if the data involved is in the form of words, the only change
would be to replace the line REP MOVSB with REP MOVSW. In this case, CLD will
cause SI and DI to be incremented by 2
4.1.2 The CMPS instruction
Now ,let use the next string instruction –i.e. CMPSB/CMPSW .This instruction is for
string comparison , byte by byte or word by word as the case may be. The conditional
flags are modified according to the result of the comparison. String comparison has to be
accompanied by the use of the conditional REP prefix .Since string comparison checks
only for equality, the Zero flag is made use of automatically.
Example 4-2 compares two character strings (of length six) which are saved in the data
segment. One of the two messages are to be displayed depending on whether WRD2 is
the same or not the same as WRD1.
Example 4-2
.MODEL SMALL
.DATA
WRD1 DB "SAMSON" ;store the first word
WRD2 DB "SAMRON" ;store the second word
GUD DB "SAME$" ;store the message for equality
BAD DB "NOT SAME$" ;store the message for inequality
.CODE
.STARTUP
MOV AX,DS
MOV ES,AX ;Copy DS to ES
LEA SI,WRD1 ; point SI to source
LEA DI,WRD2 ;point DI to destination
MOV CX,6
CLD ;clear direction flag

REPE CMPSB ;repeat comparison if equal(ZF=1)
JNZ MSG ;if ZF is reset, go to MSG
LEA DX,GUD ;point DX to the first message
JMP DISP
MSG: LEA DX,BAD ;point DX to second message
DISP: MOV AH,09 ;use the function for string display
INT 21H ;use DOS interrupt 21H
.EXIT
END
Here SI and DI point to the two character strings ,CX stores the count and the direction
flag is cleared for auto incrementing the address pointers .REPE is used as the prefix for
comparing the string bytes. REPE CMPSB means that the corresponding string bytes of
the source and destination are compared as long as they are equal. Equality also implies
that the Zero flag is set .The comparison is stopped as soon as an inequality is
encountered. One of the following two conditions cause the comparison loop to be exited.
i)an inequality is seen –i.e. the Zero flag gets reset
ii)normal exiting when CX=0.
In the example, the two character strings are shown to be different, which causes the
message ‘NOT SAME’ to be printed .If WRD1 and WRD2 are the same, the message
‘SAME’ is printed.
4.1.3 The SCAS instruction

The SCANS instruction scans a byte or word string to ascertain the presence of a specific
byte or word .This specific data is loaded into AL or AX. The string which is to be
scanned has to be in the extra segment ,and is to be pointed by DI .This is
mandatory and cannot be overridden.
Example 4-3 illustrates a typical scenario for the use of this instruction.
Suppose that an ASCII string labeled LIST is stored in memory .
The program searches the string for the presence of the ASCII character ‘S’.DI
addresses the string to be searched. The string to be searched is placed in the Extra
segment ,by making the ES have the same value as DS.Thus the extra segment is the
same as the data segment. .In this example ,the SCASB instruction has an REPNE prefix
(repeat while not equal)prefix. The REPNE prefix causes the SACASB instruction to
repeat until either the CX register reaches 0,or until an equal condition is indicated
(ZF=1)as the outcome of the SCASB instruction’s comparison operation. . The scanning
of the string continues as long as ‘S’ is not found in the string .If ‘S’ is found , the search
is terminated immediately.
Example 4-3
.MODEL SMALL
.DATA
LIST DB "ANBHTSHFGTRIUUJEHNPBGDVBTH"
PR DB "CHARACTER PRESENT$"
NOTP DB "CHARACTER NOT PRESENT$"
.CODE
.STARTUP
MOV AX,DS ;copy DS to AX

MOV ES,AX ;copy DS to ES
LEA DI,LIST+26 ;point SI to the last character
STD ;auto-decrement
MOV CX,26 ;load count in CX
MOV AL,'S' ;load the character in AL
REPNE SCASB ; repeat if not equal
JZ MSG
LEA DX,NOTP
JMP DISP
MSG: LEA DX,PR
DISP: MOV AH,09
INT 21H
.EXIT
END
In the above, a variation (from the previous examples) has been used .DI has been made
to point to the last character of the string ,and the direction flag is set ,such that it auto
decrements after each scanning operation.
Refer to Example 3-17 , where the same problem has been done without using string
instructions.
4.1.4 The STOS and LODS instructions
i)STOS
The STO instruction is the mnemonic for ‘storing’ in memory . As such ,we need to
define a memory area in which ‘storing’ is to be done .This memory area is defined to
be the extra segment ,and it is addressed by DI as it is the destination segment. The
data to be stored is placed in the AL or AX register. An area in memory can be filled with
the required data with this instruction.
Example 4-4 illustrates the use of the STOS instruction. Here AX is loaded with 0001
,and this is moved to a location named AREA., which has been defined as a array of 50
words.. This array is filled with the word 0001 by the STOSB instruction ,using the
REP prefix and the counter CX initialized with 50. Since STOS is specified for the extra
segment , ES register has to be initialized .. Notice that , as done earlier ,a data segment
is first defined (by the .DATA directive) and the DS register content is then moved to
ES .Note also that the memory AREA is addressed using the DI register .SI register
cannot be used.
Example 4-4

AREA DW 50 DUP(?) ;define AREA

MOV AX,DS ;copy DS to AX
MOV ES,AX ;copy AX to ES
LEA DI,AREA ;address AREA with DI
CLD ;clear direction flag
MOV AX,0001 ;load AX with 0
REP STOSW ;repeat until CX=0
.EXIT ;exit to DOS
END ;end of program
It is obvious that the STOS instruction is used to fill up an area in memory with the same
data.
ii)LODS
The last of the string instructions is LODS. This is an instruction for ‘loading’ .Loading
always means the act of taking data from memory and putting it into a register .Here ,the
source memory is the data segment ,the pointer to it is SI.. The data segment is the source
segment and the destination register is the AL or AX register. There is no sense in using
the REP prefix for the LODS instruction as data can be loaded to AL/AX only once .
4.2 PROCEDURES
In high level languages (C ,C++ etc.)you might have come across ‘functions’ .A
function is a program which does a specific task .When this task is to be done repeatedly,
the function is used again and again .When a ‘main’ program considers this as a
subsidiary task ,the function(or sub routine) is ‘called’ whenever its service is required.
This is applicable to assembly language programming also.. Borrowing Intel’s
terminology , we shall call it a ‘procedure’.
The figure below shows two cases. One is the case of a main program calling many
different procedures .The second is a program calling the same procedure repeatedly.
Main program Main program

… …..
… ……
….. CALL BETA
CALL ALPHA ….
….. ……
….. CALL BETA
…. …
…. …..
CALL BETA …..
….. …..
…. CALL BETA
…..
CALL GAMMA …..
…. …..
END END
Fig 4-1a Fig 4-1 b
Fig 4-1 a Main program calling different procedures

Fig 4- 1b Main program calling the same procedure repeatedly
Thus there is a main program which can call a procedure anywhere in its body. The
former is the ‘calling program’ and the latter is the ‘called program’. The main program
is in a particular code segment and the procedure may be written in the same code
segment (in which case it is a ‘near’ procedure) , or it may be in a different segment
(‘far’ procedure).
Let us now see the sequence of actions taken by a processor when using a procedure .
For now, let us assume that the procedure is a ‘near’ procedure.. In the course of the
action of execution of the main program ,a CALL instruction is encountered .This
signals that a procedure written elsewhere has to be executed. This is essentially a
branching operation ,as the normal program execution sequence is disturbed. At the time
the CALL instruction is being executed, the IP(instruction pointer) will be pointing to
the next instruction in the main program . The steps taken by the processor automatically
are
i) It saves the current IP content on the stack. (This is the ‘return’ address for
coming back to the main program after executing the procedure)
ii) The CALL destination (specified in the CALL instruction)will be the address
of the procedure. The IP is now loaded with this address and execution
proceeds from that location..
iii) The procedure is executed until a RET (return) instruction in the procedure is
encountered.
iv) Then, the old value of the IP is retrieved from the stack and control returns to
the main program at the return address.
........
CALL MULT
........
........
........
........
PROC MULT NEAR
........
Fig 4-2 Call .and
. . . Return
....
........
. . . . . . .in. a main program . Then the procedure MULT is
Fig 4-2 shows a CALL encountered
RET
taken up for execution. At the end of the procedure ,there is the RET instruction ,
executing which causes control to return to the main program .The instruction after the
CALL instruction will now be taken up.
4.2.1 Writing a procedure

Like any assembler , MASM also has specifications for writing a procedure. The
procedure should begin with the procedure name followed by the directive PROC .
We also use the directives NEAR or FAR which specify the ‘type’ of the procedure
The procedure should end with the procedure name and ENDP .
Example 4-5 shows a program which enters 10 single digit numbers through the
keyboard, find their squares and stores the squares in memory .Only byte locations have
been allocated in memory for the squares , as the square of the highest single digit
number is 81 which will fit into a byte space. In the procedure, the register assigned for
the product is AX. But the product will occupy only AL .Hence only the value in AL is
moved to memory.
Now, let us examine the salient features of this program
i) A procedure named SQUARE is used to calculate the squares
ii) Entering data from the keyboard and storing the squares in memory is done
in the main program .
iii) The procedure is in the same code segment.. Hence it is designated as ‘near’.
iv) The procedure ends with a RET (return) instruction which takes control back
to the main program.
v) The .EXIT statement is the last statement in the main program. We know that
it gets converted to the instructions for returning control to DOS. Thus, it is
the last instruction which gets executed.
vi) The last line in the code is the END directive which tells the assembler to stop
reading.
vii) We know that the stack segment is necessary for the working of a procedure.
For now, we are not defining any stack segment but using the stack defined
automatically by DOS. When we need more stack size, we will define our
own stack.
Example 4-5
.MODEL SMALL
.DATA
NUMBERS DB 10 DUP(0) ;allocate space for squares
.CODE
.STARTUP
LEA SI,NUMBERS ;let SI point to NUMBERS
REPEA: MOV AH,01 ;key board input
INT 21H
SUB AL,30H ;convert from ASCII to binary
CALL SQUARE ;call the procedure for squaring
MOV [SI],AL ;store the square in memory
INC SI ;increment pointer
LOOP REPEA ;decrement CX and repeat if CX!=0
.EXIT ;return to DOS prompt
SQUARE PROC NEAR ;define the procedure

MOV BL,AL ;move multiplicand to BL
MUL BL ;multiply
RET ;return to main program
SQUARE ENDP ; define the end of the procedure
END
In the above, the square of the numbers has been calculated and saved in memory .It may
be interesting to display them on the monitor. .This can be done by referring to Example
3-21 .The program for converting any hexadecimal number to binary and displaying can
be made another procedure and called appropriately here.
4.2.2 CALL AND RETURN INSTRUCTIONS
Now that we have seen the general format and structure of a program with procedures, let
us examine the CALL instruction in greater detail. This instruction is obviously a
‘branch’ instruction because it causes control to move to a different address (called the
target or destination) ,which may be in the same or a different code segment.
4.2.2.1 INRASEGMENT OR ‘NEAR’ CALL

i)Direct CALL
Usage: CALL label
OPCODE OFFSET LOW OFFSET HIGH

Fig 4.3 Format of the direct near CALL instruction
The direct call is like a direct jump instruction ,and is three bytes long ..It is relative and
the destination can be -32,768 bytes to +32,767 bytes from the address of the instruction
following the call (this will be the current content of the IP). This means that the offset
can be a 16 bit signed number .When this call is executed, the new value of IP =old IP+
offset , where the second and third bytes of the instruction give the offset. The assembler
must calculate the offset during its first pass. Example 4-5 uses this type of the call
instruction –i.e. the direct near call.
Example
CALL NEW_WAY ; using the label, the assembler calculates the offset
CALL MULTI
ii) Indirect CALL
Usage: CALL reg16 ,CALL [reg16]
In this case, the destination is specified in a 16 bit register or in a memory location
pointed by a register. This is not a ‘relative’ call. The content of the referred register or
memory location is loaded into IP for using the procedure.
Example
CALL BX ;the procedure’s address is in BX
CALL WORD PTR[BX] ;the address of the procedure is in memory and
; is pointed by BX
The following program illustrates the use of an indirect near call.

Example 4-6 illustrates the use of the CALL register instruction to call procedures that
begin at offset addresses ENT and DISP.(These calls could also call the procedures
directly as CALL ENT and CALL DISP).The offset address ENT is placed in BX and
DISP in SI ,and then the CALL BX and CALL SI instructions call these procedures. The
ENT procedure allows keyboard entry with echo. If an upper case letter is entered by
ENT ,the calling program converts into lowercase and the DISP procedure displays the
corresponding lowercase latter.
EXAMPLE 4-6
.MODEL TINY ;select tiny model
LEA BX,ENT ;offset of ENT in BX
LEA SI,DISP ;offset of DISP in SI
CALL BX ;call the ENT procedure
ADD AL,20H ;upper case to lower case
MOV DL,AL ;transfer lower case to DL
CALL SI ;call the DISP procedure
.EXIT
ENT PROC NEAR

MOV AH,01 ;procedure for entering key
INT 21H
RET
ENT ENDP
DISP PROC NEAR

MOV AH,02 ;procedure for displaying
INT 21H
RET
DISP ENDP
END
4.2.2.2 INTERSEGMENT OR FAR CALL

Direct Far Call
A far call is an intersegment call ,which means that the destination address is in a
different code segment .
This will be a five byte instruction ,the first byte being the opcode ,the second and third
bytes being the new value of IP ,and the fourth and fifth the new values of CS. This is not
a relative call. When the procedure is called ,the IP and CS values are replaced by the
corresponding values in the call instruction.
OPCODE IP LOW IP HIGH CS LOW CS HIGH
Fig 4-4 Format of the far jump instruction

Indirect Far Call
For an indirect call, the destination address is not to be in the instruction –rather, it is in a
register or memory .For a far call , four bytes are needed to specify a destination
.Obviously ,a register cannot specify it . Hence the four bytes needed to specify a
destination are stored in memory and pointed by a register .As an example
CALL DWORD PTR [SI] can be a far call instruction .[SI] and [SI+1] gives the new
value of IP and [SI+2] and [SI+3] gives the new value of CS.
Far calls and procedures are specified using the ‘far’ directive when defining the
procedure. In Chapter 5, we will see how the EXTRN directive is used in this context.
4.2.3 The RET instruction

i)Usage: RET
When a procedure is called, the current value of IP is pushed on to the stack .This
naturally means that when the procedure has ended, control should go back to the main
program at the point where it had branched off .This means that the value of IP ( and CS
for a ‘far’ call) will have to be retrieved .This is done by the ‘return ‘ instruction which is
the last instruction in the procedure. The execution of RET causes the return address to be
popped from the stack to IP or IP and CS..(,whenever a procedure is defined , it is known
whether it is a far or near procedure. From this ,it is determined whether the stack has
saved just the old IP value or both IP and CS)
ii)Usage: RET n
This is another form of the RET instruction .This adds the number ‘n’ to the stack
pointer(SP) after the return address has been popped off the stack ,on return from a
procedure. We will see the usage of this in Example 4-10.
4.2.4 THE USE OF THE STACK IN PROCEDURE CALLS
The stack is used in procedure calls for saving the return address . There is another
context when a stack is necessary . The main program may be using a number of general
purpose registers .Since the number of registers is limited, what happens if the procedure
too needs a few of those registers ? If the procedure uses the same registers ,obviously
their content will be changed .To avoid this problem , the contents of these registers
(including the flag register) may be pushed on to the stack before calling the procedure,
and popped back from stack on returning from the procedure. This allows both the main
program as well as the procedure, the use of the same registers without losing their
content . It is up to the programmer to write these push and pop instructions (either in the
main program or in the procedure)The only point to remember would be to push and pop
in reverse order . But now, MASM 6.x has a construct ‘USES’ which automatically
pushes the specified registers onto the stack .The popping will be automatic on returning
from the procedure.
Example 4-7a illustrates this.
EXAMPLE 4-7a
.MODEL SMALL
.DATA
----------------
.CODE
.STARTUP
..
..
..
CALL MULTI
..
..
..
MULTI PROC NEAR USES DX CX

MUL BL
MOV DX,4509H
ADD AX,DX
MOV CX,0608H
ADD AX,CX
RET
MULTI ENDP
END
Now see Example 4-7b .The main program is not shown .What is illustrated is that it uses
registers DX and CX . These registers are used in the procedure MULTI as well. The
USES construct at the start of the procedure will be converted to PUSH DX and PUSH
CX when the procedure is called ,and to POP CX and POP DX when returning from the
procedure. This can be verified by ‘debugging’ the program or by using the directive
.listall . Then the list file will show the listing of the procedure as shown below. Note the
push and pop DX and CX which we have not written specifically in the program ,but
have been caused by the USES construct.
Example 4-7b
002B MULTI PROC NEAR USES DX CX

002B 52 * push dx
002C 51 * push cx
002D F6 E3 MUL BL
002F BA 4509 MOV DX,4509H
0032 03 C2 ADD AX,DX
0034 B9 0608 MOV CX,0608H
0037 03 C1 ADD AX,CX
RET
0039 59 * pop cx
003A 5A * pop dx
003B C3 * ret 00000h
003C MULTI ENDP
END
4.2.5 PASSING PARAMETERS TO AND FROM PROCEDURES

When procedures are called, they have to be given data on which to work on, and then
these procedures will have to return results to the calling program .There are various
ways of doing this. One way would be to place it in registers which can be accessed by
the main program as well as the procedure .Another way would be to place data in
memory and access it by name ,or by using pointers . Still another method is to use the
stack for this .Data or addresses made available to both the calling and called programs
are called ‘parameters’ and now we will discuss various ways of ‘passing parameters’ to
and from procedures.
4.2.5.1 Passing parameters through registers

In this case, data is placed in registers by the main program ,and these registers are used
by the procedure.
Example 4-8 is a program which calculates and places in memory the Nth term of an
arithmetic progression . The formula for the Nth term of an A.P. is A+(N-1)D ,where A
is the first term and D is the common difference. Here ,the values of A,N and D are
placed in the data segment from where the main program takes them ,loads then into
registers and passes the values to the procedure. The procedure does the computation
and the result to the main program through register BX.
Example 4-8
.MODEL SMALL
.DATA
A DB 4 ; A=4
D DB 5 ; D=5
N DB 20 ;N=20
NTH DW ?
.CODE
.STARTUP
MOV BL,A ; copy A to BL
MOV BH,0 ;BX=0 to have A in BX as a word
MOV AL,D ;copy D to AL
MOV CL,N ;Copy N to CL
DEC CL ;decrement CL to get N-1
CALL NTH_TERM_AP ;call the procedure
MOV NTH,BX ; save the nth term in memory
.EXIT
NTH_TERM_AP PROC NEAR

MUL CL ;multiply (N-1)x D ,product in AX
ADD BX,AX ;Nth term =A+ (N-1)D will be in BX now
RET
NTH_TERM_AP ENDP
END
4.2.5.2 Passing parameters through memory

In Example 4-9, the data which is used by the procedure is accessed from memory
through the pointer register BX ,and data is put back in memory in the same way.
Example 4-9 is a program for arranging a set of numbers (stored in memory) in
descending order. The method is comparing pair wise, and repeating this N-1 times ,if
there are N numbers to be sorted .The steps are:
i) Suppose the numbers are 6,8,34,0,67 . The first two numbers are compared. If
the first number is greater than the second, no change is made to the ordering
.Otherwise exchange them , such that the bigger number comes first in the
pair.. For our set ,now the ordering becomes 8,6,34,0,67.
ii) Next, the second and third numbers (i.e. 6 and 34) are compared .The new
ordering is 8,34,6,0,67 .
iii) This is repeated N-1 times, so that due to pair wise ordering, the bigger
number comes first in the new ordering of pairs. In Example 4-9 , the
procedure one_set does this.
iv) This sequence of steps is repeated N-1 times ,such that the we get all the
numbers sorted in descending order, replacing the unsorted array.
Example 4-9
.MODEL SMALL
.DATA
N WORD 0009H
NUMS BYTE 10H,08,89H,78H,67H,07,2,99H,0FEH
.CODE
.STARTUP
LEA BX,NUMS ;BX to point to the number array
MOV CX,N ;move the array size to CX
DEC CX ;CX must contain N-1
MOV SI,BX ;SI to have copy of starting address
AG: MOV DX,CX ;DX=N-1
STRT: CALL ONE_SET ;the procedure for pair-wise ordering
DEC DX ; keep count of the calling
JNZ STRT ;repeat until DX=0
MOV BX,SI ;put the starting address back in BX
LOOP AG ;loop back until CX=0
.EXIT
ONE_SET PROC NEAR

MOV AL,[BX] ;get the first number in AL
REPEA: MOV AH,[BX] ;get the second number in AH
CMP AL,AH ;compare the numbers
JB EXCH ;jump if first number is below
BACK: RET ;otherwise return
EXCH: MOV [BX],AL ;Put AL in second address
MOV [BX-1],AH ;put AH in first address
JMP BACK ;then return
ONE_SET ENDP ; end the procedure
END
In the above program, nine numbers (bytes)are stored in the data segment and
sorted. Any number of bytes can be sorted this way , limited only by the maximum value
of N. For sorting in descending order, only one instruction in the procedure need be
changed. After sorting is done,if we write a procedure for converting hexadecimal
numbers to ASCII , the sorted numbers can be displayed as well.
4.2.5.3 Passing parameters through the stack
There may be reasons where the stack, which is an area in memory can be used to store
data . The procedure can take data from the stack for its computation. Ex 4-10 is a simple
example which also elaborates how the register BP is used to access data in the stack.
Here four words which are in the data segment are pushed on to the stack by the main
program. The procedure accesses the data using the indexing features of BP .Remember
that BP is a register associated (by default) with the stack segment ,and that BP cannot
be used without an offset.
Example 4-10 calculates (A+B)—(E+D) where A,B,E and D are words stored in data
memory .The result is also to be saved in the data segment .
Note : We don’t use C as a label because ‘C’ is a reserved word in MASM.
Example 4-10
.MODEL SMALL
.STACK 100H
.DATA
A DW 0987H ;data values in the data segment
B DW 678H
E DW 0A5EH
D DW 0034H
RESULT DW ?
.CODE
.STARTUP
PUSH A ; push to stack
PUSH B
PUSH E
PUSH D
CALL COMPUTE ;call the procedure
MOV RESULT,AX ;save AX in memory
.EXIT
COMPUTE PROC NEAR
MOV BP,SP ; Copy SP to BP
MOV AX,[BP+10] ; move the top most stack value to AX
MOV BX,[BP+8] ;move next word in stack to BX
ADD AX,BX
MOV CX,[BP+6] ;move the next word to CX
MOV DX,[BP+4] ;move the next word to DX
ADD CX,DX
SUB AX,CX
RET 8 ;return and add 8 to SP
COMPUTE ENDP
END
Note the salient features of the program

i) A stack of 100 bytes has been defined in the beginning.
ii) The push instructions are in the main program
iii) In the procedure, the SP value is copied to BP .
iv) The data in the stack is accessed by adding offsets to BP
v) The return instruction is RET 8 . This causes SP to have the value it had
before the four PUSH operations are executed. Otherwise , what would
happen is that each time this program is run , the stack pointer decrements by
8 bytes (for the four PUSH operations ) . Thus the stack size gets reduced by
that much for each procedure call which will finally cause the stack to size to
reduce to zero ,thus causing system crash.
vi) RET 8 adds 8 to SP after returning from the procedure .In effect, it erases the
data that had been pushed on to the stack
Stack Stack
Address content
011F H 09
A
011EH 87
011DH 06 B
011CH 78
011BH 0A E
011AH 5E
0119H 00 D
0118H 34
Fig 4-5: Stack operation for the PUSH and RET 8 instructions
Refer to Fig 4-5.Let’s say that before the first PUSH ,the value of SP=0120H
This figure shows the content of the stack after the four PUSH operations .
The address of SP now is 0118H.
When the CALL is executed, SP=0116 H , because the content of IP is pushed on the
stack .
On returning from the procedure, SP again contains 0118H
RET 8 causes SP=SP+8 =0120H
It is important to be very clear about stack operations if you plan to use the stack .Any
wrong alteration of the stack can cause a system crash.
Stack overflow and underflow
SP can have a maximum value of FFFFH .For each PUSH operation, The SP value
decrements by 2 ,and in the limiting case ,it can go to SP=0000 .
Any PUSH operation beyond this will cause a 'stack overflow' .This creates a condition
when there is no space in the stack for new data.
Stack underflow is the other case when POP operations cause SP to have values beyond
the defined top of stack..
4.3 MACROS
The name of our assembler is ‘Macro assembler’. As such, we see that it is expected to be
able to handle an item called ‘macros’.
What is a macro? It is like an opcode –when used ,it executes .A macro when called by
name, executes the instructions that are listed under that name. Thus essentially , a
macro is a short hand notation for a number of instruction lines. It essentially makes
assembly language coding more readable and helps to avoid repetitive coding.
Usually , a macro, like a procedure, is defined for performing a specific function .But the
‘overheads’ involved in invoking a procedure are not incurred here. A procedure call
causes pushing and popping of addresses/ data in stack .A macro when invoked just
expands the code by putting in all the instructions corresponding to the called macro . It
does not have to ‘call’ and ‘return’. Thus, when we write our code with macros it may
look small ,but when assembling the code each macro is replaced by the full set of
instructions it consists of. Thus we can say that macros execute faster but the assembled
code takes more memory .This is because a procedure is written only once in memory
,but the macro statements are written as part of the code every time the macro is invoked.
4.3.1 Writing a macro.

Whenever we have a set of code lines that we may use frequently, it could be convenient
to make a macro out of it A macro has the format
MACRO NAME MACRO [parameter list]
Instructions(body of the macro)
ENDM
Let’s think of a simple task that could be defined as a macro .

If we frequently want to enter data through the key board, it could be written as a macro.
ENTR MACRO ;the macro for entering a character with echo

MOV AH,01H
INT 21H
ENDM
This macro does not have parameters to be passed to it .

Another similar macro is for displaying a character as shown below
DISP MACRO ; the macro for displaying a character

MOV AH,02H
INT 21H
ENDM
When writing programs using macros, make sure the macros are defined before they are
used. Example 4-11 is a simple illustration of these principles.
Example 4-11
.MODEL TINY
.CODE
.STARTUP
ENTR MACRO ;define the macro for entering a key
MOV AH,01H
INT 21H
ENDM
DISP MACRO ; define the macro for displaying a character

MOV AH,02H
INT 21H
ENDM
ENTR ; invoke macro ENTR

MOV DL,AL ; copy ASCII code of key from AL to DL
DISP ;invoke macro DISP
.EXIT
END
When we run the above program , we get the pressed key displayed twice. Why?
Now let’s define and use a macro using parameters.
DISPLAY MACRO STRINGDAT

MOV AH,09
LEA DX,STRINGDAT
INT 21H
The above is a macro which displays the string whose address is loaded into DX. .The
parameter is ‘STRINGDAT’ .It is also called a dummy variable .When the macro is
invoked ,the actual name of the string to be displayed may be used .Example 4-12
illustrates these ideas.
Example 4-12
.MODEL SMALL
.DATA
MESG1 DB "MY NAME IS ANTONY GONSALVES$"
MESG2 DB "I AM SAMANTHA$"
.CODE
.STARTUP
DISPLAY MACRO STRING ;define a macro for string display
MOV AH,09
LEA DX,STRING
INT 21H
MOV DL,0AH ;DL= ASCII data for newline
MOV AH,02
INT 21H
MOV DL,0DH ;DL=ASCII data for carriage return
MOV AH,02
INT 21H
ENDM
DISPLAY MESG1 ;invoke macro for displaying MESG1

DISPLAY MESG2 ;invoke macro for displaying MESG1
.EXIT
END
In the above program, the DISPLAY macro is first defined .Then the macro is invoked
twice with two different parameters MESG1 and MESG2. Note that the macro not only
displays a string ,but also has instructions for displaying newline and carriage return .This
ensures that after displaying one line, the cursor moves to the left side of the next line.
Thus in Example 4-12, the two messages are displayed on separate lines.
4.3.2 USING THE ‘LOCAL’ DIRECTIVE IN MACROS

Whenever macros use labels, they should be declared as local to the macro .Otherwise if
the same macro is used many times ,they will create assembly errors ,as the label will
correspond to different addresses each time. So , just after the macro name is declared,
the labels must be written preceded by the word ‘LOCAL’. Any number of labels can be
declared in this way .
It would be a good idea for you to examine the list file of the following program to see
how the label ‘AGAIN’ is being managed.
Example 4-13
.MODEL TINY
.CODE
.STARTUP
STAR MACRO N ;define macro STAR with parameter N
LOCAL AGAIN ;declare AGAIN to be a local label
MOV CL,N ;move count to CL
MOV DL,'*' ;move ‘*’ to DL
AGAIN: MOV AH,02 ; AH =2 for displaying a character
INT 21H
DEC CL ;decrement the count
JNZ AGAIN ;repeat the displaying until CL=0
ENDM ;end the macro
NEW MACRO ;define a macro for moving to next line

MOV DL,0AH
MOV AH,02
INT 21H
MOV DL,0DH
MOV AH,02
INT 21H
ENDM
STAR 5 ;invoke macro STAR with N=5

NEW ;invoke macro NEW
STAR 4 :invoke macro STAR with N=4
NEW
STAR 3
NEW
STAR 2
NEW
STAR 1
NEW
.EXIT
END
Example 4-13 shows such a case. Two macros have been defined –STAR and NEW. The
former contains a label AGAIN which has been declared as LOCAL.
This macro causes the character ‘*’ to be printed on a line N times . N is a parameter
whose value is passed to this macro, when called. The macro NEW just moves the
cursor to the left side of the next line. The output of Example 4-13 is as shown below.
*****
****
***
**
*
C:\masm6.14\BIN>
4.4 Number format Conversions

We know that computers do all their calculations using binary arithmetic, but we are
accustomed to doing calculations in decimal form . We see numbers printed out in the
decimal form, and enter data using the keyboard as decimal numbers. Our conclusion
obviously is that through arithmetic data is processed mostly in binary form by
computers, there are methods to convert binary data to forms better suited for display
and understanding. Also ,if we want to process numeric data in a format other than
binary ,that should also be possible.
As such, let us examine some of the number formats frequently used.
Two of the most widely used formats are BCD and ASCII .
BCD is ‘binary coded decimal’ –two versions of which are ‘packed BCD’ and unpacked
BCD . As an example of the former, a decimal number 56 (say) is written as four bit
binary packed in a single byte as 0101 0110 .
Unpacked BCD means using a whole byte to represent a decimal number .For
example,56 is written as two bytes- 0000 0101(5) 0000 0110(6) .
Another popular and very important number format is the ASCII format .It represents a
decimal digit in a byte .Thus 6 is 0011 0110 or 36H The decimal digits from 0 to 9 have
their ASCII representation as 30H ,31H …..39H
Some useful conversions are between the following different number formats.
i) packed BCD to unpacked BCD
ii) unpacked BCD to packed BCD
iii) unpacked BCD to ASCII
iv) Binary to ASCII
v) ASCII to binary
Note: Number format conversions have been discussed in detail in Chapter 0. If you
have doubts regarding such conversions, refer to Section 0.6 .
4.4.1PACKED BCD TO UNPACKED BCD CONVERSION
This has been done in Example 3-24 for a 2 digit packed BCD number. The exact method
of conversion is detailed there along with the example . We will now see how an eight
byte packed BCD is unpacked, converted to ASCII ,and displayed.
In Example 4-14, we see that an eight digit decimal number is represented in packed
BCD such that each decimal digit has a four bit representation. This is stored as a double
word.(four bytes). But when accessing it for processing ,one byte each of this double
word is moved to AL and processed.
The steps are

i) A procedure BCD_TO converts packed BCD to unpacked BCD .
ii) This procedure saves CX and AX as they are used in the procedure.
iii) To convert to ASCII, two unpacked BCD bytes are put in a word and
logically ORed with 3030H.
iv) After the conversion of the 8 bytes is over, we find that the ASCII values are
in memory with the most significant digit in the highest memory pointed by
BX. The instructions from the label STRT onwards are for displaying the
ASCII digits .
Example 4-14
.MODEL SMALL
.DATA
BCD DD 67450823H ;store the 4 byte packed BCD number
ASC DB 8 DUP(?) ;allocate space for 8 byte ASCII number
.CODE
.STARTUP
LEA SI,BCD ;load the offset of BCD in SI
LEA BX,ASC ;load the offset of ASC in BX
MOV CX,4 ;count of BCD bytes
RPT: CALL BCD_TO ;call the conversion procedure
INC SI ; increment pointer
INC BX ; increment pointer
LOOP RPT ;continue until CX=0
;with the above loop, the conversion is
;done and only displaying is left
MOV CX,08 ;count of ASCII bytes
DEC BX ;to point to address of last ASCII digit
STRT: MOV DL,[BX] ;move ASCII value to DL for displaying
MOV AH,02 ;function to display a character
INT 21H
DEC BX ;point to next ASCII digit
LOOP STRT ;repeat until CX=0
.EXIT
BCD_TO PROC NEAR USES CX AX

MOV AL,[SI] ;move first BCD byte to AL
MOV AH,AL ;copy it to AH as well
AND AL,0FH ;mask the upper nibble of AL
AND AH,0F0H ;mask the lower nibble of AH
MOV CL,04 ;count of shift operations
SHR AH,CL ;shift AH 4 times
OR AX,3030H ;convert AX to two ASCII bytes
MOV [BX],AL ;move one ASCII value to memory
INC BX ;BX to point to next locations
MOV [BX],AH ;store the next digit
RET
BCD_TO ENDP
END
Converting from ASCII to packed BCD is just a reverse of all these processes .
4.4.2 BCD CALCULATIONS
i) ADDITION
DAA –Decimal adjust AL after addition
Usage :DAA
For BCD ,none of the digits should have a value greater than 9 ,but we know that a
nibble can contain a value of 0FH .This causes problems when BCD numbers are added.
To sort out this problem ,there is a specific instruction DAA which stands for ‘Decimal
Adjust Accumulator’. This assumes that the sum of the BCD addition is in AL.
The need for this instruction is because direct addition of BCD numbers causes
errors ,and a correction is usually needed .The exact details of this and the correction
done is discussed in Section 0.7.2 .
Now see the following example which adds two multibyte BCD numbers ,to get the
result in BCD itself ..The two BCD numbers are stored as double words (DD)
Note that when they are stored thus, the lowest byte of the number will be in the lowest
address .Now BX and SI point to the BCD numbers to be added. For adding , only one
byte each of the numbers is accessed and added. The sum is stored in the byte location
SUM .Here too ,the LSB of the sum will be in the lowest address.
Example 4-15
.MODEL SMALL
.DATA
BCD1 DD 45679834H ;store the first BCD byte as a double word
BCD2 DD 93870989H ;store the second BCD byte as double word
SUM DB 5 DUP(0) ;allocate 5 byte memory for the sum
.CODE
.STARTUP
MOV AH,0 ;clear AH
CLC ;clear carry flag
LEA BX,BCD1 ;BX to point to first BCD byte
LEA SI,BCD2 ;SI to point to second BCD byte
LEA DI,SUM ;DI to point to SUM location
MOV CX,04 ;count for the number of bytes
RPT: MOV AL,[BX] ;copy the bytes of the first number to AL
MOV DL,[SI] ; copy the bytes of the first number to AL
ADC AL,DL ;add with carry AL and DL
DAA ;do the BCD correction
MOV [DI],AL ;store the result of each byte addition
INC BX ;increment pointer BX
INC SI ; increment pointer SI
INC DI ; increment pointer DI
LOOP RPT ;loop until CX=0
ADC AH,0 ;add carry ,AH and 0;sum in AH
MOV [DI],AH ;store AH in memory
.EXIT
END
On adding 4 BCD bytes ,there is a possibility of a carry ,which corresponds to the 5th
BCD byte of the sum. To preserve this final carry ,AH register is used as shown .The sum
of the given two numbers is 0139559823 .
i) SUBTRACTION
DAS –Decimal adjust AL after subtraction
Usage: DAS
For BCD subtraction ,there is an instruction DAS which operates on the data in AL The
use of this instruction is left to you .
4.5 ASCII OPERATIONS

The processor has a number of instructions relating to the processing of ASCII numbers.
4.5.1 ASCII ADDITION
AAA
This instruction is used after addition of two ASCII numbers.
It checks the lower nibble of AL for one of the two conditions
i) whether it is within A and F or
ii) whether the auxiliary carry flag (AF) is set .
Depending on this ,it performs the required corrections. See the three cases shown .
.Add ‘5’ and ‘4’ ,get the sum in AL

Case I
35 H
34 H
6 9H
In this case the lower nibble is not within A and F, and the AC flag is not set i.e.AF=0.
Then the instruction just resorts to making the upper nibble of AL to 0.
Thus if the AAA instruction is used after the addition ,
The sum becomes 09 i.e. 0000 1001.To convert it back to ASCII ,OR it with 30H
MOV AL,’5’ ;AL=35H
ADD AL,’4’ ;AL=35H+34H =69H
AAA ;AL=09H
OR AL,30H ;AL=39H,the ASCII value of 9
We get 39H in AL which is the ASCII code of 9 .Also AH=0 .
Case 2
Add ‘7’ and ‘6’ , get the sum in AL
37 H +
36 H
6D H
In this case , the rightmost nibble is greater than 9 i.e. within A and F-
–i.e.it is no longer representing a decimal digit. Hence 6 is added to the rightmost nibble
(like in BCD correction- The number 6 is added because that is the difference between
decimal and hexadecimal ) ,it also clears the upper nibble of AL, sets CF and AF ,and
adds 1 to AH.
Thus if the AAA instruction is used after the addition ,
The sum in AL is now 03 and AH=01 (if AH had been cleared earlier).
When the AAA instruction is used after this ,it makes the lower nibble 0003 and adds 1
to AH and also sets the carry flag.
MOV AL,'7' ;AL=37H
ADD AL,'6' ;AL=37H + 36H =6DH
AAA ;AL=03 ,AH=01 ,CF=1
OR AX,3030H ;AX=3133
The AX register will contain 3133H after this ,which is the ASCII value of 13.
These facts must be taken into consideration when adding multibyte ASCII numbers.
Case 3
Add ‘9’and ‘8’ , get the sum in AL
39H +
38H
71H
.
Here the rightmost nibble is not within A and F ,but AF=1 .
Hence 6 is added to the rightmost nibble and ,it also clears the upper nibble of AL, sets
CF and AF ,and adds 1 to AH.
Thus if the AAA instruction is used after the addition ,AL=7 ,AH=1 ,CF=1 and AF=1
In all cases, AAA clears the upper nibble of AL.
These facts must be taken into consideration when adding multibyte ASCII numbers.
4.5.2 ASCII SUBTRACTION
AAS – ASCII adjust AL after subtraction.
Usage :AAS
This functions similar to the AAA instruction ,After the subtraction of two ASCII
numbers ,AAS checks the lower nibble of AL .If this number has a value between A and
F ,or if the AF flag is set , 6 is subtracted from AL Also 1 is subtracted from AH and AF
and CF are set . In all cases, the upper nibble of AL is cleared.
Case 1
Subtract ‘5’ from ‘8’.
38H –
35 H
03
If AAS is used after this subtraction , the content AL of remains 03 itself .
Case 2
Subtract ‘8’ from ‘5’ .
35H –
38 H
FD H
After AAS ,,AH =FFH ,AL =07 .
Actually the answer should be -3 . but we get
. FF07 ,which is the ten’s complement
-10 +3 =7 .
Let us subtract ‘4’ from ‘15’ .We get the ASCII value of ‘11’ in the AX register with the
following program.
MOV AX,'15' ;AX=3135H
SUB AX,'4' ;AX=3101H
AAS ;AX=3101H
OR AX,3030H ;AX=3131H
Now ,it is up to you to find out what happens when ‘9’ is subtracted from ‘4’.
Also ,note that the instructions AAA and AAS can be used after adding or subtracting
unpacked BCD numbers as well,
4.5.3 MULTIPLICATION AND DIVISION

i)AAM –ASCII adjust AX after multiplication
Usage: AAM
For multiplication and division of ASCII numbers, we need to convert them to unpacked
BCD .
Let us deal with ASCII multiplication first.
In the following program ,the numbers to be multiplied are 6 and 9. The product has to be
54. The ASCII numbers are first unpacked, and multiplied .After that, the AAM
instruction is used. This causes the product to be in the unpacked BCD format
. If the result of multiplication (MUL BL) is compared with the result of AAM ,it is
obvious that AAM accomplishes the conversion by dividing AX by 10.Following this, if
ORing with 3030H is done, the ASCII value of the product is available in AX. In the
program, this value is copied to CX, and displayed using the DISP macro. Note that the
most significant digit is displayed first.
Example 4-16
.MODEL TINY
.CODE
.STARTUP
DISP MACRO ;define macro for display
MOV AH,02
INT 21H
ENDM ;end of macro
MOV AL,'6' ;AL=36H
AND AL,0FH ;AL=06H
MOV BL,'9' ;BL=39H
AND BL,0FH ;BL=09H
MUL BL ;AX=0036H;decimal value is 54
AAM ;AX=0504H ,the unpacked BCD of 54
OR AX,3030H ; AX=3534H ,the ASCII value of 54
MOV CX,AX ;copy AX to CX
MOV DL,CH ;DL=CH to display the MSD
DISP ;call macro for display
MOV DL,CL ;DL=CL to display the LSD
DISP ;call macro for display
.EXIT
END
ii)AAD –ASCII adjust AX before division

Usage: AAD
This instruction works by converting the packed BCD in AX to binary (hex)before
division. It multiplies AH by 10,adds the product to AL and clears AH .This is the
hex representation of the BCD number in AX. After division , we find the quotient in
AL and the remainder in AH.
See the following program segment
MOV AX,'82' ;AX=3832H

AND AX,0F0FH ;AX=0802H
AAD ;AX=0052H ,the hex value of the dividend
MOV BL,'9' ;BL=39H ,the ASCII value of 9
AND BL,0FH ;BL=09H
DIV BL ;AX=0109H, the quotient in AL, remainder in AH
OR AX,3030H ; AX=3139H ,the corresponding ASCII values
4.6 CONVERSIONS FOR COMPUTATIONS AND DISPLAY/ENTRY
We have seen various number formats so far ,but by now it should be obvious that using
BCD and ASCII numbers for computation is cumbersome, especially when large
numbers are involved.. A more convenient format for all arithmetic calculations is the
binary format ,which is compactly written in hexadecimal. Another point is that, once the
computation is done the natural format for display is the ASCII format. For displaying
,we convert the binary number to unpacked BCD and then to ASCII .When entering data
through the keyboard also ,the ASCII number format is used.
All this implies the necessity of converting binary numbers to ASCII and vice versa.
4.6.1CONVERTING ASCII NUMBERS TO BINARY FORM
Let us see how we convert a decimal number( say 6754) to binary form.
6754= 6 x1000 +7 x100 + 5 x 10 + 4 x1
i.e. 4 x1 =4 +
5 x10 =50 +
7 x 100=700 +
6 x 1000 =6000
6754
This is the algorithm to be used for conversion.. Let us write a program which does this.
Here the multiplicands 1,10,100 and 1000 are stored in the data segment. The binary
value also is finally stored in data memory .
Example 4-17
.MODEL SMALL
.DATA
ASCDAT DB '6754' ;ASCII value of 6754
MULTI DW 01,0AH,64H,3E8H
BINAR DW 0
.CODE
.STARTUP
DIG EQU 4 ;DIG specifies the number of digits
MOV CX,DIG ;move into CX the number of digits
MOV DI,DIG-1 ;DI to point to LSD of the ASCII no.
LEA SI,MULTI ;use SI to point to the multiplicands
RPT: MOV AL,ASCDAT[DI] ;bring first ASCII data to AL
AND AX,000FH ;mask AX
MOV BX,WORD PTR[SI] ; get the multiplicand to BX
MUL BX ;multiply AX by BX
ADD BINAR,AX ; add to binary value
DEC DI ; decrement byte pointer
INC SI ; increment word pointer
INC SI ; two increments required
LOOP RPT ;repeat until CX=0
.EXIT
END
The above program is a direct application of the algorithm mentioned .

We get the converted binary value in the word location BINAR. We can extend this for
more number of digits too .
4.6.2 CONVERTING BINARY NUMBERS TO ASCII FORM
The method for this is repetitive division .This has been done in Example 3-21 for a 16
bit binary number.
4.7 SIGNED NUMBER ARITHMETIC
In all our discussions and problems ,whenever we dealt with numbers ,we assumed the
numbers to be unsigned . Now let us bring signed numbers also into our domain .
Negative numbers are represented in the two’s complement format . When the data length
is one byte ,the maximum value of decimal numbers it can represent is -128 to +127
.With 16 bits this is from -32,768 to +32,767. If the result of any operation exceeds this
word size, the overflow flag is set. This indicates that our result has to be re-interpreted
and corrected.
. The conditions under which the overflow flag is set can be stated as
i) When there is a carry from D6 to D7 ,or a carry from D7 outwards, but not
both .This is for byte operations.
ii) For word operations, when there is a carry from bit D14 to D15 ,or a carry
from D15 outwards, but not both .
Let us see a few cases of signed number operations.
Example 4-18
.MODEL TINY
.CODE
.STARTUP
MOV AL,+34
ADD AL,-23
.EXIT
END
For the above program in which +34(22H) and -23(E9H) are decimal numbers the
calculation in binary form is
0010 0010 +
1110 1001
1 0000 1011
Thus the sum is 0BH which is the right sum. CF=1,OV=0,SF=0
Example 4-19
.MODEL TINY
.CODE
.STARTUP
MOV AL,-28 ; AL=E4H
ADD AL,-78 ;AL=B2H
.EXIT
END
The computation of this

1110 0100 +
1011 0010
1 1001 0110
OF=0 ,SF=1,CF=1
The answer of this computation is 96H (-106) which is correct .
In both the above problems ,the overflow flag is found cleared which indicates that the
signed number computation has produced the right result.
Now ,see the next program
Example 4-20
.MODEL TINY
.CODE
.STARTUP
MOV AL,+100
ADD AL,+75
.EXIT
END
0110 0100 (64H)

0100 1010 (4BH)
1010 1110 (AFH OF=1 ,SF=1.CF=0
In the above case ,the overflow flag will be set because there has been an overflow from
bit D6 to D7 ,and the sign bit is set .Even though two positive numbers have been added
,the sign bit indicates a negative sum . Thus AFH has to be thought of as a negative
number, which is not correct. The problem is that the sum is +175 which is too large to fit
in an 8 bit register. Since the overflow flag is set ,it indicates that the register AL has
overflowed the size allotted for signed operations in 8 bit format.
Understanding that the problem that has caused the error is one of inadequacy of the
size of the destination ,it can be solved by extending the bit size of the operands. This can
be done by sign extending a byte to a word and a word to a double word.
The 8086 has two specific instructions for it.
i) CBW convert byte to word
This instruction works on the data in AL. It copies the sign bit (D7) of AL to all the bits
of AH ,Thus the byte in AL is extended to a word in AX.
ii) CWD -convert word to double word
This instruction works on the data in AX. It copies the sign bit (D15) of AX to all the bits
of DX .Thus DX-AX is the new double word .
Let us now use these instructions to avoid overflow in the case of signed number
operations.
Example 4-21
.MODEL TINY
.CODE
.STARTUP
MOV AL,+100
CBW
ADD AX,+75
.EXIT
END
The computation is as follows

0000 0000 0110 0100 +
0000 0000 0100 1010
0000 0000 1010 1110 Now OF=0,SF=0 ,CF=0
In this case ,the overflow flag is not set and hence the sum in AX is considered to be
correct. The sign bit also indicates a positive number..
Note: In a general case ,we are not sure if the result of adding/subtracting signed
numbers will exceed the register size allowed for it . To accommodate for a correction as
in Example 4-21 ,the instruction JO (Jump on overflow) can be used . The program can
be written in a way that after the addition or subtraction (as the case may be)operation,
the JO instruction tests the overflow flag and the CBW or CWD instruction is used only
if the overflow flag is found to be set. Then re-computation using the extended word or
double word can be done.
4.7.1 COMPARISON OF SIGNED NUMBERS

Comparison of two unsigned numbers is based on their numerical value only ,and the
sign does not come into the picture .For example, 7 is above 3 numerically .But when
these numbers are signed ,the picture changes .Think of the numbers -7 and -3 .We now
say that -3 is greater than -7 . With this picture, we use the terms ‘above ‘ and ‘below’ for
unsigned numbers ,and ‘greater than’ and ‘less than’ for signed numbers. The
mnemonics used and the flags used also are different.
In chapter 3, Table 3-2 lists out a number of conditional jump instructions, catering to
unsigned number operations. Now ,let us have a look at the jump instructions for signed
number operations. See Table 4-2
Sl No Mnemonic What it means Conditions tested

1 JE Jump if Equal ZF=1
2 JG Jump if Greater ZF=0 and SF=OF
3 JGE Jump if Greater or Equal SF=OF or ZF=1
4 JL Jump if Less SF != OF
5 JLE Jump if Less or Equal ZF=1 or SF != OF

6 JNG Jump if Not Greater ZF=1 or SF != OF
7 JNGE Jump if Not Greater Nor Equal SF != OF
8 JNL Jump if Not Less SF=OF
9 JNLE Jump if Not Less Nor Equal ZF=0 and SF=OF
10 JNO Jump if No Overflow OF=0

11 JO Jump if Overflow OF=1
11 JNS Jump if Not Signed SF=0
12 JS Jump if Signed SF=1
Note: The mnemonics JE/JZ and JNE/JNZ are applicable for both signed and unsigned
numbers and the condition of the Zero flag being set or reset accordingly applies here as
well.
Table 4- 2 : Conditional Jump instructions catering to signed numbers
The list in Table 4.2 shows the conditions of the sign ,overflow and zero flags and
undoubtedly causes a certain amount of confusion. Let us test a program for the various
situations possible and check the condition of these flags.
Example 4-21
.MODEL TINY
.CODE
.STARTUP
MOV AL, +40
CMP AL,-60 ;after this ,OF=0,SF=0
CMP AL,+70 ;after this ,OF=0,SF=1
MOV BL,-20 ;BL=-20
CMP BL,-70 ; after this , OF=0,SF=0
CMP BL,-10 ; after this , OF=0,SF=1
CMP BL,+10 ; after this , OF=0,SF=1
CMP BL,-20 ; after this , OF=0,SF=0,ZF=1
.EXIT
END
The result of each comparison of the above program will help to clear the confusion .
i) When the destination is greater than the source , OF=SF
ii) When the destination is less than the source, OF !=SF
iii) When the destination is equal to the source ,ZF=1
Example 4-22 finds the smallest of three signed numbers and stores it in a memory
location. It compares the first number with the second number .If the first number is less
,it is compared with the third number .Otherwise the second number is compared with the
third number and finally the smallest number is identified and stored in memory .In this
case, the negative number -90 is found to be the smallest number.
Example 4-22
.MODEL SMALL
.DATA
NUMS DB +45,-76,-90
SMALLEST DB 0
.CODE
.STARTUP
LEA BX,NUMS ;use BX as pointer to the numbers
MOV AL,[BX] ;get the first number in AL
CMP AL,[BX] ;compare the first number with the second
JLE NEXT ;if AL is less than or equal ,jump
MOV AL,[BX] ;otherwise ,the second no is loaded in AL
NEXT: INC BX ;increment the pointer
CMP AL,[BX] ;compare the second no with the third
JLE FINAL ;if the first no is less, jump
MOV AL,[BX] ;move the smallest number to AL
FINAL : MOV SMALLEST,AL ; store the smallest number in memory
.EXIT
END
4.7.2 SIGNED MULTIPLICATION AND DIVISION
There are two instructions to be used for signed multiplication and division .
i) IMUL
All that was discussed about the MUL instruction (Section 3.4.4)holds good in the case of
IMUL too .The only difference is that since the operands are signed, the product also is
signed.. Another point is that when the product is not large enough to use all the registers
allocated for it, the sign bit is copied to the upper register (AH or DX as the case may be)
and CF=OF=0.
ii) IDIV
The signed division operation is similar to unsigned division ,as discussed in Section
3.4.5 ,except that the operands and result are signed .Because of this, if the quotient
register is AL ,the value of the quotient is to be between -128 and +127 .If the quotient
register is to be AX, this value is to be between – 32,768 and +32,767. If this is violated,
a ‘divide overflow’ error message is displayed on the screen.
Now let us use the signed multiply and divide instructions in a program.
Let us compute (XY—Z2 )/ L and store the quotient alone. The values of X, Y ,Z and
L are put in the data segment as shown in the program .
For multiplication ,a procedure named MULT is defined and used.
Example 4-23
.MODEL SMALL
.DATA
X DB -6
Y DB 25
Z DB 19
L DB -9
QUO DB ?
.CODE
.STARTUP
MOV AL,X ;copy X to AL

MOV BL,Y ;copy Y to BL
CALL MULT ; call the procedure to multiply X and Y
MOV CX,AX ;copy the product to CX
MOV AL,Z ;copy Z to AL
MOV BL,AL ;copy Z to BL as well
CALL MULT ;call the procedure to get Z2
SUB CX,AX ; compute XY—Z2
XCHG CX,AX ;exchange CX AX, to get the dividend in AX
IDIV L ;signed division by L
MOV QUO,AL ;copy the quotient to memory
.EXIT
MULT PROC NEAR ;define the MULT procedure

IMUL BL ;multiply AL by BL ,product in AX
RET ;return to calling program
MULT ENDP ;end the procedure
END
In this program , positive as well as negative numbers are the operands .Let us make a
few observations.
i) With the values of X,Y , Z and L as given in the program , the product is -511
(FE01H) and the quotient is +56 ,which is found in AL as 38H.
ii) If the divisor is now changed to +9 ,the quotient is -56 ,which is found in AL
as C8H .
iii) If the divisor is changed to -3, we get a message divide overflow error and
the program execution is terminated .This is because the quotient (+170) is
too large to fit in AL .Remember that the largest positive number that AL can
hold is +127 only.
4.7.4 ARITHMETIC SHIFT

A shift operation which makes a difference in the result depending on the sign of the
operand is arithmetic shifting. There are two instructions pertaining to this .
i) SAR destination ,count -Shift right arithmetic

This is similar to the shift right logical (SHR ) discussion in Section 3.5.2 ,but here
when shifting right, the sign bit is filled into the MSB. This instruction can be used to
divide a signed number by 2 ,for one shifting each .
MOV BL, -24 ;AL = 1110 1000

SAR BL,1 ; AL =1111 0100 , which is -12
ii) SAL destination ,count -Shift left arithmetic
This is the same as shift left logical (SHL) .As shifting left does not involve any sign bit
,logical and arithmetic shifting are the same. The two mnemonics(SAL and SHL) mean
the same and can be used interchangeably .
4.8 PROGRAMMING USING HIGH LEVEL LANGUAGE CONSTRUCTS

MASM has become easier and very convenient to use ever since it was appended with a
number of high level language constructs. Such constructs are available only for
MASM 6.0 and higher versions ..They are designated as ‘dot commands’ as they are
preceded by a dot .These constructs make MASM a ‘high level assembler’. A few of
these constructs are listed below
i) IF, ELSEIF and ELSE…..ENDIF
ii) REPEAT …UNTIL….ENDW
iii) REPEAT …WHILE ….ENDW
iv) BREAK
v) CONTINUE
vi) REPEAT …..UNTILCXZ
Except the last one, these constructs function as they do in a high level language (e.g.
C,C++) . For the last construct ,the loop repeats until register CX=0 .
Now we will endeavor to use these constructs in a few interesting programs.
Example 4-24 is a simple program which takes in data through the keyboard (without
echo) and verifies three conditions.
i) Is the value of the number within 0 and 5?
ii) Is the value of the number within 6 and 9?
iii) Is the key pressed ‘not a number’?
These three questions are resolved using IF, ELSEIF and ELSE statements and
appropriate messages are displayed. The symbol ‘&&” is used for ‘and’ just as in a high
level language.
Example 4-24a
.MODEL SMALL
.DATA
FIRST DB "THE VALUE IS WITHIN 0 AND 5$"
SECOND DB "THE VALUE IS WITHIN 6 AND 9$"
OTHER DB "NOT A NUMBER$"
.CODE
.STARTUP
MOV AH,08 ;read in key without echo

INT 21H
.IF AL>='0' && AL<='5' ;first IF condition
LEA DX,FIRST ;display the first message
MOV AH,09
INT 21H
.ELSEIF AL >='6' && AL<='9' ;second IF condition
LEA DX,SECOND ;display the second message
MOV AH,09
INT 21H
.ELSE ;ELSE
LEA DX,OTHER ;display the third message
MOV AH,09
INT 21H
.ENDIF
.EXIT
END
Let us see what exactly these high level language constructs are .Obviously ,they get
converted to assembly language statements .We use the .LISTALL directive to find out.
Example 4-24b shows the listing for the code segment alone up to the .ENDIF statement.
We find the equivalent assembly code for the high level language constructs ,which in
this case are compare and jump instructions.
Example 4-24b
0017 B4 08 MOV AH,08

0019 CD 21 INT 21H
.IF AL>='0' && AL<='5'
001B 3C 30 * cmp al, '0'
001D 72 0E * jb @C0001
001F 3C 35 * cmp al, '5'
0021 77 0A * ja @C0001
0023 8D 16 0000 R LEA DX,FIRST
0027 B4 09 MOV AH,09
0029 CD 21 INT 21H
.ELSEIF AL >='6' && AL<='9'
002B EB 1A * jmp @C0004
002D *@C0001:
002D 3C 36 * cmp al, '6'
002F 72 0E * jb @C0005
0031 3C 39 * cmp al, '9'
0033 77 0A * ja @C0005
0035 8D 16 001D R LEA DX,SECOND
0039 B4 09 MOV AH,09
003B CD 21 INT 21H
.ELSE
003D EB 08 * jmp @C0008
003F *@C0005:
003F 8D 16 003A R LEA DX,OTHER
0043 B4 09 MOV AH,09
0045 CD 21 INT 21H
.ENDIF
Next we will do a program using the REPEAT…. WHILE construct.

Example 4-25 shows how the .WHILE statement is used to repeat execution of a loop
while a condition is satisfied, and to exit the loop when the condition no longer holds.
As long as CX is not equal to zero ,the loop repeats .The end of the loop is specified with
a .ENDW construct. In this program ,a string consisting of all the letters of the alphabet,
stored in location starting from DAT is to be reversed and displayed .After the reversed
string is stored in location DAT1 onwards, it is appended with a ‘$’ so that it can be
displayed with DOS INT 21H function number 9. Before the reversed string is displayed,
the message REVERSED STRING: is first displayed.
Example 4-25
.MODEL SMALL
.DATA
DAT DB 'ABCDEFGHIJKLMNOPQRSTUVWXYZ$'
MES1 DB 0DH,0AH,'REVERSED STRING: $'
DAT1 DB 27 DUP(?)
.CODE
.STARTUP
MOV BX,OFFSET DAT+25 ;address end of DAT
MOV SI,OFFSET DAT1 ;address DAT1
.WHILE CX!=0 ;loop while CX!=0
MOV AL,BYTE PTR[BX] ;move byte to AL
MOV BYTE PTR[SI],AL ;save AL in DAT1
INC SI
DEC BX
DEC CX
.ENDW ;end of while loop
MOV BYTE PTR[SI+1],'$' ;append string with $
MOV DX,OFFSET MES1
MOV AH,09
INT 21H
MOV DX,OFFSET DAT1 ;display the reversed string
MOV AH,09
INT 21H
.EXIT
END
The output of the above program is as shown below.

REVERSED STRING: ZYXWVUTSRQPONMLKJIHGFEDCBA
C:\masm6.14\BIN>
For both the above problems ,the high level language constructs are written indented to
the left. This is done only to improve the readability of the program.
The above problem can be worked out using the REPEAT ….UNTIL construct. The
loop is repeated until CX==0 .CX becoming zero is the stopping condition for the loop.
There is also a .UNTILCXZ construct available that can be used in this example .The
.UNTILCXZ instruction uses the CX register as a counter to repeat a loop a fixed number
of times. This example can be rewritten using a .REPEAT .....UNTILCXZ loop also .
Now let us see a case of nested loops. Example 4-26 shows the case of an IF loop nested
within a repeat-until loop. In this , a character is to be searched within a string and the
number of occurances of that character in the string is to be found out. To make the
program inter-active for the user, messages asking for the character and the string are
displayed using DOS INT 21H function 9. Both the character and the string are entered
through the keyboard. The string is terminated when the ‘enter’ key is pressed. This
corresponds to the ‘carriage return’ character 0DH and this is the termination condition
of the repeat ..until loop.
Example 4.26
.MODEL SMALL
.DATA
MES1 DB 0DH,0AH,'ENTER THE CHARACTER: $'

MES2 DB 0DH,0AH,'ENTER THE STRING: $'
MES3 DB 0DH,0AH,'NUMBER OF OCCURENCES: $'
STRING DB 50 DUP('?')
.CODE
.STARTUP
MOV DX,OFFSET MES1 ;address MES1

MOV AH,09H ;display message
INT 21H ; for the character
MOV AH,01H
INT 21H ;enter character
MOV BL,AL ;copy character to BL
MOV DX,OFFSET MES2 ;address MES2
MOV AH,09H ;display message
INT 21H ;for entering string
MOV CL,0 ;initialize counter
.REPEAT ;repeat loop
MOV AH,01H ;enter string, one character
INT 21H ;at a time
.IF (AL==BL) ;compare with reference
INC CL ;if matching ,increment CL
.ENDIF ;end IF loop
.UNTIL AL==0DH ;exit when ‘enter’ is pressed
ADD CL,30H ;convert to ASCII
MOV DX,OFFSET MES3 ;address MES3 location
MOV AH,09H
INT 21H ;display message
MOV DL,CL ;move count to DL
MOV AH,06H ;display the count
INT 21H
.EXIT
END
The output of the Example 4-26 for a character ‘t’ and string entered through the
keyboard is shown below..
ENTER THE CHARACTER: t

ENTER THE STRING: tyu8iolhttttfeerttt
NUMBER OF OCCURENCES: 8
C:\masm6.14\BIN>
Now that we have seen the use of the high level language constructs ,it is obvious that
many of our previous programs can be re-written using these constructs .

• String instructions are used to simplify coding when bulk data is moved, scanned,
compared etc.
• Then , SI and DI registers are used as pointers to the data segment and extra
segment, and the direction flag is used for auto increment/.decrement .
• The conditional/unconditional REP prefix is used for repetitive string operations.
• Procedures are subprograms which are ‘called’ by the main program for
performing specialized operations.
• Procedures may be intra-segment or inter-segment and this is clarified when
defining a procedure, by using the ‘near’ or ‘far’ prefix.
• Parameters to and from procedures may be passed via registers, memory or stack.
• Macros are functionally similar to procedures ,but act in a different way
• Number format conversions are necessary as BCD ,ASCII and binary numbers are
used frequently.
• 8086 has specialized instructions for handling ASCII and BCD number operations
• Signed number arithmetic involves the use of special instructions.
• The overflow flag is very important in signed operations
• The high level language constructs of MASM has made assembly language
programming easier.
QUIZ
i) What is the role of the direction flag in string instructions?
ii) What is the difference in the functioning of the instructions STD and CLD ?
iii) How does the instruction CLD function in the case of the following two
instructions?
REPMOVSB
REP MOVSW
iv) Which is the pointer register to be used when using the extra
segment in string operations?
v) Why does the LODS instruction not use the REP prefix?
vi) Do the following instructions function differently? In what way?
1. REPNE CMPSB
2. REPE CMPSB
vii) For REPNZ CMPSB ,what are the conditions under which looping is
exited?
viii) Distinguish between a near and a far call.
ix) What is the difference in the functioning of the RET and RET n instructions?
x) What is meant by the term ‘parameter passing’ in the context of procedures.
xi) What is the benefit of using macros?
xii) Compare procedures and macros.
xiii) How are local variables in a macro taken care of?
xiv) What is a dummy argument?
xv) Explain how the DAA instruction functions
xvi) Explain the action of the following instructions-AAM ,AAS,AAD and AAM.
xvii) Write down the steps required for the following conversions.
a. binary to ASCII
b. ASCII to binary
xviii) When is the CWD instruction used?
xix) Is it justified to call MASM A high level assembler?
EXERCISE
1. Write a program to move 100 words from ‘FROM’ to ‘TO’ which are ,two
areas in the data segment separated by a 200 byte space.
2. Write a program to scan the name SAHABUDDIN and replace S by B and B by
H.
3. Store a password in memory .Enter another password through the keyboard and
verify if it matches the stored password. The password entered should not be
displayed .as such, but each letter should be displayed as ‘*’.
4. Write a string program for an application which requires the pointer registers to
be auto decremented.
5. Write a program to search for a word in a block of N words.
6. Write a program which contains the following macros:

a)For calculating the Fibonacci series for N
b)For entering the value of N
c)For displaying the numbers.
7. Do the above problem using procedures.
8. Display the factorial of three numbers .Solve the problem using macros as well
as procedures..
9. Obtain the list file of the above program in both cases and observe the differences.
10. Enter a string of characters through the keyboard. Save it in memory. Verify
if the string is a palindrome.
11. Using macros/ procedures write a program to add 2 BCD numbers entered
through the keyboard and display their sum.
12. Write a program where nested macros are used.
13. There are 16 ASCII numbers stored in consecutive locations in memory .
Convert this to an eight bit packed BCD number.
14. Write a program to add two ten byte BCD numbers. The sum is to be
displayed.
15. Two BCD numbers 4093H and 2986H are stored in memory. Subtract the
second number from the first. Use the DAS instruction.
16. Two ASCII numbers ‘5678’ and ‘3498’ are to be added and displayed.
Write a program for it.
17. Divide ‘90’ by ‘9’ .Use AAD and necessary programming steps.
18. Divide ‘3476’ by ‘5’.Display the quotient alone.
19. Use AAM to help in converting a 16 bit binary number in AX to a four digit
ASCII character. HINT: Divide the content of AX-DX by 100 ,then use
AAM.
20. Write a program which checks the number of ASCII digits present in the
given number ,and converts it to the corresponding binary equivalent.
21. It is needed to convert binary numbers to ASCII format for display .Write a
program for this .with the following features.
a)First the program must check if the given number is less than 10 .If so,
b)It displays this number directly
c)The converted ASCII numbers should be in memory
d)A procedure named DISPLAA should take these numbers from memory and
display them.
22. There are 10 signed bytes stored in memory ,some of which are negative and
some of which are positive. Find the largest number of the lot.
23. Re-write Example 4-25 using REPEAT …UNTIL and REPEAT
…UNTILCXZ constructs.
.
24. Re-write Example 4-26 using .CONTINUE and .BREAK constructs along
with .IF and .REPEAT constructs.
.
CHAPTER 6
THE HARDWARE STRUCTURE OF 8086
OBJECTIVES
• The differences between 8086 and 8088.
• The pin functions of 8086 in the minimum and maximum modes.
• The use of address latches and data buffers in an 8086 based system.
• The concept of machine cycles and the associated bus timings of 8086.
• The reason for using the bus controller IC is used in a maximum mode system.
• How an 8086 is used in the maximum mode.
• To calculate instruction timing and thus create delay loops.
Upto now, we were dealing exclusively with the programming aspects of 8086 . It is time
now to take a look into the hardware aspects of the processor.
6.1 PIN CONFIGURATION
Now ,we will try to understand the processor in terms of its hardware ,which include the
pin configuration ,functions of the pins , memory bus cycles , connections to other chips
,modes of operations and so on .
Fig 6.1 a) 8088 CPU pin diagram b) 8086 CPU pin diagram
It was mentioned in Chapter 0 that the first PC was built with the 8088 processor. This
processor is in most ways exactly the same as the 8086
The minor differences are as listed
i) 8088 has an external data bus of 8 bits ,while 8086 has a 16 bit data bus.
ii) The instruction queue of 8088 is 4 bytes ,while 8086 has a 6 byte queue.
iii) For 8088, pin NO: 28 (in minimum mode)is an M / IO pin ,while for
8086 ,the polarity of the pin is M / IO .
iv) Pin No 34 is SSO for 8088 , while it is BHE / S 7 for 8086.
The pin diagrams of both these processors are given in Fig 6-1. We see that both these
processors are packaged as 40 pin DIP (dual-in-line package).
It is also seen that some pins have dual functions ,and this corresponds to two modes of
operation –i.e. minimum and maximum modes. The minimum mode is used when the
8086/8088 is used in uniprocessor systems ,and the maximum mode is when the system
is a multi processor system ,in which the 8086/8088 is one of the processors.
Now ,neither 8086 nor 8088 is used in PCs ,because of the advent of the advanced
processors of the same family .However ,we will discuss the hardware aspects of 8086
,because it is the basic processor in the x86 family ,and the features of the advanced
processors are upward extensions of the 8086 features. As such ,understanding the
features of 8086 is very fundamental to the understanding of the advanced processors of
the x86 family.
6.1.1 Minimum Mode Pins

Let us discuss the minimum mode operation of 8086 .In Fig 6.1b, pins 24 to 31 are seen
to have dual functions and the functions in brackets is the pin designation in the
minimum mode ,for those pins. The chip with minimum mode pin designations is re-
drawn in Fig6. 2.
For minimum mode operation ,pin No.33 MN / MX should be at logic high..
Fig 6-2 8086 pins in the minimum mode
It was mentioned earlier that 8086 has a 16 bit data bus and a 20 bit address bus .Let us
locate the address and data pins, in the pin diagram. We see a set of 16 pins designated as
AD –i.e.AD0-AD15 .These are the address/data pins .The notation ‘AD’ means that
these pins are used for address as well as data. They are multiplexed for data and address
,which means that at a particular time they carry address ,and at other times they carry
data. The reason for having multiplexed pins was the necessity to reduce the number of
pins of the chip, and this restriction was more stringent in the early days of
microprocessor development..Remember that 8086 has only a total pin count of 40.
But, since the data bus and address bus have to be separate and because the
‘address’ has to be available at all times , the address-data lines have to be ‘de-
multiplexed ’.i.e. separated .This is done by the use of latches ,also availing the timing
features of bus cycles
6.1.2 De-multiplexing the address/data bus
Let us assume that memory is to be read or written to ..Recollect the sequence of
steps for reading and writing memory (Section 0..7) The first step in (say) reading
memory is ‘placing the address on the address bus’. This is ,in practice ,the first part of
the bus cycle . Next, the data is to appear on the data bus , which means that the bus
must be made free to carry data.. For de-multiplexing ,during the time that the address is
on the address /data bus ,it is latched on to a ‘latch IC’ whose clock is the ALE (Address
Latch Enable) signal supplied by 8086 .The signal ALE goes high and functions as a
clock for a latch which is used to save the address values, because the address has to be
available throughout the bus cycle .Once the address is latched on to the latches ,it can
be removed from the AD lines ,and then these lines are free to carry data.
BHE /S7 BHE
8
L
0 A16/S3 –A19/S6 A
T
8 C
A0-A19
6 H
AD0 –AD15
ALE ADDRESS BUS
DATA BUS
D0-D15
Fig 6-3 Block diagram of the de-multiplexed address /data bus
But this accounts for only 16 address lines .8086 has a 20 bit address .In the pin diagram
, pin numbers 35 to 38 also cater to address ,and they have the designations A16 to A19
.But they are also multiplexed with status signals ,and they also have to be de-
multiplexed. Besides these, there is one more pin which carries address information ,and
that is the active low line BHE (Bus High Enable)which is multiplexed by the status
signal S7 . The function of this signal is explained in Chapter 7.Now, with all this
information included, the de-multiplexed block diagram is as shown in Fig 6-3.
6.1.3 Minimum Mode Pin Functions

Now, let us get to know the functions of each of the pins of 8086. Table 6-1 lists the pin
numbers ,pin designations and pin functions ,in the Minimum mode
Pin Nos Designation Function Type

16 to 2, AD0- AD14, 16 multiplexed address/data lines which Bidirectional
39 AD15 carry address when ALE is high ,and
later functions as data lines D0 –D15,
when ALE is low
35 to 38 A19 /S6 –A16/ S3 Address lines A19 to A16 which are Output
multiplexed with status signals S6 to S3
. The status bits functions are as follows
S6 -always 0
S5 - condition of the interrupt flag (IF)
S4 and S3 show the current segment in
use as below:
S4 S3
0 0 Extra Segment
0 1 Stack Segment
1 0 Code or no Segment
1 1 Data Segment
32 RD When this signal is low, data can be Output
received from memory or input
devices.
29 WR When this signal is low, it is an Output
indication that the data on the data lines
are available for writing into memory or
outputting to output devices .
19 CLK This is the clock pin to which a clock Input
with at least 33% duty cycle, is to be
supplied .
21 RESET This is an active high signal which Input
signals the microprocessor to reset itself
provided the pin is held high for at least
4 clock periods.
22 READY For the bus cycle to proceed normally Input
,the READY pin should be found to be
at logic high when it is sampled .If it is
at logic low ,WAIT states are inserted
into the current bus cycle
23 TEST This is a pin which is used usually Input
when an arithmetic co-processor is in
the system .This pin is tested by the
WAIT instruction .If the pin is at logic
zero , the ‘WAIT’ instruction becomes
a NOP instruction .Otherwise , the
processor waits until this pin becomes
logic zero.
25 ALE ‘Address Latch Enable’ –this signal Output
goes high in the beginning of a bus
cycle and indicates that the multiplexed
address bus contains address
information
26 ‘Data Enable”-This active low signal Output

DEN functions as an activation signal for the
external data bus buffers
27 DT / R ‘Data Transmit/Receive ‘-The logic Output
value of this signal indicates whether the
data is received (in a read cycle DT / R
=0)) or transmitted (in a write cycle
DT / R =1).Thus it is used as a direction
pin for external data bus buffers
28 M/ IO For I/O access this pin is low, and for Output
memory access, it is high
31 HOLD This is an signal from a peripheral Input
requesting direct memory access(DMA).
If the signal is high ,the processor issues
a Hold Acknowledge signal ,and tri-
states its data ,address and control bus.
30 HLDA ‘Hold Acknowledge’ indicates the Output
acknowledgement of the HOLD request
,
33 This pin selected the mode of operation Input
MN / MX –i.e. minimum or maximum For
minimum mode, the pin is to be
connected to the +5 V supply
34 BHE / S 7 The ‘Bus High Enable’ is a logic low Output
signal which is used to enable the ‘high
memory bank ‘ of the data bus –i.e. the
D8 – D15 lines become active then .The
status of this pin is latched along with
the address information
This is multiplexed with the status pin
S7 ,which is always 1 .
1,20 GND ‘Ground’ –The common point is to be ---
connected to two pins .Two Ground pins
are used so as to prevent having to
connect them together internally ,due to
possible noise in the internal routing of
the pins
40 VCC The power supply must be +5V+/- 10% ---
18 INTR Interrupt Request –this is used by an Input
external device to interrupt the
processor ,which responds ,only if the
interrupt flag (IF) is set, by lowering the
INTA line ,and initiating an ‘interrupt
acknowledge’ machine cycle input
24 INTA ‘Interrupt Acknowledge ‘ is an active Output
low signal acknowledging the interrupt
request placed on the INTR pin
17 NMI Non-maskable interrupt request which is Input

placed by an external device –similar to
INTR ,but Interrupt Flag (IF) does not
have to be set for it to be serviced .It is
high priority interrupt
6.1.4 THE DEMULTIPLEXED ADDRESS/DATA BUS

6.1.4.1The Address Bus
The idea of de-multiplexing has already been discussed in Section 6.1.2 .Now ,let us get
into the finer details . To ensure that the address is available on the memory or I/O
address lines throughout the complete read/write bus cycle, the 20 lines of address
information and the line BHE have to be latched ,and the output of the latch will
constitute the address bus .Thus 21 lines are to be latched. Obviously , external latch ICs
will have to be used .One very popular latch IC is the three state octal transparent latch
74LS373.Since one IC can cater only to 8 lines, 3 such latches are needed for de-
multiplexing .Fig 6-4 ..shows the pin diagram of this IC. The data sheet of this IC
specifies that ‘the eight latches of the 74LS373 are transparent D type latches meaning
that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs.. Thus
the ALE signal is connected to the G pin of the IC . The OC (OUTPUT CONTROL) is
grounded for normal operation –Otherwise ,the output lines are tri-stated. The IC also
provides a buffered output , meaning that it has the capability to drive high capacitance
buses that are normally encountered. and the current driving capability of the address
lines is raised so that more number of TTL loads may be driven.
Note : The LS (Low Power Schottky) series of ICs offer a significant reduction in
power as well as increases in speed over TTL
1D G 1Q
2D 2Q
3D 3Q
4D 4Q
74LS373
5D 5Q
6D 6Q
7D 7Q
8D OC 8Q
Fig 6-4 Pin diagram of the octal latch IC 74LS373
BHE / S 7
BHE
OC A19
A19/S6
A18/S5 A18
A17/S4 ‘373 A17
A16/S3 A16
G
A15
A14
A13
A12
A11
A10
Address Bus
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
G G
ALE ‘373 ‘373
OC
OC
Fig 6-5 The buffered and de-multiplexed address bus
Fig 6-5 shows the complete diagram of the 8086 ,connected to three latch chips .The
outputs of the latches constitute the address bus.
6.1.4.2 The Data Bus
In Fig 6.5, the data lines D0 -D15 are shown available directly from the pins AD0 to
AD15 . But in practice, these lines don’t have sufficient current driving capability for
many (more than 8 to 10) TTL loads and the capacity to drive capacitive loads .Most
memory devices are MOS chips which have capacitive inputs ,which have to be
charged/discharged when logic level changes occur . If the pin fan out is high ,the
processor cannot supply the necessary current for this .Hence buffers/line drivers which
raise the current driving capability of these pins are used. Moreover , these lines also
have to be isolated when not in use .Hence the buffers have to be tri-state buffers .
The data lines are bidirectional –the direction depending on whether the data is being
read/written. A popular octal bidirectional tri-state buffer is the 74LS245 . For 16 data
lines, two such ICs are needed. Two pins of the of the 8086 act as enable and direction
pins to be connected to the buffer . The DT / R line is high for data write and low for
data read .This pin of 8086 is connected to the DIR (Direction) pin of the buffer .This
fixes up the direction of data transfer .Another pin DEN of the processor is connected to
the Enable line ( G ))of the buffer .Only if this pin is at low level ,will the output lines of
the buffer be enabled ,otherwise the lines are tri-stated ).
A1 G B1
A2 B2
A3 B3
A4 74LS245 B4
A5 B5
A6 B6
A7 B7
A8 DIR B8
Fig 6-7 Pin diagram of the octal tri-state bi-directional buffer 74LS245
The bus cycle timing will ensure the activation of these signals at the appropriate time
for data transfer. We will soon get to the discussion of bus cycles .
6.1.5 Control signals for Read and Write:

Before getting to the discussion on bus timing ,it will be worthwhile to mention that the
associated control signals RD , WR and M / IO may also be buffered ,but since these are
output signals sent out by 8086 , these lines are unidirectional ,and hence the buffer
IC74LS244 will be sufficient for use here. This is a unidirectional tri-state octal buffer .
Thus the diagram of the processor with the buffered data bus and control signals is
given in Fig 6-8.
Buffered Control
Fig :6-8 Buffered data bus and control pins
M / IO
bus
1A1 1Y1
74LS244
M / IO
RD 1A2 1Y2 RD
WR 1A3 1Y3 WR
8086 gA1 B1 D15

A2 B2 D14
A3 B3
D13
74LS245
AD15 A4 B4 D12
AD14 A5 B5 D12
Address bus
AD13 A6 B6 D10
AD12 A7 B7 D9
AD11 A8 B8
D8
AD10 G DIR
AD9
6.1.5 Memory and I/O
The signals RD, WR and M / IO have to be used suitably to get the memory read/write
signals MEMRD and MEMWR and the I/O read/write signals IORD and IOWR . See
the circuit diagram in Fig 6-9. With this, I/O and memory have separate lines for access
.Generation of these control signals may be done with any logic gates .
RD
IORD
MEMRD
o
M / I0
o MEMWR
WR
IOWR
Fig 6-9 Generation of memory and I/O read/write signals
6.1.6 Clock Generation .

It has been emphasized that all activities within a processor are synchronized with a clock
.A clock is a square wave signal of fixed frequency . All timings of activities done by the
processor are calculated based on this clock period .One cycle of the clock is called a T
state ,and all timings and delays are multiples of this T state duration.
Thus ,it is obvious that the 8086 has to have a clock signal .There is no circuitry inside
the processor for this ,and so an external clock generator IC is used .Intel has provided
the clock generator IC 8284A which is compatible with 8086/8088 .This generates a
clock of frequency depending on the crystal connected between two of its terminals . The
crystal frequency must be three times the desired frequency for the microprocessor. 8086
operates at frequencies of 5 to 15 MHz and depending on the requirement ,the
appropriate crystal may be used .The CLK output generates a 33% duty cycle designed to
drive the 8086 processor directly.
The pin diagram of the clock generator IC is given in Fig 6.-10..
Fig 6-10 : Pin configuration of the clock generator 8284A
The clock generator IC performs a few more functions than just supplying the clock
frequency to the processor . We will discuss only a few basic functions that are in use
for a minimum mode system. See the connection diagram in Fig 6-11
Note that the crystal is connected between the X1 and X2 pins
X1 X2
8284A
READY
RDY
RESET
RES
CLK
CLK RESET
READY
8086
Fig 6-11 Connections of the clock generator IC to 8086

6.1.7 READY
The READY output pin of 8284A is connected to the READY input pin of 8086. This
pin is used to overcome the timing inconsistencies that are possible when a slow
peripheral/memory device is connected to the processor . The slow device may not be
able to complete its read or write within the normal timing period of the processor .In that
case ,it asks for extra time to complete its activity –i.e. extra ‘wait’ states are inserted into
the bus cycle . These extra wait states are inserted when the READY signal is low . For
slow peripherals/memory , a wait state generator can be added in the system ,as shown in
Fig …. If wait states are not needed , READY is found to be high when it is sampled. But
why is READY connected to the clock generator IC? This is to synchronize it with the
clock signal .READY may appear at any time ,but the 8284A sends it to the 8086 only
at the trailing edge of the clock.
6.1.8 RESET
An active low RES signal from the control bus is sent to the 8284 which synchronizes it
with the trailing edge of the clock . Most systems include a line that goes to all system
components and possibly controlled by an operator push button (or just after power
on),which causes a low signal on the RES pin of the clock generator . The reset circuitry
of 8284A makes sure that the timing requirements of reset of 8086 are met –i.e. the
RESET line of 8086 must remain high for at least 4 clock periods. The 8086 will
terminate operations on the high-going edge of RESET and will remain dormant as long
as RESET is HIGH. A high on the RESET pin of the processor causes all system
components to be reset ,and inside it, the instruction queue , PSW,DS,SS ,ES and IP are
cleared. CS gets a value of FFFFH and with IP=0000, the first instruction will be
executed from the location FFFF0H . But normally ,this address will be found in a read-
only section of memory , and the code here will be a jump instruction to a program for
loading the operating system .Such a program is called a bootstrap loader.
6.1.9 POWER ON RESET
Fig :6-12 ‘Power On Reset ‘circuit
. When the power is first switched on ,the 8086 should be reset .This is called power on
reset and Fig 6-12 shows the ‘power on reset ‘circuit .Observe the circuitry at the pin
RES .
There is an RC circuit ,and a push button switch too .Assume the push button switch to
be in the open condition now. When the 8086 is first switched on ,power is applied .Then
the capacitor in the circuit starts charging as shown in Fig 6-13 . Thus Vc increases and
the voltage at the RES increases .Inside the 8284 chip ,this RES is the input to a
Schmitt trigger as shown in Fig 6-14 .
Fig 6-13 Charging of the capacitor and generation of reset pulse.
Fig 6-14 The generation of the reset pulse using a Schmitt trigger (inside the 8284
IC)
Till the voltage VC rises to VH, ,the Schmitt trigger output is low .Once it crosses the
value of VH ,it goes low . The high pulse from the Schmitt trigger output is the RESET
pulse to be applied to the 8086 .Note ,in Fig 6-14 ,that it is applied to the D input of a flip
flop and hence it appears at the flip flop output ,in synchronism with the clock .
It is specified that the 8086 reset pulse should be high and should have a period of
at least 4 clock cycles .How is that ensured .? Simply by designing the time constant of
the RC circuit .Let’s try a simple calculation.
The Schmitt trigger switches to low, once its input crosses 1.7V (as per its specifications
).The equation for the charging of the capacitor is
Vc =Vcc[ 1-exp(-t/RC)] .
If Vc is to be at least 1 V ,t=50usecs and Vcc =4.5V ,then RC=188usecs.
So if C=10uF ,then R=18K .
These are close to the values we have used in Fig 6-12 .
By this we are designing a reset pulse of 50 usecs, which is higher than the minimum
requirements of the reset pulse for the clock frequency of 5 MHz shown in Fig 6-12 .
The reset output of the clock generator can be used for resetting other devices in the
system along with the 8086 reset .
Why the push button switch? To start a new reset cycle – if the switch is pressed ,the
capacitor discharges ,and to re-start ,the whole process should start again.
When using a crystal for frequency generation ,the F/ C pin of the 8284 IC, must be
grounded . If this pin is high ,the EF1 pin should be connected to an external oscillator
.and a pin CSYNC is used to provide synchronization in this case ,Since we are using a
crystal in our circuit, the pins F/ C and CSYNC are grounded in Fig 6-12.
6.2 CLOCK
It has been mentioned that all activities on the system bus is synchronized by the system
clock which provides the basic timing . Now ,what are the activities on the bus?
Let us list it out
i) Reading from memory or / IO
ii) Writing to memory /IO
These are obviously two fundamental bus activities .Depending on the type of activity
,different control signals are activated . Any read or write cycle is called a bus cycle .For
8086 ,a bus cycle takes 4 T states, where one T state is defined as the ‘period’ of the
clock .If the clock frequency is 10 MHz ,one T state= 0.1µsecs or 100 nsecs. A bus cycle
is also called a machine cycle .During a machine cycle ,a specific operation –say, reading
or writing is accomplished .So, we can have the following basic machine cycles,
i) Memory Read
ii) Memory Write
iii) I/O Read
iv) I/O Write
There is also the ‘Interrupt acknowledge machine cycle’ ,but that will be discussed in
Chapter 8.
6.2.1 READ MACHINE CYCLE
In chapter 0.2.5,the the steps involved in a typical read machine cycle were listed ,and
let us recollect it.
i) Place on the address bus ,the address of the location whose content is to be
read .This action is performed by the processor.
ii) Assert the read control signal which is part of the control bus
iii) Wait until the content of the addressed location appears on the data bus
iv) Transfer the data on the data bus to the processor
v) De-activate the read control signal .The read operation is over and the address
on the address bus is not relevant anymore.
T1 T2 T3 T4
CLK
BHE /S7 , S7-S3

A19-A16, BHE
A19-A16/S6-S3
AD15-AD0 Float Float

AD15-AD0 Data in
M / IO
ALE
DT / R
RD
o o
DEN
READY
Fig 6-15 Read machine cycle timing diagram

This sequence is followed in the read machine cycle of 8086 as well . But here, we have
to examine the exact signals of the processor . Many control signals are necessary and
are shown in the timing diagram. Refer to the Read machine cycle timing diagram in Fig
6-15 when reading the steps given below. This diagram is relevant for both ‘memory
read’ and ‘I/O read’ .In the diagram,. time is marked along the horizontal direction ,and
the activities on the pins of 8086 at corresponding points in time are shown. ‘Crossing
lines’ show that the data in those lines become valid at that point in time, and also that
the logic levels in the lines change.
The T sates are labeled as T1 ,T2 ,T3 and T4 . Each T state is defined from the 50% level
of the trailing edge of the clock to the next corresponding point in the clock train.
i. In T1, the address of the location to be accessed is placed on the lines AD0 to
AD15 andA16/S3 to A19/S6 . BHE is high or low depending on the type of
data(byte/word) to be accessed.
ii. In T1 ,the ALE signal goes high for one clock cycle ,and on its trailing edge ,the
address information is latched and available at the output of the latches.
iii. If it is a ‘memory read’ ,the M / IO signal is high from T1 to T4 .If it is ‘I/O read’
,this signal is low. Also the DT / R is low from T1 to T4 indicating that data is to
be ‘received’ by the processor(since it is a read cycle).
iv. In T2 , the address information is removed from AD0 to AD15 and the bus is tri-
stated(floated). The address information is removed from A16/S3 to A19/S6 and
BHE / S 7 also, and these lines now carry status information.
v. In T2 , the RD signal (which is the READ control signal) is made low . The line
shown to the data bus is indicative of a ‘cause –effect’ relationship –here when
the READ control signal goes low, the output lines of memory come out of the
‘float ‘ state.
vi. For a normal read cycle ,valid data from appears on the data lines after the period
defined as the ‘access time’ of the memory/IO.
vii. In T2 , DEN goes low to enable the data bus buffer outputs .
viii. At the end of T2 ,the READY signal is sampled and if it is high , the bus cycle
proceeds normally .This is the case shown in this diagram.
ix. The clock cycle T3 is to allow ‘access time’ for bringing data from memory/IO
and put it on the data bus. Thus, after the data appears on the data bus ,it is
transferred to the 8086 (to the relevant registers)at the end of T3 .
x. In T4, all the bus signals are de-activated in preparation for the next bus
cycle..This machine cycle ends with T4 , and the next machine cycle is scheduled
to start .
6.2.2 WAIT CYCLES
If the access time for a device is longer than can be permitted by the timing of 8086,
extra clock cycles termed ‘wait states’ have to be inserted in the bus cycle .This is
applicable for reading and writing ..
Fig 6-16 Sampling the READY signal and inserting wait states
The arrangement for this is to sample the READY line at the end of T2 If the READY
signal is found low ,an extra cycle is inserted into the bus cycle ,between T2 and T3,
which is designated as TW . All signals on the bus remain unchanged during this extra
wait state (TW).In the middle of TW , once again the READY signal is checked .If it now
at logic 1, the machine cycle will be T3 -otherwise another wait state will be inserted.
Thus bus cycles can be lengthened to accommodate slower devices in the systems . In
such cases ,a ‘wait state generator’ is connected to the READY pin of the clock
generator to control the READY pin.
.
X1 X2
CLK
8284A CLK 8
CLOCK READY
RES READY 0
GENERATOR RESET
RESET 8
6
RDY
WAIT STATE
GENERATOR
Fig 6-17 Insertion of a wait state generator to add wait states

Refer to the Intel manual in Appendix B ,for a more detailed timing diagram. of READ
with exact time values given.
If no wait states are needed, then it will be sufficient to keep the READY pin of 8086
high .Another way would be to connect the RDY1 and RDY2 pins to low and the AEN 1
and AEN 2 to high which will permanently disable this function .For more details on
these pins ,refer to the data sheet of the clock generator IC 8284A.
Example 6.1
What is the duration of the bus-cycle in a 8086 based microcomputer, if the clock
frequency is 12 MHz and the three wait states are inserted?
Solution:
The period of a 12 MHz microprocessor is, T = 1/f = 83 ns.
Thus, the duration of the bus-cycle, without any wait-states
is given by; Tbus-cycle = 4* T = 4 * 83 ns = 332 ns.
Duration of the wait-states is, TW= 3* T = 249 ns.
So, extended bus-cycle Tbus-cycle + TW = 581 ns.
6.2.3 WRITE MACHINE CYCLE

The steps in a write machine cycle are (refer Section 0.2.5)
i) Place on the address bus ,the address of the location to which data is to be
written.
ii) On the data bus, place the data to be written.
iii) Assert the write control signal which is part of the control bus.
iv) Wait until the data is stored in the addressed location.
v) De-activate the memory write signal .This ends the memory write operation.
For the 8086 ,the control signals for a write machine cycle are the same as in a READ
cycle except the WR is used in place of RD .Also the DT / R signal will be high (for
‘data transmit’)for writing .This being the case ,the complete write machine cycle is not
shown here –only the timing of placing of the address and data on the buses ,and the
lowering of the write control signal is shown here. The write bus cycle also uses 4 T
states normally ,but can be extended by adding wait states if required.
T1 T2 T3 T4
CLK
Address/
Status Address Status
Address/
Data Address Data to be written
WR
Fig 6-18 Simplified write machine cycle timing
6.3 OTHER PROCESSOR ACTIVITIES

6.3.1 INTERRUPT LINES
The word ‘interrupt’ implies that something that is being done is to be temporarily stalled
,so as to take up another activity . This is the case for a processor too .When the
processor is performing some activity ,an external device can ask for attention by placing
a signal on an ‘interrupt request’ line. Then the processor stops whatever it was doing and
attends to the request of the interrupting device When the processor gets an interrupt
request on the INTR line ,it responds by lowering the INTA (Interrupt Acknowledge
line) and enters an Interrupt acknowledge machine cycle.
NMI(Non Maskable Interrupt) is another line on which an external device can place an
interrupt request. .One difference between the two is that, for an interrupt request on the
INTR line to be acknowledged and taken up ,the interrupt flag should be set (IF=1),while
this is not necessary for a request on the INTR line. The details of interrupt processing
will be discussed in Chapter 8 .(We will also discuss why the RESET pin can also be
called an interrupt pin).
6.3.2 DMA
DMA stands for ‘direct memory access’ .So far, we have seen the processor
communicating with memory or I/O i.e. the communication always involved the
processor .Is it possible for data in memory to be sent directly to I/O or vice versa without
involving the processor? For example, we might need to print a large chunk of data which
is in memory .This data can be sent to the output device (printer) from memory. In this
case ,there is no necessity to involve the processor in the data transfer .This is called
‘direct memory access’ . But since the processor is in the system ,it must be isolated
from this process. That means that ,when DMA is to take place ,the connection of the
processor to memory and I/O is blocked –i.e the buses of the processor are to be tri-stated
(in the high impedance state), leaving the path open for data to be transferred directly
between I/O and memory .
MEMORY
S
Y
S
T
8086 E
FLOAT M
B
U
S
I/O
HOLD HLDA
Fig 6-19 Concept of Direct Memory Access
Fig 6-19 shows the typical scenario . Data transfer occurs between the memory and I/O
,in either direction .The processor cannot do any bus related operation ,as its buses are in
the float state . This whole process is managed and controlled by a DMA controller
,which we will discuss in detail in Chapter 11. . At this point, what is needed to be
understood is that when DMA operation is to be done, the DMA controller places a DMA
request on the HOLD pin of 8086.This is essentially a request for permission take
control of the system bus. Since DMA is a high priority service, the processor stops
whatever it is doing and acknowledges the request by raising the HLDA (hold
acknowledge) line and DMA is initiated. Fig 6-20 ..shows the timing associated with the
HOLD and HLDA lines.
DMA
T4 or T1 cycles
CLK
HOLD
HLDA
Hold Execution
Execution State resumes
Suspends
Fig 6-20 Timing of the HOLD and HLDA signals
The HOLD pin is sampled at every rising edge of the clock ,and the acknowledge signal
is activated at the end of the current machine cycle –i.e. at T4 .In this state ,the address
,data and control pins of the 8086 are in the high impedance state ,and this continues until
the HOLD request is taken away by the requesting device.
6.3.3 TEST : This pin can be used as an alternative to interrupts. But usually ,this pin is
not used in the minimum mode of operation where 8086 operates in a single processor
environment . In the maximum mode, when an arithmetic coprocessor is also present in
the system , this pin is needed to synchronize the activities of both the processors .The
two processors normally can execute separate instructions ,but if the 8086 needs a result
from the co-processor before it can proceed further ,it executes a WAIT instruction
,which forces the TEST to be high . This is because this pin is connected to the BUSY
pin of the coprocessor ,which is high when the coprocessor is executing instructions Then
the 8086 goes into an idle state where it simply waits until the TEST becomes low (this
happens when the required result is obtained from the processor).After that ,the 8086 can
continue its normal sequence of operations. If the TEST pin is low ,the WAIT
instruction is a NOP for 8086. The communication between the 8086 and the co-
processor is discussed in detail in Chapter 13.
6.3.5 BUS HIGH ENABLE( BHE )
This active low signal is used to activate the higher order memory bank ,the details of
which is discussed in Chapter 7..
Power Supply
VCC GND
Address/data bus
INTR AD0-AD15, A16/S3-AS19/S6

INTA
Interrupt
Interface TEST
NMI
ALE
RESET
8086 BHE / S7
M / IO Memory/IO
DMA HOLD DT / R Control
Interface
HLDA RD
VCC WR
DEN
Mode MN / MX READY
Select
CLK
Clock
Fig 6-21 8086 in the minimum mode configuration
Now that all the signals in the minimum mode have been discussed ,the minimum mode
configuration can be observed and understood from Fig 6-21 .
6.3.6 HALT MACHINE CYCLE
Another machine cycle is the HALT machine cycle .The processor enters this machine
cycle in response to a HLT (Halt) instruction. In the minimum mode ,the processor issues
an ALE signal with no other control signals .In the maximum mode, the processor signals
cause the bus controller (will be discussed in Section 6.4) to generate the ALE signal
.Since no other signals are generated ,the bus cycles are halted .To bring the processor out
of this state, an interrupt or a RESET signal must be issued
6.4 MAXIMUM MODE

Now let us discuss the maximum mode pins .It is necessary to use the maximum mode if
the processor is to be used in multiprocessor configurations .The most important issues in
a multiprocessor environment are inter-processor communication and bus contention. In
this mode,8086 has special pins for resolving these issues. To use the maximum mode,
pin No:33 MN / MX must be connected to ground. Then , pins No 24 to 31 have
different designations from what we saw in the minimum mode.
…
Fig 6-22Maximum mode pins of 8086

In this mode, some of the most important control functions are not obtained from the
processor, but will have to be generated from an external chip called bus controller. The
functions of INTA, ALE , DT / R, M / IO, and WR are to be generated externally . This
mode of operation was designed by Intel for allowing the 8086 to communicate with
other processors like the arithmetic co-processor (8087) and the input/output processor
8089 . It was also used to allow 8086 to be used in large loosely coupled multiprocessor
systems. This mode was dropped from Intel’s designs from 80286 onwards .Later
processors (80486 onwards) had the arithmetic co-processor integrated on the processor
chip itself .
Now let us see how the lost signals of the processor are generated by the bus controller
The bus controller 8288 was designed by Intel to be compatible with the 8086 .
6.4.1 BUS CONTROLLER
In the maximum mode configuration, pin no.s 26 ,27 and 28 are designated as S 0 , S 1
and S 2 .On these pins ,the 8086 outputs a code which specify the type of bus cycle to be
initiated . The listing of the codes , corresponding machine cycles and the important
control signal generated by the 8288 is shown in Table 6-1
STATUS SIGNALS CONTROL SIGNAL

S2 S1(BAR) S0 MACHINE CYCLE GENERATED BY 8288
0 0 0 Interrupt Acknowledge INTA
0 0 1 I/O Read IORC
0 1 0 I/O Write IOWC
0 1 1 Halt NONE
1 0 0 Instruction Fetch MRDC
1 0 1 Memory Read MRDC
1 1 0 Memory Write MWTC
1 1 1 Inactive NONE
Table 6.1 : Control signals generated by the bus controller
The connection diagram between the 8086 and 8288 is shown in Fig 6-21
Note that the clock generator applies the same clock to both the ICs .Thus ,according to
the code on S 0 , S 1 and S 2 ,the appropriate signals are generated and can be used to
read/write memory or I/O , and provide the necessary signals for latches and transceivers
etc .
Note that the bus controller generates the read and write control signals for memory and
I/O ,the ALE signal for the latches ,the DT / R and DEN signals for the transceivers and
the INTA signal for acknowledging interrupts etc
There are a few more pins for the bus controller IC ,but we shall not discuss those
,because such maximum mode systems have become obsolete. But to complete our
understanding of the 8086 ,let us see the rest of the maximum mode pins.
Fig 6-23 :Pin diagram of the bus controller IC 8288
8284
CLOCK
GENERATOR
CLK MRDC
MWTC
CLK 8
S0 2 IORC
S0
8086
S1 8 IOWC
S1
S2
8 DT/ R
S2 DEN
ALE
Fig 6-24 : Connection between the 8086 and 8288
6.4.1REQUEST/GRANT pins.
Pin numbers 30 and 31 are designated as RQ / GT . These are special pins ,in the sense
that they are bidirectional .As the name implies ,they cater to ‘request’ and ‘grant’. Each
of these pins act similar to the HOLD and HLDA pins .In the minimum mode , HOLD
is for bus request ,and HLDA is for bus grant .In the maximum mode ,one pin performs
both functions .Here the request/grant pins are more likely to be used for communicating
with other processors, than for DMA operations .Remember that this mode is used in
multiprocessor configurations-i.e. systems in which there are other processors besides the
8086. .In multiprocessing systems ,resources like memory and I/O are likely to be shared
and the system bus is common to all processors .When one processor is using the bus
,another processor may request the use of the bus and the current bus master may
relinquish the bus (subject to conditions). Thus ,requests from another processor will be
placed on these lines and the grant signal is also placed on these pins, but in the opposite
direction ,obviously .That is how these pins are ‘bidirectional’.
T4or T1
CLK
RG / GT
A processor requests 8086 grants bus to Processor

bus access requesting processor releases bus
Fig 6-25 Timing associated with the RQ / GT pin
.There are timings associated with requests and grants, and are shown in Fig 6-25.
Three pulses are needed to complete a request/grant/release of the bus. The RQ / GT pins
are examined at the rising edge of each clock pulse .If a request (low logic for one T
state) is detected ,and if the conditions are conducive for granting the request, the grant
pulse appears on the same pin immediately following the next T4 or T1 state. This allows
the requesting processor to use the bus .When this processor is ready to return the bus
after use, it sends the release pulse on the same line..Incidentally there are two such pins
and in a maximum mode system , if bus requests are received on both the pins ,the pin
RQ 0 / GT 0 will get the priority. This can happen if there are two other processors in the
system besides the 8086 .
6.4.2 QUEUE STATUS pins QS0 ,QS1

These pins are inputs to the 8086 . It becomes useful when an arithmetic coprocessor is
the second processor in the system .Since the co-processor is expected to work in step
with 8086 ,the co-processor can interrogate the 8086 about its queue status on these lines
,and decide its course of action accordingly. More details are available in Chapter 13.
6.4.3 LOCK This is an output signal from the 8086 .If this processor wants to prevent
any other bus masters from accessing the bus, this signal will be asserted low .The 8086
can use an instruction with a LOCK prefix to cause the hardware LOCK signal to be
asserted. For example if the 8086 wants to retain the bus until a string transfer is
completed fully ,it can use the instruction (say) LOCK REP MOVSB. So the processor
does not have to relinquish the bus after one bus cycle ,as may be the case if the LOCK
prefix is not used.
We have discussed all the maximum mode pins of 8086 and the diagram with all the
control signals is shown in Fig 6.26
CLK
.
Vcc GND CLK AEN
Interrupt S0 MRDC
Interface CLK MWTC
S1
INTR S2 8288 IORC
S0 Bus
TEST IOWC
Controller
NMI S1
INTA
RESET S2 DEN
DT / R
ALE
ALE
8086 DT / R
DEN
MIN / MX AD0 - AD15 -
A16/ S3 - A19/S1
LOCK
BHE
RD
READY
QS1 ,QS 0
Local bus
RQ1 / GT1 RQ0 / GT0 control
Fig 6.26 Maximum mode configuration of the 8086

6.5 INSTRUCTION CYCLE
Now ,let us decide what we mean by the word ‘instruction cycle’.
The time taken by the processor to execute an instruction is called an instruction cycle
,and it is specified in terms of the number of clock cycles needed to do it. But this is not
as direct as it seems .
Let us examine the important issues in this. The operation of the CPU is just ‘fetch
,decode and execute’. Once an instruction is fetched and is ready for execution, it will be
decoded immediately ,and after that execution can be set in motion.
The fetch-execute cycle can be decomposed into 6 stages.
FI – Fetch instruction
DI – Decode instruction
CO – Calculate operand addresses
FO – Fetch operands
EI – Execute instruction
WO – Write or store result in memory
The time for al these activities should constitute the ‘instruction cycle’.
If for example we fetch an ADD instruction which is a 2-byte instruction, the first 8-bits
specify this operation..The other bits identify the source and destination operands of our
instruction. The ADD instruction may have a memory operand or an immediate operand.
If a memory address or immediate operand is specified, there will be optional bytes
following the instruction which will have to be fetched. There may also be the
requirement of having to calculate the operand address. The BIU will separate the
operation type from the operands and fetch any operands from memory if required, and
after that , execution in done.
In the execution phase,, any instruction involving loading from or storing into memory
,will cause a read or write cycle to occur. An instruction which moves data between two
registers, or must execute a more complicated instruction with operands available within
the processor, is done in the Arithmetic and Logic Unit (ALU) alone.
Now ,let us look at the ’instruction fetch cycle ‘ once again .The instruction is in memory
and fetching it requires a ‘memory read’ cycle which takes 4 T states . But in 8086,
‘fetch and execute ‘are overlapped –i.e .instructions are fetched during the execution
phase of an earlier instruction , and thus the current instruction is normally available in
the instruction queue when it is ready for execution. The result is that, in most cases, the
time normally required to fetch instructions "disappears", because the Execution unit
(EU) executes instructions that have already been pre-fetched by the BIU. Thus the
instruction cycle time does not include the time required to fetch the instruction .But for
instructions which have memory operands not specified directly ,there is a time involved
in calculating the ‘effective address’. Take the case of an addressing mode like ,say,
based indexed mode or relative based indexed mode .The BIU takes time to do the
address calculation ,and this time is also included in the instruction cycle.
Another factor for an extra delay to occur is , if an operand which is a word whose
address is aligned with an odd address has to be accessed ,In this case ,one more memory
read/write cycle may be incurred ,in comparison to a word which is at an even address.(
the mechanics of this is discussed in Chapter 7)..This is not taken into account in the
ensuing calculations .
No Instruction No of clock cycles for execution

1 ADD AX ,BX 2
2 MOV AX,BX 2
3 MUL BX 133
4 MOV BX, N 4
5 CMP AX,[BX][SI] 9+EA
6 JNZ label 16/4
7 LOOP label 17/5
Table 6-2 : Execution times of some sample instructions
Now look at some execution times. in Table 6-2. In the first three instructions, all the
operands are register operands ,and the execution time is just the time required to perform
the operation in the ALU. Note that MUL requires quite a lot of time compared to ADD,
because it is a complex instruction involving many steps. The fourth instruction is in the
immediate addressing mode .
In the fifth instruction , there is a memory operand and the execution time is given as
9+EA ,where EA is the time for calculating the effective address .The EA values for
different addressing modes is given in Table 6-3 .
For instruction 6 and 7 ,the execution times are 16/4 and 17/5 .These instructions are
conditional branch instructions .The first figure gives the execution time if the branch is
taken and the second number corresponds to the case when branching is exited. When a
branch is taken ,the instruction queue is to be cleared and reloaded. That is why more
time is expended when a ‘branch’ is taken ,in contrast to the case of execution in the
normal sequence.
No Addressing mode No of clocks for

calculation of EA
1 Direct 6
2 Register Indirect 5
3 Register relative 9
4 Based Indexed with BP as the base register 8
5 Based Indexed with BX as the base register 7

6 Relative Based Indexed 12
with BP as the base register
7 Relative Based Indexed 11

with BX as the base register
Table 6-3 : Number of cycles expended in calculating the ‘Effective Address’
In short ,if all such information is provided ,we will be in a position to calculate the
‘instruction cycle’ of an instruction ,and note that the time for ‘instruction fetch ’doe not
need to be included herein The instruction cycle times for each instruction is included
along with the instruction set ,in Appendix ……
6.5.1 DELAY LOOPS
Now that we have the means to calculate the time required to execute any instruction of
the processor ,let us use the execution time for an interesting application .We see that a
certain amount of time or rather a ‘delay’ is associated with the execution of an
instruction .Thus instruction execution gives us a means of generating a delay .See the
instructions below.
MOV CX, 100 4 cycles
HERE: LOOP HERE 17/5 cycles
How many clock cycles are necessary for executing the above program segment? The
MOV instruction takes 4 clocks .The LOOP instruction takes 17 cycles for repeating ,and
5 when exiting the loop .Thus totally we have 4+(17 x100) -12 =1692 cycles .( 12 is
subtracted ,because the last execution of the LOOP instruction takes 5 cycles rather than
17 )In a system with a clock of 12 MHz , one clock period is 0.083 µ secs, which makes
for a total delay of 140 µ sec s delay . Also note that most of the delay is incurred in the
repetition of the LOOP instruction .Thus the delay caused by the peripheral instruction
(MOV CX,100 ) may be neglected.
This idea may be used to fix up the value of N so as to get a desired value of delay .To
increase the delay,we can use the NOP (No operation ) instruction which has no operands
and no function except to execute within 3 cycles. The NOP instruction is usually used
to reserve space in programs ,for instructions which may needed to be added later.
Here we use it here to create a delay –any number of NOP instructions may be added.
Example 6-2
Write a program to create a delay of 1 msec.
Solution
Instruction No. of cycles

MOV CX,N 4
HERE: NOP 3
LOOP HERE 17/5
As most of the delay occurs within the loop ,the total cycles of delay
is =[(3+17) x N]-12.
Total delay time =1 msec =20N x 0.083 usecs
1m sec
For 1 msec delay ,the value of N = = 602 or 25AH
(20 x0.083µ sec s)
This value of N if inserted into the program will give us a delay of 1 msec. There is a
small % of error in this ,because of having to leave out peripheral instructions ,but for
most situations this can be neglected, as the delay that we get is anyway only
approximate.
The maximum value that can be loaded into a register is FFFFH , and if larger delays
are needed, a nested delay loop can be used as shown below .
Example 6-3
Write a delay loop with appropriate values of the count to get a delay of 1 second .
Solution:
The program is
Instructions Cycles
MOV BX,N1 4
THERE: MOV CX,N2 4
HERE: LOOP HERE 17
DEC BX 2
JNZ THERE 16
The inner loop is that which corresponds to the LOOP instruction .It repeats N2 times
,which is the count in the CX register . The LOOP instruction plus a few overheads(
caused by the instructions MOV CX,N2 and DEC BX ) repeat N1 times ,which is the
count of the outer loop .
.Thus a large delay can be obtained .To calculate N1 and N2 , the best way would be to
make N2=FFFFH and then get a corresponding value for N1 .
For a total delay of 1 second,
Total cycles = N1 x [17x N2 +4+2+16]=N1 [22+17 N2]
If N2 =FFFFH i.e. 65,535 the calculation comes to
1114117 x N1 x .083 =1000 000 usecs
92471.711 xN1 =1000000
N1 =10.81
Thus a value of 11 (0BH) can be used in the place of N1 in the program.
Note : No values are subtracted to take into account the decreased number of cycles when
a loop is exited .Thus ,this calculation is only approximate ,but the error is negligible .
6.5.2 WHY DELAY LOOPS?

What application is there for the exercise that we have just done ? Where are these
delays to be used ?
Generating delays in this manner is called ‘software delay’.
One can generate a square wave using a soft ware delay .Suppose we have an output port
with an address of 78H.See Example 6-4 .
Example 6-4
Generate a square wave of frequency 1 KHz at the output port with address 78H
Solution:
AGAIN: MOV AL,0FFH

OUT 78H,AL
CALL DELAY_1MS
MOV AL,00
OUT 78H,AL
CALL DELAY_1MS
JMP AGAIN
The above program assumes that a program named DELAY_1MS has been written and
used as a procedure along with this . This procedure is like the programs in Examples 6-2
or 6-3 ,with a count which gives a delay of 1 msecs.
If a CRO is connected to any pin of the data bus of the output port ,a continuous square
wave can be observed.
This is an application of software delay ,but in practical cases, we are more likely to use
dedicated timer chips for generating square waves of any frequency ,which is more easy
to program and gives more accurate delays.
In Chapter 5, Example 5-2 gets 20 temperature values from 20 input ports .Usually there
should be a time delay between each measurement ,and a software delay can be used
there .It is only necessary to write a procedure for a specific delay and call this delay
between each measurement.
• 8088 and 8086 processors are similar in most ways, except for three differences.
• There are two modes of operation for the 8086-which are designated as minimum
mode and maximum mode.
• When in the minimum mode, the 8086 functions in a uniprocessor environment.
• The address bus of the processor is multiplexed with the data bus ,and hence to
use these buses separately ,de-multiplexing must be done.
• The address bus ,data bus and control bus must be buffered to increase the driving
capability of the buses.
• An external clock generator is used to provide the clock and to synchronize the
reset and ready signals with the clock
• A machine cycle is a bus activity during which a specific operation is performed.
• Reading and writing of memory and I/O are important bus cycles
• A typical read/write machine cycle of 8086 is 4 T states long.
• Wait states are inserted into machine cycles to accomodate slow memory or
peripherals
• In the minimum mode ,all control signals are obtained from the processor.
• In the maximum mode, an external bus controller IC generates the important
control signals
• In the maximum mode ,there will be other processors in the system
• There are pins on the 8086 on which other processors can request the service of
the system bus.
• It is important to know how many cycles are expended for the execution of each
instruction.
• The delay caused by instruction execution can be used to create delay loops
QUIZ
1. List out the differences between 8086 and 8088.
2. How is the mode of operation of the processor selected and what is the
purpose of each mode?
3. Why are buffers/line drivers used in the address ,data and control lines?
4. What is the specification of the clock to be applied to the CLK pin of the
processor?
5. What is the specification of the RESET signal to be given to the
processor?
6. At what address does the 8086 wake up?
7. Why are RESET and READY signals applied to the clock generator IC?
8. When DT / R is high ,what is indicated?
9. What is the difference between the 74LS244 and 74LS245 ICs?
10. When is the READY pin sampled?
11. What is the difference in the interrupt signals INTR and NMI ?
12. What are the functions of the HOLD and HLDA pins?
13. When is the HOLD pin sampled?
14. How many wait cycles can be inserted in a bus cycle?
15. How can the processor be taken out of the HALT state?
16. What is ALE expected to do? What is the duration of ALE?
17. What is the purpose of the LOCK pin ?
18. Which are the control signals which are not available from the 8086 in the
maximum mode?
19. Why is it that the time for fetching an instruction is not included in the
instruction cycle time of an instruction?
20. What is the use of the NOP instruction?
EXERCISE
1) Draw the de-multiplexed and buffered data bus, address bus and
the read/write control signals with latches and buffers connected.
2) Draw a logic diagram using NAND gates to get the signals IORD ,
IOWR , MEMRD and MEMWR from the three processor signals
M / IO , RD and WR .
3) Draw a memory write machine cycle showing the state of all

important signals.
4) Redraw the above bus cycle with two wait states included.
5) Explain with relevant timing ,the operation of the RQ / GT pins.
6) In a typical write machine cycle, list out the activities occurring
during each of the four T states.
7) Write a program for getting a delay of 100 msecs.
8) Write a program to generate a square wave at the LSB of the data
bus of an output port with address F767H.
9) In a pressure monitoring environment ,10 pressure sensors have
been connected. The pressure from these sensors have to be read at
intervals of 5 msecs. Write a program to read the sensor values
from input ports having address 0FF0H to 0FF9H
CHAPTER 7
MEMORY AND I/O DECODING
In this chapter ,you will learn

• The pin functions of a typical memory chip
• The technique of memory address decoding
• The reason and logic of using partial address decoding
• The reason for organizing memory in banks
• The principles of I/O address decoding
Introduction
In the previous chapter we took a peep into the hardware structure of 8086 and a few
ICs which have to be used along with it. Now we will delve a bit deeper- the focus of this
chapter will be on the way memory and I/O are connected to the processor.
Let us start with memory . Whenever we talked about reading or writing from memory ,
an address was referred to . Assuming that memory is byte organized , it is thought that
every location in memory which can store a byte of data ,has a unique address .The total
address space of 8086 is from 00000 to FFFFFH . How is it that each location gets a
unique address ?
Another issue is that the total address space of 1 MB is not obtained as a single chip of
RAM –also it is not entirely RAM . ROM is also part of memory and a number of RAM
and ROM chips together constitute the total memory i.e. the total address space .
Also, when the processor is used , its address space is partitioned such that certain
address ranges are standardized for certain specific applications .Thus the IBM PC has a
standard memory map –if it is not standardized ,incompatibility issues are likely to arise.
This chapter attempts to find answers to all these doubts and queries.
The assumption here is that memory space and I/O space are disjoint (Refer Chapter 5) –
i.e. the scheme of I/O interfacing used is ‘peripheral or Isolated I/O’. This allows memory
to use the full 1 MB of space for itself.
7.1 MEMORY DEVICE PINS

The memory that we are talking about can be RAM or ROM –The difference is that
ROM can only be read from, so the MEMWR signal from the processor does not have
any relevance for ROM.
A typical RAM has the pin lines as shown in Fig 7-1.
As shown , it has data lines Do to DM-1 .If it is a byte organized memory ,the data lines
are D0 to D7 . The number of address lines ( A0 to AN-1 ) depends on the number of
locations it contains .For example if it is specified to be a 256 x 8 RAM ,it means that it
has 8 data lines and a storage capacity of 256 locations –thus it needs 8 address lines as
256 =28 . Think of the following cases then - a 1 K x 8 RAM needs 10 address lines ,as
1K=1024 =210 , a 2K x 8 RAM has 11 address lines and so on. Thus, it is the capacity
of the chip which decides the number of address lines.
A0
D0
RAM
DM-1
AN-1
WE CS OE
MEMRD
MEMWR
SELECT
Fig 7.1 Typical RAM with control pins
Coming to the other pins of the chips , the active low signals WE is to be connected to the
MEMWR signal from the processor side .Only if this pin is activated ,can the write
operation be done in the addressed location . WE enables the input tri-state buffers of the
data lines of the RAM.
For reading ,the pin MEMRD (from the processor side) is to be connected to the OE
(output enable) pin of the memory chip for reading .When this pin is low, the output
lines are activated ,otherwise they remain tri-stated. Thus OE is meant to enable the
output tri state buffers of the RAM.
Some RAM devices have only a single pin for reading or writing, which is R/ W .This is
fine, as it is obvious that only one of the activities (read or write ) can occur at a time.
The pin CS (chip select) or CE ( chip enable or S (Select)) is the pin which enables the
memory chip .No activity is possible if this pin is inactivated , as the chip remains turned
off . How does this pin get activated? It will be activated only if the address placed on the
address bus of the processor is one of the addresses in the address range of this chip
.When this condition is satisfied, a select pulse is obtained from the ‘address decoder’
output and the memory chip is turned ON for reading or writing. It is during a memory
read or write cycle that the select pulse is obtained i.e. when reading or writing to the
particular chip is required and the address is placed on the address bus .
A ROM chip is similar except that it does not have the WE pin, as it can only be read
from . The ROMs that are used are usually EPROM ,which have a pin to enable the chip
to be programmed .( PGM ).
Why active low control signals?
You might have noticed that most of the control signals discussed here and in the
previous
chapters are active low. This is a TTL concept .The stray capacitances of the control pins
can get charged from noise voltages ,and this may cause the signals to cross the threshold
of ‘high’ level as defined for TTL –thus if the control signals are active high ,it may
cause wrong triggering . On the other hand , an active low signal trigger will happen
only when the line is pulled low deliberately by the controller.
Example 7-1
How many address and data lines are needed for the memory chips with the following
organization?
i) 256 x4
ii) 512 x 8
iii) 1K x16
iv) 32K x 8
v) 128K x 8
Solution
i) 256 x 4 means, it has 4 data lines , and 256 memory locations ,each of width 4
bits.
256 =28 .Thus 8 address lines are needed.
ii) 512 x 8
This chip has 8 data lines .
512 =29 . Thus ,it has 9 address lines.
iii) 1K x 16 .
This chip has 16 data lines .
1K =1024 =210 .It has 10 address lines to access each of the 16 bit data words.
iv) 32K x 8
It has 8 data lines.
32K = 25 x 210 =215 .
It has 15 address lines
ii) 128 K x 8
It has 8 data lines.
128 K = 27 x 210 =217 .
It has 17 address lines .
7.2 MEMORY ADDRESS DECODING

See Fig 7.2 in which a 2K x 8 memory chip is shown.
This memory chip has 11 address lines ,which are directly connected to the 11 lower lines
of the address bus of the processor .Now the remaining 9 lines of the address bus of the
processor are connected to the inputs of a NAND gate whose output pin feeds the CS
pin of the memory chip .Thus it is obvious that the chip is selected(enabled) only if all
the input lines of the NAND gate are high –which means that A11-A19 of the address has
to be high for the memory chip to be selected and made active .The NAND gate thus
functions as the address decoder for the memory It fixes up the address range of the chip.
A0
Address Bus of
A0 - A10
A10 MEMORY
8086
A11 2K x 8
A19
CS
SELECT
o
Fig 7.2 Memory with address decoding
Example 7-2
i)Find out the range of addresses that the memory chip in Fig 7.2 contains
ii) Repeat the same when the logic of the NAND gate is changed as in Fig 7.3
A19 o
A18 o
A17 o
A16 o
A15 o o SELECT
A14 o
A13 o
A12 0
A11 0
Fig 7.3 NAND gate decoder

Solution
The address lines from A10 to A0 can vary from 000 0000 0000 to 111 1111 1111. The
address lines A19 to A11 must always be 1111 1111 1 for this chip to be selected.
As such ,the lower and upper range of the addresses in the chip are seen as
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A A A A A A A A A A
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
The first address on the chip is

1111 1111 1000 0000 0000
The last address on the chip is
1111 1111 1111 1111 1111
Thus the address range of the chip is FF800H to FFFFFH .i.e.2048 bytes i.e. 2K bytes.
If the logic on the NAND gate is modified as in fig 7.3 ,the address range will be
0000 0000 0000 0000 0000
to
0000 0000 0111 1111 1111
i.e. 00000 to 007FFH .ie, 0 to 2047 bytes ,which is 2K bytes.
7.2.1ADDRESS DECODING CONCEPTS

• Thus the basic idea of address decoding is to decode the extra unused address
lines of the processor to specify the address range.
• When more chips are to be interfaced, decode the extra address lines to a different
range for each group.
• Any logic /logic gate can be used to perform address decoding .From the address
decoder output ,the right logic value should be obtained to turn the chip on .Thus
the ‘select’ pulse obtained from the address decoding logic can be high or low
,depending on the requirement of the chip select pin of the memory chip.
• In general , address decoders can built using:
– Random logic (simple gates)
– Block decoders (e.g.. 2×4 , 3×8 … etc)
– Programmable Logic (PLAs,CPLDs, FPGAs, … etc.)
The first two types of address decoders will be discussed in detail here .The last type
follows the same principle –only ,the devices used are ‘programmable ‘ or even ‘re-
programmable’ .This brings in more flexibility to the design .The design of the address
decoder is then done using advanced design techniques involving hardware description
languages and CAD tools . This is beyond the scope of this book and hence is not
covered here.
Example 7-3
Design an address decoder using OR logic for a 32K x 8 RAM .Find the address space of
this memory chip.
Solution:
Since it is a 32K RAM , it has 15 address lines . Thus the lower 15 lines of the address
bus of the processor is connected to the address lines of the RAM .The upper 5 lines A15
– A19 are used for address decoding . Here the lines are given as input to the OR gate .
When the address on the address bus corresponds to A15 to A19 being all at logic 0 , the
decoder gives the SELECT pulse to the CS pin of the memory chip and thus it is
selected.
32K x 8
A0 D0
ADDRESS BUS RAM DATA BUS
A14 D15
CS
A19 SELECT
A15
Fig 7.4 Address decoding using OR logic
The lowest address is thus

0000 0000 0000 0000 0000
and the highest address is

0000 0111 1111 1111 1111
The address range of this memory chip is
00000 to 07FFFH .
Example 7-4
Find the address space of the following chips with the address decoding circuitry as
shown in the figure7.5a and b .
i) 8K x 8 EPROM
ii) 8K x 8 RAM
+5V
o
A0 A0 PGM A0 A0
EPROM RAM
8Kx8 D0 D0 8Kx8 D0 D0
A12 A12
A12 D7 A12 D7
D7 D7
OE CS OE WE CS
A19 o
A18 o o
A19
A17 o
SELECT
A o
18 A16
o o o
A17 A15
SELECT
o o
A14
A16
A15
A13 o
A14 o
A13
Fig 7-5 a EPROM with address decoder Fig 7-5 b RAM with address
decoder
Solution:
Both the memory chips are of 8K capacity .Hence they have 13 address lines .The
remaining 7 lines of the processor system bus are used for address decoding.
i) In Fig 7-5 a, for the EPROM chip to be selected ,the values of A19 to A13 are
to be
1111 101 .Thus the lowest and highest addresses in the chip are
1111 1010 0000 0000 0000

and
1111 1011 1111 1111 1111
i.e. FA000 H to FBFFFH.
ii) In Fig 7-5 b, for the RAM chip to be selected , the values of A19 to A13 are
0001 111. Thus the lowest and highest addresses in the chip are
0001 1110 0000 0000 0000
and
0001 1111 1111 1111 1111
i.e. 1E000 to 1FFFFH .
7.2.2 ADDRESS DECODING USING BLOCK DECODERS

A very popular decoder is the three to 8 decoder (74LS138) whose block diagram is
shown in Fig 7.6a
A Y0 o
Select
B Y1 o
Inputs 7
C Y2 o
4
L Y3 o
S Y4 o
1 Y5 o
G2 A 3 Y6 o
Enable 8
G2 B Y7 o
Inputs
G1
Fig 7.6a Functional block diagram of the 3 to 8 decoder 74LS138
Inputs
Enable Select Outputs
*
G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X H H H H H H H H
L X X X X H H H H H H H H
H L L L L L H H H H H H H
H L L L H H L H H H H H H
H L L H L H H L H H H H H
H L L H H H H H L H H H H
H L H L L H H H H L H H H
H L H L H H H H H H L H H
H L H H L H H H H H H L H
H L H H H H H H H H H H L
Fig 7.6b Decoding Table of 74LS138
Note: G2* =G2A and G2B
The output lines are active low and depending on the selection inputs , one output line
alone will be active . To enable the decoder chip ,it must be ensured that G2 A and
G2 B
are at logic level 0 and G1 is at logic 1. The decoding table of the chip is shown in Fig
7.6b
Consider that a 1K x 8 RAM chip uses a 3 to 8 decoder for memory decoding .The RAM
has 10 address lines .Thus the remaining 10 lines of the processor address bus can be
used for decoding . Let us calculate its address space .
Consider a hardware connection as shown in Fig 7-7
A10
A11
A12
1 1 0
A13
A B C CS
A14 o G2A 7 Y3 o
4
L RAM
A15 S
o G2B
A16 1 1K x 8
3
A17
G1 8
A18
A19
A0-A9
Fig 7.7 Address decoding of a RAM using a block decoder
In this ,the address linesA0 to A9 ,from the address bus of the processor are directly
connected to the address lines of RAM .The logic on these lines can vary from 00 0000
0000 to 11 1111 1111 .
The remaining 10 address lines of the processor are used for address decoding .
Thus we see them connected to the pins of the decoder .To enable the decoder ) G 2 A and
G 2 B must be 0,and G1 must be 1. Also ,to enable Y3 , CBA must be 011 .
Thus the logic on the lines from A19 to A10 should be
1111 1111 10 .
Thus the upper and lower range of the address is as shown in the table .
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
The address range is

1111 1111 1000 0000 0000
To
1111 1111 1011 1111 1111
i.e. FF800H to FFBFFH
Subtracting FF800H from FFBFFH ,we get 3FFH which is 1023 which means that there
are 1023 +1 addresses on this chip..
Thus there are 1024 (1K)byte locations in the chip.
Example 7.5
The figure shows a RAM and a ROM connected to an address decoder ,which is a 3 to 8
decoder.
Find the address space of each of these chips.
A16 A17 A18

A0 – A15 ROM
64K x 8
A B C
CS
SELECT
A19 G1 Y1 o
G2A
G2B Y4 o
A0 – A15 RAM
64K x 8
SELECT
CS
Fig 7.8 Address decoding of a RAM and ROM using a 3 to 8 decoder
Solution: Only 4 lines of the address bus are to be used for address decoding, as the
remaining 16 lines are to be connected to each of the 64K memory chips .
For the ROM ,A19 to A16 are to be 1001 ( A19 =1,CBA=001).
.Thus the address range of this chip is
90000H to 9FFFFH. Similarly for the RAM , A19 to A16 are to be 1100
(A`9=1,CBA=100) . Thus the address range of this chip is
C0000H to CFFFFH.
7.2.3 PARTIAL ADDRESS DECODING

In the hardware connection between a memory and a processor ,the lower order address
lines are connected directly to the memory address lines ,and the higher order lines are
used for addressing .We find that in all our discussions so far the addresses generated are
unique and create no ambiguity. This is also called exhaustive decoding.
But sometimes, to reduce the hardware used , only some of the upper address lines are
used for decoding and this is called partial address decoding. This may be made use of, if
it is sure that the system will need much less memory than the full 1MB of the address
space .
A0 -A13
16K x 8 16K x 8
RAM ROM
CS CS
o
A14
Fig 7.8 Partial address decoding
See Fig 7.8. Here two 16 KB memory chips are decoded using just the condition of the
A14 line .For the RAM ,A14 should be 0 and for ROM A14 should be 1 for the respective
chips to be enabled .The address lines A15 to A19 are don’t cares ,which means that each
of these chips can be accessed using a number of different addresses which will map to
the same physical location. In effect ,this causes ‘foldback memory ‘ or ‘multiple-mapped
memory’ to exist . Suppose we try to read from the lowest RAM location .We use the
physical address 00000 .But the same data can be read using an address F8000H or
E0000H .In fact 32 different addresses can be used to read this data .This is because 5
bits of the address i.e. A15 to A19 ,are don’t cares ,232 =32 .
Thus this is the amount of foldback memory that exists.
Does this cause any problem? Not really ,but if the memory of the system needs to be
expanded ,the hardware will have to be modified .As a rule ,partial address decoding is
perfectly safe for a small system which does not need any memory expansion.
Example 7.6
Draw a decoding circuit using partial decoding for a RAM and EPROM each of size 8K
x 8 .For decoding use only the address lines A13 and A14 . What is the size of its
foldback memory?
A0 -A12
8K x 8 8K x 8
RAM EPROM
CS CS
A14 o o
A13 o
Fig 7.9 Partial address decoding using two address lines
Solution:
For the RAM ,it is mandatory to have only the address lines A13 and A14 to be 00. The
addresses can vary as shown below. Since 5 address lines are don’t cares ,there are 32
different addresses with which each location can be accessed.
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
X X X X X 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
For the EPROM ,it is only mandatory to have the address lines A13 and A14 to be 11.
The addresses can vary as shown below. Since 5 address lines are don’t cares ,there are
32 different addresses with which each location can be accessed.
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
X X X X X 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
X X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
7.3 MEMORY BANKS

8086 has a 16 bit memory bus –which means that data transfer can occur at a maximum
rate of 16 bits (one word ) per bus cycle. But sometimes only a byte needs to be
accessed. This means that the processor must have both options –both byte and word
transfer must be possible.
MEMORY-1 MEMORY-2
Address Bus
Address Bus
D0 –D7 D8 –D15
Fig 7.10: 16 bit memory realized using two 8 bit memory chips
We know that for a word transfer , two byte locations must be accessed –i.e. two
addresses are actually needed
Keeping these concepts in mind, let us see how memory is organized for 8086 .A 16 bit
data can be obtained by accessing two memory chips in parallel each having 8 bits each
of the word. See Fig 7.10 . This is the way memory is organized in 8086 .A 16 bit word is
obtained as the concatenation of two bytes in two ‘memory banks’. i..e. memory is
organized as two banks –one, the upper bank or high bank with the data corresponding to
the upper byte D8-D15 , and the other ,the lower bank or low bank which has the data
lines D0-D7. The upper bank is also called the odd memory bank,because it has the odd
addresses mapped to it –in the same way ,the lower bank is called the even bank .Let’s
how this works out .
High bank (selected Low bank (Selected

by BHE ) by A0)
FFFFF FFFFE
FFFFD FFFFC
8 Bits D15 –D8 8 Bits
D7 –D0
Odd Address Even Address
00003 00002
00001 00000
Fig 7.11 Memory banks of 8086
See Fig 7.11 .Remember that a 16 bit word has one byte with an odd address and one
byte with an even address .If a byte alone is to be accessed ,it may be in the odd bank or
even bank .Thus for reading /writing a byte ,only one of the banks is to be accessed
,but to access a word ,both memory banks have to be accessed .In the second case, the
byte in the given logical address and the byte in the next address are accessed .For
instance ,if the instruction is MOV AX ,[0002] the logical addresses involved are 0002
and 0003 –one byte in the even bank ,and one byte in the odd bank . For an instruction
MOV AX,[0001] the addresses are 0001 and 0002 –again ,both banks have to be
accessed to get the complete word.
How are the two banks differentiated.? An even address implies that the LSB of its
address i.e. A0 is low . Thus , A0 can be used to enable the even bank .To enable the high
(odd) bank ,8086 generates a signal BHE (Bus High Enable)which goes low
whenever the addressed data is in the high (odd) bank.
In Fig 7.12, see how these two signals are used along with the address decoder output ,to
enable the two banks independently . BHE is enabled if and only if the address on the
address bus is for accessing a byte in the high bank. That is why it is designated ‘BUS
HIGH ‘ enable.
A0 is frequently called ( BLE} (Bus Low Enable)because it used to enable the low bank.
.
Fig No 7.12 ,shows a case when two 32 K x 8 RAMs form the16 bit memory. . Thus
the total memory is 64K x 8 bytes. A 32 K RAM needs 15 address lines . Of the 20
address bits from the address bus of the processor , A0 is used to enable the even bank..
A1 to A15 are connected to the address pins A0 to A14 of each RAM chip. The rest of
the address lines are used for address decoding . A0 and BHE are used for selecting
each of the banks separately
A0
BHE
A16-A19
Address
Decoder
CS CS
RAM RAM
32K x 8 32K x 8
Address Bus A1-A15
LOW HIGH
(EVEN) (ODD)
BANK BANK
D0 –D7 D8 –15
Fig 7.12 Memory banks with the respective bank enable signals ,along with the
decoder
Address Typical instruction Data type BHE A0 Bank No of

accessed machine
cycles
(even) MOV AL, [0000] byte 1 0 Low 1
(odd) MOV AL,[0001] byte 0 1 High 1
(even) MOV AX,[0000] word 0 0 Both 1
(odd) MOV AX,[0001] odd byte 0 1 High I cycle
even byte 1 0 Low II cycle
Table 7.2 Status of control signals for memory bank access

Now see Table 7.2 and note how and when BHE goes low.
What emerges from the table is that , for byte access , BHE goes high if the referred
byte is in the high (odd) bank .When a word whose logical address is even, both A0
and BHE are low simultaneously .Hence for the reading or writing of such a word,
only one machine cycle is needed.
7.3.1 ODD ADDRESSES WORD

For accessing a word whose address is odd ,two machine cycles are expended.
See the example instruction MOV AX,[0001] in Table 7.2 .This means that the effective
addresses to be accessed are 0001 and 0002 .When the address 0001 ( i.e. physical
address corresponding to this) is placed on the address bus ,A0 is not low .So only the
upper bank address is accessed in this machine cycle .Only one byte is read in this
machine cycle. To get the next byte from the even bank ,one more machine cycle must be
used
This is why it was mentioned (Section 6.6) that for accessing a word operand from an
odd location ,an extra machine cycle machine time has to be added to the instruction
cycle time. Thus it is advantageous (in terms of speed) to align all words at even
addresses. Many optimized assemblers do this automatically .Otherwise, there is a
directive named EVEN which does this.
Take the case when the data segment has 7 bytes and a word .The bytes are stored in
location 0000 to 0006 .Obviously ,the word will be aligned at the next address, which is
odd. If the EVEN directive is used ,the location counter is incremented by 1 ,and the
word is stored at location 0008 .This is illustrated in the following data segment
definition.
.DATA
NUMS DB 7 DUP(05)
EVEN ;increments location counter to 0008
WDR DW 2345H
But this obviously wastes one byte space, and memory is fragmented But this situation
cannot be avoided if speed is to be optimized.
7.3.2 WHY MEMORY BANKS ?
Thus we see that arranging memory to be in two memory banks causes an additional
burden. Then why is the memory system designed this way ?
What is being attempted is that ,when a byte alone is to be accessed ,only the bank in
which that byte resides , should be enabled –the other bank should remain disabled .
What is the problem if both the banks are enabled for any and every access?
The answer is that there won’t be any problem in case of a read operation , but it may
cause havoc for a write operation .See the following cases.
MOV AL,[0000]
Note the above instruction which initiates a read cycle. .It is the case of reading a byte
.Only the even (low) bank need be enabled to read .But even if the high bank is also
enabled ,it doesn’t matter .The data present on the lines D8 to D15 will not be used by
the processor .It takes into AL , only the data on lines D0 to D7 and ignores the data on the
upper bus.
But the writing process creates a problem.

Observe the case of the following write instruction .
MOV [0000],AL
This should cause only the even bank to be enabled . If the odd (upper) bank also gets
enabled ,the logic levels on the data lines D8 –D15 will get written onto the enabled
location in the upper bank , which is not admissible. Thus when a ‘byte ‘ alone is to be
written into memory ,it is important to ensure that only one of the memory banks is
enabled .
7.3.3 USING SEPARATE WRITE STROBES

Another approach is used to enable memory banks ,and it is by generating separate write
strobes.
Now that the problem has been identified to be associated with ‘writing ‘ ,there is another
way to solve it, and it is by generating separate write strobes.
BHE HWR
MEMWR
A 0 ( BLE} LWR
Fig 7.13 Using separate write strobes
We can use the logic shown in Fig7.13 . When there is the necessity to write a byte to
the high order (upper)bank , only the HWR (High write ) signal will be enabled –
similarly for writing a byte to the lower bank ,only that bank will be enabled ,but for
writing a word , both banks get enabled . Only the write control signal is taken into
consideration- reading unwanted data is not a problem as the processor takes from the
data bus ,only the byte that it needs.
In this scheme, the LWR and HWR signals are applied to the WE pins of the
respective memory banks only . Separate bank select signals from the address decoding
circuitry is not used. .
7.3.4 MEMORY MAP OF IBM –PC

Table 7.1 shows the memory map of IBM PC –i.e. the first version of the PC
manufactured by IBM with the 8088 processor ,which has a total memory address space
of 1 MB .
Address range Size Type Allocation

00000 to 640K RAM User RAM –with some areas with special
9FFFFH allocations like , 1 K (00000 to 003FFH)for
interrupt vector table, and
some portions for storing BIOS and DOS
parameters ,operating system etc
A0000H to 128K VDR Video display RAM with portions allocated for
BFFFFH video buffers and other video applications
C0000H to 192K ROM Memory expansion area for ROM
EFFFFH
F0000H to 64K ROM BIOS ROM , hard disk and other peripherals’
FFFFFH ROM
Table 7.3 IBM PC memory map

For a 4GB (FFFFFFFFH) memory of the current x86 PC, the same memory mapping is
followed, with RAM at the lower end and ROM area at the upper end.
7.4 I/O ADDRESS DECODING

It was mentioned in Chapter 5 that there are two schemes for I/O port interfacing .The
simpler scheme is ‘memory mapped I/O ‘ ,but this causes I/O to encroach on the memory
address space . Hence most systems prefer the other scheme which is designated as
‘Isolated I/O’ ,Peripheral I/O or I/O mapped I/O .
We will confine our discussion to this scheme alone.
Even though our processor has 20 bits for address ,I/O uses only 16 bits .Thus I/O port
addresses can range from 0000 to FFFFH –i.e. the total I/O space is only 64K .i.e. we can
use 65,536 different I/O addresses .But since the instructions for input (IN) and output
(OUT) are separate , we can have 64 K input ports and 64K output ports .This is actually
quite a lot, practically .
Input Ports
8 Data in
0
8 Data bus
Data out
6
Output Ports
Fig 7.14 Input and output ports connected to the 8086

Now recollect that ports with 8 bit port addresses use ‘fixed port addressing’ ,while
port addresses beyond that have to use the ‘variable port addressing scheme’. Another
point to keep in mind that any port can have a 8 bit or 16 bit data bus .
FFFFH
Variable port addressing
FFH
Fixed port addressing
0000 00
Fig 7.15 Schemes of port addressing
7.4.1 OUTPUT PORTS

Output ports use the instruction ‘OUT’ for writing into it .Then the data in the
accumulator (AL or AX) gets written into the output device. An output device may be as
complex as a video display or as simple as LEDs which have to lighted up .
Data from the processor is sent to an output port during the I/O write cycle .This data
will be available on the data bus only until the end of a machine cycle. For the output port
to be able to use this data, it must be latched .Thus a latch is mandatory for an output port
set up.(For memory ,there are latches inside the chip).Fig 7.16 shows a basic output port
.
Requirements of an output port
i) To identify /select the specific device , an address decoder should give
a select pulse .
ii) To read from the output device ,the IOWR signal must be active.
iii) When both the above two conditions are true, the data on the data bus
is latched
to the output port.
iv) All the above activities occur during an I/O write cycle.
Output
Device
Address Select CLK

Address Bus Decoder o
LATCH
Data Bus
IOW System
Data Bus
Fig 7.16 Basic output port setup
Example 7.5
Design a system with 8LEDs connected to the lower 8 bits of the data bus of the 8086
data bus.
The LEDs must switch ON and OFF with a delay of 1 second between each switching
action.
Solution:
Fig 7-17 shows the hardware setup .
Q0
7
D0 4
D0 L
Data Bus of 8086 S 8 LEDs
D7 3
D7 7
3 R
G Q7
OC
A0 o
A1 o
A2 o
A3 Select
A4
A5
A6
A7
o
IOW
Fig 7-17 Output port with 8 LEDs interfaced to it
i) The diagram with the address decoder ,the select pulse and the IOW signal is
shown .The address decoder gives a high select pulse . This is ANDed with
the inverted IOW pulse, and applied to the G pin of the octal transparent
latch 74LS373 (Refer Section 6.1.4).The G pin needs a high level pulse to
latch the data on its D inputs to its Q outputs . OC must be strapped to ground
to enable the output pins of the latch.
ii) Current limiting resistors are connected to the cathodes of the LEDs
iii) The address decoder specifies an 8 bit address of F8H for the port.
iv) The program for switching the LEDs ON and OFF is
STRT: MOV AL,0FFH ;data to light up all the LEDs

OUT 0F8H,AL ; transfer it to the output port
CALL DELAY_1SEC ;call the delay procedure
MOV AL,00 ;data to switch off the LEDs
OUT 0F8H,AL ;transfer it to the output port
CALL DELAY_1SEC ;transfer it to the output port
JMP STRT ;repeat continuously
v) For the delay procedure refer Example 6.3..
7.4.2 INPUT PORTS
Input ports use the IN instruction to give data to the processor which is received in the
accumulator of the processor (AL or AX) . An input port requires a tri-state buffer along
with it to ensure that is isolated from the bus when it is not selected. A simple switch can
be an input port , and the alphanumeric keyboard used in PCs is also an input port.
Fig 7.18 shows a basic input port .
System Data
Bus
SELECT TSB
Address E
Address Bus Decoder
Input
Device
IOR
Fig 7.18 Basic input port

Requirements of an input port
i) To identify /select the specific device , an address decoder should give a select
pulse .
ii) To read from the input device ,the IORD signal must be active
iii) When the above two conditions are true, the corresponding tri-state buffer gets
enabled and data is transferred to the processor.
Taking into consideration all these requirements ,let us design a system with two sets of
switches acting as two input ports. The tri-state buffer 74LS244 is used. This has two
active low enable inputs 1OE and 2OE .When both of them are low ,data at the A inputs
appear at the at the Y outputs. But if the enable pins are high ,the output is tri-stated.
1OE 1 20 VCC
1A0 2 19 2OE
2Y0 3 18 1Y0
1A1 4 17 2A0
2Y1 5 16 1Y1
74LS244
1A2 6 15 2A1
2Y2 7 14 1Y2
1A3 8 13 2A2
2Y3 9 12 1Y3
10 11 2A3
GND
Fig 7.19 Functional pin diagram of the octal tri-state buffer 74LS244
Example 7.6
Find the addresses of the two input devices shown in the figure and write a program to
read data from each of these ports and move it to some other registers.
Solution:
i) Two sets of 8 switches S0 to S7 are connected to the data bus through two
tri-statebuse and this setup functions as two input ports .
ii) The address of the ports are 8 bit ,as only address lines A0 to A7 have been
considered for decoding ,The address of the first port is 7EH and that of the
second is 3EH.
iii) The address on the address bus decides which of the input ports get selected .
The tri-state buffer ensures that the port which is not selected is isolated from the bus.
iv) The program for inputting data from each of these ports is
STRT: IN AL ,3EH ;take in data from Port2

MOV BL, AL ;move data to BL
IN AL, 7EH ; take in data from Port1
MOV DL ,AL ;move data to DL
Thus after reading both ports , the switch settings are available in BL and CL.
This data can be used for processing and/or display
TSB-1
S0
7 Y0
4 D0-D7
Y7
L
S
2
S7 4
4
Port-1
o 1OE 2OE
SELECT
o
IOR
o
TSB-2
S0 Y0
7
4
Y7
L
S
2
S7 4
Port-2 4
1OE 2OE
A0 o
A1
A2 SELECT
A3 o
A4
A5
A6 o IOR
A7 o
Fig 7.20 Two sets of switches acting as two 8 bit input ports
7.4.3 DECODING 16 BIT I/O ADDRESSES

We have used 8 bit addresses so far for I/O devices . But personal computers use 16 bit
addresses .as well .In that case ,only the decoding circuitry changes .Address lines A0 to
A15 should be used by the address decoder to generate the device select pulse. The
other point to remember is use ‘variable port addressing ‘ when writing I/O instructions
for ports with 16 bit addresses.
7. 4. 4 PORTS WITH 16 BIT DATA BUS
So far we have discussed only I/O ports with 8 bit data bus. But 16 bit data bus is also
possible for I/O ports .What becomes different then ?
The answer is that ,the situation is similar to the case of memory banks .Recollect the
concept of memory banks .If each of the 16 bit ports need to be accessed as two 8 bit
ports as well, we have to have 8 bit I/O banks . So we can have I/O banks too ,with 8 bits
in the upper bank and 8 bits in the lower bank .To read a word ,both banks can be
enabled ,by using both A0 and BHE bits .
Fig 7.21 shows the upper and lower I/O banks .Note that here the addresses can have only
a maximum size of 16 bits, while for memory ,the addresses are 20 bits.
ODD BANK EVEN BANK

ENABLED BY BHE ENABLED BY A0
HIGH I/O LOW I/O
BANK BANK
0005
0003 0004
0001 0002
D15 D8 D7 D0
Fig 7-21 I/O memory banks
Most of the I/O ports used for PCs have 8 bits wide data , but there are 16 bit wide ports
like video and analog to digital conversion ports etc . If a port is .by definition , a 16 bit
wide port ,use of separate bank select signals are not needed-the port can be selected
directly by the address decoding and the I/O read/write signals. That is because data is
always read or written as a word, and byte access is not necessary.
1. Memory mapped I/O causes I/O space to encroach on the memory

address space of the processor.
2. Active low control signals prevent accidental triggering by noise voltages
or open connections.
3. 74LS138 is a very popular 3 to 8 decoder.
4. The number of locations in a memory chip is 2N where N is the number of
address lines of the chip.
5. Memory is always organized as ‘banks’.
6. The BHE signal goes low when the addressed byte is in the upper bank
of memory.
7. The LSB of the address bus i.e..A0 is used to enable the low bank of
memory.
8. Memory chips have tri-state buffers and latches inside the chip.
9. All input ports need a tri-state buffer to connect it to the system bus.
10. All output ports need a latch to keep the outputted data ,until it is changed
by the next OUT instruction.
11. An I/O address can be 16 bits in size ,in which case ‘variable port
addressing ‘ is necessary for writing I/O instructions.
QUIZ
1. How many address lines does a 256K memory chip need?
2. Name the important pins in a typical RAM and explain the function of
each.
3. Find the numbers of two standard ROM chips and two EPROM chips ,
along with the way the chips are organized(how many address and data
lines).
4. Why are active low signals preferred for use as control signals?
5. What is meant by the term ‘address decoding’ with respect to memory as
well as I/O devices?
6. Why is memory organized in ‘banks’?
7. Why is the address line A0 also designated as BLE ?
8. Why are separate write strobes used for memory banks ,but not read
strobes?
9. Whenever LEDs are connected to the data output lines ,it is preceded by
latches .Why?
10. What is the range of address space for I/O in an 8086 based system?
EXERCISE
1. Design an address decoder for two RAM chips and two ROM chips each
organized as
1K x 8 chips. Use gates for the decoding circuitry and specify the address range
of each chip.
2. Repeat the above problem using the chip 74LS159 (2 to 4 decoder) as address
decoders.
3. Using a 3 x 8 decoder , design the decoding setup for eight RAM chips each of
size
8Kx 8 .Indicate the address space of each chip.
4. For the following (Fig 7.22a and b)decoding circuitry , find the address range of
the
memory addresses .
A19 O
A18
A17
A16 O
A15
A14 SELECT
A13
Fig 7-22 a
A19 O
A18 O
O
A17
A16 O
SELECT
A15 O
A14 O
Fig 7-22 b
5. .Design a memory system using partial address decoding for 4 RAM chips of size
1K x 8 each .
6. Draw a diagram using memory banks for a 16 K x 16 memory . Draw the decoding
circuitry ,and use write strobes for enabling the WE pins of the banks .
7. Design a I/O system in which there are two switches connected as an input port .
The status of these switches are to be read and fed to corresponding LEDs connected
at
the output side. Draw the hardware diagram for this and write a program to do this .
The address of the ports should be designed .
8. .Design an I/O system in which an input counter counts from 0 to 9 ,then goes back to
0
and then repeats .this sequence.. This count has to be displayed on a seven segment
LED.
Design the setup with input and output ports.
CHAPTER 8
THE INTERRUPT STRUCTURE OF 8086

In this chapter ,you will learn
• The concept of an interrupt.

• The interrupt response of the 8086.
• The way the interrupt vector table is organized for 8086.
• The idea of software interrupts.
• The operation of hardware interrupts of 8086.
• The significance of DOS and BIOS interrupts.
• How to access the video display by the use of BIOS interrupts.
• How to access the video display by direct writing/reading to the video RAM.
• How the PC’s keyboard and its controller are organized.
• How to use BIOS interrupts for keyboard access.
• The method of ‘hooking’ interrupts.
• How to write TSR programs.
Introduction
The word ‘interrupt’ brings to our mind many situations .It could be that we are at
home doing something rather important and interesting .and suddenly the doorbell rings .
There is no option but to go to the door and attend to the person who has interrupted us –
it may be that the visitor needs only a few minutes of our time –but it may also happen
that the visitor needs us to go out and do some errand for him .In either case ,the task we
were at ,is suspended temporarily We spend some time attending to the task requested by
the visitor after which we get back to the suspended task . This is a real life situation, and
if you think it over, it happens quite frequently –which means that ,being social beings
,none of us ever gets to do any of our tasks uninterruptedly
.
This is exactly the case with the processor too . Since the processor is connected to
various peripherals and also because it has various programs stored in its memory ,there
is very little chance of it being able to perform a single task without interruption .
Besides, performing a task only when ‘requested’ of it is actually the most efficient way
of using the capabilities of the processor.
Let us look at it this way . The keyboard is a peripheral connected to the processor –this
means that the processor expects a key to be pressed at any time .One option is for the
processor to do ‘polling’ .i.e. the processor continually keeps checking if a key has been
pressed .When a key press is detected ,the processor goes on to the task of identifying
the key . But if the processor is ‘polling ‘ for a key press ,it is obviously waiting and
doing nothing else . This is just a waste of processor time .A better way of organizing the
setup would be to let the processor do some task, and ‘interrupt’ it only when a key is
pressed . When a ‘key press’ interrupt is received, the processor performs the ‘interrupt
service routine’(ISR) which is the process of identifying the key that was pressed . This,
in essence ,is the philosophy of interrupts-and it helps utilize the processor with
maximum efficiency .
8.1 INTERRUPTS OF 8086: Now that we have accepted that interrupts are a part of
the normal working of a processor, let us see the interrupt processing mechanism of
8086.
8086 has hardware interrupts ,software interrupts and error generated interrupts .For the
three cases mentioned here ,the interrupting mechanism is different ,but the way the
processor responds is similar .So let us first have a look at the way 8086 responds to any
interrupt .The point to note is that ,after an interrupt request is processed, the processor
has to come back to its previous task which was left unfinished .Thus , an interrupt is not
very different from a CALL instruction in its philosophy ,but there are some differences
in the way it is handled and processed.
8.1.1 INTERRUPT RESPONSE OF 8086
After every instruction cycle ,the processor checks if any interrupt is awaiting service. If
it finds an interrupt request, and decide to acknowledge and service it , the response is
the following sequence of steps.
i) The flag register is pushed on to the stack.
ii) The interrupt flag is disabled (IF=0).
iii) The trap flag is disabled (TF=0).
iv) The CS register is pushed on to the stack.
v) The IP register is pushed on to the stack.
vi) Control is transferred to the location in which the corresponding ‘Interrupt
Service Routine’(ISR) is stored. This in effect ,would be a far jump.
vii) The program corresponding to the ISR is executed .The last instruction in the
ISR will be IRET .
viii) Then IP is popped off the stack.
ix) CS is popped off the stack.
x) The Flag register is popped off the stack.
xi) Control returns to the point at which it had left off.
Steps i to vi constitute the actions before getting to the interrupt service routine ,and
steps viii to xi occur on returning from the interrupt.
MAIN PROGRAM PUSHF
INT CLEAR IF ISR
CLEAR TF
PUSH CS
PUSH IP
CET ISR
POP IP
POP CS
POPF IRET
Fig 8.1 : Steps in processing an interrupt request

Let us go into the details of the steps in the above list . See Fig 8.1 .
A. The first step is part of the action of saving the ‘context ‘ of the current
program . First the flag status is saved in stack for later retrieval .This is
because the ISR may change the status of flags.
B. The second step is for ensuring that this interrupt routine does not get
interrupted by interrupts received on the INTR line .(We will see later that
for interrupts on the INTR line to get acknowledged, it is mandatory for
the interrupt flag to be set).
C. The third step is for ensuring that the program taken up does not stop after
the execution of each instruction (this happens if the Trap flag is set).
D. The fourth and fifth steps are for saving on stack, the address of the next
instruction in the current sequence,just as is done in the case of a far
CALL They will be taken back from the stack after the interrupt
processing is over. Both IP as well as CS are saved , because the new
program taken up will in a different code segment.
E. The sixth step is that of control being transferred to a location in a
different code segment .That is why it is designated as a ’far jump’.
F. The interrupt service routine which is the program to which the jump has
occurred ,will now be taken up for execution. The last instruction of an
ISR is an IRET instruction which will cause the reversal of the previous
actions
G. In the eighth and ninth steps ,the IP first and then CS are popped from
stack .Thus the address of the next instruction in the normal sequence is
back in the required registers.
H. In the tenth step, the flag register is popped off ,and thus the original status
of all flags is restored.
I. Finally ,instruction execution resumes from where it had been diverted .
8.1.2 INTERRUPT SERVICE ROUTINE AND INTERRUPT VECTOR

Now ,what is an interrupt service routine ? When an interrupt occurs ,the processor
suspends the execution of its current task and takes on another task as required by the
interrupting source .This program ,or routine as it may be called ,is designated as an
‘interrupt service routine’ .This routine corresponds to the request of a particular
source of interrupt and it is also called its ‘interrupt handler’ . This means that for
any interrupt that occurs ,there is a particular interrupt service routine (ISR).
Now where is this ISR available ? It is to be available in memory and must be
accessed on the occurrence of the specific interrupt . For that ,the address of the ISR
must be obtained .The address of an ISR is called its ‘interrupt vector’.
For an 8086 based system ,any address of code is in the form CS:IP .Thus the
interrupt vector for any interrupt has 4 bytes –two for the CS value and two for the IP
value . Thus ,if the interrupt vector for a particular interrupt is obtained ,control can
be transferred to the new location by using the new values of CS and IP specified as
the ‘interrupt vector’.
8.1.3 INTERRUPT VECTOR TABLE

It is obvious that the number of interrupt vectors in a system is the same as the
number of interrupts that the system can process. The 8086 has 256 interrupt vectors
and since each vector is specified by 4 bytes ,it implies that 256 x 4=1024 bytes (1K)
of memory are allocated to store the interrupt vectors .These 256 vectors are stored in
a table called the ‘Interrupt Vector Table’ in system RAM from locations 00000 to
003FFH i.e. 0000: 03FF .See Fig 8.2.a
CS INT 255 VECTOR
3FC IP
000B
CS
0008 IP INT 2 VECTOR
CS
CS
Fig 8.2a Interrupt Vector table of 8086
CS HIGH
CS LOW
IP HIGH
IP LOW
byte
Fig 8.2b A typical interrupt vector(4 bytes)
Each interrupt vector is numbered from 0 to 255 ,and as such , each interrupt is also
numbered in the same way .These numbers thus turn out to be what can be called as the
‘type numbers’ of the interrupts. Thus there are interrupts designated as Int 0, Int 1,Int
2……Int 255 . As is obvious from Fig 8-2a, these numbers show the position of the
corresponding interrupt vector in the interrupt vector table . Thus the vector of INT 0 ,is
the 1st entry in the IVT , that of INT 1 is the second entry … that of INT 6 is the 7th
entry and so on. Since each interrupt vector is 4 bytes long ,the memory location
corresponding to the vector of INT n is obtained as n x 4.i.e. for INT 1 ,the address of
the first byte of its vector is 1x4 =0004 ,for INT 0 it is 0000 etc as can be verified from
Fig 8.2a. In fact ,this is how the 8086 reacts to an interrupt with a type number n. It
multiplies the type number by 4 ,gets the address of its interrupt vector ,loads IP
and CS with these new values and starts executing the ISR it has thus located .
Example 8-1
Find the address (in the IVT) of the interrupt vector of INT 61H . Find the physical
address of the ISR corresponding to this interrupt if the vector is 0F00:9872 .
Solution:
The type number of the interrupt is 61H =97 in decimal.
The address of the interrupt vector is 97 x 4 =388 =184H.
Thus the interrupt vector is to be stored in the IVT in location 0000:0184 onwards.
For the ISR the CS value is 0F00H and the IP value is 9872H . The
part of the interrupt vector table which has these vectors stored is shown.
0FH
0186H 00
98H
0184H 72H
Address
Now ,how does the interrupt vector table get these entries?
It was mentioned in Chapter 6 that after’ power on’ ,the processor wakes up at the
address FFFF0H .This is the entry point to BIOS in ROM.(Ref Table 7.3)
BIOS contains a set of routines that provide device support. These routines check
,verify and initialize various devices ,and also establish two data areas, one of which is
the interrupt vector table from locations 00000 to 003FEH.
How is an interrupt different from a ‘call’?
An interrupt seems to perform actions similar to a far CALL instruction .It differs in a
few points ,however. An interrupt causes the flag register to be pushed on the stack in
addition to CS and IP values . It clears the trap and interrupt flags .The action of clearing
the flags is not associated with a CALL ,but is part of the automatic response due to an
interrupt. Also ,note that the ISR ends with IRET rather than a RET instruction. The
IRET instruction ensures that the flag register is also popped off the stack ,rather than just
the CS and IP.
8.2 DEDICATED INTERRUPT TYPES

Intel has dedicated certain interrupt types for specific applications directly related to CPU
operations..These are listed below:
8.2.1 INT 0 (DIVIDE BY ZERO ERROR):
The interrupt with type number 0 is dedicated to the ‘divide by zero ‘error. This interrupt
is an ‘error generated’ interrupt (also called an ‘exception’)s .On division ,if the quotient
register is not large enough to contain the quotient ,this interrupt is generated
automatically .Dedicating Type 0 for this case means that the corresponding interrupt
vector in the interrupt vector table is available at 0000:0000 (see Fig 8.2a) .Thus ,the
ISR for this error generated interrupt is to written in the address specified in the IVT
.What could be a possible ISR for this condition? One possibility is just to display a
message indicating ‘divide overflow’ and expect the programmer to correct his
data/program .Another possibility is to write as the ISR , a program which increases the
size of the quotient register ,so that the problem is corrected without user intervention. It
is up to the system designer to decide how the error handler is to be written.
8.2.2 INT 1 (SINGLE STEPPING ):

This type number is dedicated for ‘single stepping’ or ‘trace’ .Single stepping is an
important idea in debugging .During logical debugging of our programs ,we would like to
stop after the execution of each instruction and check the contents of registers ,memory
etc , We usually perform the action of ‘trace’ this way ..Intel has provided the ‘Trap ‘ flag
for this ,and this flag has to be set to let this happen . The ISR for viewing the register and
memory contents will be pointed by the vector of interrupt type 1.
But an important issue in this is how to set the trap flag .No such instruction has been
encountered so far.
Recollect the flag register configuration
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

U U U U OF DF IF TF SF ZF U AF U PF U CF
The Trap flag is the D8 bit of the flag register.

PUSHF ;push the flag register to the stack
POP AX ;pop it to AX
OR AX, 0000000100000000B ;OR it to set bit D8 i.e. TF
PUSH AX ;push AX to stack
POPF ;pop it to the flag register
This program segment sets the trap flag which causes INT 1 to occur .
Note that the Trap flag will be reset as part of the interrupt response ,so the ISR can
execute without stopping after each program line. But on going back to the mainline
program , when the flags are popped back ,the set condition of the Trap flag will be
retrieved ,and therefore single stepping can be continued for the mainline program until
the Trap flag is reset again.
8.2.3 INT 2 (NON MASKABLE INTERRUPT):

This interrupt corresponds to the vector(pointer) of the hardware interrupt NMI .When
an interrupt is received on the pin NMI (non maskable interrupt) of the processor , a type
2 interrupt occurs –this means that the ISR for NMI must be written in the address
pointed by the corresponding IVT content . We will deal with the NMI interrupt in detail
in Section 8.4.1 .
8.2.4 INT 3 (BREAKPOINT INTERRUPT) :
This is the breakpoint interrupt ,which is useful for de-bugging .We will need to set
breakpoints (stop after executing a group of instructions) and check the content of
registers and memory after executing instructions up to the breakpoint . Since setting
breakpoints is an important aspect of debugging, the breakpoint interrupt is special in that
it is a single byte instruction with the code CCH .
When we set breakpoints in debugging, what is really happening is that this code (CCH)
is inserted and getting executed at the position in the program where the breakpoint is set
.Just like in single stepping , the ISR will be written to dump the register and memory
contents on the video display .
8.2.5 INT 4 (OVERFLOW INTERRUPT):
This interrupt corresponds to the overflow flag .If the overflow flag is set , this interrupt
occurs ,but not automatically .An instruction INTO (interrupt on overflow ) must be
written after the program segment which is likely to cause the overflow flag (OF) to be
set .For example
MOV AL ,NUM1
ADD AL ,NUM2
INTO ; interrupt on overflow
The last line of this program segment can pass control to the ISR written for INT 3 ,if the
overflow flag is set by the result of the addition .Otherwise INTO acts as a NOP
instruction.
8.2.6 ALLOCATION OF INTERRUPT TYPE NUMBERS
Thus we see that interrupts with type numbers 0 to 4 have been allotted pre-defined
actions related to the CPU . Interrupts with type numbers 5 to 31 are reserved by Intel ,for
special uses and for future processors. As a matter of fact ,a few of them are used for
various hardware and I/O devices and some for error conditions of the higher processors
in the x86 family .Ref Table 8.1 The rest of the interrupts can be used by the user .But in
the PC , many interrupt types have been used by BIOS and DOS .We will see the list of
those interrupts and also use some of them.
INT type No Location in IVT (HEX) Application

0 0000:0000 Divide by zero error
1 0000:0004 Single Step Interrupt
2 0000:0008 Non Maskable Interrupt
3 0000:000C Breakpoint
4 0000:0010 Overflow
5 to 31 Reserved by Intel
32 to 255 Available to user
Table 8.1 : Interrupt vector table allocation
8.3 SOFTWARE INTERRUPTS
What it meant by a software interrupt? When an interrupt is initiated by an instruction, it
is called a software interrupt .The format of this instruction is
INT type number .
The type numbers can vary from 0 to 255 . This is a very important and interesting way
of using functions whose vectors are inserted into the IVT .
Thus the user can write any procedure as an ISR ,store it in some address in memory and
call it by using the instruction INT n .Before using it this way ,the user must however
insert the CS and IP values of his ISR in the IVT in the location corresponding to INT n.
Hardware interrupt service routines can be tested using software interrupts .Take the
case of NMI which is a hardware interrupt .This is vectored to location 0000:0008 ,i.e. it
corresponds to type number 2 . The routine corresponding to this hardware interrupt can
be tested by using the instruction INT 2 . In effect, a hardware interrupt on the NMI pin
and the software instruction INT 2 takes us to the same absolute address . Similarly the
effect of a ‘divide by zero ‘error can be simulated by writing the instruction INT 0 which
takes control to the ISR which has been written for the ‘divide by zero ‘ error.
What is the size of an interrupt instruction?

The format of an interrupt instruction is INT n where n can only be a byte .The opcode
for INT is ‘CD’ ,again a byte –for example INT 5 has the opcode CD 05 .Thus an
interrupt instruction is 2 bytes long ,except the breakpoint interrupt INT 3 which has the
code of just CC H. This feature is given to this interrupt because setting of breakpoints is
very frequently done in debugging ,and having one byte only means a lot of memory
space saving .
8.3.1 DOS and BIOS interrupt routines
We have used software interrupts in the form of the DOS function INT 21H . DOS has a
number of functions to access input/output devices, and we can use these functions by
knowing the interrupt type number .The absolute address of the function need not be
known to us .
Besides DOS interrupts, there is another set of functions for I/O access and this is
supplied by the system BIOS. BIOS stands for ‘Basic Input output System ’.A collection
of routines are available here too ,to access I/O .These functions are accessed by
interrupts with type numbers specified for a particular peripheral .Refer Table 8.2 .
Thus DOS and BIOS interrupts belong to the class of software interrupts and will be
discussed in greater detail soon.
8.4 HARDWARE INTERRUPTS

Now we will examine the hardware interrupt pins of 8086. There are two pins on which
interrupt requests can be received –they are the INTR pin and the NMI pin.
8.4.1 NMI: This is a positive edge triggered interrupt ,but it is also required to have a
duration in the HIGH state of more than two clock cycles .Any high going transition of
NMI is latched on-chip and will be serviced at the end of the current instruction .This is a
non-maskable interrupt ,in that it does not depend on the setting of the interrupt flag (IF)
.It cannot be masked or prevented from being activated.
It is a type 2 interrupt ,meaning that its vector is obtained from the corresponding
location in the interrupt vector table .NMI caters to applications of the highest priority
,like power failure.
8.4.2 INTR
This is the non-vectored interrupt pin of the 8086,which means that when an interrupt
request is received on this pin ,it doesn’t get automatically directed towards any
particular entry in the interrupt vector table .Another feature of this interrupt is that the
interrupt flag (IF) is required to be set for an interrupt request on the INTR line to be
honored. When the processor is reset ,all flags are found to be cleared and so is the IF .It
is to be ensured that the IF is set by the instruction STI if interrupts on the INTR lines are
to be acknowledged..
INTR is a high level triggered interrupt. To be responded to , the line should be high
during the clock period preceding the end of the current instruction .During any interrupt
response, further interrupts on the INTR line are blocked, because clearing the IF is part
of the processor’s interrupt response.
1st Machine Cycle 2nd Machine Cycle
T1 T2 T3 T4 T1 T2 T3 T4
ALE
INTA
FLOAT
AD0 –AD15 Type No.
Fig 8.3 Interrupt Acknowledge machine cycle of the 8086
Now let us see the sequence of actions following an interrupt request on this line.
On being interrupted ,the processor goes into an ‘interrupt acknowledge’ state which
causes two ‘interrupt acknowledge machine’ cycles to occur.
During the first machine cycle, the address /data buses are floated and the INTA
(interrupt acknowledge) pin goes low in T2 and remains low till T4 . This is an indication
for the interrupting device that its interrupt request has been accepted by the processor .In
the second machine cycle, once again the line INTA is low from T2 to T4 ,and then the
interrupting device places the ‘type number’ of the interrupt on the lower data lines (D0 to
D7 ),which comes out of the float condition. The processor accepts this number
,multiplies it by 4 ,and accesses the interrupt vector table at that location.
In Fig 8.3, the ALE signal is also shown .Actually ,this signal has no role in the
INTA cycle, but is included just to show that in the first T state of any machine cycle ,
the ALE signal is activated.
8.4.2.1 GENERATION OF A TYPE NUMBER

VCC
D00
D 1
7
8 D11
D 0
4 0
0 D22
D
D L 0
8 D33
D S 0
6 D44 0
D5 2
D65
D 0
4
D76
D 4 1
OE OE
INTA
Fig 8.4 Generation of a type number during the INTA cycle
Fig 8.4 shows a simple circuit which is capable of sending a ‘type number ‘ to the
processor .Consider an interrupting device interrupting the 8086 on its INTR pin. The
processor responds by lowering the INTA line. This signal is connected to the enable
pins of a tristate buffer (74LS244). Eight switches are connected to the input pins of the
TSB .When a switch is closed ,the line is grounded corresponding to a ‘0’ level on the
pin. When a switch is open ,it gets Vcc on it and hence is in the ‘1’ state .In the figure
,the switch configuration corresponds to 1000 0001 or 81H. This is because the first and
last switches are open ,and the rest are closed .When the enable pins (OE) of the TSB are
low (i.e. when INTA becomes low),the data at the input of the TSB is transferred to the
output of the TSB chip.
During the first Interrupt acknowledge machine cycle ,the address /data lines of the
processor are floated . This ‘interrupt acknowledge ‘machine cycle signals the
interrupting device that its interrupt request has been acknowledged ,and that it is to get
ready .In this cycle even though the type number appears on the output of the TSB , the
bus of the 8086 is in the high impedance state and so nothing happens. But during the
second machine cycle ,when the INTA line is lowered ,the lines D0 to D7 of the processor
are enabled , and the switch settings of the TSB are transferred to the data lines D0 to D7
of the 8086 ,constituting the type number . Thus it is understood that this INTR interrupt
is now vectored to type 81H.
Thus INTR is an interrupt pin with which an interrupt can be funneled to any location in
the IVT and thus facilitates flexibility for use in any application . It is also possible that
more than one device can place interrupt requests on this line ,and each of them may
have to be associated with different type numbers. All these necessitate the need of extra
hardware to manage the possible interrupts arriving on this pin from various peripherals
.This is done by a peripheral chip named Programmble Interrupt Controller (PIC ) 8259
,the details of which will be presented in Chapter 10.
The INTR pin along with the PIC is used in PCs for managing various hardware devices.
Can we consider the reset pin as an interrupt pin?

When the reset pin is activated ,the processor resets and control branches to the absolute
address FFFF0H .Thus reset has a particular pointer or vector –which is just the way an
interrupt functions. Thus RESET is sometimes included in the list of hardware interrupts
along with NMI and INTR .
For a PC, the process of resetting also occurs when the system is powered on .Let us note
some points regarding ‘power on’ .In fact ,the address FFFF0H is designated as the
‘power on reset vector’ .This address (FFFF0H) is in ROM and contains a far jump
instruction to the beginning of the BIOS chip power –on reset code . To find this vector
,go to command prompt C drive ,type ‘debug’ and get the contents of the reset location
.This is shown below.
C:\>debug
-dffff:0000
FFFF:0000 EA 5B E0 00 F0 30 36 2F-32 30 2F 30 35 00 FC 00 .[...06/20/05...
The first 5 bytes constitute the assembly code for the jump instruction i.e. JMP (EA)
F000:E05B. The next eight bytes were originally called the "RELEASE MARKER" by
IBM, as they always contain the release date of the code (which is 20th June 2005 for this
PC). See the ASCII code of this marker
30 36 2F 32 30 2F 30 35 i.e. 06/20/05.
8.5 PRIORITY OF INTERRUPTS

When many interrupts occur at the same time , which source gets its request honored
first? To resolve this matter, there in an inbuilt priority decided by the processor .The
order of priority is as follows
i)Internal interrupts and Software interrupts -highest
ii)NMI
iii)INTR -lowest priority.
Consider a case when the INTO ,NMI and INTR occur simultaneously .Because of the
inbuilt priority mechanism, the internal interrupt ( INTO ) will be taken up for servicing
first . One step in the interrupt response would be to disable IF .Hence INTR will not be
taken up now .However the NMI can interrupt the current ISR ,as its functioning does
not depend on the setting of the IF. Thus the NMI will interrupt the INTO ISR. .The end
result is that effectively NMI gets serviced before the internal interrupt .This is fine
,because NMI caters to highest priority .After the NMI ISR is processed ,the INTO ISR is
taken up ,and after it is done with ,the request on the INTR is dealt with .
8.6 INTERRUPT TYPE ALLOCATION FOR CURRENT PCs

The allocation of type numbers for the PC is shown in Table 8.2 .This will be our
reference when discussing video and keyboard interrupts.
Interrupt Type No(HEX) FUNCTION

0 CPU - Divide by zero (exception interrupt)
1 CPU - Single step
2 CPU – Non-maskable interrupt (NMI)
3 CPU - Break point instruction
4 CPU - Overflow
5 BIOS - Print screen
6 CPU - Invalid op-code
7 CPU - Math coprocessor not present
8 System timer interrupt (IRQ 0)
9 Keyboard data ready (IRQ 1)
A Reserved (IRQ 2) cascade from slave interrupt controller
B,C Hardware interrupt for serial communication (IRQ 3, IRQ
D Parallel port hardware interrupt (IRQ 5, LPT 2)
E Diskette controller hardware interrupt (IRQ 6)
F Printer hardware interrupt (IRQ 7, LPT 1)
10 BIOS - Software interrupt to use video
11 BIOS - Equipment check call
12 BIOS - Memory check call
13 BIOS - Software interrupt to use hard drive
14 BIOS - Software interrupt to use serial port
15 Not used
16 BIOS - Keyboard software interrupt
17 BIOS – Printer software interrupt
18 BIOS – ROM BASIC loader
19 BIOS – Bootstrap loader
1A BIOS – System and real time clock software interrupt
1B BIOS – Control-Break handler
1C BIOS – System timer tick handler
1D BIOS – Video initialization parameter table pointer
1E BIOS – Diskette initialization parameter table pointer
1F BIOS – Graphics display character bitmap table
20
DOS – Program Terminate
21 DOS – Function request services
TABLE 8.2 - Interrupt allocation for type numbers 0 to 21 in the IBM PC
1. Why are the interrupt and trap flags cleared as part of the interrupt response?
2. How many hardware and software interrupts can the 8086 support?
3. Explain the terms ‘Interrupt service routine’ and interrupt vector.
4. The hardware interrupt INTR is called a non –vectored interrupt .Why?
5. List the interrupts reserved by Intel.
6. Explain the sequence of actions that occur in an interrupt acknowledge cycle.
7. What happens if a number of interrupts occur at the same time?
8. DOS interrupts be used in TSR programs?
EXERCISE
1. Find the address in the IVT for the interrupts of types 102H and 200H.

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CHAPTER 1

THE ARCHITECTURE OF 8086

In this chapter you will learn

• The internal architecture of the 8086

1.1 INTERNAL BLOCK DIAGRAM OF THE 8086

1.2 THE EXECUTION UNIT

But registers constitute on chip RAM ,which is costly.

Register Set of 8086

Pointer and Index Registers

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Fig 1-3 : 8086 Flag register

Carry flag (CF)

Auxiliary Carry Flag(AF)

After computation ,AL will contain 0000 0011 and

The sum will be in BX which is the destination register.

Arithmetic Logic Unit

1.3 BUS INTERFACE UNIT

1.3.1 THE INSTRUCTION QUEUE

1.3.2 MEMORY SEGMENTATION

22236H Addressed Byte

Fig 1-3 Calculation of a physical address from the logical address

Fig 1-4 Segment Registers and Corresponding segments

1.3.2.2 The Code Segment and the Instruction Pointer

1.3.2.3 The Stack Segment and the Stack Pointer

Fig : 1.5 Stack and physical address of the top of stack

1.3.2.4 The Data Segment and Extra Segment

SEGMENT OFFSET REGISTERS FUNCTION

1. Segments begin at paragraph boundaries ,where a paragraph is 16 bytes.

1.4 ADDRESSING MODES

For computations in assembly language ,we need an opcode and operands .

4) Register Indirect Addressing

EA= { [BX] / [DI] /[SI]}

MOV AL,[BX] ; move into AL the content of the location whose

ii)This is also a case of direct addressing . The physical address is calculated as

iii)This is a case of register indirect addressing . BX is a pointer to the address 3400H

5) Register relative addressing

7) Relative Based Indexed Mode

ii) MOV AL,5[SI[[BP]

Sl No Addressing mode Effective address Segment

6 Based Indexed [BX] +[SI] DS

Key points of this chapter

1. Name the 8 bit registers of 8086.

2. Add the numbers 100 and 89 using the following instructions

In this chapter you will learn

A. ASSEMBLY LANGUAGE PROGRAMMING

2.1 The Assembly Process

In assembly language programming ,coding is done in symbolic language (called

2.1.1 Features of assemblers

2.1.2 Instructions and Directives

2.1.3 The Forward Reference Problem

A typical line in a program could be

BEGIN : MOV AX , COST ; move the content of the location COST to AX

2.1.4 Two Pass Assemblers

2.2 ASSEMBLERS FOR x86

2.2.1 Why MASM ?

2.2.2 ASSEMBLY LANGUAGE PROGRAMMING

2.3 Memory Models

. MODEL MODEL NAME

2.3.1 The Tiny Model

Let us now write a program using the tiny model.