Mitac 8050d

SERVICE MANUAL FOR
8050D
BY: Grass.Ren
Repair Technology Research Department /EDVD
Mar.2004
8050D N/B Maintenance
Contents
1. Hardware Engineering Specification ………………………………………………………………….. 3

1.1 Introduce ……………………………………………………………………………………………… 3
1.2 System Overview ………………………………………………………………………………………. 6
1.3 System Hardware Parts ………………………………………………………………………………… 7
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1.4 Other Functions …………………………………………………………………………………….…. 34
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1.5 Power Management …………………………………………………………………………………….
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2. System View & Disassembly ………………………………………………………………………….. 43
2.1 System View
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2.2 System Disassembly
c Setting c
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……………………………………………………………………………………. 46
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3. Definition & Location of Connectors / Switches 66
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4. Definition & Location of Major Component a 69
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5. Pin Description of Major Component………………………………………………………………….. 71
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5.1 Intel Pentium M (Banias) Processor
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5.2 Intel 855GM/GME North Bridge 75
6. System Block DiagramC

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5.3 Intel 82801 IDBM I/O Controller Hub 4 Mobile(ICH4-M) South Bridge
……………………………………………………….……………………….....
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7. Maintenance Diagnostics ……………………………………………………………………………….. 93

7.1 Introduction …………………………………………………………………………………………… 93
7.2 Debug Card …………………………………… ……………………………………………………… 94
7.3 Error code……………………………… …………………………………………………………….. 95
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Contents
8. Trouble Shooting ……………………………………………………………………………………..…. 98
8.1 No Power ………………………………………………………………………………………………. 99
8.2 Battery Can not Be Charged …………………………………………………………………………….. 104
8.3 No Display ………………………………… …………………………………………………………... 106
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8.4 External Monitor No Display ……………………………………………………………………………. 112
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8.5 Memory Test Error ……………………………………………………………………………………..
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8.6 Keyboard/Touch-pad Test Error ………………………………………………………………………...
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8.7 USB Port Test error……………………………………………………………………………………... 118
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8.8 Hard Disk Drive Test Error……………………………………………………………………………… 120
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8.9 CD-ROM Test Error ……………………………………………………………………………………. 122
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8.10 Audio Test Failure………………………………………………………………………………..….… 124
8.11 LAN Test Error ………………………………………………………………………………………..
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8.12 Modem Test Error…………… …………………………………………………………………..……
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8.13 Mini-PCI Test Error……….. ……… ……………………………………………………………….... 131
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8.14 Card Bus&Reader Test Error…………………………………………………………………………... 133
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8.15 IEEE1394 Test Failure ………………………………………………………………………………… 135
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9. Spare Parts List ………………………………………………………………………………….…..…... 137
10. System Exploded View ……………………………………………………………………………...….. 148
11. Circuit Diagram ……………………………………………………………………………………….... 149
12. Reference Material …………………………………………………………………………………..…. 183
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1. Engineer Hardware Specification

1.1 Introduce
The MiTAC 8050D model is designed for Intel Banias processor with 400MHz FSB with Micro-FCPGA package.
It can support Banias 1.5G ~ 1.9GHz/Dothan 2.0GHz and above.
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This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has
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standard hardware peripheral interface. The power management complies with Advanced Configuration and
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Power Interface (ACPI) 2.0. It also provides easy configuration through CMOS setup, which is built in system
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BIOS software and can be pop-up by pressing F2 key at system start up or warm reset. System also provides icon
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LEDs to display system status, such as AC Power indicator, Battery Power indicator, Battery status indicator,
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HDD,CD-ROM, NUM LOCK, CAP LOCK, SCROLL LOCK, RF on/off Card Reader indicator. It also equipped
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with LAN, 56K Fax MODEM, 3 USB port, S-Video and audio line in/out , external microphone function.
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The memory subsystem supports two expansion DDR SDRAM slot with unbuffered PC1600/PC2100 DDR-
SDRAM.
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The Montara-GME GMCH Host Memory Controller integrates a high performance host interface for Intel Banias
processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, Digital Video port
(DVOB & DVOC) interface, and Intel Hub interface Technology connecting with Intel 82801DBM ICH4-M.
The Intel ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio
Controller with AC97 interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers,
and Intel Hub interface technology.
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The MOBILITY M10 provides one of the fastest and most advanced 2D, 3D, and multimedia graphics
performance for notebooks. It’s architecture introduces the latest achievements in the graphics industry, which
enable the use of the progressive new features in upcoming applications, but without compromising performance.
ATIs support of support of DirectX® 9 features, highly optimized Open GL® support, and flexible memory
configurations allow implementations targeted at the gaming enthusiast, consumer, business and workstation
platforms.
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The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides
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32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications
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and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management
Interface (ACPI). S cu
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The VT6307L is a single chip PCI Host Controller for IEEE 1394-1995 Release 1.0 and IEEE 1394a P2000. It
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implements the Link and PHY layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0
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and 1394a P2000. It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high
performance data transfer via a 32-bit bus master PCEI host bus interface. The VT6307L supports 100, 200 and
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400 Mbit/sec transmission via an integrated 2-port PHY. The VT6307L services two types of data packets:
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asynchronous and isochronous(real time). The 1394 link core performs arbitration requesting, packet generation
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and checking, and bus cycle master operations. It also has root node capability and performs retry operations.
The RICOH R5C592 CardBus/Media Reader controller functions as a single slot PCI to Cardbus bridge and also
PCI interface smart card and MS/SD/MMC flash card reader. The R5C592 provide one Cardbus slot and all reader
interface may operate simultaneously.
The CH7011A is a display controller device which accepts a digital graphics input signal, and encodes and
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transmits data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide
variable voltage data port which supports five different data format including RGB and YcrCb. The TV-Out
processor will perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data
into any of the NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to
enable superior text display. Eight graphics resolutions are supported up to 1024 X 768 with full vertical and
horizontal underscan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create
VGA CRT with the input data.

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outstanding video quality. Support is provided for Macrovision and RGB bypass mode which enable driving a
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The W83L950D is a high performance micro-controller on-chip supporting functions optimized for embedded
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control. These include ROM, RAM, four types of timers, a serial communication interface, optional I²C bus
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interface, host interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system
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configurations, so that compact, high performance systems can be implemented easily.
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A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME,
Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus
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mastering IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled
power shutdown.
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Following chapters will have more detail description for each individual sub-systems and functions.
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1.2 System Overview
CPU Mobile Pentium-M Processor 1.5G ~ 1.9GHz/Dothan 2.0GHz and above

Thermal spec 35W TDP
Core logic Intel 855GME + ICH4-M chipset
VGA Control ATi M10
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System BIOS ST39SF040
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Memory DDR RAM : Apacer : 77.11021.460 Samsung 16*16 256MB 1st
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Apacer : 77.11021.580 Winbond 16*16 256MB 2nd
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A-DATA : 256MB
Video Memory Share memory 32Mb
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Clock Generator ICS 950812
TV
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ATi M10
IEEE1394
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VT6307L
LAN
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RTL8100C
Audio System
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PCMCIA + 4 IN 1 CARD ENE CB710
AC97 CODEC: Advance Logic, Inc, ALC655
Power Amplifier: TI TPA0212
Modem AC97 Link: MDC (Mobile Daughter Card) Askey: V1456VQL-P1(INT)
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1.3 System Hardware Parts
1.3.1 Intel Banias Processors in Micro-FCPGA Package
Intel Banias Processors with 478 pins Micro-FCPGA package.
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The first Intel mobile processor with the Intel Net Burst micro-architecture which features include hyper-pipelined
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technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced dynamic execution,
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advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2).
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The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications
including 3-D graphics, video decoding/encoding, and speech recognition.
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Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four
times per bus clock.
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Support Enhanced Intel Speed Step technology, which enables real-time dynamic switching of the voltage and
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frequency between two performance modes.
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1.3.2 Clock Generator
System frequency synthesizer: ICS950812 Programmable output frequency, divider ratios, output rise/fall time,
output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if
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system malfunctions. Programmable watchdog safe frequency. Support I2C Index read/write and block read/write
operations. Use external 14.318MHz crystal.
Provides standard frequencies and additional 5% and 10% over-clocked frequencies

Supports spread spectrum modulation: No spread, Center Spread (±0.35%, ±0.5%,or ±0.75%), or Down
Spread (- 0.5%, -1.0%, or -1.5%)
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Offers adjustable PCI early clock via latch inputs
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Selectable 1X or 2X strength for REF via I2C interface

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Efficient power management scheme through PD#,CPU_STOP# and PCI_STOP#.

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Uses external 14.318MHz crystal
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Stop clocks and functional control available through
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fidIGUI 3D Graphic DDR/SDR Chipset
1.3.3 Montara-GME GMCH
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Montara-GME GMCH IGUI Host Memory Controller integrates a high performance host interface for Intel
Banias processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP
4Xinterface, and Intel®’ I/O Hub architecture INTEL 82801DBM ICH4-M
Montara-GME GMCH Host Interface features the AGTL & AGTL+ compliant bus driver technology with
integrated on-die termination to support Intel Banias processors. Montara-GME GMCH provides a 12-deep In
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-Order-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D
Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for
the Intel Banias series based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory
controller to sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as
well as the multi I/O masters. In addition to integrated GUI, Montara-GME GMCH also can support external AGP
slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature Intel®’ I/O Hub
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architecture is incorporated to connect Montara-GME GMCH and INTEL 82801DBM ICH4-M together. Intel®’
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I/O Hub architecture is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB
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bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O
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Link layer, the Multi-threaded I/O Link Encoder/Decoder in INTEL 82801DBM ICH4-M to transfer data w/ 533
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MB/s bandwidth from/to Multi-threaded I/O Link layer to/from Montara-GME GMCH, and the Multi-threaded
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I/O Link Encoder/Decoder in Montara-GME GMCH to transfer data w/ 533 MB/s from/to Multi-threaded I/O
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Link layer to/from INTEL 82801DBM ICH4-M.
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An Unified Memory Controller supporting DDR266 DRAM is incorporated, delivering a high performance data
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transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP
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master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining
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the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The Montara-GME GMCH
adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by
organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.
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Features
Processor/Host Bus Support

Intel® Banias processor
2X Address, 4X data
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Support host bus Dynamic Bus Inversion (DBI)
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Supports system bus at 400MT/s (100 MHz)
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Supports 64-bit host bus addressing
8-deep In-Order-Queue
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AGTL+ bus driver technology with integrated GTL termination resistors and low voltage operation (1.05V)
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Supports Enhanced Intel® Speed Step TM Technology (EIST) and Geyserville III
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Support for DPWR# signal to Banias processor for PSB power management
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Memory System
Directly supports one DDR channel, 64-bits wide (72-b with ECC).
Supports 200-MHz and 266-MHz DDR devices with max of 2 Double-Sided SO-DIMMs(4 rows populated)
with unbuffered PC1600/PC2100 DDR(with ECC).
Supports 128-Mb, 256-Mb and 512-Mbit technologies providing maximum capacity of 1-GB with only x
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16 devices.
All supported devices have 4 banks.
Supports up to 16 simultaneous open pages.
Supports page sizes of 2KB, 4KB, 8KB, and 16KB. Page size is individually selected for every row.
UMA support only.
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System Interrupt
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Supports 8259 and Processor System Bus interrupt delivery mechanism
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Supports interrupts signaled as upstream Memory Writes from PCI and Hub interface
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MSI sent to the CPU through the system Bus
From IOxAPIC in ICH4-M

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Provides redirection for upstream interrupts to the System Bus
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Video Stream Decoder
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Improved HW Motion Compensation for MPEG2All format decoder (18 ATSC formats) supported
Dynamic Bob and Weave support for Video Streams
Software DVD at 60 fields/second and 30 frames/second full screen
Support for 720x480 pixel resolution DVD quality encoding at low CPU utilization
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Video Overlay
Single high quality scalable overlay and second Sprite to support second overlay
Multiple overay functionality provided via Arithmetic Stretch Blt
Direct YUV from Overlay to TV-out
Independent Gamma Correction
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Independent Brightness / Contrast / Saturation
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Independent Tint / Hue support
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Destination Color keying
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Source Chromakeying
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Maximum source resolution of 1920x1080 pixels
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Maximum overlay clock of 133 MHz/200 MHz provides a pixel resolution up to 1600x1200@ 60Hz or
1280x1024@ 85 Hz
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Analog Display Support 350 MHz integrated 24-bit RAMDAC that can drive a standard progressive scan
analog monitor up to 1800x1350 @ 85 Hz accompanying I2C and DDC channels provided through
multiplexed interface hot plug and display support
Dual independent pipe with single display support Simultaneous: Same images and native display timings on
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each display device
DVO (DVOB) support
Digital video out port DVOB with 165-MHz dot clock on 12-bit interface
Variety of DVO devices channel
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Compliant with DVI Specification 1.0, thereby providing support for a flat panel up to 2048x1536 pixel
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resolution, or digital CRT up to 1920x1080 pixel resolution
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1.3.4 I/O Controller Hub : INTEL 82801DBM c
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The INTEL 82801DBM ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers, the Audio Controller
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with AC 97 Interface, the IDE Master/Slave controllers, and Intel®’ I/O Hub architecture. The PCI to LPC Bridge,
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I/O Advanced Programmable Interrupt Controller, legacy system I/O and legacy power management
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functionalities are integrated as well.
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The integrated Universal Serial Bus Host Controllers features Dual Independent UHCI Compliant Host controllers
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with six USB ports delivering 480 Mb/s bandwidth and rich connectivity. Besides, Legacy USB devices as well as
over current detection are also implemented.
The Integrated AC97 v2.3 compliance Audio Controller that features a 7-channels of audio speaker out and HSP
v.90 modem support. Additionally, the AC97 interface supports 4 separate SDATAIN pins that is capable of
supporting multiple audio codecs with one separate modem codec.
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The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode
transfers up to 16 Mbytes/sec and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE
channels that sustain the high data transfer rate in the multitasking environment.
INTEL 82801DBM ICH4-M supports 6 PCI masters and complies with PCI 2.2 specification. It also incorporates
the legacy system I/O like: two 82C37 compatible DMA controllers, Channels 0-3 are hardwired to 8 bit, three
8254 compatible programmable 16-bit counters channels 5-7, hardwired keyboard controller and PS2 mouse
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interface(not use in MiTAC 8050 model), Real Time clock with 512Bytes CMOS SRAM and two 82C59
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compatible Interrupt controllers. Besides, the I/O APIC managing up to 14 interrupts with both Serial and FSB
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interrupt delivery modes is supported.
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The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2
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compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and
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power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for
Mobile processor.
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specific application. In addition, the INTEL 82801DBM ICH4-M supports Deeper Sleep power state for Intel
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A high bandwidth and mature Intel®’ I/O Hub architecture is incorporated to connect Montara and Intel
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82801DBM ICH4-M Hub interface together. Intel®’ I/O Hub architecture is developed
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1.3.5 VGA Control
Introducing MOBILITY M10

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The MOBILITY M10 provides one of the fastest and most advanced 2D, 3D, and multimedia graphics
performance for notebooks. Its architecture introduces the latest achievements in the graphics industry, which
enable the use of the progressive new features in upcoming applications, but without compromising performance.
ATI’s support of DirectX® 9 features, highly optimized OpenGL® support, and flexible memory configurations
allow implementations targeted at the gaming enthusiast, consumer, business and workstation platforms.
SMARTSHADER™ 2.0 — Advanced Shader Technology

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Provides complete hardware-accelerated support for the new DirectX® 9 programmable shader model,
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enabling more complex and realistic texture and lighting effects than ever before.
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Significant improvement over first-generation shaders introduced in DirectX® 8, with a much more
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powerful and intuitive instruction set.
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Offers full support for this feature in OpenGL® applications.
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MOOTHVISION™ 2.0 — Flexible Anti-Aliasing and Anisotropic Filtering
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2x/4x/6x full-scene anti-aliasing modes
Adaptive algorithm with programmable sample patterns
2x/4x/8x/16x anisotropic filtering modes
Adaptive algorithm with bi-linear (performance) and tri-linear (quality) options
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High Performance Memory Support
Incorporates support for DDR SDRAM/SGRAM.
Features key items from ATI’s third generation HYPER Z™ III technology that conserves memory
bandwidth for improved performance in demanding applications.
Dual Display Support

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Leading-edge technology, fully optimized with HYDRA VISION™, flexibly supports multiple
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combinations of notebook LCD, traditional CRT monitors, flat panel displays and TV.
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Features Dual Channel DVI support.
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230MHz LVDS transmitter supports LCD panels up to QXGA (2048x1536) resolution.
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Integrated 165MHz TMDS transmitter supports external flat panels up to UXGA (1600x1200) resolution.
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High performance DAC speeds of 400MHz.
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Features in Detail
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VIDEO Acceleration
M10 allows the integration of industry leading digital video features, including advanced de-interlacing
algorithms for unprecedented video quality and integrated digital TV decode capability. Includes
programmable,independent gamma control for the video overlay.
New FULLSTREAM™ technology removes blocky artifacts from streaming and Internet video and
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provides sharper image quality.
Integrated general purpose xDCT engine (capable of performing both forward and inverse discrete cosine
transform) and motion compensation (MC) support for the acceleration of MPEG encoding and decoding
as well as DV (digital video) encoding and decoding.
1.3.6 CardBus: CB710

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Features
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3.3V operation with 5V tolerant
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208-pin LQFP / 209-ball LFBGA package for CB710
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328-ball LFBGA package for CB720
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PCI Interface compliant with
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PCI Local Bus Specification, Revision 2.2
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PCI Bus Power Management Interface Specification, Revision 1.1
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PCI Mobile Design Guide, Version 1.1
Advanced Configuration and Power Interface Specification, Revision 1.0
CardBus Interface
Compliant with PC Card Standard 8.0Support Standardized Zoomed Video Register Model
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Support CardBay PC card interface
Smart Card Interface
Compliant with PC/SC Specification 1.0
Support ISO7816 T=0 and T=1 asynchronous communication protocols
Two power enable pins to support 5V and 3V smart cards
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Support programmable card clock frequencies
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Programmable F and D parameters to support different data rates
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One traffic LED pin.
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Secure Digital Interface
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Compliant with SD Memory Card Specification Version 1.0
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Support 4 parallel data lines
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Has an optional reference clock source to control the operating clock frequency of SD card
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Up to 10MByte/sec Read/Write rate when the optional reference clock source is used
Contains 16 Bytes of data buffer to regulate the data flow between PCI interface and the SD card interface
Support Write Protect Switch
Support Card Detect either by DAT3 or by dedicated Card Detect Switch
One Traffic LED pin

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One power enable pin.
Memory Stick Interface
Compliant with Memory Stick Standard Format Specification Version 1.3
Has an optional reference clock source to control the operating clock frequency of Memory Stick
Up to 2.5MByte/sec Read/Write rate when the optional reference clock source is used
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Stick interface
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One Traffic LED pin
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One power enable pin
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Smart Media Interface
One traffic LED pin

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Interrupt configuration
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Supports CLKRUN# protocol
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Supports SUSPEND#
Supports D3STATE#
Supports Zoomed Video port.
Power Switch Interface
Misc Control Logic

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Supports socket activity LED
Supports 12 GPIOs and GPE#
Supports PCI LOCK
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1.3.7 AC’97 AUDIO SYSTEM: Advance Logic, Inc, ALC655
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The ALC655 is a 16-bit, full duplex AC'97 2.3 compatible six channels audio CODEC designed for PC
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multimedia systems,including host/soft audio and AMR/CNR based designs. The ALC655 incorporates
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proprietary converter technology to meet performance requirements on PC99/2001 systems. The ALC655
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CODEC provides three pairs of stereo outputs with 5-Bitvolume controls, a mono output, and multiple stereo and
mono inputs, along with flexible mixing, gain and mute functions to provide a complete integrated audio solution
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for PCs. The digital interface circuitry of the ALC655 CODEC operates from a 3.3V power supply for use in
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notebook and PC applications. The ALC655 integrates 50mW/20ohm headset audio amplifiers at Front-Out and
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Surr-Out, built-in 14.318M 24.576MHz PLL and PCBEEP generator, those can save BOM costs. The
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ALC655also supports the S/PDIF input and output function, which can offer easy connection of PCs to consumer
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electronic products, such as AC3 decoder/speaker and mini disk devices. ALC655 supports host/soft audio from
Intel ICHx chipsets as well as audio controller based VIA/SIS/ALI/AMD/nVIDIA/ATI chipset. Bundled
Windows series drivers (Win XP/ME/2000/98/NT), EAX/Direct Sound 3D/ I3DL2/ A3D compatible sound effect
utilities (supporting Karaoke, 26-kind of environment sound emulation,10-band equalizer), HRTF 3D positional
audio and Sensaura™ 3D (optional) provide an excellent entertainment package and game experience for PC users.
Besides, ALC655 includes Realtek’s impedance sensing techniques that makes device load on outputs and inputs
can be detected.
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Meets performance requirements for audio on PC99/2001 systems
Meets Microsoft WHQL/WLP 2.0 audio requirements
16-bit Stereo full-duplex CODEC with 48KHz sampling rate
Compliant with AC’97 2.3 specifications
14.318MHz- 24.576MHz PLL to save crystal
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12.288MHz BITCLK input can be consumed
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Integrated PCBEEP generator to save buzzer
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Interrupt capability
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Three analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, AUX
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High quality differential CD input
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Two analog line-level mono input: PCBEEP,PHONE-IN
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Two software selectable MIC inputs applications (software selectable)
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Boost preamplifier for MIC input
50mW/20 amplifier
External Amplifier Power Down (EAPD) capability
Power management and enhanced power saving features.
Stereo MIC record for AEC/BF application

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Supports Power Off CD function
Adjustable VREFOUT control Supports double sampling rate (96KHz) of DVD audio playback
Support 48KHz of S/PDIF output is compliant with AC’97 rev2.3 specification
Power support: Digital: 3.3V; Analog: 3.3V/5V
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1.3.8 MDC:PCTEL MODEM DAUGHTER CARD PCT2303W (ASKEY
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V1456VQL-P1)
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The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR/MDC market. The
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combination of PC-TEL’s well proven PCT2303W chipset and the HSP56TM MR software modem driver allows
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systems manufactures to implement modem functions in PCs at a lower bill of materials (BOM) while maintaining
higher system performance.
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PC-TEL has streamlined the traditional modem into the Host Signal Processing (HSP) solution. Operating with
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the Pentium class processors, HSP becomes part of the host computer’s system software. It requires less power to
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operate and less physical space than standard modem solutions. PC-TEL’s HSP modem is an easily integrated,
cost-effective communications solution that is flexible enough to carry you into the future.
The PCT2303W chip set is an integrated direct access arrangement (DAA) and Codec that provides a
programmable line interface to meet international telephone line requirements. The PCT2303W chip set is
available in two 16-pin small outline packages (AC’97 interface on PCT303A and phone-line interface on
PCT303W). The chip set eliminates the need for an AFE, an isolation transformer, relays, opto-isolators, and 2-to
22
4-wire hybrid. The PCT2303W chip set dramatically reduces the number of discrete components and cost
required to achieve compliance with international regulatory requirements. The PCT2303W complies with
AC’97 Interface specification Rev. 2.1.
The chip set is fully programmable to meet world-wide telephone line interface requirements including those
described by CTR21, NET4, JATE, FCC, and various country-specific PTT specifications. The programmable
parameters of the PCT2303W chip set include AC termination, DC termination, ringer impedance, and ringer
t nt
threshold. The PCT2303W chip set has been designed to meet stringent world-wide requirements for out-of-band
re e
energy, billing-tone immunity, lightning surges, and safety requirements.
ec m
S cu
Features
ac Do
iT ial
Virtual com port with a DTE throughout up to 460.8Kbps.
G3 Fax compatible M t
en
id
Auto dial and auto answer
Ring detection
nf
Codec/DAA Features
Co
AC97 2.1 compliant
86dB dynamic range TX/RX paths
2-4-wire hybrid
Integrated ring detector

23
High voltage isolation of 4000V
Support for “Caller ID”
Compliant with FCC Part68, CTR21, Net4 and JATE
Low power standby
Low profile SOIC package 16 pins 10x3x1.55mm
t nt
Low power consumption
re e
10mA @ 3.3V operation
ec m
S cu
1mA @ 3.3V power down
ac Do
iT ial
Integrated modem codec
M t
Standard Features
en
Data
fid
on
ITU-T V.90 (56Kbps), V.34 (4.8Kbps TO 33.6 Kbps), V.32 bits (4.8Kbps to 14.4Kbps), V.22 bits (1.2 bps
C
to 2.4 Kbps), V.21 and Bell 103 and 212A(300 to 1200 bps) modulation protocol.
Data Compression ITU-T V.42bis MNP Class 5
Error Correction ITU-T V.42 LAPM MNP 2-4
24
Fax
ITU-T V. 17, V.29, V.27ter, V.21, Channel 2, Group 3, EIA Class I
t nt
re e
ec m
S cu
a c Do
iT ial
M t
e n
id
1.3.9 IEEE1394 VT6307L f(Option)
on
1.3.9.1 Overview C
The VT6307 IEEE 1394 OHCI Host Controller provides high performance serial connectivity. It implements the
Link and Phy layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0 and 1394a-2000.
It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high performance data transfer via
a 32-bit bus master PCI host bus interface. The VT6307 supports 100, 200 and 400 M bit/sec transmission via an
25
integrated 2-port PHY. The VT6307 services two types of data packets: asynchronous and isochronous (real time).
The 1394 link core performs arbitration requesting, packet generation and checking, and bus cycle master
operations. It also has root node capability and performs retry operations. The VT6307 is ready to provide
industry-standard IEEE 1394 peripheral connections for desktop and mobile PC platforms. Support for the
VT6307 is built into Microsoft Windows 98, Windows ME, Windows 2000, and Windows XP.
t nt
e e
1.3.9.2 Features
r
c m
Se
32 bit CRC generator and checker for receive and transmit data
u
c Do c
On-chip isochronous and asynchronous receive and transmit FIFOs for packets (2K for general receive plus
a
iT ial
2K for isochronous transmit plus 2K for asynchronous transmit)
M t
8 isochronous transmit contexts
en
4 isochronous receive context
fid
3-deep physical post-write queue
on
2-deep physical response queue
C
Dual buffer mode enhancements
Skip Processing enhancements
Block Read Request handling

Ack_tardy processing
26
1.3.10 System Flash Memory (BIOS)
Firmware Hub for Intel® 810, 810E, 815, 815E,815EP, 820, 840, 850 Chipsets
Flexible Erase Capability

Uniform 4 K Byte Sectors
t n
Uniform 16 K Byte overlay blocks for SST49LF002At
re e
c m
Uniform 64 K Byte overlay blocks for SST49LF004ATop boot block protection
e
16 K Byte for SST49LF002A
S cu
64 K Byte for SST49LF004A a c Do
iT ial
Chip-Erase for PP Mode
M t
Single 3.0-3.6V Read and Writee
n

fid Operations
Superior Reliability n

C o
Firmware Hub Hardware Interface Mode
5-signal communication interface supporting byte Read and Write
33 MHz clock frequency operation
WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block
27
Block Locking Register for all blocks
Standard SDP Command Set
Data# Polling and Toggle Bit for End-of-Write detection
5 GPI pins for system design flexibility
4 ID pins for multi-chip selection
t nt
re e
e c m
1.3.11 Memory System
S c u
a c (x64)D200-Pin
o DDR SDRAM SODIMM
iT ial
1.3.11.1 64MB, 128MB, 256MB, 512MB
M t
n
JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)
e
id
Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM components
f
o n
64MB (8 Meg x 64 [H]); 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); 512MB (64
Meg x 64 [HD])
C
VDD= VDDQ= +2.5V ±0.2V
VDDSPD = +2.2V to +5.5V
2.5V I/O (SSTL_2 compatible)
Commands entered on each positive CK edge
28
DQS edge-aligned with data for READs; center-aligned with data for WRITEs
Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
Bidirectional data strobe (DQS) transmitted/received with data—i.e.,source-synchronous data capture
Differential clock inputs (CK and CK# - can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.)
Four internal device banks for concurrent operation
t nt
e e
Selectable burst lengths: 2, 4, or 8
r
Auto precharge option
ec m
S cu
c Do
Auto Refresh and Self Refresh Modes
a
iT ial
15.6µs (MT4VDDT864H, MT8VDDT1664HD), 7.8125µs (MT4VDDT1664H, MT8VDDT3264HD,
M t
MT8VDDT6464HD) maximum average periodic refresh interval
n
Serial Presence Detect (SPD) with EEPROM
e
fid
Fast data transfer rates PC2100 or PC1600
on
Selectable READ CAS latency for maximum compatibility
C
Gold-plated edge contacts
29
1.3.12 PHY: 3.3-V 10Base-T/100Base-TX Integrated PHY Ceiver ,The ICS1893

is a low-power, physical-layer device (PHY)
General
The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides
t nt
32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications
e e
and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management
r
c m
Interface (ACPI), PCI power management for modern operating systems that are capable of Operating System
e
S u
Directed Power Management (OSPM) to achieve the most efficient power management possible. The
c
c Do
RTL8100C(L) does not support CardBus mode as the RTL8139C does. In addition to the ACPI feature, the
a
iT ial
RTL8100C(L) also supports remote wake-up(including AMD Magic Packet, LinkChg, and Microsoft® wake-up
frame) in both ACPI and APM environments. The RTL8100C(L) is capable of performing an internal reset
M t
through the application of auxiliary power. When auxiliary power is applied and the main power remains off, the
en
RTL8100C(L) is ready and waiting for the Magic Packet or Link Change to wake the system up. Also, the
id
LWAKE pin provides 4 different output signals including active high, active low, positive pulse, and negative
f
n
pulse. The versatility of the RTL8100C(L) LWAKE pin provides motherboards with Wake-On-LAN (WOL)
o
C
functionality. The RTL8100C(L) also supports Analog Auto-Power-down, that is, the analog part of the
RTL8100C(L) can be shut down temporarily according to user requirements or when the RTL8100C(L) is in a
power down state with the wakeup function disabled. In addition, when the analog part is shut down and the
Isolate B pin is low (i.e. the main power is off), then both the analog and digital parts stop functioning and the
power consumption of the RTL8100C(L) will be negligible. The RTL8100C(L) also supports an auxiliary
power auto-detect function, and will auto-configure related bits of their own PCI power management
registers in PCI configuration space.
30
128 pin QFP/LQFP
Integrated Fast Ethernet MAC, Physical chip and transceiver in one chip
10 Mb/s and 100 Mb/s operation
Supports 10 Mb/s and 100 Mb/s N-way Auto-negotiation operation
PCI local bus single-chip Fast Ethernet controller
t nt
Compliant to PCI Revision 2.2
re e
ec m
Supports PCI clock 16.75MHz-40MHz
S cu
c Do
Supports PCI target fast back-to-back transaction
a
iT ial
Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of
M t
RTL8100C(L)'s operational registers
en
Supports PCI VPD (Vital Product Data)
fid
Supports ACPI, PCI power management
on
Supports 25MHz crystal or 25MHz OSC as the internal clock source.
C
The frequency deviation of either crystal or OSC must be within 50 PPM.
Compliant to PC99/PC2001 standard
Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and Microsoft® wake-up
frame)
31
Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse)
Supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still remains
off
Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI
configuration space.
t nt
Includes a programmable, PCI burst size and early Tx/Rx threshold.
re e
Supports a 32-bit general-purpose timer with the external PCI clock as clock source, to generate timer-
interrupt
ec m
S cu
c Do
Contains two large (2Kbyte) independent receive and transmit FIFOs
a
iT ial
Advanced power saving mode when LAN function or wakeup function is not used
M t
Uses 93C46 (64*16-bit EEPROM) to store resource configuration, ID parameter, and VPD data.
en
Supports LED pins for various network activity indications
fid
n
Supports loop back capability
Co
Half/Full duplex capability
Supports Full Duplex Flow Control (IEEE 802.3x)
32
1.3.13 Keyboard System: Winbond W83L950D
The Winbond Keyboard controller architecture consists of a Turbo 51 core controller surrounded by various
registers, nine general purpose I/O port, 2k+256 bytes of RAM, four timer/counters, dual serial ports, 40K MTP-
ROM that is divided into four banks, two SMBus interface for master and slave, Support 4 PWM channels, 2 D-A
and 8 A-D converters. 2
t nt
e e
8051 uC based
r
c m
Keyboard Controller Embedded Controller
Se u
c Do c
Supply embedded programmable flash memory (internal ROM size: 40KB) and RAM size is 2 KB.
a
iT ial
Support 4 Timer (8 bit) signal with 3 prescalers.
M t
Support 2 PWM channels, 2 D-A and 8 A-D converters.
en
Reduce Firmware burden by Hardware PS/2 decoding
fid
Support 72 useful GPIOs totally
on
Support Flash utility for on board re-flash
Support ACPI
C
Hardware fast Gate A20 with software programmable
33
1.4 Other Functions
1.4.1 Hot Key Function
Keys Combination Feature Meaning

Fn + F1 Power down
t nt Mini PCI power down
e e
Fn + F2 Reserve
Fn + F3 Volume Down
r
c m
Fn + F4 Volume Up
Se u
Fn + F5
c Do c
LCD/external CRT switching Rotate display mode in LCD only, CRT only, and simultaneously display.
a
iT ial
Fn + F6 Brightness down Decreases the LCD brightness
M t
Fn + F7 Brightness up Increases the LCD brightness
Fn + F10
Fn + F11 Panel Off/On
en
Battery Low Beep On/Off Battery Low Beep
Toggle Panel on/off
Fn + F12
fid
Suspend to DRAM / HDD Force the computer into either Suspend to HDD or Suspend to DRAM
on mode depending on BIOS Setup.
34
1.4.2 Power on/off/suspend/resume button
APM mode
At APM mode, Power button is on/off system power.

t
ACPI mode
t
e e n
At ACPI mode. Windows power management control panel set power button behavior.You could set
r
c m
“standby”, “power off” or “hibernate”(must enable hibernate function in power Management) to power
button function.
Se u
c Do c
a
Continue pushing power button over 4 seconds will force system off at ACPI mode.
iT ial
M t
1.4.3 Cover Switch en
fid
on
System automatically provides power saving by monitoring Cover Switch. It will save battery power and prolong
C
the usage time when user closes the notebook cover.
At ACPI mode there are four functions to be chosen at windows power management control panel.
None
Standby
35
Off
Hibernate (must enable hibernate function in power management)
1.4.4 LED Indicators
t nt

e e
Three LED indicators at front side:
r
ec m
From left to right that indicate BATTERY POWER, BATTERY STATUS and AC POWER
S cu
AC POWER:
ac Do
iT ial
This LED lights green when the notebook was powered by AC power line, Flashes (on 1 second, off 1 second)
M t
when entered suspend to RAM state with AC powered. The LED is off when the notebook is in power off state or
powered by battery.
en
fid
BATTERY POWER:
on
C
This LED lights green when the notebook is being powered by Battery, and flashes (on 1 second, off 1 second)
when entered suspend to RAM state with AC powered. The LED is off when the notebook is in power off state or
powered by AC adapter.
36
BATTERY STATUS:
During normal operation, this LED stays off as long as the battery is charged. When the battery charge drops to
10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC is connected, this
indicator glows green if the battery pack is fully charged or orange (amber) if the battery is being charged.
AC POWER:
t nt
e e
This LED lights green when AC is powering the notebook, and flash (on 1 second, off 1 second) when Suspend to
r
c m
RAM no matter using AC power or Battery power. The LED is off when the notebook is off or powered by battery.
e
S cu
BATTERY POWER:
ac Do
iT ial
M t
This LED lights green when the notebook is being powered by Battery, and flash (on 1 second, off 1 second) when
n
Battery is low. The LED is off when the notebook is off or powered by AC adaptor.
e
Seven LED indicators:
fid
o n
C
System has seven status LED indicators at front side which to display system activity. From left to right that
indicate HARD DISK, CD-ROM, NUM LOCK, CAPS LOCK, SCROLL LOCK, Mini PCI and Card Reader.
37
1.4.5 Battery status
Battery Warning
System also provides Battery capacity monitoring and gives users a warning signal to alarm they to store
data before battery dead. This function also protects system from mal-function while battery capacity is low.
t t
Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2
n
seconds.
re e
ec m
System will Suspend to HDD after 2 Minutes to protect users data.
S cu
ac Do
iT ial
Battery Low State
M t
After Battery Warning State, and battery capacity is below 5%, system will generate beep sound for twice
per second.
en
fid
n
Battery Dead State
C o
When the battery voltage level reaches 11.5 volts, system will shut down automatically in order to extend
the battery packs' life.
38
1.4.6 Fan power on/off management
FAN is controlled by W83L950D embedded controller-using ADT7460 to sense CPU temperature and PWM
control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature faster Fan Speed.
1.4.7 CMOS Battery

t nt
re e
ec m
CR2032 3V 220mAh lithium battery When AC in or system main battery inside, CMOS battery will consume no
S cu
power AC or main battery not exists, CMOS battery life at less (220mAh/5.8uA) 4 years.
ac Do
iT ial
1.4.8 I/O Port M t
en
id
One Power Supply Jack.
nf
One External CRT Connector For CRT Display
Co
Supports three USB port for all USB devices.
One MODEM RJ-11 phone jack for PSTN line
One RJ-45 for LAN.
One IEEE1394 port
39
Headphone Out Jack.
Microphone Input Jack.
Line in Jack
t nt
1.4.9 Battery current limit and learning.
re e
c m
Implanted H/W current limit and battery learning circuit to enhance protection of battery.
Se u
c o c
a D
iT ial
1.5 Power management
M t
The 8050D system has built in several power saving modes to prolong the battery usage for mobile purpose. User
en
can enable and configure different degrees of power management modes via ROM CMOS setup (booting by
fid
pressing F2 key). Following are the descriptions of the power management modes supported.
o n
C
1.5.1 System Management Mode
Full on mode
In this mode, each device is running with the maximal speed. CPU clock is up to its maximum.
40
Doze Mode
In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This
can save battery power without loosing much computing capability.
The CPU power consumption and temperature is lower in this mode.
Standby mode
t nt
re e
c m
For more power saving, it turns of the peripheral components. In this mode, the following is the status of each
e
device:
S cu
ac Do
-- CPU: Stop grant
iT ial
M t
-- LCD: backlight off
-- HDD: spin down
en
fid
n
Suspend to DRAM
C o
The most chipset of the system is entering power down mode for more power saving. In this mode, the following
is the status of each device:
Suspend to DRAM
CPU: off
Intel 855GME: Partial off

41
VGA: Suspend
PCMCIA: Suspend
Audio: off
SDRAM: self refresh
t
Suspend to HDD
t
e e n
All devices are stopped clock and power-down
r
c m
S e
System status is saved in HDD
u
c Do c
All system status will be restored when powered on again
a
iT ial
M functions
t
1.5.2 Other power management
en
fid
HDD & Video access
o n
C
System has the ability to monitor video and hard disk activity. User can enable monitoring function for video
and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU state
depending on the application. When the VGA activity monitoring is enabled, the performance of the system will
have some impact.
42
2. System View and Disassembly

2.1 System View
2.1.1 Front View

1394 Jack
t nt
Line Out Connector
re e
Line In Connector
ec m
u

MIC In Connector S
c Do c
SD Card Slot
a
Top Cover Latch
iT ial
M t
en
2.1.2 Left-side View
fid
VGA Port
on
S-Video Port C
USB Ports *1
Ventilation Openings
RJ-11 Connector

RJ-45 Connector
PCMCIA Card Socket
43
2.1.3 Right-side View

CD-ROM/DVD-ROM Drive
Kensington Lock

t nt
re e
ec m
S cu
ac Do
2.1.4 Rear View iT ial
M t
Kensington Lock en
Power Connector fid
USB Port*2 on
C

44
2.1.5 Bottom View

Hard Disk Drive
DDR SDRAM Card
Wireless Card
CPU
Battery Park
t nt
e e

r
Stereo Speaker Set
ec m
S cu
ac Do
2.1.6 Top-open View iT ial
M t
LCD Screen
en
Power Button
fid

n
Stereo Speaker Set
o

Keyboard
C
Device LED Indicators

Touch Pad
Hard Disk Drive Indicator

Battery Power Charging Indicator
Power Indicator

45
2.2 System Disassembly

The section discusses at length each major component for disassembly/reassembly and show corresponding
illustrations.Use the chart below to determine the disassembly sequence for removing components from the
notebook.
NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the
notebook is not turned on or connected to AC power.
t nt
re e 2.2.1 Battery Pack
ec m 2.2.2 Keyboard
S cu
c Do
2.2.3 CPU
a
Modular Components
iT ial
2.2.4 HDD Module
M t
2.2.5 DVD-ROM Drive
en 2.2.6 Wireless Card
id
NOTEBOOK 2.2.7 Modem Card
nf 2.2.8 DDR-SDRAM
Co 2.2.9 LCD Assembly

LCD Assembly Components 2.2.10 LCD Panel
2.2.11 Inverter Board
2.2.12 System Board
Base Unit Components
2.2.13 Touch Pad
46
2.2.1 Battery Pack

Disassembly
1. Carefully put the notebook upside down.
2. Slide the two release lever outwards to the “unlock” ( ) position (), while take the battery pack out of
the compartment (). (Figure 2-1)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid Figure 2-1 Remove the battery pack
on
C
Reassembly
1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you
hear a clicking sound.
2. Slide the release lever to the “lock” ( ) position.
47
2.2.2 Keyboard
Disassembly
1. Remove the battery pack. (Refer to section 2.2.1 Disassembly)
2. Open the top cover.
3. Loosen the four latches locking the keyboard. (Figure 2-2)
(Figure 2-3)
t nt
4. Slightly lift up the keyboard and disconnect the cable from the mother board, then separate the keyboard.
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on
C
Figure 2-2 Loosen the four latches Figure 2-3 Disconnect the cable
Reassembly
1. Reconnect the keyboard cable and fit the keyboard back into place with four latches.
2. Replace the battery pack. (Refer to section 2.2.1 reassembly)
48
2.2.3 CPU
Disassembly
1. Remove the battery pack. (Refer to section 2.2.1 Disassembly)
2. Remove three screws fastening the heatsink cover. (Figure 2-4)
3. Remove three spring screws that secure the heatsink upon the CPU and disconnect the fan’s power cord
from system board. (Figure 2-5)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on
Figure 2-4 Remove three screws
C
Figure 2-5 Free the heatsink
49
4. To remove the existing CPU, Loosen the screw by a flat screwdriver,upraise the CPU socket to unlock
the CPU. (Figure 2-6)
t nt
re e
ec m
S cu
ac Do
iT ial
M t Figure 2-6 Remove the CPU
en
fid
on
C
Reassembly
1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU
pins into the holes. Tighten the screw by a flat screwdriver to locking the CPU.
2. Connect the fan’s power cord to the system board, fit the heatsink upon the CPU and secure with three
spring screws.
3. Replace the CPU cover and secure with three screws.
50
2.2.4 HDD Module

Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)
2. Remove two screws fastening the HDD compartment cover. (Figure 2-7)
3. Remove the one screw and slide the HDD module out of the compartment. (Figure 2-8)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on
Figure 2-7 Remove the HDD compartment cover Figure 2-8 Remove HDD module
51
4. Remove four screws to separate the hard disk drive from the bracket, remove four screws.
(Figure 2-9)
t nt
re e
ec m
S cu
ac Do Figure 2-9 Remove hard disk drive
iT ial
M t
Reassembly
en
id
1. Attach the bracket to hard disk drive and secure with four screws.
f
n
2. Slide the HDD module into the compartment and secure with one screw.
o
C
3. Place the HDD compartment cover and secure with two screws.
52
2.2.5 CD/DVD-ROM Drive

Disassembly
2. Remove one screw fastening the CD/DVD-ROM drive. (Figure 2-10)
3. Push firmly to release the tray. Then gently pull out the CD/DVD-ROM drive by holding the tray that
t
pops out. (Figure 2-11)
t
e e n
r
c m
Se u
c Do c
a
iT ial
M t
en
fid
on
Figure 2-10 Remove one screw Figure 2-11 Remove the CD/DVD-
C
ROM drive
Reassembly
1. Push the CD/DVD-ROM drive into the compartment and secure with one screw.
53
2.2.6 Wireless Card

Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to sections 2.2.1 Disassembly)
2. Remove the two screws fastening the Mini PCI compartment cover. (Figure 2-12)
3. Disconnect the wireless card’s antennae first (). Then pull the retaining clips outwards () and remove
t
the wireless card (). (Figure 2-13)
t n

re e

ec m
S cu
ac Do
iT ial

M t
en
fid
on
Figure 2-12 Remove two screws Figure 2-13 Remove the Wireless card
Reassembly C
1. To install the wireless card, match the wireless card 's notched part with the socket's projected part and firmly
insert it into the socket. Then push down until the retaining clips lock the wireless card into position. Then
sure that the antennae fully populated.
2. Tighten the screws to secure the wireless card compartment cover to the housing.
54
2.2.7 Modem Card

Disassembly
2. Remove two screws fastening modem card’s compartment cover. (Refer to steps 1-2 of section 2.2.6
Disassembly)
t
3. Remove two screws fastening the modem card. (Figure 2-14)
t n
4. Lift up the modem card and disconnect the cord. (Figure 2-15)
e e
r
c m
Se u
c Do c
a
iT ial
M t
en
fid
on
Figure 2-14 Remove two screws Figure 2-15 Disconnect the cord
Reassembly
C
1. Reconnect the cord and fit the modem card.
2. Fasten the modem card by two screws.
3. Replace the modem card’s compartment cover by two screws. (Refer to step 2 of section 2.2.6 reassembly).
55
2.2.8 DDR-SDRAM
Disassembly
1. Carefully put the notebook upside down. And remove the battery pack. (See section 2.2.1 disassembly)
2. Remove two screws fastening the DDR compartment cover to access the SO-DIMM socket. (Figure 2-16)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
Figure 2-16 Remove the cover
en Figure 2-17 Remove the SO-DIMM
fid
n
3. Pull the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-17)
o
Reassembly C
1. To install the DDR, match the DDR's notched part with the socket's projected part and firmly insert the
SO-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR
into position.
2. Replace two screws to fasten the DDR compartment cover.
3. Replace the battery pack. (See section 2.2.1 reassembly)
56
2.2.9 LCD ASSY

Disassembly
1. Remove the battery pack, keyboard,CPU, hard disk drive, CD/DVD-drive and wireless card.
(See sections 2.2.1,2.2.2, 2.2.3, 2.2.4, 2.2.5 and 2.2.6 Disassembly)
2. Remove the nineteen screws on the bottom of notebook. (Figure 2-18)
t
3. Remove the four screws that secure the hinge cover. (Figure 2-19)
t
e e n
r
c m
Se u
c Do c
a
iT ial
M t
en
fid
on
Figure 2-18 Remove nineteen screws Figure 2-19 Remove four screws
57
4. Remove the two screws and disconnect the touch pad’s cable, then free the top cover.(Figure 2-20)
5. Remove the two hinge covers. (Figure 2-21)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
e
Figure 2-20 Free the Top covern Figure 2-21 Remove the hinge covers
fid
on
C
58
6. Disconnect the two cables and remove the four screws. (Figure 2-22)
7. Remove the eight screws. (Figure 2-23)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
Figure 2-22 Remove the four screws and
Disconnect the two cables
Figure 2-23 Remove the eight screws
on
C
59
8. Carefully pull the antenna wires out. Now you can lift up the LCD ASSY from base unit. (Figure 2-24)
t nt
re e
ec m
S cu
ac Do
iT ial
Figure 2-24 Free the LCD ASSY
M t
Reassembly
en
id
1. Attach the LCD assembly to the base unit and secure with four screws.
f
n
2. Rip the antenna wires back into Min-PCI compartment.
o
C
3. Reconnect the two cables to the system board. Screw the hinge covers by two screws.
4. Replace the shield and secure with eight screws.
5. Replace the top cover and secure with two screws. And reconnect the touch pad’s cable.
6. Upside down the notebook. secure the housing by nineteen screws and secure two screws in the rear.
7. Replace the Wireless card, CD/DVD-ROM, hard disk drive, CPU, keyboard and battery pack. (Refer to
sections 2.2.6, 2.2.5, 2.2.4, 2.2.3, 2.2.2 and 2.2.1 reassembly)
60
2.2.10 LCD Panel

Disassembly
1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive and LCD assembly. (Refer to
section 2.2.1, 2.2.2, 2.2.4, 2.2.5 and 2.2.9 Disassembly)
2. Remove the two rubber pads and two screws on the corners of the panel. (Figure 2-25)
3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the
t nt
process until the cover is completely separated from the housing.
re e
4. Remove the twelve screws and disconnect the cable. (Figure 2-26)
ec m
S cu
ac Do
iT ial
M t
en
fid
on
C
Figure 2-25 Remove LCD cover Figure 2-26 Remove twelve screws and
disconnect the cable
61
5. Remove the six screws that secure the LCD bracket. (Figure 2-27)
6. Disconnect the cable to free the LCD panel. (Figure 2-28)
t nt
re e
ec m
S cu
ac Do
iT ial
Figure 2-27 Remove the six screws Figure 2-28 Free the LCD panel
M t
en
id
Reassembly
nf
1. Replace the cable to the LCD.
Co
2. Attach the LCD panel’s bracket back to LCD panel and secure with six screws.
3. Replace the LCD panel into LCD housing.and reconnect two cables to inverter board and secure with two
screws.
4. Fasten the LCD panel by ten screws.
5. Fit the LCD cover and secure with two screws and rubber pads.
6. Replace the LCD assembly, CD/DVD-ROM drive, hard disk drive, keyboard, battery pack. (See sections
2.2.9, 2.2.5, 2.2.4, 2.2.2, and 2.2.1 reassembly)
62
2.2.11 Inverter Board

Disassembly
1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive and LCD assembly. (Refer to
section 2.2.1, 2.2.2, 2.2.4, 2.2.5 and 2.2.9 Disassembly)
2. Remove the LCD cover and LCD panel. (Refer to the steps 1-4 of section 2.2.10 Disassembly )
3. Remove the one screw fastening the inverter board and disconnect the cable, Then free the inverter board.
(Figure 2-29)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on Figure 2-29 Free the inverter board
Reassembly C
1. Reconnect the cable. Fit the inverter board back into place and secure with one screw.
2. Replace the LCD Panel and LCD cover. (Refer to section 2.2.10 reassembly)
3. Replace the LCD assembly. (Refer to section 2.2.9 reassembly)
4. Replace the CD/DVD-ROM drive, hard disk drive, keyboard and battery pack. (Refer to sections 2.2.5,
2.2.4, 2.2.2 and 2.2.1 reassembly)
63
2.2.12 System Board

Disassembly
1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive, Wireless card and LCD assembly.
(Refer to sections 2.2.1, 2.2.2, 2.2.4, 2.2.5, 2.2.6 and 2.2.9 Disassembly)
2. Remove the four screws that secure the system board and disconnect the two speaker’s cables. Then lift it
up from the housing. (Figure 2-30)
t nt
3. Disconnect the one speaker’s cables from the system board and remove the two screws, Then separate the
re e
bracket and free the system board. (Figure 2-31)
ec m
S cu
ac Do
iT ial
M t
en
fid
Figure 2-30 Remove four screws and
on
disconnect the two cables Figure 2-31 Free the system board
Reassembly C
1. Fit the bracket and secure with two screws .
2. Turn over the system board. Reconnect the speaker’s cords.
3. Replace the system board back into the housing and secure with four screws, then reconnect the cable.
4. Replace the LCD assembly, CD/DVD-ROM, HDD, keyboard and battery pack. (Refer to previous section
reassembly)
64
2.2.13 Touch Pad

Disassembly
1. Remove the battery pack, keyboard, hard disk drive and CD/DVD-drive. (See sections 2.2.1,2.2.2 , 2.2.4 and
2.2.5 Disassembly)
2. Remove the top cover. (See steps 1-5 in section 2.2.9 Disassembly)
3. Remove the two screws and free the touch pad. (Figure 2-32).
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on Figure 2-32 Remove the two screws
C
Reassembly
1. Replace the touch pad and secure the two screws.
2. Replace the top cover. (Refer to the section in 2.2.9 reassembly)
3. Replace the battery pack, keyboard, hard disk drive and CD/DVD-drive. (See sections 2.2.1,2.2.2 ,
2.2.4 and 2.2.5 Disassembly).
65
3. Definition & Location of Connectors / Switches

3.1 Mother Board - A
t J1 : Inverter Board Connector

J3
J2 t
e e n
SW2 J2 : LCD panel connector
r
c m J3 : Internal Left Speaker Connector
J6
Se
J1
u
c Do c J4 : Touch-pad Module Connector
a J5 : Internal Key-board Connector
iT ial J6 : PCMCIA Card Connector

M t
n
J7 : Internal Right Speaker Connector
SW4
e
fid
on
J5
SW2 : Power Button
J7 CJ4
SW4 : Left Button Switch of Touch-pad
SW5 : Right Button Switch of Touch-pad
SW5
66

3.2 Mother Board - B
J706 PJ701 : AC Adaptor Connector

J709
t
J702 J704
J701&J706 : USB Port Connector
t
e e n
r
J702 : CRT Connector
c m
J701 J713
Se u
J703 : Battery Connector
PJ701
c Do c J704 : External VGA Connector
a
iT ial
J705 : Internal Subwoofer Speaker
J707
M t
J707: FAN Connector
en J708 : CD-ROM IDE Connector
id
J709: RJ45 & RJ11 Connector
nf J710 : RTC Battery Connector
o
J711
J712
C J711&J712 : DDR SO-DIMM Module Socket

J713 : Mini-PCI Connector
J703
J710
J714 : Hard Disk Driver Connector
J705 J708 J714 -----To next page-----
67

-----Continue From Previous Page-----

J715
t
J717
nt J715&J717: Modem Daughter Board Connector
re e J716 : SD&MS Card Socket
ec m J718 : IEEE 1394 Connector
S cu
ac Do J719 : External Micro Phone Jack
iT ial
J720 : Line Out HP/OPT Jack
M t
J721 : External Line-in Jack
J718
en
id
J720
nf J721
Co J719
J716
68
4. Definition & Location of Major Components

4.1 Mother Board - A
PU2 : +3VS/+5VS Voltage Generator
t nt PU3 : CPU Core Voltage Generator
re e PU14: +1.8V/+1.35V Voltage Generator
ec m
PU2
PU15 : +2.5VS/+1.25V Voltage Generator
S cu
ac Do
PU3
U2 : TV Encoder Controller
iT ial
U15: SYS BIOS Controller
M t
U16: WINBOND KBC Controller
n
U15
U524: TPA02012 Audio Amplifier
U524
e
fid
on
PU15
C
U2
U16 PU14
69
4. Definition & Location of Major Components

U706 : Thermal Sensor/Fan Controller
t nt U710 : ATI-M10-P
U719
re e U713 : Intel BANIAS CPU
ec m U714 : Intel 855GM/GME North Bridge

S cu
ac Do
U727
U724
U715 : Intel ICH4-M South Bridge
iT ial
U713 U719 : LAN-RTL8100CL Controller
U706
M t U724 : IEEE1394 Controller
en U725 : SUBWOOFER AMP Controller
f
U714
id U726 : Audio CODEC(ALC655)
on U727 : CB710 Card Bus Reader Controller
U710 C U725
U726
U715
70
5. Pin Descriptions of Major Components

5.1 Intel Pentium M(Banias) Processor(1)
Signal Name Type Description Signal Name Type Description
A[31:3]# I/O A[31:3]# (Address) define a 2 32 -byte physical memory address space. BPRI# I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
In sub-phase 1 of the address phase, these pins transmit the address of a processor system bus. It must connect the appropriate pins of both
transaction. In sub-phase 2, these pins transmit transaction type processor system bus agents. Observing BPRI# active (as asserted by
t
information. These signals must connect the appropriate pins of both the priority agent) causes the other agent to stop issuing new requests,
t n
agents on the Intel Pentium M processor system bus. A[31:3]# are source unless such requests are part of an ongoing locked operation. The
e e
synchronous signals and are latched into the receiving buffers by priority agent keeps BPRI# asserted until all of its requests are
r
ADSTB[1:0]#. Address signals are used as straps which are sampled completed, then releases the bus by deasserting BPRI#.
c m
before RESET# is deasserted. BR0# I/O BR0# is used by the processor to request the bus. The arbitration is done
e
A20M# I If A20M# (Address-20 Mask) is asserted, the processor masks physical between the Intel Pentium M processor (Symmetric Agent) and the
u
address bit 20 (A20#) before looking up a line in any internal cache and MCH-M (High Priority Agent) of the Intel 855PM or Intel 855GM
S
c Do c
before driving a read/write transaction on the bus. Asserting A20M#
emulates the 8086 processor's address wrap-around at the 1-Mbyte COMPP3:0]
chipset.
Analog COMP[3:0] must be terminated on the system board using precision
a
boundary. Assertion of A20M# is only supported in real mode. (1% tolerance) resistors. Refer to the platform design guides for more
A20M# is an asynchronous signal. However, to ensure recognition of implementation details.
iT ial
this signal following an Input/Output write instruction, it must be valid D[63:0]# I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data
along with the TRDY# assertion of the corresponding Input/Output path between the processor system bus agents, and must connect the
M t
Write bus transaction. appropriate pins on both agents. The data driver asserts DRDY# to
ADS# I/O ADS# (Address Strobe) is asserted to indicate the validity of the indicate a valid data transfer.
n
transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents D[63:0]# are quad-pumped signals and will thus be driven four times in
e
observe the ADS# activation to begin parity checking, protocol a common clock period. D[63:0]# are latched off the falling edge of
checking, address decode, internal snoop, or deferred reply ID match
id
both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals
operations associated with the new transaction. correspond to a pair of one DSTBP# and one DSTBN#. The following
f
ADSTB[1:0]# I/O Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising table shows the grouping of data signals to data strobes and DINV#.
n
and falling edges. Strobes are associated with signals as shown below. Quad-Pumped Signal Groups
o
Signals Associated Strobe Data Group DSTBN#/DSTBP# DINV#
REQ[4:0]#, A[16:3]# ADSTB[0]# D[15:0]# 0 0
BCLK[1:0] I
A[31:17]#
C
ADSTB[1]#
The differential pair BCLK (Bus Clock) determines the system bus
frequency. All processor system bus agents must receive these signals to
drive their outputs and latch their inputs.
D[31:16]#
D[47:32]#
D[63:48]#
1
2
3
1
2
3
Furthermore, the DINV# pins determine the polarity of the data signals.
BNR# I/O BNR# (Block Next Request) is used to assert a bus stall by any bus agent Each group of 16 data signals corresponds to one DINV# signal. When
that is unable to accept new bus transactions. During a bus stall, the the DINV# signal is active, the corresponding data group is inverted and
current bus owner cannot issue any new transactions. therefore sampled active high.
BPM[2:0]# O BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance DBR# O DBR# (Data Bus Reset) is used only in processor systems where no
BPM[3] I/O monitor signals. They are outputs from the processor that indicate the debug port is implemented on the system board. DBR# is used by a
status of breakpoints and programmable counters used for monitoring debug port interposer so that an in-target probe can drive system reset. If
processor performance. BPM[3:0]# should connect the appropriate pins a debug port is implemented in the system, DBR# is a no connect.
of all Intel Pentium M processor system bus agents. This includes debug DBR# is not a processor signal.
or performance monitoring tools.
71

DBSY# I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving DPWR# I DPWR# is a control signal from the Intel 855PM and Intel 855GM
data on the processor system bus to indicate that the data bus is in use. chipsets used to reduce power on the Intel Pentium M data bus input
The data bus is released after DBSY# is deasserted. This signal must buffers.
connect the appropriate pins on both processor system bus agents. FERR#/PBE# O FERR# (Floating-point Error)/PBE#(Pending Break Event) is a
DEFER# I DEFER# is asserted by an agent to indicate that a transaction cannot be multiplexed signal and its meaning is qualified by STPCLK#. When
guaranteed in-order completion. Assertion of DEFER# is normally the STPCLK# is not asserted, FERR#/PBE# indicates a floating point when
responsibility of the addressed memory or Input/Output agent. This the processor detects an unmasked floating-point error. FERR# is
agents.
t nt
signal must connect the appropriate pins of both processor system bus similar to the ERROR# signal on the Intel 80387 coprocessor, and is
included for compatibility with systems using MS-DOS* type
e e
I/O DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate floating-point error reporting. When STPCLK# is asserted, an assertion
r
DINV[3:0]#
the polarity of the D[63:0]# signals. The DINV[3:0]# signals are of FERR#/PBE# indicates that the processor has a pending break event
c m
activated when the data on the data bus is inverted. The bus agent will waiting for service. The assertion of FERR#/PBE# indicates that the
e
invert the data bus signals if more than half the bits, within the covered processor should be returned to the Normal state. When FERR#/PBE# is
S u
group, would change level in the next cycle. asserted, indicating a break event, it will remain asserted until
c
STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active
c Do
DINV[3:0]# Assignment To Data Bus
will also cause an FERR# break event.
a
Bus Signal Data Bus Signals
DINV[3]# D[63:48]# GTLREF I GTLREF determines the signal reference level for AGTL+ input pins.
iT ial
DINV[2]# D[47:32]# GTLREF should be set at 2/3 VCCP . GTLREF is used by the AGTL+
DINV[1]# D[31:16]# receivers to determine if a signal is a logical 0 or logical 1.
I/O HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop
M t
DINV[0]# D[15:0]# HIT#
HITM# I/O operation results. Either system bus agent may assert both HIT# and
DPSLP# I DPSLP# when asserted on the platform causes the processor to
HITM# together to indicate that it requires a snoop stall, which can be
n
transition from the Sleep state to the Deep Sleep state. In order to return
continued by reasserting HIT# and HITM# together.
e
to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the
IERR# O IERR# (Internal Error) is asserted by a processor as the result of an
ICH4-M component and also connects to the MCH-M component of the
id
internal error. Assertion of IERR# is usually accompanied by a
Intel 855PM or Intel 855GM chipset.
f
SHUTDOWN transaction on the processor system bus. This transaction
DRDY# I/O DRDY# (Data Ready) is asserted by the data driver on each data may optionally be converted to an external error signal (e.g., NMI) by
n
transfer, indicating valid data on the data bus. In a multi-common clock system core logic. The processor will keep IERR# asserted until the
o
data transfer, DRDY# may be deasserted to insert idle clocks. This assertion of RESET#, BINIT#, or INIT#.
signal must connect the appropriate pins of both processor system bus
C
IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to
agents.
ignore a numeric error and continue to execute noncontrol floating-point
DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#. instructions. If IGNNE# is deasserted, the processor generates an
Signals Associated Strobe exception on a noncontrol floating-point instruction if a previous
D[15:0]#, DINV[0]# DSTBN[0]# floating-point instruction caused an error. IGNNE# has no effect when
D[31:16]#, DINV[1]# DSTBN[1]# the NE bit in control register 0 (CR0) is set.
D[47:32]#, DINV[2]# DSTBN[2]# IGNNE# is an asynchronous signal. However, to ensure recognition of
D[63:48]#, DINV[3]# DSTBN[3]# this signal following an Input/Output write instruction, it must be valid
DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#. along with the TRDY# assertion of the corresponding Input/Output
Signals Associated Strobe Write bus transaction.
D[15:0]#, DINV[0]# DSTBP[0]# REQ[4:0]# I/O REQ[4:0]# (Request Command) must connect the appropriate pins of
D[31:16]#, DINV[1]# DSTBP[1]# both processor system bus agents. They are asserted by the current bus
D[47:32]#, DINV[2]# DSTBP[2]# owner to define the currently active transaction type. These signals are
D[63:48]#, DINV[3]# DSTBP[3]# source synchronous to ADSTB[0]#.
72

INIT# I INIT# (Initialization), when asserted, resets integer registers inside the PWRGOOD I PWRGOOD (Power Good) is a processor input. The processor requires
processor without affecting its internal caches or floating-point registers. this signal as a clean indication that the clocks and power supplies are
The processor then begins execution at the power on Reset vector stable and within their specifications. ‘Clean’ implies that the signal will
configured during power on configuration. The processor continues to remain low (capable of sinking leakage current), without glitches, from
handle snoop requests during INIT# assertion. INIT# is an asynchronous the time that the power supplies are turned on until they come within
signal. However, to ensure recognition of this signal following an specification. The signal must then transition monotonically to a high
Input/Output Write instruction, it must be valid along with the TRDY# state. PWRGOOD can be driven inactive at any time, but clocks and
t nt
assertion of the corresponding Input/Output Write bus transaction.
INIT# must connect the appropriate pins of both processor system bus
power must again be stable before a subsequent rising edge of
PWRGOOD.
e e
agents. If INIT# is sampled active on the active to inactive transition of The PWRGOOD signal must be supplied to the processor; it is used to
r
RESET#, then the processor executes its Built-in Self-Test (BIST) protect internal circuits against voltage sequencing issues. It should be
c m
LINT[1:0] I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of driven high throughout the boundary scan operation.
e
all APIC Bus agents. When the APIC is disabled, the LINT0 signal ITP_CLK[1:0] I ITP_CLK[1:0] are copies of BCLK that are used only in processor
S u
becomes INTR, a maskable interrupt request signal, and LINT1 systems where no debug port is implemented on the system board.
c
becomes NMI, a nonmaskable interrupt. INTR and NMI are backward ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
Both signals are asynchronous.
ac Do
compatible with the signals of those names on the Pentium processor. implemented on an interposer. If a debug port is implemented in the
system, ITP_CLK[1:0] are no connects. These are not processor signals.
iT ial
Both of these signals must be software configured using BIOS RESET# I Asserting the RESET# signal resets the processor to a known state and
programming of the APIC register space and used either as NMI/INTR invalidates its internal caches without writing back any of their contents.
or LINT[1:0]. Because the APIC is enabled by default after Reset, For a power-on Reset, RESET# must stay active for at least two
I/O
M t
operation of these pins as LINT[1:0] is the default configuration.
LOCK# indicates to the system that a transaction must occur atomically.
milliseconds after VCC and BCLK have reached their proper
specifications. On observing active RESET#, both system bus agents
n
LOCK#
This signal must connect the appropriate pins of both processor system will deassert their outputs within two clocks. All processor straps must
e
bus agents. For a locked sequence of transactions, LOCK# is asserted be valid within the specified setup time before RESET# is deasserted.
id
from the beginning of the first transaction to the end of the last RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the agent
f
transaction. responsible for completion of the current transaction), and must connect
When the priority agent asserts BPRI# to arbitrate for ownership of the the appropriate pins of both processor system bus agents.
n
processor system bus, it will wait until it observes LOCK# deasserted. RSVD - These pins are RESERVED and must be left unconnected on the board.
o
This enables symmetric agents to retain ownership of the processor However, it is recommended that routing channels to these pins on the
C
system bus throughout the bus locked operation and ensure the board be kept open for possible future use. Please refer to the platform
atomicity of lock. design guides for more details.
PRDY# O Probe Ready signal used by debug tools to determine processor debug SLP# I SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to
readiness. enter the Sleep state. During Sleep state, the processor stops providing
PREQ# I Probe Request signal used by debug tools to request debug operation of internal clock signals to all units, leaving only the Phase-Locked Loop
the processor. (PLL) still operating. Processors in this state will not recognize snoops
PROCHOT# O PROCHOT# (Processor Hot) will go active when the processor or interrupts. The processor will recognize only assertion of the
temperature monitoring sensor detects that the processor has reached its RESET# signal, deassertion of SLP#, and removal of the BCLK input
maximum safe operating temperature. This indicates that the processor while in Sleep state. If SLP# is deasserted, the processor exits Sleep
Thermal Control Circuit has been activated, if enabled. state and returns to Stop-Grant state, restarting its internal clock signals
This signal may require voltage translation on the motherboard. to the bus and processor core units. If DPSLP# is asserted while in the
PSI# O Processor Power Status Indicator signal. This signal is asserted when the Sleep state, the processor will exit the Sleep state and transition to the
processor is in a lower state (Deep Sleep and Deeper Sleep). Deep Sleep state.
73

SMI# I SMI# (System Management Interrupt) is asserted asynchronously by VCC I Processor core power supply.
system logic. On accepting a System Management Interrupt, the VCCA[3:0] I VCCA provides isolated power for the internal processor core PLL’s.
processor saves the current state and enter System Management Mode VCCP I Processor I/O Power Supply.
(SMM). An SMI Acknowledge transaction is issued, and the processor VCCQ[1:0] I Quiet power supply for on die COMP circuitry. These pins should be
begins program execution from the SMM handler. connected to VCCP on the motherboard. However, these connections
If SMI# is asserted during the deassertion of RESET# the processor will should enable addition of decoupling on the VCCQ lines if necessary.
tristate its outputs. VCCSENSE O VCCSENSE is an isolated low impedance connection to processor core
t
power (VCC ). It can be used to sense or measure power near the silicon
STPCLK# I STPCLK# (Stop Clock), when asserted, causes the processor to enter a
t n
with little noise.
low power Stop-Grant state. The processor issues a Stop-Grant
e e
VID[5:0] O VID[5:0] (Voltage ID) pins are used to support automatic selection of
Acknowledge transaction, and stops providing internal clock signals to
r
power supply voltages (Vcc). Unlike some previous generations of
all processor core units except the system bus and APIC units. The
c m
processors, these are CMOS signals that are driven by the Intel Pentium
processor continues to snoop bus transactions and service interrupts M processor. The voltage supply for these pins must be valid before the
e
while in Stop-Grant state. When STPCLK# is deasserted, the processor VR can supply Vcc to the processor. Conversely, the VR output must be
S u
restarts its internal clock to all units and resumes execution. The disabled until the voltage supply for the VID pins becomes valid. The
c
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
c Do
VID pins are needed to support the processor voltage specification
asynchronous input. variations.
a
TCK I TCK (Test Clock) provides the clock input for the processor Test Bus VSSSENSE O VSSSENSE is an isolated low impedance connection to processor core
iT ial
(also known as the Test Access Port). VSS. It can be used to sense or measure ground near the silicon with
TDI I TDI (Test Data In) transfers serial test data into the processor. TDI little noise.
provides the serial input needed for JTAG specification support.
TDO O
M t
TDO (Test Data Out) transfers serial test data out of the processor. TDO
n
provides the serial output needed for JTAG specification support.
I TEST1, TEST2, and TEST3 must be left unconnected but should have a
e
TEST1,
TEST2, stuffing option connection to V SS separately using 1-k, pull-down
id
TEST3 resisitors.
f
THERMDA Other Thermal Diode Anode.
Other Thermal Diode Cathode.
n
THERMDC
O The processor protects itself from catastrophic overheating by use of an
o
THERMTRIP#
internal thermal sensor. This sensor is set well above the normal
C
operating temperature to ensure that there are no false trips. The
processor will stop all execution when the junction temperature exceeds
approximately 125°C. This is signalled to the system by the
THERMTRIP# (Thermal Trip) pin.
TMS I TMS (Test Mode Select) is a JTAG specification support signal used by
debug tools.
TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both system bus agents.
TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
74
5.2 Intel 855GM/GME North Bridge(1)

Host Interface Signal Descriptions Host Interface Signal Descriptions(Continued)
ADS# I/O Address Strobe: The system bus owner asserts ADS# to indicate the DINV[3:0]# I/O Dynamic Bus Inversion: Driven along with the HD[63:0]# signals.
AGTL+ first of two cycles of a request phase. The GMCH can assert this AGTL+ Indicates if the associated signals are inverted or not. DINV[3:0]# are
signal for snoop cycles and asserted such that the number of data bits driven electrically low (low
interrupt messages. voltage) within the corresponding 16-bit group never exceeds 8.
BNR# I/O Block Next Request: Used to block the current request bus owner DINV# Data Bits
AGTL+ from issuing a new request. This signal is used to dynamically control DINV[3]# HD[63:48]#
the CPU bus pipeline depth.
t
DINV[2]# HD[47:32]#
BPRI# O Bus Priority Request: The GMCH is the only Priority Agent on the DINV[1]# HD[31:16]#
AGTL+
t
e e n
system bus. It asserts this signal to obtain the ownership of the
address bus. This signal has priority over symmetric bus requests and I
DINV[0]# HD[16:0]#
Deep Sleep #: This signal comes from the ICH4-M device, providing
r
DPSLP#
will cause the current symmetric owner to CMOS an indication of C3 and C4 state control to the CPU. Deassertion of
c m
stop issuing new transactions unless the HLOCK# signal was this signal is used as an early indication for C3 and C4 wake up (to
e
asserted. active HPLL). Note that this is a low-voltage
S u
BREQ0# I/O Bus Request 0#: The GMCH pulls the processor bus BREQ0# signal CMOS buffer operating on the FSB VTT power plane.
c
AGTL+ low during CPURST#. The signal is sampled by the processor on the
c Do
DRDY# I/O Data Ready: Asserted for each cycle that data is transferred.
active-to-inactive transition of CPURST#. The minimum setup time AGTL+
a
for this signal is 4 BCLKs. The minimum hold time is 2 clocks and HA[31:3]# I/O Host Address Bus: HA[31:3]# connects to the CPU address bus.
iT ial
the maximum hold time is 20 BCLKs. BREQ0# should be tristated AGTL+ During processor cycles the HA[31:3]# are inputs. The GMCH drives
after the hold time requirement has been satisfied. HA[31:3]# during snoop cycles on behalf of Hub interface.
During regular operation, the GMCH will use BREQ0# as an early HA[31:3]# are transferred at 2x rate. Note that the
M t
indication for FSB Address and Ctl input buffer and sense amp address is inverted on the CPU bus.
activation.
n
HADSTB[1:0]# I/O Host Address Strobe: HA[31:3]# connects to the CPU address bus.
CPURST# O CPU Reset: The CPURST# pin is an output from the GMCH. The
e
AGTL+ During CPU cycles, the source synchronous strobes are used to
AGTL+ GMCH asserts CPURST# while RESET# (PCIRST# from ICH4-M) transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.
id
is asserted and for approximately 1 ms after RESET# is deasserted. Strobe Address Bits
The CPURST# allows the processor to begin execution in a known
f
HADSTB[0]# HA[16:3]#, HREQ[4:0]#
state. HADSTB[1]# HA[31:17]#
n
Note that the ICH4-M must provide CPU strap set-up and hold-times
I/O Host Data: These signals are connected to the CPU data bus.
o
HD[63:0]#
around CPURST#.
AGTL+ HD[63:0]# are transferred at 4x rate. Note that the data signals are
This requires strict synchronization between GMCH, CPURST#
C
inverted on the CPU bus.
deassertion and ICH4-M driving the straps.
DBSY# I/O Data Bus Busy: Used by the data bus owner to hold the data bus for
AGTL+ transfers requiring more than one cycle.
DEFER# O Defer: GMCH will generate a deferred response as defined by the
AGTL+ rules of the GMCH’s Dynamic Defer policy. The GMCH will also
use the DEFER# signal to indicate a CPU retry response.
75

Host Interface Signal Descriptions (Continued) DDR SDRAM Interface Descriptions
HDSTBP[3:0]# I/O Differential Host Data Strobes: The differential source synchronous SCS[3:0]# O Chip Select: These pins select the particular DDR SDRAM
HDSTBN[3:0]# AGTL+ strobes are used to transfer HD[63:0]# and DINV[3:0]# at the 4x SSTL_2 components during the active state.
transfer rate. NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM
Strobe Data Bits device row.
HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, DINV[3]# These signals can be toggled on every rising System Memory Clock
HDSTBP[2]#, HDSTBN[2]# HD[47:32]#, DINV[2]# edge (SCMDCLK).
HDSTBP[1]#, HDSTBN[1]# HD[31:16]#, DINV[1]# O Multiplexed Memory Address: These signals are used to provide
t
SMA[12:0]
HDSTBP[0]#, HDSTBN[0]# HD[15:0]#, DINV[0]# SSTL_2 the multiplexed row and column address to the DDR SDRAM.
HIT# I/O
AGTL+
t
e e n
Hit: Indicates that a caching agent holds an unmodified version of the
requested line. Also, driven in conjunction with HITM# by the target
SBA[1:0] O
SSTL_2
Bank Select (Memory Bank Address): These signals define which
banks are selected within each DDR SDRAM row. The SMA and
r
to extend the snoop window. SBA signals combine to address every possible location within a
c m
HITM# I/O Hit Modified: Indicates that a caching agent holds a modified version DDR SDRAM device.
e
AGTL+ of the requested line and that this agent assumes responsibility for SRAS# O DDR Row Address Strobe: SRAS# may be heavily loaded and
S u
providing the line. SSTL_2 requires tw0 DDR SDRAM clock cycles for setup time to the DDR
c
Also, driven in conjunction with HIT# to extend the snoop window. SDRAMs. Used with SCAS# and SWE# (along with SCS#) to define
HLOCK# I/O
AGTL+
ac Do
Host Lock: All CPU bus cycles sampled with the assertion of
HLOCK# and ADS#, until the negation of HLOCK# must be atomic, SCAS# O
the system memory commands.
DDR Column Address Strobe: SCAS# may be heavily loaded and
iT ial
i.e. no Hub interface snoopable access to system memory is allowed SSTL_2 requires two clock cycles for setup time to the DDR SDRAMs. Used
when HLOCK# is asserted by the CPU. with SRAS# and SWE# (along with SCS#) to define the system
I/O Host Request Command: Defines the attributes of the request. memory commands.
M t
HREQ[4:0]#
AGTL+ HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting SWE# O Write Enable: Used with SCAS# and SRAS# (along with SCS#) to
agent during both halves of the Request Phase. In the first half the SSTL_2 define the DDR SDRAM commands. SWE# is asserted during writes
en
signals define the transaction type to a level of
detail that is sufficient to begin a snoop request. In the second half the
to DDR SDRAM.
SWE# may be heavily loaded and requires two clock cycles for setup
id
signals carry additional information to define the complete transaction time to the DDR SDRAMs.
f
type. SDQ[71:0] I/O Data Lines: These signals are used to interface to the DDR SDRAM
The transactions supported by the GMCH Host Bridge are defined in SSTL_2 data bus.
n
the Host Interface section of this document. NOTE: ECC error detection is supported: by the SDQ[71:64] signals.
o
HTRDY# O Host Target Ready: Indicates that the target of the processor
C
AGTL+ transaction is able to enter the data transfer phase.
RS[2:0]# O Response Status: Indicates the type of response according to the
AGTL+ following the table:
RS[2:0]# Response type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by GMCH)
100 Hard Failure (not driven by GMCH)
101 No data response
110 Implicit Write back
111 Normal data response
76

DDR SDRAM Interface Descriptions (Continued) AGP Addressing Signal Descriptions
SDQS[8:0] I/O Data Strobes: Data strobes are used for capturing data. During GPIPE# I Pipelined Read: This signal is asserted by the AGP master to
SSTL_2 writes, SDQS is centered on data. During reads, SDQS is edge AGP indicate a full width address is to be enqueued on by the target using
aligned with data. The following list matches the data strobe with the the AD bus. One address is placed
data bytes. in the AGP request queue on each rising clock edge while PIPE# is
There is an associated data strobe (DQS) for each data signal (DQ) asserted. When PIPE# is deasserted no new requests are queued
and check bit across the AD bus.
(CB) group. During SBA Operation: This signal is not used if SBA (Side Band
SDQS[7] -> SDQ[63:56]
SDQS[6] -> SDQ[55:48]
t nt Addressing) is selected.
During FRAME# Operation: This signal is not used during AGP
e e
SDQS[5] -> SDQ[47:40] FRAME# operation.
r
SDQS[4] -> SDQ[39:32] PIPE# is a sustained tri-state signal from masters (graphics
c m
SDQS[3] -> SDQ[31:24] controller), and is an input to the GMCH.
e
SDQS[2] -> SDQ[23:16] GSBA[7:0] I Side-band Address: These signals are used by the AGP master
S u
SDQS[1] -> SDQ[15:8] AGP (graphics controller) to pass address and command to the GMCH. The
c
SDQS[0] -> SDQ[7:0] SBA bus and AD bus operate independently. That is, transactions can
c Do
NOTE: ECC error detection is supported by the SDQS[8] signal. proceed on the SBA bus and the
a
SCKE[3:0] O Clock Enable: These pins are used to signal a self-refresh or power AD bus simultaneously.
iT ial
SSTL_2 down command to the DDR SDRAM array when entering system During PIPE# Operation: These signals are not used during PIPE#
suspend. SCKE is also used to dynamically power down inactive operation.
DDR SDRAM rows. There is one During FRAME# Operation: These signals are not used during
M t
SCKE per DDR SDRAM row. These signals can be toggled on every AGP FRAME# operation.
rising SCK edge. NOTE: When sideband addressing is disabled, these signals are
n
SMAB[5,4,2,1] O Memory Address Copies: These signals are identical to isolated (no external/internal pull-ups are required).
e
SSTL_2 SMA[5,4,2,1] and are used to reduce loading for selective 5 contains two mechanisms to queue requests by the AGP master. Note that the master can only use
id
CPC(clock-per-command). These copies are not inverted. one mechanism. The master may not switch methods without a full reset of the system. When PIPE# is
O Data Mask: When activated during writes, the corresponding data
f
SDM[8:0] used to queue addresses the master isnot allowed to queue addresses using the SBA bus. For example,
SSTL_2 groups in the DDR SDRAM are masked. There is one SDM for every during configuration time, if the master indicates that it can use either mechanism, the configuration
n
eight data lines. SDM can be sampled on both edges of the data software will indicate which mechanism the master will use. Once this choice has been made, the
o
strobes. master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use
NOTE: ECC error detection is supported by the SDM[8] signal.
C
the other mode. This change of modes is not a dynamic mechanism, but rather a static decision when
RCVENOUT# O Clock Output: Reserved, NC. the device is first being configured after reset
SSTL_2
RCVENIN# O Clock Input: Reserved, NC.
SSTL_2
77

AGP Status Signal Descriptions AGP Flow Control Signals
GST[2:0] O Status: Provides ST[2:0 Meaning GRBF# I Read Buffer Full: Read buffer full indicates if the master is ready to
AGP information from AGP accept previously requested low priority read data. When RBF# is
the arbiter to an 000 Previously requested low priority asserted the GMCH is not allowed to initiate the return low priority
AGP Master on read data is being returned to the read data. That is, the GMCH can finish
what it may do. master arbiter to an AGP returning the data for the request currently being serviced. RBF# is
ST[2:0] only only sampled at the beginning of a cycle.
have meaning If the AGP master is always ready to accept return read data then it is
to the master
when its GNT# is
t nt not required to implement this signal.

e e
001 Previously requested high priority
asserted. When FRAME# operation.
r
read data is being returned to the
GNT# is GWBF# I Write-Buffer Full: indicates if the master is ready to accept Fast
c m
master
deasserted AGP Write data from the GMCH. When WBF# is asserted the GMCH is
010 The master is to provide low priority
e
these signals have not allowed to drive Fast Write data to the AGP master. WBF# is
u
write data for a previously queued
S
no meaning and only sampled at the beginning of a cycle.
c
write command
must be gnored. If the AGP master is always ready to accept fast write data then it is
c Do
011 The master is to provide high
not required to implement this signal.
a
priority write data for a previously
queued write command.
iT ial
FRAME# operation.
100 Reserved
101
M t
Reserved
110
en
Reserved
111
fid
The master has been given
onpermission to start a bus transaction.

The master may queue AGP requests
C
by asserting PIPE# or start a PCI
transaction by asserting FRAME#
78

AGP/PCI Signals-Semantics Descriptions AGP Strobe Descriptions
GFRAME# I/O G_FRAME: Frame. GADSTB[0] I/O Address/Data Bus Strobe-0: provides timing for 2x and 4x data on
AGP During PIPE# and SBA Operation: Not used by AGP SBA and AGP AD[15:0] and C/BE[1:0]# signals. The agent that is providing the
PIPE# operations. data will drive this signal.
During Fast Write Operation: Used to frame transactions as an GADSTB#[0] I/O Address/Data Bus Strobe-0 Complement: With AD STB0, forms a
output during Fast Writes. AGP differential strobe pair that provides timing information for the
During FRAME# Operation: G_FRAME# is an output when the AD[15:0] and C/BE[1:0]# signals. The agent that is providing the
GMCH acts as an initiator on the AGP Interface. G_FRAME# is data will drive this signal.
asserted by the GMCH to indicate the
t nt
beginning and duration of an access. G_FRAME# is an input when
GADSTB[1] I/O
AGP
Address/Data Bus Strobe-1: Provides timing for 2x and 4x data on
AD[31:16] and C/BE[3:2]# signals. The agent that is providing the
e e
the GMCH acts as a FRAME#-based AGP target. As a data will drive this signal.
r
FRAME#-based AGP target, the GMCH latches the C/BE[3:0]# and GADSTB#[1] I/O Address/Data Bus Strobe-1 Complement: With AD STB1, forms a
c m
the AD[31:0] signals on the first clock edge on which AGP differential strobe pair that provides timing information for the
e
GMCH samples FRAME# active. AD[15:0] and C/BE[1:0]# signals in 4X mode. The agent that is
S u
GIRDY# I/O G_IRDY#: Initiator Ready. providing the data will drive this signal.
c
AGP During PIPE# and SBA Operation: Not used while enqueueing
c Do
GSBSTB I Sideband Strobe: Provides timing for 2x and 4x data on the
requests via AGP SBA and PIPE#, but used during the data phase of AGP SBA[7:0] bus. It is driven by the AGP master after the system has
a
PIPE# and SBA transactions. been configured for 2x or 4x sideband address mode.
iT ial
During FRAME# Operation: G_IRDY# is an output when GMCH GSBSTB# I Sideband Strobe Complement: The differential complement to the
acts as a FRAME#-based AGP initiator and an input when the GMCH AGP SB_STB signal. It is used to provide timing 4x mode.
acts as a FRAME#-based AGP target. The assertion of G_IRDY#
M t
indicates the current FRAME#-based AGP bus initiator's ability to
complete the current data phase of the transaction.
en
During Fast Write Operation: In Fast Write mode, G_IRDY#
indicates that the AGP-compliant master is ready to provide all write
id
data for the current transaction. Once G_IRDY# is asserted for a write
f
operation, the master is not allowed to insert wait states. The master is
never allowed to insert a wait state during the initial data transfer (32
n
bytes) of a write transaction. However, it may insert wait states after
o
each 32-byte block is transferred.
79

AGP/PCI Signals-Semantics Descriptions (Continued) ATP/PCI Signals-Semantics Descriptions(Continued)
GTRDY# I/O G_TRDY#: Target Ready. GGNT# O G_GNT#: Grant.
AGP During PIPE# and SBA Operation: Not used while enqueueing AGP During SBA, PIPE# and FRAME# Operation: G_GNT#, along
requests via AGP SBA and PIPE#, but used during the data phase of with the information on the ST[2:0] signals (status bus), indicates
PIPE# and SBA transactions. how the AGP interface will be used next. Refer to the AGP Interface
During FRAME# Operation: G_TRDY# is an input when the Specification, Revision 2.0 for further explanation
GMCH acts as an AGP initiator and is an output when the GMCH of the ST[2:0] values and their meanings.
acts as a FRAME#-based AGP target. The assertion of G_TRDY#
t
GAD[31:0] I/O G_AD[31:0]: Address/Data Bus.
indicates the target’s ability to complete the current data phase of the AGP During PIPE# and FRAME# Operation: The G_AD[31:0] signals
transaction.
t
e e n
During Fast Write Operation: In Fast Write mode, G_TRDY#
are used to transfer both address and data information on the AGP
interface.
r
indicates the AGP-compliant target is ready to receive write data for During SBA Operation: The G_AD[31:0] signals are used to
c m
the entire transaction (when the transfer size is less than or equal to 32 transfer data on the AGP interface.
e
bytes) or is ready to transfer the initial or GCBE#[3:0] I/O Command/Byte Enable.
S u
subsequent block (32 bytes) of data when the transfer size is greater AGP During FRAME# Operation: During the address phase of a
c
than 32 bytes. The target is allowed to insert wait states after each transaction, the G_CBE[3:0]# signals define the bus command.
GSTOP# I/O G_STOP#: Stop.
ac Do
block (32 bytes) is transferred on write transactions. During the data phase, the G_CBE[3:0]# signals are used as byte
enables. The byte enables determine which byte lanes carry
iT ial
AGP During PIPE# and SBA Operation: This signal is not used during meaningful data. The commands issued on the G_CBE# signals
PIPE# or SBA operation. during FRAME#-based AGP transactions are the same G_CBE#
During FRAME# Operation: G_STOP# is an input when the command described in the PCI 2.2 specification.
M t
GMCH acts as a FRAME#-based AGP initiator and is an output when
the GMCH acts as a FRAME#-based AGP target. G_STOP# is used
During PIPE# Operation: When an address is enqueued using
PIPE#, the C/BE# signals carry command information. The command
GDEVSEL# I/O G_ DEVSEL#: Device Select.

en
for disconnect, retry, and abort sequences on the AGP interface. encoding used during PIPE#-based AGP is different than the
command encoding used during FRAME#-based AGP cycles (or
id
AGP During PIPE# and SBA Operation: This signal is not used during standard PCI cycles on a PCI bus).
f
PIPE# or SBA operation. During SBA Operation: These signals are not used during SBA
During FRAME# Operation: G_DEVSEL#, when asserted, operation.
n
indicates that a FRAME#-based AGP target device has decoded its GPAR I/O Parity.
o
address as the target of the current access. The GMCH asserts AGP During FRAME# Operation: G_PAR is driven by the GMCH when
C
G_DEVSEL# based on the DDR SDRAM it acts as a FRAME#-based AGP initiator during address and data
address range being accessed by a PCI initiator. As an input, phases for a write cycle, and during the address phase for a read
G_DEVSEL# indicates whether the AGP master has recognized a cycle. G_PAR is driven by the GMCH when it acts as a
PCI cycle to it. FRAME#-based AGP target during each data phase of a
GREQ# I G_REQ#: Request. FRAME#-based AGP memory read cycle. Even parity is generated
AGP During SBA Operation: This signal is not used during SBA across G_AD[31:0] and G_CBE[3:0]#.
operation. During SBA and PIPE# Operation: This signal is not used during
During PIPE# and FRAME# Operation: G_REQ#, when asserted, SBA and PIPE# operation.
indicates that the AGP master is requesting use of the AGP interface PCIRST# from the ICH4-M is assumed to be connected to RSTIN# and is used to reset AGP interface
to run a FRAME#- or PIPE#-based operation. logic within the GMCH. The AGP agent will also typically use PCIRST# provided by the ICH4-M as
an input to reset its internal logic.
80

Hub Interface Signals Digital Video Output B (DVOB) Port Signal Descriptions
Signal Name Type Description Name Type Description
HL[10:0] I/O Packet Data: Data signals used for HI read and write operations. DVOBD[11:0] O DVOB Data: This data bus is used to drive 12-bit RGB data on each
Hub DVO edge of the differential clock signals, DVOBCLK and DVOBCLK#.
HLSTB I/O Packet Strobe: One of two differential strobe signals used to transmit This provides 24-bits of data per clock period. In dual channel mode,
Hub or receive packet data over HI. this provides the lower 12-bits of pixel data.
HLSTB# I/O Packet Strobe Complement: One of two differential strobe signals DVOBD[11:0] should be left as left as NC (“Not Connected”) if not
Hub used to transmit or receive packet data over HI. used.
O Horizontal Sync: HSYNC signal for the DVOB interface.
t
DVOBHSYNC
DVO DVOBHSYNC should be left as left as NC (“Not Connected”) if not
t
e e n DVOBVSYNC O
used.
Vertical Sync: VSYNC signal for the DVOB interface.
r
c m
DVO DVOBVSYNC should be left as left as NC (“Not Connected”) if the
signal is NOT used when using internal graphics device.
e
DVOBBLANK# O Flicker Blank or Border Period Indication: DVOBBLANK# is a
u
Dedicated LVDS LCD Flat Panel Interface Signal Descriptions
S
DVO programmable output pin driven by the GMCH.
c
Name Type Voltage Description
When programmed as a blank period indication, this pin indicates
ICLKAP O
LVDS 245-800 MHz
ac Do
1.25 V± 225 mV Channel A differential clock pair output (true): active pixels excluding the border. When programmed as a border
period indication, this pin indicates active pixel including the border
iT ial
ICLKAM O 1.25 V±225 mV Channel A differential clock pair output pixels.
LVDS (compliment): 245-800 MHz. DVOBBLANK# should be left as left as NC (“Not Connected”) if not
IYAP[3:0] O 1.25 V±225 mV Channel A differential data pair 3:0 output (true): used.
LVDS
O
245-800MHz.
M t
1.25 V±225 mV Channel A differential data pair 3:0 output
DVOBFLDSTL I TV Field and Flat Panel Stall Signal. This input can be
n
IYAM[3:0] DVO programmed to be either a TV Field input from the TV encoder or
LVDS (compliment): 245-800 MHz. Stall input from the flat panel.
ICLKBP O
e
1.25 V±225 mV Channel B differential clock pair output (true): DVOB TV Field Signal: When used as a Field input, it synchronizes
id
LVDS 245-800 MHz. the overlay field with the TV encoder field when the overlay is
f
ICLKBM O 1.25 V±225 mV Channel B differential clock pair output displaying an interleaved source.
LVDS (compliment): 245-800 MHz. DVOB Flat Panel Stall Signal: When used as the Stall input, it
IYBP[3:0] O
LVDS 245-800MHz.
on
1.25 V±225 mV Channel B differential data pair 3:0 output (true): indicates that the pixel pipeline should stall one horizontal line. The
signal changes during horizontal blanking. The panel fitting logic,
C
IYBM[3:0] O 1.25 V± 225 mV Channel B differential data pair 3:0 output when expanding the image vertically, uses this.
LVDS (compliment): 245-800 MHz. DVOBFLDSTL needs to be pulled down if not used.
81

DVOB and DVOC Port Common Signal Descriptions Digital Video Output C (DVOC) Port Signal Descriptions
Name Type Description Name Type Description
DVOBCINTR# I DVOBC Interrupt: This pin is used to signal an interrupt, typically DVOCD[11:0] O DVOC Data: This data bus is used to drive 12-bit RGB data on each
DVO used to indicate a hot plug or unplug of a digital display. DVO edge of the differential clock signals, DVOCCLK and DVOCCLK#.
ADDID[7:0] I ADDID[7:0]: These pins are used to communicate to the Video BIOS This provides 24-bits of data per clock period. In dual channel mode,
DVO when an external device is interfaced to the DVO port. this provides the upper 12-bits of pixel data.
Note: Bit[7] needs to be strapped low when an on-board DVO device DVOCD[11:0] should be left as left as NC (“Not Connected”) if not
is present. used.
The other pins should be left as NC.
t
DVOCHSYNC O Horizontal Sync: HSYNC signal for the DVOC interface.
I DVODETECT: This strapping signal indicates to the GMCH DVO DVOCHSYNC should be left as left as NC (“Not Connected”) if not
t
DVODETECT
n
DVO whether a DVO device is present or not. When a DVO device is used.
connected, then DVODETECT = 0.
re e DVOCVSYNC O
DVO
Vertical Sync: VSYNC signal for the DVOC interface.
DVOCVSYNC should be left as left as NC (“Not Connected”) if the
c m
signal is NOT used when using internal graphics device.
e
O Flicker Blank or Border Period Indication: DVOCBLANK# is a
u
DVOCBLANK#
S
DVO programmable output pin driven by the GMCH.
Analog CRT Display Signal Descriptions

c Do c When programmed as a blank period indication, this pin indicates
active pixels excluding the border. When programmed as a border
a
Pin Name Type Description period indication, this pin indicates active pixel including the border
iT ial
pixels.
VSYNC O CRT Vertical Synchronization: This signal is used as the vertical DVOCBLANK# should be left as left as NC (“Not Connected”) if not
CMOS sync signal. used.
M t
HSYNC O CRT Horizontal Synchronization: This signal is used as the DVOCFLDSTL I TV Field and Flat Panel Stall Signal. This input can be
CMOS horizontal sync signal.
n
DVO programmed to be either a TV Field input from the TV encoder or
RED O Red (Analog Video Output): This signal is a CRT Analog video Stall input from the flat panel.
e
Analog output from the internal color palette DAC. The DAC is designed for DVOC TV Field Signal: When used as a Field input, it synchronizes
id
a 37.5-§Ù equivalent load on each pin (e.g., 75-§Ù resistor on the the overlay field with the TV encoder field when the overlay is
board, in parallel with the 75-§Ù CRT load).
f
displaying an interleaved source.
RED# O Red# (Analog Output): Tied to ground. DVOC Flat Panel Stall Signal: When used as the Stall input, it
n
Analog indicates that the pixel pipeline should stall one horizontal line. The
o
GREEN O Green (Analog Video Output): This signal is a CRT analog video signal changes during horizontal blanking. The panel fitting logic,
C
Analog output from the internal color palette DAC. The DAC is designed for when expanding the image vertically, uses this.
a 37.5-§Ù equivalent load on each pin (e.g.,75-§Ù resistor on the DVOCFLDSTL needs to be pulled down if not used.
board, in parallel with the 75- §Ù CRT load).
GREEN# O Green# (Analog Output): Tied to ground.
Analog
BLUE O Blue (Analog Video Output) : This signal is a CRT Analog video
Analog output from the internal color palette DAC. The DAC is designed for
a 37.5-§Ù equivalent load on each pin (e.g., 75-
ohm resistor on the board, in parallel with the 75-§Ù CRT load).
BLUE# O Blue# (Analog Output): Tied to ground.
Analog
82

GPIO Signal Descriptions GPIO Signal Descriptions(Continued)
GPIO I/F Total Type Comments GPIO I/F Total Type Comments
RSTIN# I Reset: Primary Reset, Connected to PCIRST# of ICH4-M. MI2CCLK I/O DVO I2C Clock: This signal is used as the I2C_CLK for a digital
CMOS DVO display (i.e. TV-Out Encoder, TMDS transmitter). This signal is
PWROK I Power OK: Indicates that power to GMCH is stable. tri-stated during a hard reset.
CMOS MI2CDATA I/O DVO I2C Data: This signal is used as the I2C_DATA for a digital
AGPBUSY# O AGPBUSY: Output of the GMCH IGD to the ICH4-M, which DVO display (i.e. TV-Out Encoder, TMDS transmitter). This signal is
CMOS indicates that certain graphics activity is taking place. It will indicate tri-stated during a hard reset.
t
to the ACPI software not to enter the C3 state. It will MDVICLK I/O DVI DDC Clock: This signal is used as the DDC clock for a digital
also cause a C3/C4 exit if C3/C4 was being entered, or was already DVO display connector (i.e. primary digital monitor). This signal is
entered when
t
e e n
AGPBUSY# went active. Not active when the IGD is in any ACPI I/O
tri-stated during a hard reset.
DVI DDC Data: The signal is used as the DDC data for a digital
r
MDVIDATA
state other than D0. DVO display connector (i.e. primary digital monitor). This signal is
EXTTS_0 I
CMOS
ec m
External Thermal Sensor Input: This signal is an active low input
to the GMCH and is used to monitor the thermal condition around the I/O
DVI DDC Clock: The signal is used as the DDC data for a digital
u
MDDCDATA
S
system memory and is used for triggering a read throttle. The GMCH DVO display connector (i.e. secondary digital monitor). This signal is
to the ICH4-M upon the triggering

c Do c
can be optionally programmed to send a SERR, SCI, or SMI message
MDDCCLK I/O
DVI DDC Data: The signal is used as the DDC clock for a digital
a
of this signal. DVO display connector (i.e. secondary digital monitor). This signal is
iT ial
LCLKCTLA O SSC Chip Clock Control: Can be used to control an external clock tri-stated during a hard reset.
CMOS chip with SSC control.
O SSC Chip Data Control: Can be used to control an external clock
M t
LCLKCTLB
CMOS chip for SSC control.
n
PANELVDDEN O LVDS LCD Flat Panel Power Control: This signal is used enable
e
CMOS power to the panel interface.
PANELBKLTE O LVDS LCD Flat Panel Backlight Enable: This signal is used to
id
N CMOS enable the backlight inverter (BLI)
f
PANELBKLTC O LVDS LCD Flat Panel Backlight Brightness Control: This signal
CMOS is used as the Pulse
n
TL
Width Modulated (PWM) control signal to control the backlight
DDCACLK
DDCADATA
I/O
CMOS
I/O
inverter.
Co
CRT DDC Clock: This signal is used as the DDC clock signal
between the CRT monitor and the GMCH.
CRT DDC Data: This signal is used as the DDC data signal between
CMOS the CRT monitor and the GMCH.
DDCPCLK I/O Panel DDC Clock: This signal is used as the DDC clock signal
CMOS between the LFP and the GMCH.
DDCPDATA I/O Panel DDC Data: This signal is used as the DDC data signal
CMOS between the LFP and the GMCH.
83
5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(1)

Hub Interface Signals Firmware Hub Interface Signals
HI[11:0] I/O Hub Interface Signals FWH[3:0]/ I/O Firmware Hub Signals. Muxed with LPC address signals.
HI_STB/HI_STBS I/O Hub Interface Strobe/ Hub Interface Strobe Second: One of two LAD[3:0]
differential strobe signals used to transmit and receive data through FWH[4]/ I/O LFRAME# Firmware Hub Signals. Muxed with LPC LFRAME#
the hub interface. LFRAME# signal.
Hub Interface 1.5 mode this signal is not differential and is the
second of the two strobe signals.
t
HI_STB#/ I/O Hub Interface Strobe Complement / Hub Interface Strobe First: PCI Interface Signals
t
One of two differential strobe signals used to transmit and receive
n
HI_STBF Signal Name Type Description
e e
data through the hub interface. AD[31:0] I/O PCI Address/Data: AD[31:0] is a multiplexed address and data
r
Hub Interface 1.5 mode this signal is not differential and is the first bus. During the first clock of a transaction, AD[31:0] contain a
of the two strobe signals.
c m
physical address (32 bits). During subsequent clocks, AD[31:0]
I/O Hub Interface Compensation: Used for hub interface buffer
e
HICOMP contain data. The ICH4 drives all 0s on AD[31:0] during the address
u
compensation.
S
phase of all PCI Special Cycles.
c
HI_VSWING I Hub Interface Voltage Swing: Analog input used to control the C/BE[3:0]# I/O Bus Command and Byte Enables: The command and byte enable
c Do
voltage swing and impedance strength of hub interface pins. signals are multiplexed on the same PCI pins. During the address
a
phase of a transaction, C/BE[3:0]# define the bus command. During
the data phase, C/BE[3:0]# define the Byte Enables.
iT ial
LAN Connect Interface Signals C/BE[3:0]# Command Type
Signal Name Type Description 0000 Interrupt Acknowledge
M t
LAN_CLK I LAN I/F Clock: Driven by the LAN Connect component. 0001 Special Cycle
Frequency range is 5 MHz to 50 MHz. 0010 I/O Read
n
I Received Data: The LAN Connect component uses these signals to 0011 I/O Write
e
LAN_RXD[2:0]
transfer data and control information to the integrated LAN 0110 Memory Read
id
Controller. These signals have integrated weak pull-up resistors. 0111 Memory Write
1010 Configuration Read
f
LAN_TXD[2:0] O Transmit Data: The integrated LAN Controller uses these signals
1011 Configuration Write
to transfer data and control information to the LAN Connect
n
1100 Memory Read Multiple
component.
o
1110 Memory Read Line
LAN_RSTSYNC O LAN Reset/Sync: The LAN Connect component’s Reset and Sync
1111 Memory Write and Invalidate
C
signals are multiplexed onto this pin.
All command encodings not shown are reserved. The ICH4 does not
decode reserved values, and therefore will not respond if a PCI
master generates a cycle using one of the reserved values.
EEPROM Interface Signals DEVSEL# I/O Device Select: The ICH4 asserts DEVSEL# to claim a PCI
Signal Name Type Description transaction. As an output, the ICH4 asserts DEVSEL# when a PCI
EE_SHCLK O EEPROM Shift Clock: Serial shift clock output to the EEPROM. master peripheral attempts an access to an internal ICH4 address or
an address destined for the hub interface (main memory or AGP).
EE_DIN I EEPROM Data In: Transfers data from the EEPROM to the ICH3.
As an input, DEVSEL# indicates the response to an ICH4-initiated
This signal has an integrated pull-up resistor.
transaction on the PCI bus. DEVSEL# is tri-stated from the leading
EE_DOUT O EEPROM Data Out: Transfers data from the ICH3 to the edge of PCIRST#. DEVSEL# remains tri-stated by the ICH4 until
EEPROM. driven by a Target device.
EE_CS O EEPROM Chip Select: Chip select signal to the EEPROM.
84

PCI Interface Signals (Continued) PCI Interface Signals (Continued)
FRAME# I/O Cycle Frame: The current Initiator drives FRAME# to indicate the STOP# I/O Stop: STOP# indicates that the ICH4, as a Target, is requesting the
beginning and duration of a PCI transaction. While the Initiator Initiator to stop the current transaction. STOP# causes the ICH4, as
asserts FRAME#, data transfers continue. When the Initiator an Initiator, to stop the current transaction. STOP# is an output
negates FRAME#, the transaction is in the final data phase. when the ICH4 is a Target and an input when the ICH4 is an
FRAME# is an input to the ICH4 when the ICH4 is the Target, and Initiator. STOP# is tri-stated from the leading edge of PCIRST#.
FRAME# is an output from the ICH4 when the ICH4 is the Initiator. STOP# remains tri-stated until driven by the ICH4.
FRAME# remains tri- stated by the ICH4 until driven by an
t
PERR# I/O Parity Error: An external PCI device drives PERR# when it
Initiator. receives data that has a parity error. The ICH4 drives PERR# when
IRDY# I/O
t
e e n
Initiator Ready: IRDY# indicates the ICH4's ability, as an
Initiator, to complete the current data phase of the transaction. It is
it detects a parity error. The ICH4 can either generate an NMI# or
SMI# upon detecting a parity error (either detected internally or
r
used in conjunction with TRDY#. A data phase is completed on any reported via the PERR# signal).
c m
clock that both IRDY# and TRDY# are sampled asserted. During a REQ[4:0]# I PCI Requests: The ICH4 supports up to 6 masters on the PCI bus.
e
write, IRDY# indicates the ICH4 has valid data present on REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the
u
REQ[5]#/
S
AD[31:0]. During a read, it indicates the ICH4 is prepared to latch REQ[B]#/ other, but not both). If not used for PCI or PC/PCI,
c
data. IRDY# is an input to the ICH4 when the ICH4 is the Target GPIO[1] REQ[5]#/REQ[B]# can instead be used as GPIO[1].
ac Do
and an output from the ICH4 when the ICH4 is an Initiator. IRDY#
remains tri-stated by the ICH4 until driven by an Initiator.
NOTE: REQ[0]# is programmable to have improved arbitration
latency for for supporting PCI-based 1394 controllers.
iT ial
TRDY# I/O Target Ready: TRDY# indicates the ICH4's ability, as a Target, to GNT[4:0]# O PCI Grants: The ICH4 supports up to 6 masters on the PCI bus.
complete the current data phase of the transaction. TRDY# is used GNT[5]#/ GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the
in conjunction with IRDY#. A data phase is completed when both GNT[B]#/ other, but not both). If not needed for PCI or PC/PCI, GNT[5]# can
M t
TRDY# and IRDY# are sampled asserted.
During a read, TRDY# indicates that the ICH4, as a Target, has
GPIO[17] instead be used as a GPIO.
n
Pull-up resistors are not required on these signals. If pull-ups are
placed valid data on AD[31:0]. During a write, TRDY# indicates used, they should be tied to the Vcc3_3 power rail.
e
that the ICH4, as a Target, is prepared to latch data. TRDY# is an GNT[B]#/GNT[5]#/GPIO[17] has an internal pull-up.
id
input to the ICH4 when the ICH4 is the Initiator and an output from PCICLK I PCI Clock: This is a 33 MHz clock. PCICLK provides timing for
f
the ICH4 when the ICH4 is a Target. TRDY# is tri-stated from the all transactions on the PCI Bus.
leading edge of PCIRST#. TRDY# remains tri-stated by the ICH4 NOTE: This clock does not stop based on STP_PCI# signal.
n
until driven by a target. PCICLK only stops based on SLP_S1# or SLP_S3#.
o
PAR I/O Calculated/Checked Parity: PAR uses “even” parity calculated on PCIRST# O PCI Reset: ICH4 asserts PCIRST# to reset devices that reside on
C
36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the the PCI bus. The ICH4 asserts PCIRST# during power-up and when
ICH4 counts the number of 1s within the 36 bits plus PAR and the S/W initiates a hard reset sequence through the RC (CF9h) register.
sum is always even. The ICH4 always calculates PAR on 36 bits The ICH4 drives PCIRST# inactive a minimum of 1 ms after
regardless of the valid byte enables. The ICH4 generates PAR for PWROK is driven active. The ICH4 drives PCIRST# active
address and data phases and only guarantees PAR to be valid one a minimum of 1 ms when initiated through the RC register.
PCI clock after the corresponding address or data phase. The ICH4 PLOCK# I/O PCI Lock: This signal indicates an exclusive bus operation and
drives and tri-states PAR identically to the AD[31:0] lines except may require multiple transactions to complete. ICH4 asserts
that the ICH4 delays PAR by exactly one PCI clock. PAR is an PLOCK# when it performs non- exclusive transactions on the PCI
output during the address phase (delayed one clock) for all ICH4 bus. Devices on the PCI bus (other than the ICH4) are not permitted
initiated transactions. PAR is an output during the data phase to assert the PLOCK# signal.
(delayed one clock) when the ICH4 is the Initiator of a PCI write I/OD System Error: SERR# can be pulsed active by any PCI device that
SERR#
transaction, and when it is the Target of a read transaction. ICH4 detects a system error condition. Upon sampling SERR# active, the
checks parity when it is the Target of a PCI write transaction. If a ICH4 has the ability to generate an NMI, SMI#, or interrupt.
parity error is detected, the ICH4 will set the appropriate internal
status bits, and has the option to generate an NMI# or SMI#. 85

PCI Interface Signals (Continued) IDE Interface Signals (Continued)
PME# I/OD PCI Power Management Event: PCI peripherals drive PME# to PDD[15:0], I/O Primary and Secondary IDE Device Data: These signals directly
wake the system from low-power states S1-M–S5. PME# assertion SDD[15:0] drive the corresponding signals on the primary or secondary IDE
can also be enabled to generate an SCI from the S0 state. In some connector. There is a weak internal pull-down resistor on PDD[7]
cases the ICH4 may drive PME# active due to an internal wake and SDD[7].
event. The ICH4 will not drive PME# high, but it will be pulled up PDDREQ, I Primary and Secondary IDE Device DMA Request: These input
to VccSus3_3 by an internal pull-up resistor. SDDREQ signals are directly driven from the DRQ signals on the primary or
I/O PCI Clock Run: Used to support PCI Clock Run protocol. secondary IDE connector. It is asserted by the IDE device to request
t
CLKRUN#
Connects to PCI devices that need to request clock re-start, or a data transfer, and used in conjunction with the PCI bus master IDE
t n
prevention of clock stopping. function and are not associated with any AT compatible DMA
e e
NOTE: An external pull-up to the core power plane is required. channel. There is a weak internal pull-down resistor on these
r
REQ[A]#/ I PC/PCI DMA Request [A:B]: This request serializes ISA-like signals.
c m
GPIO[0] DMA Requests for the purpose of running ISA-compatible DMA PDDACK#, O Primary and Secondary IDE Device DMA Acknowledge: These
e
REQ[B]#/ cycles over the PCI bus. This is used by devices such as PCI based SDDACK# signals directly drive the DAK# signals on the primary and
S u
REQ[5]#/ Super I/O or audio codecs which need to perform legacy 8237 DMA secondary IDE connectors. Each is asserted by the ICH4 to indicate
c
GPIO[1] but have no ISA bus. to IDE DMA slave devices that a given data transfer cycle (assertion
ac Do
When not used for PC/PCI requests, these signals can be used as
General Purpose Inputs. REQ[B]# can instead be used as the 6th
of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is
used in conjunction with the PCI bus master IDE function and are
iT ial
PCI bus request. not associated with any AT-compatible DMA channel.
GNT[A]#/ O PC/PCI DMA Acknowledges [A: B]: This grant serializes an PDIOR#/ O Primary and Secondary Disk I/O Read (PIO and Non-Ultra
GPIO[16] ISA-like DACK# for the purpose of running DMA/ISA Master (PDWSTB/PRDMA DMA): This is the command to the IDE device that it may drive
M t
GNT[B]#/ cycles over the PCI bus. This is used by devices such as PCI based RDY#) data onto the PDD or SDD lines. Data is latched by the ICH4 on the
GNT[5]#/ Super/IO or audio codecs which need to perform legacy 8237 DMA deassertion edge of PDIOR# or SDIOR#. The IDE device is
n
GPIO[17] but have no ISA bus. selected either by the ATA register file chip selects (PDCS1# or
e
SDIOR#/
When not used for PC/PCI, these signals can be used as General SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the
(SDWSTB/SRDMA
id
Purpose Outputs. GNTB# can also be used as the 6th PCI bus IDE DMA acknowledge (PDDAK# or SDDAK#).
RDY#)
Primary and Secondary Disk Write Strobe (Ultra DMA Writes to
f
master grant output. These signal have internal pull-up resistors.
Disk): This is the data write strobe for writes to disk. When writing
n
to disk, ICH4 drives valid data on rising and falling edges of
o
PDWSTB or SDWSTB. Primary and Secondary Disk DMA Ready
IDE Interface Signals (Ultra DMA Reads from Disk): This is the DMA ready for reads
C
Signal Name Type Description from disk. When reading from disk, ICH4 deasserts
PDCS1#, SDCS1# O Primary and Secondary IDE Device Chip Selects for 100 Range: PRDMARDY# or SRDMARDY# to pause burst data transfers.
For ATA command register block. This output signal is connected PDIOW#/ O Primary and Secondary Disk I/O Write (PIO and Non-Ultra
to the corresponding signal on the primary or secondary IDE (PDSTOP) DMA): This is the command to the IDE device that it may latch
connector. data from the PDD or SDD lines. Data is latched by the IDE device
PDCS3#, SDCS3# O Primary and Secondary IDE Device Chip Select for 300 Range: on the deassertion edge of PDIOW# or SDIOW#. The IDE device is
SDIOW#/
For ATA control register block. This output signal is connected to selected either by the ATA register file chip selects (PDCS1# or
(SDSTOP)
the corresponding signal on the primary or secondary IDE SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the
connector. IDE DMA acknowledge (PDDAK# or SDDAK#).
PDA[2:0], O Primary and Secondary IDE Device Address: These output Primary and Secondary Disk Stop (Ultra DMA): ICH4 asserts this
SDA[2:0] signals are connected to the corresponding signals on the primary or signal to terminate a burst.
secondary IDE connectors. They are used to indicate which byte in
either the ATA command block or control block is being addressed.
86

IDE Interface Signals (Continued) LPC Interface Signals
PIORDY#/ I Primary and Secondary I/O Channel Ready (PIO): This signal LAD[3:0]/ I/O LPC Multiplexed Command, Address, Data: For the LAD[3:0]
(PDRSTB/PWDMA will keep the strobe active (PDIOR# or SDIOR# on reads, PDIOW# FWH[3:0] signals, internal pull-ups are provided.
RDY#) or SDIOW# on writes) longer than the minimum width. It adds wait LFRAME#/ O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an
states to PIO transfers. FWH[4] abort.
Primary and Secondary Disk Read Strobe (Ultra DMA Reads from LDRQ[1:0]# I LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used
SIORDY#/
Disk): When reading from disk, the ICH4 latches data on rising and to request DMA or bus master access. These signals are typically
(SDRSTB/SWDMA
falling edges of this signal from the disk.
t
RDY#) connected to an external Super I/O device. An internal pull-up
Primary and Secondary Disk DMA Ready (Ultra DMA Writes to resistor is provided on these signals.
t n
Disk): When writing to disk, this is de-asserted by the disk to pause
burst data transfers.
e e
r
c m
USB Interface Signals
e
Signal Name Type Description
Interrupt Signals
S u
USBP0P, I/O Universal Serial Bus Port 1:0 Differential: These differential
c
USBP0N, pairs are used to transmit data/address/command signals for ports 0
c Do
SERIRQ I/O Serial Interrupt Request: This pin implements the serial interrupt USBP1P, and 1. These ports can be routed to USB UHCI Controller #1 or the
a
protocol. USBP1N USB EHCI Controller.
I/OD PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals NOTE: No external resistors are required on these signals. The
iT ial
PIRQ[D:A]#
can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as ICH4 integrates 15 k . pull-downs and provides an output driver
described in the Interrupt Steering section. Each PIRQx# line has a impedance of 45 . which requires no external series resistor
M t
separate Route Control Register. USBP2P, I/O Universal Serial Bus Port 3:2 Differential: These differential
In APIC mode, these signals are connected to the internal I/O APIC USBP2N, pairs are used to transmit data/address/command signals for ports 2
n
in the following fashion: PIRQ[A]# is connected to IRQ16, USBP3P, and 3. These ports can be routed to USB UHCI Controller #2 or the
e
PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. USBP3N USB EHCI Controller.
id
This frees the legacy interrupts. NOTE: No external resistors are required on these signals. The
PIRQ[H:E]#/ I/OD PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals ICH4 integrates 15 k . pull-downs and provides an output driver
GPIO[5:2]
nf
can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in the Interrupt Steering section. Each PIRQx# line has a USBP4P, I/O
impedance of 45 . which requires no external series resistor.
Universal Serial Bus Port 5:4 Differential: These differential
o
separate Route Control Register. USBP4N, pairs are used to transmit data/address/command signals for ports 4
In APIC mode, these signals are connected to the internal I/O APIC and 5. These ports can be routed to USB UHCI Controller #3 or the
C
USBP5P,
in the following fashion: PIRQ[E]# is connected to IRQ20, USBP4N USB EHCI Controller
PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. NOTE: No external resistors are required on these signals. The
This frees the legacy interrupts. If not needed for interrupts, these ICH4 integrates 15 k . pull-downs and provides an output driver
signals can be used as GPIO. impedance of 45 . which requires no external series resistor
IRQ[14:15] I Interrupt Request 14:15: These interrupt inputs are connected to OC[5:0]# I/O Overcurrent Indicators: These signals set corresponding bits in
the IDE drives. IRQ14 is used by the drives connected to the the USB controllers to indicate that an overcurrent condition has
Primary controller and IRQ15 is used by the drives connected to the occurred.
Secondary controller. USBRBIAS O USB Resistor Bias: Analog connection point for an external
APICCLK I APIC Clock: This clock operates up to 33.33 MHz. resistor to ground. USBRBIAS should be connected to
APICD[1:0] I/OD APIC Data: These bi-directional open drain signals are used to USBRBIAS# as close to the resistor as possible.
send and receive data over the APIC bus. As inputs the data is valid USBRBIAS# I USB Resistor Bias Complement: Analog connection point for an
on the rising edge of APICCLK. As outputs, new data is driven external resistor to ground. USBRBIAS# should be connected to
from the rising edge of the APICCLK. USBRBIAS as close to the resistor as possible.
87

Power Management Interface Signals Power Management Interface Signals (Continued)
THRM# I Thermal Alarm: This is an active low signal generated by external LAN_RST# I LAN Reset: This signal must be asserted at least 10 ms after the
hardware to start the hardware clock throttling mode. The signal can resume well power (VccLAN3_3 and VccLAN1_5 is valid. When
also generate an SMI# or an SCI. deasserted, this signal is an indication that the resume well power is
THRMTRIP# I Thermal Trip: When low, THRMTRIP# indicates that a thermal stable.
trip from the processor occurred; the ICH4 will immediately SUS_STAT#/ O Suspend Status: This signal is asserted by the ICH4 to indicate that
transition to a S5 state. The ICH4 will not wait for the processor LPCPD# the system will be entering a low power state soon. This can be
stop grant cycle since the processor has overheated. monitored by devices with memory that need to switch from normal
SLP_S1# O
t nt
S1 Sleep Control: SLP_S1# provides Clock Synthesizer or Power
plane control. Optional use is to shut off power to non-critical
refresh to suspend refresh mode. It can also be used by other
peripherals as an indication that they should isolate their outputs
e e
systems when in the S1- M (Powered On Suspend), S3 (Suspend To that may be going to powered-off planes. This signal is called
r
RAM), S4 (Suspend to Disk) or S5 (Soft Off) states. LPCPD# on the LPC I/F.
c m
SLP_S3# O S3 Sleep Control: SLP_S3# is for power plane control. It shuts off C3_STAT# O C3_STAT#: This signal will typically be configured as C3_STAT#.
e
power to all non-critical systems when in S3 (Suspend To RAM), It is used for indicating to an AGP device that a C3 state transition
S u
S4 (Suspend to Disk), or S5 (Soft Off) states.
c
is beginning or ending. If C3_STAT# functionality is not required,
this signal may be used as a GPO.
c Do
SLP_S4# O S4 Sleep Control: SLP_S4# is for power plane control. It shuts
power to all non-critical systems when in the S4 (Suspend to Disk) NOTE: This signal will be asserted in S1-M on the ICH4-M.
a
or S5 (Soft Off) state. SUSCLK O Suspend Clock: Output of the RTC generator circuit to use by other
iT ial
SLP_S5# O S5 Sleep Control: SLP_S5# is for power plane control. The signal chips for refresh clock.
is used to shut power off to all non-critical systems when in the S5 AGPBUSY# I AGP Bus Busy: To support the C3 state. This signal is an
(Soft Off) states. indication that the AGP device is busy. When this signal is asserted,
PWROK I
M t
Power OK: When asserted, PWROK is an indication to the ICH4 the BM_STS bit will be set. If this functionality is not needed, this
signal may be configured as a GPI.
n
that core power and PCICLK have been stable for at least 1 ms.
O Stop PCI Clock: This signal is an output to the external clock
e
PWROK can be driven asynchronously. When PWROK is negated, STP_PCI#
the ICH4 asserts PCIRST#. generator for it to turn off the PCI clock. Used to support PCI
id
NOTE: PWROK must deassert for a minimum of 3 RTC clock CLKRUN# protocol. If this functionality is not needed, This signal
f
periods for the ICH4 to fully reset the power and properly generate can be configured as a GPO.
the PCIRST# output STP_CPU# O Stop CPU Clock: Output to the external clock generator for it to
PWRBTN# I
on
Power Button: The Power Button causes SMI# or SCI to indicate a
system request to go to a sleep state. If the system is already in a
turn off the processor clock. Used to support the C3 state. If this
functionality is not needed, this signal can be configured as a GPO.
C
sleep state, this signal causes a wake event. If PWRBTN# is pressed BATLOW# I Battery Low: This signal is an input from the battery to indicate
for more than 4 seconds, this causes an unconditional transition that there is insufficient power to boot the system. Assertion will
(power button override) to the S5 state with only the PWRBTN# prevent wake from S1-M–S5 state. Can also be enabled to cause an
available as a wake event. Override occurs even if the system is in SMI# when asserted.
the S1-M–S4 states. This signal has an internal pull-up resistor. CPUPERF# OD CPU Performance: CPUPERF# is used for Intel SpeedStep
RI# I Ring Indicate: This signal is an input from the modem interface. It technology support. The signal selects which power state to put the
can be enabled as a wake event, and this is preserved across power processor in.
failures. SSMUXSEL O SpeedStep Mux Select: SSMUXSEL is used for Intel SpeedStep
SYS_RESET# I System Reset: This pin forces an internal reset after being technology support. The signal selects the voltage level for the
debounced. The ICH4 will reset immediately if the SMBus is idle; processor.
otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle VGATE/ I VGATE/VRM Power Good: VGATE/VRMPWRGD is used for
before forcing a reset on the system. VRMPWRGD Intel SpeedStep technology support. This is an output from the
RSMRST# I Resume Well Reset: This signal is used for resetting the resume processor’s voltage regulator to indicate that the voltage is stable.
power plane logic. This signal may go inactive during an Intel SpeedStep transition.
88

Power Management Interface Signals (Continued) Processor Interface Signals (Continued)
DPRSLPVR O Deeper Sleep - Voltage Regulator: This signal is used to lower the IGNNE# O Ignore Numeric Error: This signal is connected to the ignore error
voltage of VRM during C4 and S1-M states. When the signal is pin on the processor. IGNNE# is only used if the ICH4 coprocessor
high, the voltage regulator outputs the lower “Deeper Sleep” error reporting function is enabled in the General Control Register
voltage. When the signal is low (default), the voltage regulator (Device 31:Function 0, Offset D0, bit 13). If FERR# is active,
outputs the higher “Normal” voltage. During PCIRST#, the output indicating a coprocessor error, a write to the Coprocessor Error
driver is disabled and an internal pull-down is enabled. This is Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains
needed for implementing a strap on the pin. When PCIRST# asserted until FERR# is negated. If FERR# is not asserted when the
t nt
deasserts, the output driver is enabled. To guarantee no glitches on
the DPRSLPVR pin, the pull-down is disabled after the output
Coprocessor Error Register is written, the IGNNE# signal is not
asserted.
e e
driver is fully enabled. Speed Strap: During the reset sequence, ICH4 drives IGNNE# high
r
NOTE: DPRSLPVR is sampled at the rising edge of PWROK as a if the corresponding bit is set in the FREQ_STRP register.
c m
functional strap. INIT# O Initialization: INIT# is asserted by the ICH4 for 16 PCI clocks to
e
reset the processor. ICH4 can be configured to support CPU BIST.
S u
In that case, INIT# will be active when PCIRST# is active.
c
O Non-Maskable Interrupt: NMI is used to force a non-Maskable
c Do
NMI
Processor Interface Signals interrupt to the processor. The ICH4 can generate an NMI when
a
Signal Name Type Description either SERR# or IOCHK# is asserted. The processor detects an NMI
iT ial
when it detects a rising edge on NMI.
A20M# O Mask A20: A20M# will go active based on either setting the NMI is reset by setting the corresponding NMI source
appropriate bit in the Port 92h register, or based on the A20GATE enable/disable bit in the NMI Status and Control Register.
M t
input being active. Speed Strap: During the reset sequence, ICH4 drives NMI high if
Speed Strap: During the reset sequence, ICH4 drives A20M# high the corresponding bit is set in the FREQ_STRP register.
n
if the corresponding bit is set in the FREQ_STRP register.
O System Management Interrupt: SMI# is an active low output
e
SMI#
CPUSLP# O CPU Sleep: This signal puts the processor into a state that saves synchronous to PCICLK. It is asserted by the ICH4 in response to
substantial power compared to Stop-Grant state. However, during
id
one of many enabled hardware or software events.
that time, no snoops occur. The ICH4 can optionally assert the
f
STPCLK# O Stop Clock Request: STPCLK# is an active low output
CPUSLP# signal when going to the S1-M state.
synchronous to PCICLK. It is asserted by the ICH4 in response to
n
FERR# I Numeric Coprocessor Error: This signal is tied to the coprocessor one of many hardware or software events. When the processor
o
error signal on the processor. FERR# is only used if the ICH4 samples STPCLK# asserted, it responds by stopping its internal
coprocessor error reporting function is enabled in the General
C
clock.
Control Register (Device 31:Function 0, Offset D0, bit 13). If
RCIN# I Keyboard Controller Reset CPU: The keyboard controller can
FERR# is asserted, the ICH4 generates an internal IRQ13 to its
generate INIT# to the processor. This saves the external OR gate
interrupt controller unit. It is also used to gate the IGNNE# signal to
with the ICH4’s other sources of INIT#. When the ICH4 detects the
ensure that IGNNE# is not asserted to the processor unless FERR#
assertion of this signal, INIT# is generated for 16 PCI clocks.
is active. FERR# requires an external weak pull-up to ensure a high
NOTE: The ICH4 ignores RCIN# assertion during transitions to the
level when the coprocessor error function is disabled.
S1-M, S3, S4 and S5 states.
NOTE: FERR# can be used in some states for notification by the
processor of pending interrupt events. This functionality is A20GATE I A20 Gate: A20GATE is from the keyboard controller. The signal
independent of the General Control Register bit setting. acts as an alternative method to force the A20M# signal active. It
saves the external OR gate needed with various other PCIsets.
INTR O CPU Interrupt: INTR is asserted by the ICH4 to signal the
processor that an interrupt request is pending and needs to be
serviced. It is an asynchronous output and normally driven low.
Speed Strap: During the reset sequence, ICH4 drives INTR high if
the corresponding bit is set in the FREQ_STRP register.
89

Processor Interface Signals (Continued) Real Time Clock Interface Signals
CPUPWRGD OD CPU Power Good: This signal should be connected to the RTCX1 Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal.
processor’s PWRGOOD input. To allow for Intel ® SpeedStep™ RTCX2 Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal.
technology support, this signal is kept high during an Intel
SpeedStep technology state transition to prevent loss of processor
context. This is an open-drain output signal (external pull-up
resistor required) that represents a logical AND of the ICH4’s Other Clock Signals
PWROK and VGATE / VRMPWRGD signals.
t
DPSLP# O Deeper Sleep: This signal is asserted by the ICH4 to the processor.
t
I Oscillator Clock: Used for 8254 timers. It runs at 14.31818 MHz.
n
CLK14
When the signal is low, the processor enters the Deeper Sleep state This clock is permitted to stop during S1-M (or lower) states.
e e
by gating off the processor Core clock inside the processor. When
r
CLK48 I 48 MHz Clock: This clock is used to run the USB controller. It runs
the signal is high (default), the processor is not in the Deeper Sleep
c m
at 48 MHz. This clock is permitted to stop during S1-M (or lower)
state. This signal behaves identically to the STP_CPU# signal, but states.
e
at the processor voltage level.
u
I 66 MHz Clock: This is used to run the hub interface. It runs at 66
S
CLK66
c
MHz. This clock is permitted to stop during S1-M (or lower) states.
SMBus Interface Signals

ac Do Miscellaneous Signals
iT ial
SMBDATA I/OD SMBus Data: External pull-up is required. O Speaker: The SPKR signal is the output of counter 2 and is
M t
SPKR
SMBCLK I/OD SMBus Clock: External pull-up is required. internally “ANDed” with Port 61h bit 1 to provide Speaker Data
Enable. This signal drives an external speaker driver device, which
n
SMBALERT#/ I SMBus Alert: This signal is used to wake the system or generate
in turn drives the system speaker. Upon PCIRST#, its output state is
e
GPIO[11] SMI#. If not used for SMBALERT#, it can be used as a GPI.
0.
id
NOTE: SPKR is sampled at the rising edge of PWROK as a
f
functional strap.
RTCRST# I RTC Reset: When asserted, this signal resets register bits in the
n
System Management Interface Signals RTC well and sets the RTC_PWR_STS bit (bit 2 in
o
Signal Name Type Description GEN_PMCON3 register).
C
INTRUDER# I Intruder Detect: Can be set to disable system if box detected open. NOTES:
This signal’s status is readable, so it can be used like a GPI if the 1. Clearing CMOS in an ICH4-based platform can be done by using
Intruder Detection is not needed. a jumper on RTCRST# or GPI, or using SAFEMODE strap.
SMLINK[1:0] I/OD System Management Link: SMBus link to optional external Implementations should not attempt to clear CMOS by using a
system management ASIC or LAN controller. External pull-ups are jumper to pull VccRTC low.
required. 2. Unless entering the XOR Chain Test Mode, the RTCRST# input
Note that SMLINK[0] corresponds to an SMBus Clock signal, and must always be high when all other RTC power planes are on.
SMLINK[1] corresponds to an SMBus Data signal.
90

AC’97 Link Signals Power and Ground Signals
Signal Name Type Description Signal Name Description
AC_RST# O AC ’97 Reset: This signal is a master hardware reset to external VCC3_3 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5
Codec(s). or G3 states.
AC_SYNC O AC ’97 Sync: This signal is a 48 kHz fixed rate sample sync to the VCC1_5 1.5 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3
Codec(s). states.
AC_BIT_CLK I AC97 Bit Clock: This signal is a 12.288 MHz serial data clock VCCHI 1.5 V supply for Hub Interface 1.5 logic.
generated by the external Codec(s). This signal has an integrated 1.8 V supply for Hub Interface 1.0 logic.
t
pull-down resistor. This power may be shut off in S3, S4, S5 or G3 states.
O AC97 Serial Data Out: Serial TDM data output to the Codec(s). Reference for 5 V tolerance on core well inputs. This power may be shut off in
t
AC_SDOUT V5REF
n
NOTE: AC_SDOUT is sampled at the rising edge of PWROK as a S3, S4, S5 or G3 states.
AC_SDIN[1:0] I
functional strap.
re e
AC97 Serial Data In 2:0: These signals are Serial TDM data inputs
HIREF Analog Input. Expected voltages are:
• 0.9 V for HI 1.0 (Normal Hub Interface) Series Termination
from the three Codecs.
ec m
NOTE: An integrated pull-down resistor on AC_BIT_CLK is enabled when either: The ACLINK
• 350 mV for HI 1.5 (Enhanced Hub Interface) Parallel Termination
This power is shut off in S3, S4, S5, and G3 states.
S cu
Shutoff bit in the AC’97 Global Control Register is set to 1, or Both Function 5 and Function 6 of VCCSUS3_3 3.3 V supply for resume well I/O buffers. This power is not expected to be shut
c Do
Device 31 are disabled. Otherwise, the integrated pull-down resistor is disabled. off unless the main battery is removed or completely drained and AC power is
not available.
a VCCSUS1_5 1.5 V supply for resume well logic. This power is not expected to be shut off
iT ial
General Purpose I/O Signals unless the main battery is removed or completely drained and AC power is not
Signal Name Type Description available.
M t
V5REF_SUS Reference for 5 V tolerance on resume well inputs. This power is not expected
GPIO[43:32] I/O Can be input or output. Main power well.
to be shut off unless the main battery is removed or completely drained and AC
GPIO[31:29] O Not implemented.
n
power is not available.
GPIO[28:27] I/O Can be input or output. Resume power well. Unmuxed.
e
VCCLAN3_3 3.3 V supply for LAN Connect interface buffers. This is a separate power plane
GPIO[26] I/O Not implemented. that may or may not be powered in S3–S5 states depending upon the presence or
id
GPIO[25] I/O Can be input or output. Resume power well. Unmuxed. absence of AC power and network connectivity. This plane must be on in S0 and
f
GPIO[24:18] I/O Not Implemented in Mobile (Assign to native Functionality). S1-M.
n
GPIO[17:16] O Fixed as Output only. Main power well. Can be used instead as VCCLAN1_5 1.5 V supply for LAN Controller logic. This is a separate power plane that may
PC/PCI GNT[A:B]#. GPIO[17] can also alternatively be used for or may not be powered in S3–S5 states depending upon the presence or absence
GPIO[15:14]
GPIO[13:12]
GPIO[11]
I
I
I
Not implemented.
o
PCI GNT[5]#. Integrated pull-up resistor.
C
Fixed as Input only. Resume power well. Unmuxed.
Fixed as Input only. Resume power well. Can be used instead as
VCCRTC
of AC power and network connectivity. This plane must be on in S0 and S1-M.
3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power
is not expected to be shut off unless the RTC battery is removed or completely
drained.
SMBALERT#. NOTE: Implementations should not attempt to clear CMOS by using a jumper
GPIO[10:9] I Not implemented. to pull VccRTC low. Clearing CMOS in an ICH4-based platform can be done
GPIO[8] I Fixed as Input only. Resume power well. Unmuxed. by using a jumper on RTCRST# or GPI, or using SAFEMODE strap.
GPIO[7] I Fixed as Input only. Main power well. Unmuxed. VCCPLL 1.5 V supply for core well logic. This signal is used for the USB PLL. This
GPIO[6] I Not Implemented in Mobile (Assign to Native Functionality) power may be shut off in S3, S4, S5 or G3 states.
GPIO[5:2] I Fixed as Input only. Main power well. Can be used instead as VBIAS RTC well bias voltage. The DC reference voltage applied to this pin sets a
PIRQ[E:H]#. current that is mirrored throughout the oscillator and buffer circuitry.
GPIO[1:0] I Fixed as Input only. Main power well. Can be used instead as V_CPU_IO Powered by the same supply as the processor I/O voltage. This supply is used to
PC/PCI REQ[A:B]#. GPIO[1] can also alternatively be used for PCI drive the processor interface outputs.
REQ[5]#. VSS Grounds.
NOTE: Main power well GPIO are 5V tolerant, except for GPIO[43:32]. Resume power well GPIO 91
are not 5V tolerant.
6. System Block Diagram

U713
INTEL
BANIAS/DOTHAN CRT
RGB
Host
J6 400MHZ LVDS
U727
PCMCIA
t nt LCD
e e
Card Reader U714
U710
r
CARD READER J711 AGP
Socket
c m
CB710 North Bridge
e
DDR 266 TV
ATI-M10
u
855GME
S
c Do c
a
Mini PCI U719
iT ial
Card Socket RTL8100CL 66MHZ Amplifier
TPA0212
M t MIC
n
PCI BUS
e
IEEE 1394 U726 Speaker
U715
id
AC 97 AUDIO U524 HP/OPT Jack
f
CODEC
Subwoofer
n
ICH4-M ALC655
HDD
o
Line In
C MDC RJ11
CD-ROM LPC BUS
Internal KB
USB2.0
U16
U15 Touch Pad
WINBOND
FWH
W83L950D FAN
BIOS 92
7. Maintenance Diagnostics
7.1 Introduction
Each time the computer is turned on, the system BIOS runs a series of internal checks on the hardware. This
t nt
power-on self test (post) allows the computer to detect problems as early as the power-on stage. Error messages of
re e
post can alert you to the problems of your computer.If an error is detected during these tests, you will see an error
ec m
message displayed on the screen. If the error occurs before the display is initialized, then the screen cannot display
S cu
the error message. Error codes or system beeps are used to identify a post error that occurs when the screen is not
available.
ac Do
iT ial
M t
The value for the diagnostic port is written at the beginning of the test. Therefore, if the test failed, the user can
n
determine where the problem occurred by reading the last value written to the port by the debug card plug at MINI
PCI slot.
e
fid
on
C
93
7.2 Diagnostic Tool for Mini PCI Slot :
The Mini PCI DOG killer card is a single-step debug tool which utilizes Mini PCI interface (Type III A) and is
able to hold a PCI bus cycle so that address, data and control bus states on PCI bus can be inspected. Especially,
the tool can help an engineer trace address/data bus for BIOS read cycles as soon as power on and debug open
t nt
or short circuit problems easily. Usually, this sort of problem will make a PC motherboard fail to boot.
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on
C
P/N:411906900001
Description: PWA-MPDOG;MINI PCI DOGKELLER CARD
Note: Order it from MIC/TSSC
94
7.3 Error Codes - 1

Following is a list of error codes in sequent display on the debug board.
POST (HEX) DESCRIPTION POST (HEX) DESCRIPTION

00h Boot started 17H Size Memory
t
01h Disable A20 through A20 18H Dispatch To RAM Test
02h Initialize CS
t
e e n
19H checksum the ROM
r
03h Test RAM 1AH Reset PIC's
04h Move BL into the RAM
ec m 1BH Initialize Video Adapter(s)

05h Execution in RAM
S cu 1CH Initialize Video (6845 Regs)
c Do
06h Check OVERRIDE option 1DH Initialize Color Adapter
07h
a
Shadow System BIOS 1EH Initialize Monochrome Adapter
08h
iT ial
Checksum System BIOS ROM 1FH Test 8237A Page Registers
M t
09h Proceed with Normal Boot 20H Test Keyboard
n
0Ah Proceed with Crisis Boot 21H Test Keyboard Controller
0Fh Fatal Error
e 22H Check If CMOS Ram Valid
id
F0h .... - No RAM 23H Test Battery Fail & CMOS X-SUM
F1h
nf
..._ - RAM test failed 24H Test the DMA controllers
99h
10H
11H Co
Resume SMRAM not Found
Some Type Of Long Reset
Turn off FASTA20 for POST
25H
26H
27H
Initialize 8237A Controller
Initialize Int Vectors
RAM Quick Sizing
12H Signal Power On Reset 28H Protected mode entered safely
13H Initialize the Chipset 29H RAM test completed
14H Search For ISA Bus VGA Adapter 2AH Protected mode exit successful
15H Reset Counter/Timer 1 2BH Setup Shadow
16H user register config through CMOS 2CH Going To Initialize Video
95
7.3 Error Codes - 2


2DH Search For Monochrome Adapter 42H Initialize the hard disk
t
2EH Search For Color Adapter 43H Initialize option ROMs
2FH Signon messages displayed
t
e e n
44H OEM's init of power management
r
30H special init of keyboard ctlr 45H Update NUMLOCK status
31H
ec m
Test If Keyboard Present 46H Test For Coprocessor Installed
32H
S
Test Keyboard Interrupt
cu 47H OEM functions before boot
c Do
33H Test Keyboard Command Byte 48H Dispatch To Op. Sys. Boot
34H
a
TEST, Blank and count all RAM 49H Jump Into Bootstrap Code
35H
iT ial
Protected mode entered safely (2). 50H ACPI INIT
M t
36H RAM test complete 51H PM INIT & GEYSERVILLE CPU INIT
n
37H Protected mode exit successful 52H USB HC INIT
38H
e
Update OUTPUT port F8H PXE BIOS decomp error
id
39H Setup Cache Controller F9H PCI BIOS decomp error
3AH
nf
Test If 18.2Hz Periodic Working FAH PNP BIOS decomp error
3BH
3CH
3DH Co
test for RTC ticking
initialize the hardware vectors
Search and Init the Mouse
FBH
FCH
FDH
LOGO BIOS decomp error
LOGO Image decomp error
Energy Image decomp error
3EH Update NUMLOCK status FEH ROMDEBUG Image decomp error
3FH special init of COMM and LPT ports 88H PM code decomp error
40H Configure the COMM and LPT ports CAH CPU SMM remap code
41H Initialize the floppies CBH CPU SMM BASE remap Done
96
7.3 Error Codes - 3


D0H check rom signature, 1.x video E5H disable add-in rom card decode
t
D1H enable RAM area in regs E6H PCI return(config and no video)
D2H copy ROM to RAM in regs
t
e e n
E7H look for PCI bridge device
r
D3H update segment range attr E8H search IDE controllers on the PCI bus
D4H
ec m
configure memory registers E9H start of cardbus config
D5H
S
configure I/O registers
cu A1H Enable/Verify R/W Status Runtime Data
c Do
D6H configure IRQ assignments A2H Get/Verrify R/W Stattus NVRAM data area
D7H
a
turn on PCI device A3H Resolve System Nodes with the CMOS settings
D8H
iT ial
2.x video r/w segment A4H Init. var. in the PNP BIOS Runtime Data area
M t
D9H OEM defined, rom init A5H Hook INT 15
n
DAH disable add-in rom card decode A6H copy/setup $PnP Install Check in F0000 seg.
DBH
e
PCI return(config and no video) A7H Allow the OEM any Last Minute Hooks
id
DCH enable RAM area in regs A8H Write protect RTData Area & NVRAM Copy Buffer
DDH
nf
copy ROM to RAM in regs A9H return from pnp_init proc
DEH
DFH
E0H
o
update segment range attr
C
configure memory registers
configure I/O registers
E1H configure IRQ assignments
E2H turn on PCI device
E3H 2.x video r/w segment
E4H OEM defined, rom init
97
8. Trouble Shooting
8.1 No Power 8.9 CD-ROM Driver Test Error
8.2 Battery Can not Be Charged 8.10 Audio Failure

t n t
re 8.11eLAN Test Error
8.3 No Display
e c m
8.4 External Monitor No Display c
S cu8.12 Modem Test Error
a Do
iT a l
8.5 Memory Test Error M
ti 8.13 MINI-PCI Test Error
e n
fid
8.6 Keyboard/Touch pad Test Error 8.14 Card Bus&Reader Test Error
o n
CError
8.7 USB Port Test 8.15 IEEE 1394 Failure
8.8 Hard Disk Drive Test Error
98
8.1 No Power
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
P32 P32 P25 P25
PF1 PD702 U11 Q13
Power In PWR_VDDIN
PL1 PL2 VDD5 VDD5S
PJ 701 PR701
F3,U13 P25 Q48 P25 Q51,L71 P25 U6 P25
t
VDD3_AVREF VDD3 VDD3S VDD1.5
P32
t
PQ701 PD704
e e n
r
Q43
P32
ec m P27 P24 P25 P18
S u
PD703 JS704 PL703 JS711,JS713,JS715 U707,Q701 L746
c
ADINP DVMAIN +3VS-P +3VS +3V 1394_AVCC
c Do
PU2 PU702 L706,L707
PF703 PL708
PL701 PR711 P25
a
L743
PU7 PQ707 +PHYVDD
iT ial
PL710 PD709
PD713
M t
P27 P24 P15
PQ704 PL702 JS718,JS719,JS721 U701 L702
P33 +5VS_P +5VS +VCC_USB_0
n
PD704
PR707
e
Charge PU701 L701
P32 +VCC_USB_1
id
Discharge U705,L708
f
Battery +VCC_USB_2
on U704,L70 3
P25
U728
P17
C
+5V +CARD_VCC
L704,Q10
NOTE:. U18
P20
VA
P27 Page on M/B board circuit diagram.
P31
PU3,PU9,PU10,PU11
+VCC_CORE
PU12,PU13,PL711,
PD718,PR740
To Next Page
99
8.1 No Power
Continue To Previous Page
P27
t
DVMAIN
t
e e n
r
JS706,PL712 PU705,PL713,PR739 P29 JS71,JS717 P24
c m
+1.8V_P +1.8V
e
PU14
S c
PU707,PL714,PR741
u P29
JS72,JS722
P5
c Do
+1.35V_P +1.35V
a
JS10,PL3
iT ial
PU6,PL707,PR732
P28
JS728,JS729,JS730
P24
M t
+1.05V_P +VCCP
PU703
n
P28 P24
e
PU4,PL706,PR719 JS72,JS725
+1.5V_P +1.5V
fid
n
P26 P24
o
JS703,PL716 PU709,PL717,PR744 JS1,JS12
+1.25V_DDR_P +1.25V_DDR
C
PU15
P26 P24 P16

PU708,PL715,PR742 JS708,JS709,JS710 L732
+2.5VS_DDR_P +2.5VS_DDR DVDD
100
8.1 No Power
No power
AC Check following parts and signals:
POWER Parts: Signals:
t nt PF1 ALWAYS
Is the
Notebook connected No
re e
Connect
PL1 DVMAIN
c m
PL2 ADEN#
AC adaptor
e
to power (Either AC adaptor
S u
or battery PD702 BATT_DEAD
or battery)?
c Do c PQ701
Yes
a
iT ial Where
Please try another known good battery
M t From Power Source
BATTERY
n
or AC adapter.
Problem(First use
e AC to power it)
fid
n
Please replace Check following parts and signals:
Power
OK?
Yes
Co the faulty
AC adaptor or
Battery.
Parts:
J703
Signals:
BATT
NO PF702
PQ6
PQ704
Board-level PL704
Troubleshooting
PL705
101
8.1 No Power(1)
PL1 120Z/100M
PD702
t
BAV70LT1
t
PJ701
n
PWR_VDDIN
PF1 7A/24VDC PL2 120Z/100M PR701 .01
PD701
re e PD704
c m
RLZ24D BAV70LT1
e
To chapter 8.2
S u
ADINP
c Do c
PQ701
AO4407 PD703
SBM1040
a
8 1 DVMAIN
3 7 3
2 6 2
iT ial
PU1 1 S 5
4 3 D
RS+ P32 VCC PR702 G
5 2 470K
M t
RS- GND1 PR720 100K
76 H8_I_LIMIT R428 0 I_LIMIT PR1 10 6 1
OUT GND0 PR703
n
100K
e
P22
1
2
3
S
id
PQ702 PR71 PQ704
G
23 LEARNING 2N7002 226K AO4407
f
D
8
5
6
7
n
U16 PR705 PR45
o
1M
33K BATT
C
WINBOND
KBC
D21
RLS4148 PQ6
14 ADEN#
2N7002
PQ24
DTC144WK
102
8.1 No Power(2)
PD704
BAV70LT1
t
PWR_VDDIN
t n
PQ704
PR720
AO4407
e e
4 100K
PF702 PL705 8 3
r
VDD3S 7A/24VDC 120Z/100M 7 2 DVMAIN
c m
BATT 6 1
5
e
PL704
S u
120Z/100M
c Do c
PR716
PR20 499K
a
4.99K PC722
0.01U RP45 PR45
P32 J703 PR714 22*4 33K
iT ial
100K
BAT_V 8 1 78
7
BATTCONNECTOR
M t
P22
BAT_T 7 2 77
5
n
D21
4 PQ6
RLS4148
e
14 ADEN# 2N7002
3
U16
id
2
f
WINBOND
1
KBC
n
PR23 0 BAT_C 6 3 2
Co
PR24 0 BAT_D
PD2
5 4 3
BAV99
VDD3
PD3
BAV99
103
8.2 Battery Can not Be Charged

There are problems in charging the battery.
Battery can not Charge
Board-level
t nt Troubleshooting
re e
Is the
No
ec m
u
Connect
S
notebook connected
to power (AC adaptor)?
c Do c
AC adaptor.
a Check following parts and signals:
iT ial
M t
Yes Parts Signal
Replace
n
Motherboard
e
PF703 PR70 ADINP
PL708 PQ11
id
1. Make sure that the battery is good. CHANGING
PQ707 PC33
f
2. Make sure that the battery is installed properly. BATT
PL710 PR63
n
PD713 PU5 BAT_V
o PD714 PR74 BAT_T
C
PD709 PR75 BAT_C
PQ13 PR76 BAT_D
PQ14 PQ12
BATT_DEAD
PU7
I_CTRL
PQ15
Yes Please replace the PD5
Battery charge PR65
faulty Battery.
OK?
No
104
8.2 Battery Can not Be Charged

There are problems in charging the battery.
PQ707
AO4407
PF703 PL708 8 PL710 PL709 PD713
3 7 33UH 3.0UH EC31QS04 Reference chapter 8.1(1)
From chapter 8.1(1) TR/3216FF-3A BEAD_120Z/100M 2 6
1 5 BATT
ADINP S
D
G
t nt PR87
4.7K
PR88
4.7K
PD714
EC31QS04
PD709
BZV55C15V
PC39
1000P
PR75
20K
e e
PR89
PR86 0 100K PR74
r
PQ15 13.7K
MMBT2222A
c m
PQ13
e
DTA144WK PR76
u
249K
S
PD5
c
BAS32L
26 CHARGING
PQ14
2N7002
ac Do From U16 PQ12

2N7002
iT ial
CHARGING
PC48 0.01U
M t
11 8
C2 C1
P33
P22 12 16 21N+
n
VCC 21IN+
PR78 13
e
0
10 R483 0 I_CTRL PR79 124K 2 PU7
id
TL594C
U16
WINBOND
15
nf BATT_DEAD#
o
DVMAIN VDD5
KBC
78
C
Reference chapter 8.1(2)
BAT_V PR69 PR65 PR70

100K 590K 3.3K
77 8
BAT_T
5 1.25V
2 +
BAT_C Q39 =8.56V BATT_DEAD 7
DTC144TKA 6
3 PU5 -
BAT_D PQ11
LMV393M 4 SCK431LCSK-.5
PC36 PR63 PC33
0.01U 80.6K 0.1U
105
8.3 No Display
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.
No Display
Monitor
or LCD module
No
t
Replace monitor
nt
e e
Board-level
or LCD.
OK?
r
c m
Troubleshooting
e
Yes
S cu
c Do
Make sure that CPU module,
a
DIMM memory are installed
iT ial
Properly.
Replace
M t
Motherboard
Yes Using debug card,depending
Display
OK?
en
Correct it. on the error codes to make
sure which parts maybe faulty
No
fid
1.Try another known good CPU
on
C
module, DIMM module and BIOS.
2.Remove all of I/O device (FDD,
HDD, CD-ROM…….) from
motherboard except LCD or monitor. Using circuit diagram ,check
the faulty parts
1. Replace faulty part.
Yes 2. Connect the I/O device to the
Display
OK? M/B one at a time to find out
which part is causing the problem.
No
106
8.3 No Display(1)
****** System Clock Check ******
R874
+3V 44,45 R875 33*2
R860 4.7K FS0 54 HCLK_CPU HCLK_CPU# P2 P3
CPU
FS1 R863 4.7K 55 U713
t
FS2 R894 4.7K 40
t n
35,38 R865 R872 48M_DREFCLK HCLK_MCH
48,49 R873 R878 33*4 66M_DEFSSCLK HCLK_MCH#
e e
P4 P5
NB
r
+3V U714
R863 8.2K 43
c m
L722 120Z/100M CLKANA 1,26,37
e
11 R816 33 PCICLK_MINIPCI
u
P19 MINI
S
L726 120Z/100M CLK66 19,32 P11 33 R1137 0
39 R895 MINIPCI_SIO48M
c
J713 -PCI
c Do
L43 120Z/100M CLKCPU 46,50
a
L718 120Z/100M CLKPCI 8,14 R877 33 USBCLK_ICH
iT ial
U712 7 R824 33 PCICLK_ICH P13 P14
ICH4_M
Clock R858 33 14M_ICH U715
M t
2
X703 Generator
14.318MHZ
n
3 P20
56 R859 33 R472 0 14M_CODEC AUDIO
ICS950810
e
C804 C794 U726 CODEC
+3V 27P 27P
id
+3V
12 R826 33 PCICLK_CARD P17 CARDBUS
f
PR731 R831 U727 READER
n
2K 10K
PR56 R821
o
0 0 13 R827 33 PCICLK_LAN P16
28
CORE_CLKEN# VTT_PWRGD# LAN
U719
C
+3VS_P
SMBCLK
29,30 SMBDATA P6 DDR
PR715 J711 SODIMM
100K
PR59 P28
PQ8
1M 16 R828 33
2N7002 PR57 0 VCCP_PWRGD PR717 0 27 PCICLK_1394 P18 IEEE
PU703
LTC3728L U724 1394
10 R825 33 PCICLK_FWH P23 BIOS
U15 SYS
FS2 FS1 FS0 CPU 17 R817 33 PCICK_KBC P22 WINBOND

001 x 0 1 100.00 U16 KBC
0:00 UNIT:MHZ
1:3.3V
107
8.3 No Display(2)
****** System Reset Check ******
U10 P25
MAX809
SW2 R7 +3VS +3V
1K 3
VCC RESET#
PWRBTN# 1 18 H8_PWRON P26 P27 P31 2 PWROK HCPURST# P2 P3
Convert
P22
U713
GND
Power +VCCP HPWRGD
Module BANIAS
t
1
TC010-PSS11CET U16 PWROK
t
LTC3728L R301
n
330 P4 P5
WINBOND
e e
7 ICH_PWRBTN Q31 HPWRGD
U21 KBC Convert to P13 P14
r
RSMRST#
R531 IMP811 P25 +3V
c m
VDD3 10K
3 MN U714
e
2 25 Q42
H8_RESET# 8 H8_RSMRST U9D
RESET
u
4 FDV301N
S
VCC H8_SUSB ICH_VGATE
U715
c
VRMPWRGD
c Do
W83L950D NORTH
a
+5V
BRIDGE
CONNECTOR CONNECTOR
iT ial
ICH_PWRBTN#
P15
ICH4_M 855GM
HDD
44 RSTDRV1# R492 10K

/GME
J714
Q49 SUSB#
M t
R476 Convert to +3V
Q41 10K
n
DTC144TKA
R909 U9A
e
Q37
0 1 PCIRST#
DTC144TKA JL3
PCIRST#0 3
P15
CDROM
id
2
f
J708
5 RSTDRV2# 74AHC08_V
JL4 MCH_PCIRST#
P18
n
92 1394_PCIRST# JL1
+3V
U724
o
1394
C
VT6307L U9B P22
P17 4
JL5 64
6 KBC_PCIRST# U16
U727 CARD_PCIRST# JL7 5 WINBOND
CARDBUS 74AHC08_V KBC
P19 J713
READER
+3V
CONNECTOR
26 MINIPCI_PCIRST# JL8
MINIPCI
P16
JL6 LAN_PCIRST# 27 U719

U9C
P23
JL9
7 LAN
2 FWH_PCIRST# 9 Controller
U15 8
BIOS RTL8100CL
P11 74AHC08_V
SST49LFOO4A
U2 13 TV_PCIRST# JL10
TV_CARD
CH7011A
108
8.3 No Display(3)
****** VGA Controller Checking ******
AGP_ VREF
R120 1.02K R16 1M F1 2A

AGP_VDDQ +3V
C146 C149 R110
t
10U 0.01U 1.02K
t n
Q9
e e
SI4835DY
1
2
3
S
R140 47K
c m
+3V R19 10K G
R104 10K
e
D
S u
Q11
8
5
6
7
C14
c
R752 0 ENAVDD R20 0 2N7002 0.22U
c Do
+3V L15 120Z/100M 1,2,3
a
R11~R14
P7
iT ial
10K*4
6,7,10,14
PANEL_ID[0..3] P12
M t
TXCLK-_ATI R160 0 TXCLK- 15
n
U710 TXCLK+_ATI R161 0 TXCLK+ 13
e
J2
TXOUT0-_ATI R153 0 TXOUT0- 28
id
TXOUT0+_ATI R154 0 TXOUT0+ 26
f
ATI-M10
LCD CONNECTOR
on
C
66M_AGP P11
R819 33 23
U712
CLK-GEN
109
8.3 No Display(4)
****** Back Light & Cover Switch Checking ******
+3V
To U715 in this page
R372
P7
10K
t
D2 BAT54 R386 0
P4
+3V U710
t n
U714 PWROK D15 BAT54 ATI-M10
e e
855GM
r
R380 DVMAIN
L17 120Z/100M 1,2
c m
10K
e
VDD3S
L18 120Z/100M 3
u
P12
S c
27 H8_ENABKL R383 0 D16 BAT54 ENABKL_VGA R323 0 ENABKL_VGA_C L10 120Z/100M 4
c Do
J1
a
P22
11 BLADJ R5 0 L9 120Z/100M 6
iT ial
Inverter
35 BATT_R# 8 1 8
36 BATT_G# 7 2 9
M t
79 AC_POWER# 6 3 10
BATT_POWER# 5 4 11
n
U16 R468 0
e
id
+3VS +3VS +3VS
f
U703D U703C U703B Q720 Q719
74AHC14_V 74AHC14_V 74AHC14_V DTC114TKA DTC114TKA
n
SUSB#
WINBOND P13
o
KBC
C947
C
4.7U U715
R1152 1M R1140 180K
13 BATT_LED#
ICH4-M
PWROK
+3VS
R373
470K
SW1
16 H8_LIDSW# R1152 1M R3 1K
C385
0.1U
30V/0.1A
110
8.3 No Display(5)
CPU Core does not exist .
DD_CPU
PF2 PL5
7A/24VDC 120Z/100M
S1+
DVMAIN
PL4
120Z/100M
PU9 PU10 S1-
8
5
6
7
5
6
7
8
t
D FDS6694 D FDS6694
t n
24 G G
e e
+5VS_P
PR5 10 29 S S
1
2
3
1
2
3
c m
PL711
PR740
PR4 10K 31
e
0.68UH 0.001 +VCC_CORE
23
S u
7
5
6
7
5
6
7
8
5
6
8
c
P13 P31 D PU12 D PU13 D PU11
PR32 0 4
c Do
STOP_CPU# FDS6694 FDS6694 FDS6694
U715 21 G G G
a
ICH4_M PD718
S S S EC31QS04-TE12L
iT ial
1
2
3
1
2
3
1
2
3
VID0 PR52 0 13 PU3
P3
M t
VID1 PR44 0 14 22 PC12 0.1U PR104 0
LTC3734 VOS-
VID2 PR40 0 15
U713 +5VS_P
PC13 10U
n
VID3 PR34 0 17
CPU
PR33 0 18
e
VID4
BANIAS
VID5 PR31 0 19 PQ9
PR729 +VCC_PWRGD P28
id
MMBT3904L PR59 1M PR57 0 TO
+3VS 249K
f
PC18 PR30 +3V PU703
30 From Left +3V
n
1000P 100K LTC3728L
PR28 576K 2 12
o
VOS- PR731
PR29 R831 2K
3 G
C
10K PQ8
13.3K P11 2N7002
R821 PR56
PR38 28 D S
10 U712
7 0 0 PD4
S1-
CLK- PR58 BAT54C VDD5
PR37 PC21 4.12K 2
10 1000P GEN 3
6 PR60
S1+ ICS950810 43.2K 1
DVMAIN PQ10 PR49
PC11 MMBT3904L 100K
PQ5
220P +3VS
2N7002 PR50
+2.5VS_DDR R251
PR19 13.3K PC15 100P 28 1M
220K
Q19
1 P26 2N7002 PQ7 PC28
PR61 0 2N7002 3300P
PR15 56.2k 8 PU15 PWRON_SUSB#
PR16 1.3M 9
LTC3728L
PR43 499K 11 10 RUN/SS
PR17 12.7K To Pin12
111
8.4 External Monitor No Display

There is no display or picture abnormal on CRT monitor, but LCD can normally display.
External Monitor No Display
t nt
re e
c m
Board-level Check if J702 Yes
1. Confirm monitor is good and check
the cable are connected properly.
Se u
Troubleshooting are cold solder? Re-soldering.
2. Try another known good monitor.
c Do c
a
iT ial
No
M t
en Check following parts and signals:
id
Display Yes
f
Replace faulty monitor.
OK?
n
Parts: Signals:
o
Replace
C
Motherboard U715 R139 CRT_IN#
R6 Q5 DDCK
R10 Q6 DDDA
R785 Q7 HSYNC
No R138 Q8 VCYNC
R136
L12 RED
R137
R783 L13 GREEN
R135 L11 BLUE
L7
112
8.4 External Monitor No Display

There is no display or picture abnormal on CRT monitor, but LCD can normally display.
R703 0
+5V_H +5V_H
R6 4.7K
R1 0
R10 4.7K
t
Q6 L12
2N7002 120Z/100M
t
R785 0
n
ATI_CRT_DDCK CHAGND GND
re e +3V
c m
Q5
2N7002
e
ATI_CRT_DDDA R138 0
u
R804
S
8.2K
c
15
L13
c Do
P13 BEAD_600Z/100M
P7 +5V_H CRT_IN# R9 1K 5
a
U715 P12
ICH L11
iT ial
Q7
120Z/100M
ATI_CRT_VSYNC R136 0 2N7002 14
M t
U710
Q8 L7
J702
n
2N7002 120Z/100M
ATI_CRT_HSYNC R137 0 13
ATI_M10
e
fid
CONNECTOR
n
ATI_CRT_RED R783 0 L58 220Z/100M 1
CRT
2
3
C
ATI_CRT_GREEN R135 0 L59 220Z/100M L74 120Z/100M 12
ATI_CRT_BLUE R139 0 L60 220Z/100M
6,7,8,16,17
CHAGND
113
8.5 Memory Test Error

Either on board or extend SDRAM is failure or system hangs up.
Memory Test Error
t nt
1.If your system installed with expansion
re e
c m
SO-DIMM module then check them for
Board-level
e
proper installation. Check following parts and signals
u
Troubleshooting
2.Make sure that your SO-DIMM sockets
are OK. S
c Do c
a
3.Then try another known good SO-DIMM Parts: Signals:
iT ial
modules.
U714 MD[0..63]
M t
J711 SMBCLK
J712 SMBDATA
Test
Yes
enReplace the faulty
U712
R979
DQS[0..7]
DM[0..7]
id
OK? SDRAM module. R1040 MCB[0..7]
nf Replace
Motherboard
R1030
R1031
MA0
MA3
o
No
R1011 MA[6..12]
If your system host bus clock

running at 100MHZ then make
C No Replace the faulty
R1016
R948
R949
WE#
CAS#
RAS#
R950 BA[0,1]
sure that SO-DIMM module SDRAM module.
R955 NB_DM8
meet require of DDR 333.
R340 NB_DQS8
C337 CLK_DDR[0..5]
C346 CLK_DDR[0..5]#
Yes
114
8.5 Memory Test Error

Either on board or extend SDRAM is failure or system hangs up.
+3V
197
+2.5VS_DDR
+1.25V_DDR
R340 C337 C346

RP29~RP43
t
75 0.01U 0.1U
56*8
NB_MD[0..63]
t
e e
R948,R949…
n 10 MD[0..63]
r
P6
c m
NB_DQS[0..7] R1011,R1016.. 10 DQS[0..7]
e
NB_DM[0..7] R950,R955.. 10 DM[0..7]
P4 P5 NB_CB[0..7]
S cu
R977,R978.. 10 MCB[0..7]
c Do
NB_MA0 NB_MA3 R972~R975 MA0 MA3
J711
a
NB_MA[6..12] R1032~R1036 10 MA[6..12]
NB_WE# NB_CAS# R969~R971 WE# CAS#
iT ial
NB_RAS# NB_BA[0,1] R1030 R1031 10 RAS# BA[0,1] &
U714
SMA [1,2] SMAB[1,2]
SMA[4,5] SMAB [4,5] J712
NB CKE [0~3]
M t
n
CS# [0,1]
DDR-SODIMM
855GM
id
NB_DM8 R979 10 NB_DM8
/GME
f
NB_DQS8 R1040 10 NB_DQS8
n
NB_CLK_DDR[0..5] R335~R338 R319 R359 NB_CLK_DDR[0..5]
NB_CLK_DDR[0..5]# R1103~R1106 R320 R360 10*12 NB_CLK_DDR[0..5]#
P11 29
Co SMBDATA 193
U712 30 SMBCLK 195

CLOCK
VDD3S +3V
GENERATOR
R315 R318 R316 R317

P13 2.2K 2.2K Q21 10K 10K
2N7002
SMB_DATA
U715
Q22
2N7002 0.6MM/200P
ICH4-M SMB_CLK
/H5.2
115
8.6 Keyboard (K/B) /Touch-Pad (T/P) Test Error

Error message of keyboard or touch-pad failure is shown or any key does not work.
Keyboard or Touch-Pad
Test Error
t nt Check
e e
Yes
U16, J4,J5
r
Re-soldering
c m
for cold solder?
e
Is K/B or
u
No
T/P cable connected to
notebook S c
Correct it.
c Do
Board-level
Troubleshooting
a
properly? No
iT ial
M t
Yes
Check following parts and signals:
en
id
Try another known good Keyboard Parts Signals
or Touch-pad.
nf U16 VDD3
o
Replace U715 VDD_AVREF
C Motherboard F701 KBC X+

L716 KBC X-
Yes Replace the faulty L36
Test H8/T_CLK
Keyboard or L37
Ok? R132
H8/T_DATA
Touch-Pad KI[0:7]
R151
J4 KO[0:15]
J5 PWRBTN#
KBD_US/JP#
No
116
8.6 Keyboard (K/B) /Touch-Pad (T/P) Test Error

Error message of keyboard or touch-pad failure is shown or any key does not work.
VDD3_AVREF F701 L716

R414 0 72
0.5A/POLYSW 120Z/100M
+5V
6
VDD3
t nt 71 9 T_DATA L36 120Z/100M 5

P23
e e
C445 C448 C449 6 L37 120Z/100M 4
r
T_CLK
0.1U 0.1U 10U
c m
30 SW4
e
SW_LEFT R132 0 3
J4
u
P22
P11 S
c Do c
SW_RIGHT R151 0 2
a
17 PCICK_KBC R817 33 PCICLK_KBC 70 SW5 1
U712 U16
iT ial
CLKGEN
+3V
GND
M t
VDD3
R392 WINBOND
n
8.2K KBC RP44
4.7K*8
e
SERIRQ 69
55~62 KI 0~7 17~24
id
65~68
f
LAD[0..3]
P13 39~54 KO 0~15 1~16
n
U9
o
KBC_PCIRST# 64
P22
29 KBC_X-
C
U715 LFRAME# 63 R404
1M
28 KBC_X+
H8_SUSB 22
J5
1 2 +3V
ICH4_M
SUSB# Q49 X1
DTC144TKA C447 8MHz C450
22P 22P
R165
10K
KBD_US/JP# 25
117
8.7 USB Port Test Error

An error occurs when a USB I/O device is installed.
USB Test Error
t nt
e e
Board-level
Check if the USB device is installed
properly. (Including charge board.) r
c m
Troubleshooting
Se u
c Do c
a
iT ial
Test Yes
Correct it
OK?
M t
Replace Check following parts and signals:
Motherboard
n
No
e Parts: Signals:
id
U715 L22
f
+5VS USBOC0#
Replace another known good USB U705 L708
n
device. USBP0+ +VCC_USB_0
o
U701 R701
USBP0- +VCC_USB_1
C
U712 C701
J701 R706 USBP1+ +VCC_USB_2
J706 C713 USBP1-
L701 C703
Yes Replace USBP2+
Re-test L702 C709
OK? the faulty part L2 USBP2-
L5
No
118
8.7 USB Port Test Error

An error occurs when a USB I/O device is installed.
+5VS
U701 P15 L702
R877 P11 1 120Z/100M
3 +VCC_USB_0 1
33 VIN0 VOUT0
USBCLK_ICH 39
U712
4 5 P15
GND
VIN1 VOUT1
CLK-GEN R701 + C701 L701
33K 150U 120Z/100M
t
C703 2 +VCC_USB_1 A1
1U J701
USB_OC0#
t
e e n
r
c m
L2
USB Port Connector

90Z/100M 3
e
USBP0+
u
P14 1 2
USBP0-
S
c Do c
4
L5
3
2
a
USBP1+ 90Z/100M A3
1 2
U715 USBP1-
iT ial 4 3
A2
M t 4
n
A4
e
ICH4_M USB/4PX2/DIP
id
+5VS
U705 P15 L708
f
120Z/100M
3 1 +VCC_USB_2 1
VIN0 VOUT0
n
4 VOUT1 5
GND
VIN1 P15
o
+
R706 C713
C709
C
2
1U 33K 150U
J706
USB_OC1#
USB Port Connector

L22
USBP2+ 90Z/100M 3
1 2
4 3
USBP2- 2
GND1
GND2
USB/4PX1
119
8050 N/B Maintenance
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
Hard Driver Test

Error
t nt
re e
1.Check the BIOS setup
ec m Board-level
S u
Troubleshooting
c
2.Replace another good hard driver or try again
ac Do
iT ial
M t
Yes
Re-boot Parts: Signals:
Replace the faulty parts.
n
OK?
e U715 PCIRST#0 PDDREQ
id
No J714 PIORDY IRQ14
f
Q37 PDD[0..15] +5V
n Replace Q41 PDA[0..2] +5V_HDD
o
Check the system driver for proper L733 PDIOR#
C
Motherboard
installation. R476 PDIOW#
R492
PDDACK#
R1081
PDCS1#
R1074
PDCS3#
Re - Test Yes
End
OK?
No
1

Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk. +3V
+5V_HDD
t
L733
R1081 R1074 +5V 120Z/100M
3
t n
4.7K 8.2K
re e 27~42
c m
PD_D[0..15]
P15
e
22
u
PDIOW#
S
P11
c
PDIOR# 20
ac Do
PIORDY 18 J714
iT ial
PDDACK# 16
U715
IRQ14 14
M t
HDD CONNECT
PDA[0.. 2] 9,10,12
ICH4_M
en
PDCS1# 8
id
PDCS3# 7
f
+5V
on R492 10K 44
C
PCIRST#0 RSTDRV1#
R476
10K
Q41
DTC144TKA
Q37
DTC144TKA
121
8.9 CD-ROM Test Error

CD-ROM driver can’t run normally,maybe an error message is shown when reading data from CD-ROM.
CD-ROM Driver
Test Error
t nt
Check the CD-ROM driver for proper
re e Board-level
installation.
ec m Troubleshooting
S cu Check following parts and signals:
ac Do
iT ial
Parts: Signals:
Test Yes
Correct it
M t
OK? U715 PCIRST#0 CDROM_COMM
J708 RSTDRV2#
No
en Q37
Q41
SIORDY
SDD[0..15]
id
R492 SDA[0..2]
Try another known good compact disk.

nf Replace R476
R909
SDIOR#
SDIOW#
o
Motherboard
R833 SDDACK#
C R834
L723
SDCS1#
SDCS3#
SDDREQ
IRQ15
Re - Test Yes Replace +5V
OK? the faulty parts. +5V_CDROM
CDROM_LEFT
CDROM_RIGHT
No
122
8.9 CD-ROM Test Error

CD-ROM driver can’t run normally,maybe an error message is shown when reading data from CD-ROM.
+3V
+5V_CDROM
L723
+5V 120Z/100M
38~42
t
R833 R834
4.7K 8.2K
SD_D[0..15]
t
e e n 6~21
r
P11
c m
SDIOW# 25
e u
P15
S
SDIOR# 24
c Do c
SIORDY 27
U715
a
SDDACK# 28
iT ial
IRQ15 29
J708
ICH4_M
M t
SDA[0.. 2] 31,33,34
n
SDCS1# 35
CDROM CONNECT
SDCS3# 36
id
+5V
nf R492 10K R909 5
o
PCIRST#0 0 RSTDRV2#
C R476
10K
Q41
DTC144TKA
18 C507 1U R538 6.8K CDROM_LEFT 1
P20
Q37 20 C513 1U R547 6.8K CDROM_RIGHT 2
DTC144TKA
U726
19 C515 0.22 R550 0 CDROM_COMM 3
AUDIO
CODEC R549 R546 R537
6.8K 6.8K 6.8K
123
8.10 Audio Failure

There is trouble with the sound from speaker or completely no sound
Audio Failure
t nt
1. Check if speaker cables are connected
re e
properly.
ec m Board-level
u
2. Make sure all the drivers are installed
properly.
S
c Do c
Troubleshooting
a
iT ial
Parts: Signals:
Test Yes
M t U18 D715 ROUT+ AMP_LEFT
n
Correct it. U17 Q711 ROUT- AMP_RIGHT
OK?
e
U524 Q713 SBSPKR SUB_LEFT
id
U726 Q23 CARDSPK# SUB_RIGHT
No
f
U715 D17 PC_BEEP AMP_SHUTDOWN
U712 D19 AVDD ROUT+
Try another known good speaker,

on U19
U725
D22
U18
ACRST#
ACSDOUT
ROUT-
LOUT+
C
Replace J3 ACSDIN0 LOUT-
CD-ROM. Motherboard J7 ACBITCLK
J705 14M_CODEC
J719 MIC_VREF
L741 2464_VREF
Re-test Yes Replace the

OK? faulty parts.
No
124
8.10 Audio Failure(Audio Codec)

+5V J719
EXTERNAL MIC JACK
VA
INTERNAL
P20 U17 P20
U18 MIC1
To U715 L734 BEAD_600Z/100M
5 1 C457 0.1U +
IN OUT VCC A SBSPKR R1150 0
t
-
GND
4 2 C458 0.1U CARDSPK#
t
R1155 0
n
EN ADJ Y B
L70
e e
MIC5205BM5 NC7S32
BEAD_600Z/100M
P17
r
R438
c m
C467 10K U727
0.01U
L66 CARD
e
L744
120Z/100M READER
S u
BEAD_600Z/100M
C456
c
CB710
1U
ac Do
+3V
1,9 21 MIC C975 1U R1157 0
iT ial
PC_BEEP 12
R535 0 R1154 4.7K R1153 0
P20J721
Line/In Jack
M t
AVDD 25,38 P20 2464_VREF
28 R532 0
To Next Page U19
n
C969 R519 L76
e
24
U726 1U 0 BEAD_600Z/100M
id
C974 R324 L53
SBSPKR 24 L751
f
BEAD_600Z/100M 120Z/100M
P14 ACRST# 11 1U 0
AUDIO
n
ACSDOUT 5
CODEC +5V
L67 120Z/100M 7,18,19
o
U715 ACSDIN0 R530 22 8
C
ICH4_M R812 0 ACSYNC 10 ALC655 35 AOUT_L R1130 0 R1135 0 AMP_LEFT C484 1U 5 P21
C480 1U 6
ACBITCLK L69 0 R498 22 6
U524
36 AOUT_R R1127 0 R1128 0 AMP_RIGHT C492 1U 20 AMP
C497 1U 23
TPA0212_GND
TO NEXT PAGE J720 TO NEXT PAGE U19

P11 48
56 R859 33 14M_CODEC R472 0 2 SPDIFOUT SUB_LEFT
U712
TO NEXT PAGE D22 TO NEXT PAGE U19
CLKGEN 47
EAPD SUB_RIGHT
ICS950810
125
8.10 Audio Failure(Audio Amplifier & Subwoofer)

From Previous Page U726
SPDIFOUT
15,17 VA
DEVICE_DECT
21 ROUT+ L52 600Z/100M

R322 R1183
10K P21
J7 Internal 4.7K J720
t
16 L50 600Z/100M
HP/OPT CONNECTOR
ROUT-
L754 600Z/100M
P21 Speaker
t n
L755 600Z/100M
Connector AGND
e e
4 LOUT+ L14 600Z/100M
U524
r
9 LOUT- L16 600Z/100M
J3 HDR/MA-2 DECT_HP#OPT L55 600Z/100M
c m
+ +
AUDIO AMP C474 C489 L757 LED
e
C474
100U 100U 600Z/100M
u
R329 22 L80 600Z/100M Drive
S
TPA0212_GND
c
R528 22 L78 600Z/100M IC
c Do
L758
+3V 600Z/100M GP1FD310TP
a
+5V
Q711
iT ial
DTA144WK
DECT_HP#/
R1158 DEVICE_DECT# OPT REMARK
10K R1185
M t
10K 0 0 HP in
D715
BAW56 0 1 OPT in
n
OPTIN#
VA 1 0 No this condition
e
VDD3S Q713
1 1 No device
id
+3V +5V
R367
From Previous Page U726 10K
R906
f
0 D22 DEVICE_DECT
EAPD BAT54C To U524
Q38 R477
n
R905
P13 8.2K AMP_SHUTDOWN
DEVICE_DECT# Q23
o
U715 DTC144TKA
C
ICH4_M
D27 D19
R445 0 KBC_MUTE RLS4148
P2
VA RLS4148
80
U16
WINBOND U19 C471 1000P
KBC LMV822
R1122 2.1K
From Previous Page U726 D17 R1125
R511 100 R463 22.1K 3
2464_VREF
1 C496 0.22U R502 8.2K
RLS4148 0
1
5 R26 0 P21 Subwoofer
Speaker
J705
C482 0.15U R479 22.1K 2 SUB_OUTR P21
SUB_RIGHT 8 R27 0
Connector
R510 22.1K 5 U725 HDR/MA-2
7 C483 0.22U R496 8.2K 4 6 L63 120Z/100M
+5V
C490 0.15U R509 22.1K 6 SUB_OUTL LM4871
SUB_LEFT
126
8.11 LAN Test Error

An error occurs when a LAN device is installed.
LAN Test Error
t nt
1.Check if the driver is installed properly.
re e
2.Check if the notebook connect with the
ec m
u
LAN properly.
S
c Do c
Board-level Check following parts and signals:
a Troubleshooting
iT ial
Parts: Signals:
M t
Test Yes U719 EECK AVDDL
Correct it. U717 EEDI DVDD
n
OK? U723 EEDO SB_PME#
e J709 EECS PCLKRUN#
id
No L732 PJRX+ PCI_DEVSEL#
f
L735 PJRX- PCI_FRAME#
n
L737 PJTX1- PCI_INTE#
o
L51 PJTX+ PCI_REQ3
Check if BIOS setup is ok.
C
L49 LAN_XTANL1 PCI_IRDY#
Q709 LAN_XTANL2 PCI_SERR
Replace X706 PCICLK_LAN
Motherboard R1101 LAN_WAKE
R1111 PCI_AD[0..31]
Yes R1115 PCI_C/BR#[0..3]
Re-test Correct it. R907 PCI_PAR
OK? R211 LAN_PCIRST#
R212 PCI_STOP#
No
127
8.11 LAN Test Error

An error occurs when a LAN device is installed.
+3VS
AVDDL 26,41,56,71
+3VS 84,94,107 R1110 3.6K
t
L737 120Z/100M 3,7,16,20
111 EECK 1 8
CS VCC
t n
+2.5VS_DDR L732 DVDD 24,32,45,54,64 P16
109 EEDI 2
78,99,110,116,126
e e
SK
C911
120Z/100M 1U
r
108 EEDO 3 U723
L735 120Z/100M 12 DI
5
c m
GND
VDD3S +3VS 106 EECS 4
DO
e
P16
u
93C46
R907
10K
R211,R212,R241…
8.2K*11
S
c Do c
a
SB_PME# 31
1 MDI0+ PMDI0+ 8 9 1
iT ial
PJTX+
PCLKRUN# PCI_GNT3# L51 P16
65,68,61,29,25 2 1
PCI_DEVSEL# PCI_FRAME# PCI_INTE# 10 PJTX1- 2
J709
P16
M t
PCI_TRDY# PCI_PERR# 3 4 15 PJRX+ 3
LAN CONNECTOR
63,67,70,75,69 2 MDI0- PMDI0- 7
PCI_IRDY# PCI_SERR# PCI_STOP#
P13 16 PJRX- 6
n
U719
PCI_REQ3# 30 R152 RP27
U717
e
75 0*4
5 MDI1+ PMDI1+ 2 11 MCT4 MDO2+ 4
L49
76 44,60.. 33,34…
id
PCI_PAR PCI_C/BE#[0..3] PCI_AD[0..31] 2 1
U715 LAN Controller R930
MD23- 5
f
LAN_PCIRST# 27 75
3 14 MCT3 MDO3+ 7
6 MDI1- 4 PMDI1- 1
n
+3VS
ICH4_M RTL8100CL MDO3- 8
o
LF-H80P
PCI_AD18 R947 100
R1115
C
10K
Q709
R1111 0 DTC144TKA
LAN_WAKE 105
121 LAN_XTAL1
122 LAN_XTAL2
R1101 1M
X706
1 2
P11
13 PCICLK_LAN 28 25MHZ
U712 C914 C915
27P 27P
ICS950810
128
8.12 Modem Test Error

An error occurs when run the modem
MODEM Test Error
t nt
1.Check if the driver is installed properly.
re e
2.Check if the notebook connect with the
ec m Board-level
u
phone LAN properly.
S
Troubleshooting
c Do c
a
iT ial
M t
Test Yes
Correct it.
n
OK? Parts: Signals:
e J717 +5V
id
No J715 +3VS
f
U726 +3V
n
R1132 MONO_OUT
Replace
o
C937
Replace a known good modem Motherboard R498
ACSDOUT
C L69 ACRST#
R1120 ACSYNC
R1131 ACBITCLK
L724 ACSDIN1
Yes F2 MODEMP
Re-test Correct it. MODEMN
OK?
No
129
8.12 Modem Test Error

An error occurs when run the modem
+5V 10,18
17
+3VS
P20
t
+3V 21
t n
R1132 4.7K 16
re e
37 C937 0.1U
ec m MONO_OUT 1
S u
J717
c
P20 5 ACSDOUT 23
c Do
CONNECTOR
a
U726 11 ACRST# 25
MODEM
iT ial
10 ACSYNC 22
ALC555
M t
6 R498 22 L69 0 R1120 22 ACBITCLK 30
en
id
P14
f
R1131 22 ACSDIN1 24
U715
ICH4_M
on
C C148
C806
1000P
1000P
2 2 3 MODEMP A2
P16
JP, use 4pcs of 2kV 1000P cap
Phone Lan P20 Lan Connector
L724
Connector 1 4 50UH
US, use 2pcs of 2kV 1000P cap
RJ11-2P
J709
J715
1 MODEMN A1
/RJ45-8P UK, use 4pcs of 3kV 1000P cap
HDR/MA-2 F2
MINISMDC014-2
130
8.13 Mini PCI Test Error

An error message is shown after Mini PCI device is installed or the Mini PCI device does’t work.
Mini PCI Test Error
t nt
1.Please check if the Mini PCI device is
re e
c m
installed properly. Board-level
2.Confirm Mini PCI device driver is
Se u
Troubleshooting
c
installed ok.
ac Do
iT ial
Parts: Signals
Yes
Test
M t
Correct it U715 PCI_AD[0:31] CLKRUN#
n
OK? PCI_C/BE# [0:3] PCI_PERR#
e
J509
PCI_REQ2# LAD [0:3]
id
No U712
f
PCI_FRAME# LFRAME#
U9
Please replace
n
PCI_IRDY# LRDQ0#
Q704
o
Please try another known good Mini PCI device. Motherboard PCI_TRDY# WIRELESS_PD#
C
R1137
PCI_DEVSEL# MINIPCI_PME#
R1079
PCI_STOP# SIO_48M
R1007 PCI_INTD# PCICLK_MINIPCI
Yes R1077
Re-test Please change the PCI_RESET#
OK? R1075 PCI_GNT2#
faulty part then end.
R1091 PCI_SERR#
No
131
8.14 CardBus & Reader Test Error

An error occurs when a PC card device is installed.
PC Card Slot Failure
t nt
1. Check if the PCMCIA CARD device is
re e
c m
installed properly. Board-level
2. Confirm PCMCIA card driver is installed ok.
Se u
Troubleshooting
c Do c Check following parts and signals:
a
Test Yes
iT ial Parts: Signals
OK?
M t
Correct it
n
U727 AD[0..31] PCIRST#
No
e J716 C/BE# [0..3] P_GNT0#
id
U728 DEVSEL# PIRQA#
Try another known good PCMCIA card device.

nf Replace J6
U9
FRAME# SUSB#
o
Motherboard IRDY# RI#
R186
C
TRDY# PCLK_CARD
R180 VCC5_EN#
R211 STOP#
VCC3_EN#
R212 PAR VPPD0
Re-test Yes Change the faulty PERR# VPPD1
R1121
OK? part then end. R1129 SERR# +VPPOUT
R826 P_REQ0# +3V
R1203 +5V
No SERIRQ
132
8.13 Mini PCI Test Error

An error message is shown after Mini PCI device is installed or the Mini PCI device does’t work.
+3V
+5V
18，97
R179 +3V
R211.. R1007 10K 13
t
PCI_INTD#
PCI_GNT2#
R1068 R1080 R1083
t
PCI_REQ2#
P13 P14
e e n
r
P19
PCI_PERR# PCI_STOP#
c m
PCLKRUN# PCI_DEVSE# WIRELESS_PD# 14,24
e
PCI_IRDY# PCI_FRAM#
S u
PCI_SERR# PCI_TRDY#
c
U715 PCI_AD[0..31]
ac Do PCI_AD17 R1092 100 48
iT ial
ICH4_M LAD[0..3] PCI_C/BE#[0..3]
R1075 R1091
LFRAME# LRDQ0# MINIPCI_LPCDRQ#
J713
M t
+3V
MINIPCI CONNECTOR
n
PCIRST# U9C
9
JL8 R1077 0 26
e
8
10
id
+3V
f
Q704
n
SB_PME# R915 0
MINIPCI_PME# 34
Co
0 121
P11 39 R895 33 SIO_48M R1137
U712 11 R1079
25
R816 33 PCICLK_MINIPCI 0
ICS950810
133
8.14 CardBus & Reader Test Error

An error occurs when a PC card device is installed.
+3V
R1201
+3V
R1199 10K*2 VCC5_EN# 1
R211, R180 VCCD0#
R212… R186 R231
8.2k PCI_AD20 R1202 100 VCC3_EN# 2
t
8.2K*7 8.2k*2 VCCD1# P17 +CARD_VCC 17,51
PCI_AD[0..31]
t n
VPPD0 15
P13 VPPD0 +VPPOUT 18,52
e e
PCI_DEVSEL# PCI_IRDY# PCI_STOP#
r
VPPD1 14
PCLKRUN# PCI_FRAME# PCI_TRDY# PCI_PERR# VPPD1 U728
c m
P17
e u
PCI_GNT0#
S
U715 P17 TPS2211A
c
3,4
+3V
c Do
PCI_REQ0# PCI_SERR# SERIRQ R1121 10K 16
a
R1129 10K 8
ICH4_M
iT ial
SUSB# R1200 4.7K U727 5,6
+5V
U9 J6
M t
10
JL7
8 CARD_PCIRST# CardBus
9
Reader
en
PCI_PAR PCI_C/BE#[0..3]
CCBE[0..3]# 7,12,21,61
id
CB710 FM/34
CCD2# CCD1# 36,67
f
PX2/1.
CAD[0..31] 2~6,8~11… 27MM
n
P11
o
12 R826 33 PCICLK_CARD CVS[1,2] 43,57
U712
C
CLKGEN R2_ A18 R2_ D2 R2_ D14 4732,40
ICS950810 CBLOCK# CSTOP# CDEVSEL# 48~50
CPAR CGNT# CTRDY# 13,15,53

+SD_MSVDD
20,27,29
59,62,63
SD Card
CSERR# CAUDIO CSTSCHG

7 R1198 10 SD_CLK
P17
1,4,6 SDCD# SD_WP# SD_CMD CPERR# CINT# CIRDY# 14,16,20
8~11 SD[0..3]
J716 CFRAME# CRST# CREQ# 54,58,60
MS Card
5 R1203 10 MS_SCLK R1213 33 CCLK 19

MA/15PX2/ST
2,12,14 MS_INS# MS_BS MS_SDIO
134
8.15 IEEE 1394 Test Failure

An error occurs when a IEEE 1394 device is installed..
IEEE 1394 Fail
t nt
1. Check if the 1394 device is installed
re e
c m
properly.
2. Confirm 1394 driver is installed ok.
Se u
c Do cBoard-level Check following parts and signals:
a Troubleshooting
iT ial
Parts: Signals
Yes
M t
Test Correct it. U724 PCI_AD[0..31] 1394_PCIRST#
OK?
n
U722 PCI_GNT1#EE
PCI_C/BE# [0..3]
e
J718 CS_1394
No
id
U9 PC_DEVSEL#
EECK_1394
f
U712 PCI_FRAME# EEDI_1394
U715
n
PCI_IRDY# EEDO_1394
L743
Check if BIOS setup is ok.
Co Replace
Motherboard
L746
L740
L83
PCI_TRDY#
PCI_STOP#
PCI_PAR
TPBIAS
TPA+_6307
TPA-_6307
R1117 TPB+_6307
R828 PCI_PERR#
TPB-_6307
Yes R1116 PCI_REQ1# 1394_AVCC
Re-test Correct it. R1142 PCI_PME# XI
OK? R1141
+3V,+3VS XO
X707
+PHYVDD
No
135
8.15 IEEE 1394 Test Failure

An error occurs when a IEEE 1394 device is installed..
+PHYVDD 1394_AVCC
+3V +3V 24,8,20… VCC0~7

VCCRAM
L743 +3V
39,49 8
VCC
120Z/100M
t
L746 62,65,75
R211, +3VS 76,89,90
t
R212, 29 EECS_1394 1
n
CS P18
R218… 120Z/100M
e e
8.2K
r
PCI_AD[0..31] 5~28,97~120 32 EECK_1394 2
SK U722
PCI_AD21
ec m R1117 100 108 31 EEDI_1394 3

DI
u
93C46
S
P13
c
PCI_C/BE#[0..3] 4,15,107,122 P18 30 EEDO_1394 4
c Do
DO
123,126…
a
PCI_FRAME# PCI_DEVSEL# PCI_TRDY# PCI_IRDY#
U715 PCI_GNT1# PCI_REQ1# PCI_INTG# PCI_STOP# PCI_PERR#
iT ial
PCI_PAR 3
ICH4_M U724
M t PCI_PME# 37
n
U9 70 TPB-_6307 1
e
1
JL2 92 P18
3 1394_PCIRST# 3 4
2
id
L740
120Z/100M
2 1
J718
f
71 TPB+_6307 2
VT6307L
CONNECTOR
o
72 TPA-_6307 3
1394
P11 3 4
C
16 R828 33 PCICLK_1394 93
L83
U712 2 1
120Z/100M
73 TPA+_6307 4
ICS950810
XI 60
R1143 R1144
54.9 54.9
R1116 1M XO 61 R1142 R1141
54.9 54.9
C965 R1148
X707 270P 4.99K
24.576MHZ
C939 C932 74 TPBIAS
10P 10P
136
9. Spare Part List(1)

Part Number Description Location(S) Part Number Description Location(S)
221600020252 CARTON;BATTERY,CAIMAN,PWR 242600000439 LABEL;25*6,HI-TEMP,COMMON
221600050218 PARTITION;BATTERY,MARLIN,CAIMAN, 242600000452 LABEL;BLANK,7MM*7MM,PRC
221600050219 PARTITION;TOP/BTM,BATTERY,MARLIN 242600000452 LABEL;BLANK,7MM*7MM,PRC
t
221673120003 CARTON;N-B,8060 242664800013 LABEL;CAUTION,INVERT BD,PITCHING
221673140001 BOX;AK,8060
t n
242668300028 LABEL;32*7MM,POLYESTER FILM,HOPE
e e
r
221673150001 PARTITION;AK BOX,8060 242669600005 LABEL;LOT NUMBER,RACE
221673150002 CARD BOARD;FRAME,PALLET,8060
ec m 242669900009 LABEL;BLANK,60*80MM,7170
S u
221673150003 CARD BOARD;TOP/BTM,PALLET,8060 242670800113 BFM-WORLD MARK;WINXP,7521N
221673150004 PARTITION;PALLET,8060
c Do c242678500005 CFM-INTEL;CENTRINO,NOTEBOOK,8081
222503220001 PE BUBBLE BAG;BATTERY,GRAMPUS
a 242679900005 LABEL;BAR CODE,(25*10MM)*12pcs,8
iT ial
222670820003 PE BAG;L560*W345,7521N 242680900001 LABEL;AGENCY-GLOBAL,8050
M t
224670830002 PALLET;1250*1080*130,7521N 242680900002 LABEL;BATT,11.1V/4.4AH,LI,SANYO,
n
225600000054 TAPE;INSULATING,POLYESTER FILM,1 242680900007 LABEL;17.3*5MM,BLANK,PWR
e
225600000061 TAPE;ADHENSIVE,DOUBLE-FACE,W20,U 271002000301 RES;0 ,1/10W,5% ,0805,SMT L62,L65,L73,L88,R1,R123,R26,R2
id
226600030332 SPONGE;320*290*10,CAIMAN,PWR 271002472301 RES;4.7K ,1/10W,5% ,0805,SMT PR704,PR706
227680900002 PAD;LCD/KB,8050
nf 271002604011 RES;604 ,1/10W,1% ,0805,SMT R945,R946
o
227680900003 END CAP;NORMAL,L/R,8050 271012000301 RES;0 ,1/8W,5% ,1206,SMT PR86
C
242600000001 LABEL;PAL,20*5MM,COMMON 271035012711 RES;.012,1W,1%,2010,LR2010,IRC,S PR707,PR711,PR719,PR732,PR73
242600000145 LABEL;10*10,BLANK,COMMON 271044100101 RES;0.010,1.5W, 1%,2512,SMT;PWR R6
242600000145 LABEL;10*10,BLANK,COMMON 271045087101 RES;.008 ,1W ,1% ,2512,SMT PR742
242600000157 LABEL;BAR CODE,125*65,COMMON 271045107101 RES;.01 ,1W ,1% ,2512,SMT PR701
242600000232 LABEL;6*6MM,GAL,BLANK,COMMON 271045507103 RES;0.050,1W, 1%,2512,SMT, only R24A,R24B,R24C
242600000378 LABEL;27*7MM,HI-TEMP 260'C 271046017301 RES;.001,2W,5%,2512,CYNTEC,SMT PR740
242600000385 LABEL;27*10,LAN ID BAR CODE 271061000002 RES;0 ,1/16W,0402,SMT PR103,PR104,PR11,PR111,PR120
242600000433 LABEL;BLANK,11*5MM,COMMON 271061010101 RES;1,1/16W,1%,0402,SMT PR18
137

271061100102 RES;10,1/16W,1%,0402,SMT PR37,PR38,PR5 271061180101 RES;18.2 ,1/16W,1% ,0402,SMT R838
271061100501 RES;10 ,1/16W,5% ,0402,SMT PR1,PR100,R1000,R1001,R1009,R 271061183102 RES;18K,1/16W,1%,0402,SMT PR718,R462,R507
271061101103 RES;100 ,1/16W,1% ,0402,SMT R1092,R1117,R1202,R208,R257,R 271061184302 RES;180K ,1/16W, 5%,0402,SMT R1140,R288
t
271061102105 RES;1K ,1/16W,1% ,0402,SMT PR121,PR53,R1006,R141,R32,R32 271061196212 RES;1.96K,1/16W,1%,0402,SMT PR710
271061102211 RES;1.02K,1/16W,1% ,0402,SMT R110,R120
t
e e n
271061196213 RES;19.6K,1/16W,1%,0402,SMT PR36,PR97,PR99
r
271061102303 RES;1K ,1/16W,5% ,0402,SMT R102,R1136,R1147,R155,R206,R2 271061201101 RES;200 ,1/16W, 1%,0402,SMT R280
271061102312 RES;10.2K,1/16W,1% ,0402,SMT R496,R502
ec m 271061202102 RES;2K ,1/16W,1% ,0402,SMT PR101,PR124,PR46,PR725,PR731
S u
271061103102 RES;10K ,1/16W,1% ,0402,SMT PR102,PR119,PR127,PR129,PR4,P 271061203102 RES;20K ,1/16W,1% ,0402,SMT PR117,PR21,PR41,PR722,PR726,R
271061103501 RES;10K ,1/16W,5% ,0402,SMT
c Do c
R1007,R104,R1098,R11,R1103,R1 271061203701 RES;20K ,1/16W,.1%,0402,SMT PR75
271061104102 RES;100K ,1/16W,1% ,0402,SMT
a
PR10,PR112,PR114,PR12,PR130,P 271061204102 RES;200K ,1/16W,1% ,0402,SMT PR54,PR55
iT ial
271061104501 RES;100K ,1/16W,5% ,0402,SMT PR69,PR703,PR720,PR83,PR89,R 271061205212 RES;20.5K,1/16W,1%,0402,SMT PR113
M t
271061105501 RES;1M ,1/16W,5% ,0402,SMT PR106,PR115,PR123,PR26,PR27,P 271061220102 RES;22,1/16W,1% ,0402,SMT R253
n
271061106501 RES;10M ,1/16W,5% ,0402,SMT R296,R938 271061220501 RES;22 ,1/16W,5% ,0402,SMT R105,R1120,R1131,R306,R329,R4
e
271061107411 RES;107K,1/16W,1%,0402,SMT PR35 271061221212 RES;2.21K,1/16W,1% ,0402,SMT R72,R79
id
271061118211 RES;11.8K,1/16W,1%,0402,SMT PR116 271061221312 RES;22.1K,1/16W,1% ,0402,SMT R463,R479,R509,R510
271061124312 RES;124K,1/16W,1%,0402,SMT
nf
PR79 271061221313 RES;220 ,1/16W, 5%,0402,SMT R552,R555,R556,R557
o
271061127212 RES;12.7K,1/16W,1%,0402,SMT PR17 271061222101 RES;2.2K,1/16W,1%,0402,SMT PR6
C
271061133101 RES;13.7K,1/16W,1%,0402,SMT PR96 271061222501 RES;2.2K ,1/16W,5% ,0402,SMT R315,R318
271061133311 RES;13.3K,1/16W,1%,0402,SMT PR19,PR29 271061223102 RES;22K,1/16W,1% ,0402,SMT R325,R520
271061135101 RES;1.3M,1/16W,1%,0402,SMT PR16,R1158 271061224501 RES;220K ,1/16W,5% ,0402,SMT R251
271061137371 RES;13.7K,1/16W,.1%,0402,SMT PR74 271061226311 RES;226K,1/16W,1%,0402,SMT PR71
271061151102 RES;150 ,1/16W, 1%,0402,SMT R220,R446,R772,R791,R850,R884 271061232111 RES;2.32K,1/16W,1%,0402,SMT PR39
271061152302 RES;15K ,1/16W,5% ,0402,SMT R1008 271061240302 RES;24,1/16W,5%,0402,SMT R106,R107,R108,R109,R29,R30,R3
271061152501 RES;1.5K ,1/16W,5% ,0402,SMT R1084 271061249211 RES;2.49K,1/16W,1% ,0402,SMT PR77
271061153102 RES;15K ,1/16W,1% ,0402,SMT PR105,PR107,PR122,PR727,PR72 271061249212 RES;24.9K,1/16W,1%,0402,SMT PR128,PR98
138

271061249312 RES;249K,1/16W,1%,0402,SMT PR729,PR76 271061562212 RES;56.2K,1/16W,1%,0402,SMT PR15
271061270102 RES;27.4 ,1/16W, 1%,0402,SMT R133,R213,R291 271061576411 RES;576K ,1/16W,1% ,0402,SMT PR28
271061272102 RES;2.7K ,1/16W,1% ,0402,SMT R448,R449 271061590411 RES;590K,1/16W,1%,0402,SMT PR65
t
271061301112 RES;301 ,1/16W,1% ,0402,SMT R793,R855 271061604011 RES;60.4 ,1/16W,1% ,0402,SMT R923,R924
271061330501 RES;33 ,1/16W,5% ,0402,SMT
t n
R1213,R77,R78,R816,R817,R818,R
e e
271061619211 RES;6.19K,1/16W,1% ,0402,SMT PR81
r
271061331304 RES;330 ,1/16W,5% ,0402,SMT R1073,R1089,R301 271061634211 RES;6.34K,1/16W,1% ,0402,SMT R1145
271061332312 RES;3.3K,1/16W,5% ,0402,SMT PR70
ec m 271061634214 RES;63.4K,1/16W,1%,0402,SMT PR42
S u
271061333501 RES;33K ,1/16W,5% ,0402,SMT PR45,R701,R706 271061649212 RES;6.49K,1/16W,1% ,0402,SMT PR721
271061390501 RES;39, 1/16W, 5%,0402,SMT R225
c Do c 271061681501 RES;680 ,1/16W,5% ,0402,SMT R214

271061391103 RES;390,1/16W,1% ,0402,SMT R876
a 271061682501 RES;6.8K ,1/16W,5% ,0402,SMT R537,R538,R546,R547
iT ial
271061402011 RES;40.2 ,1/16W,1% ,0402,SMT R119,R832 271061750501 RES;75 ,1/16W,5% ,0402,SMT R152,R271,R277,R767,R768,R769
M t
271061412111 RES;4.12K,1/16W,1%,0402,SMT PR58 271061752102 RES;7.5K,1/16W,1%,0402,SMT PR84
n
271061432212 RES;43.2K,1/16W,1%,0402,SMT PR118,PR60,R1187,R1189,R1205, 271061753101 RES;75,1/16W,1%,0402,SMT R334,R340
e
271061470501 RES;47 ,1/16W,5% ,0402,SMT R750 271061806311 RES;80.6K,1/16W,1% ,0402,SMT PR63,PR66
id
271061471501 RES;470 ,1/16W,5% ,0402,SMT R1085,R553,R554,R558 271061822501 RES;8.2K ,1/16W,5% ,0402,SMT PR126,R1004,R1005,R1074,R1119
271061472501 RES;4.7K ,1/16W,5% ,0402,SMT
nf
R10,R1081,R1132,R1154,R1200,R 271071000002 RES;0 ,1/16W,5% ,0603,SMT L69,L719,L728,L744,L747,L751,L
o
271061473501 RES;47K ,1/16W,5% ,0402,SMT R140,R442,R443,R702,R708,R929 271071101301 RES;100 ,1/16W,5% ,0603,SMT R11,R12,R14,R15,R16,R20,R21
C
271061474501 RES;470K ,1/16W,5% ,0402,SMT PR702,R373 271071102302 RES;1K ,1/16W,5% ,0603,SMT R11
271061499012 RES;49.9 ,1/16W,1% ,0402,SMT R1082,R1086,R1087,R1090,R209, 271071103302 RES;10K ,1/16W,5% ,0603,SMT R2
271061499212 RES;4.99K,1/16W,1% ,0402,SMT PR20,R1148 271071103302 RES;10K ,1/16W,5% ,0603,SMT R1122
271061499411 RES;499K ,1/16W,1% ,0402,SMT PR43,PR716 271071103302 RES;10K ,1/16W,5% ,0603,SMT R5,R7,R8
271061510303 RES;51, 1/16W, 5%,0402,SMT R224,R228,R238,R243,R289 271071104101 RES;100K ,1/16W,1% ,0603,SMT R18,R22,R23,R9
271061549011 RES;54.9 ,1/16W,1% ,0402,SMT R1141,R1142,R1143,R1144,R142, 271071104302 RES;100K ,1/16W,5% ,0603,SMT R7
271061560501 RES;56 ,1/16W,5% ,0402,SMT R198,R264,R269,R273,R42,R43,R7 271071105301 RES;1M ,1/16W,5% ,0603,SMT R10,R3
271061562102 RES;5.6K ,1/16W, 1%,0402,SMT R1099,R542 271071127011 RES;127 ,1/16W,1% ,0603,SMT R14A
139

271071127011 RES;127 ,1/16W,1% ,0603,SMT R163 271071681813 RES;68.1,1/16W,1%,0603,SMT R903
271071131101 RES;130 ,1/16W,1% ,0603,SMT R911 271071684101 RES;680K ,1/16W,1% ,0603,SMT R5
271071152302 RES;1.5K ,1/16W,5% ,0603,SMT R17 271071713102 RES;715 ,1/16W,1% ,0603,SMT R762
t
271071152302 RES;1.5K ,1/16W,5% ,0603,SMT R19 271071753301 RES;75K ,1/16W,5% ,0603,SMT R8
271071181101 RES;180 ,1/16W,1% ,0603,SMT R777
t
e e n
271071822102 RES;8.2K ,1/16W,1% ,0603,SMT R14B
r
271071201301 RES;200 ,1/16W,5% ,0603,SMT R1A,R1B 271072287011 RES;287 ,1/10W,1% ,0603,SMT R914
271071202301 RES;2K ,1/16W,5% ,0603,SMT R12
ec m 271072474101 RES;470K ,1/10W,1% ,0603,SMT R4
S u
271071224301 RES;220K ,1/16W,5% ,0603,SMT R1 271571000301 RP;0*8 ,16P ,1/16W,5% ,1606,SM RP14,RP15,RP6,RP8
271071274811 RES;27.4 ,1/16W,1% ,0603,SMT
c Do
R792,R839
c 271571560302 RP;56*8 ,16P,1/16W,5% ,1606,SMT RP29,RP30,RP31,RP32,RP33,RP3
271071301311 RES;301K ,1/16W,1% ,0603,SMT R13,R3
a 271586026101 RES;.02 ,2W,1%,2512,SMT PR22
iT ial
271071331301 RES;330 ,1/16W,5% ,0603,SMT R16,R21,R22 271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP10,RP16,RP27,RP718
M t
271071331301 RES;330 ,1/16W,5% ,0603,SMT R18,R20,R23 271611103301 RP;10K*4 ,8P ,1/16W,5% ,0612,SMT RP719
n
271071331301 RES;330 ,1/16W,5% ,0603,SMT C14 271611220301 RP;22*4 ,8P ,1/16W,5% ,0612,SMT RP45
e
271071362101 RES;3.6K ,1/16W,1% ,0603,SMT R1110 271611240302 RP;24*4 ,8P ,1/16W,5% ,0612,SMT RP11,RP12,RP13,RP17,RP18,RP1
id
271071374812 RES;37.4 ,1/16W,1% ,0603,SMT R898 271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP2
271071432111 RES;4.32K,1/16W,1% ,0603,SMT
nf
R10 271621103302 RP;10K*8 ,10P,1/32W,5% ,1206,SMT RP46,RP715
o
271071432211 RES;43.2K,1/16W,1% ,0603,SMT R1 271621472302 RP;4.7K*8,10P,1/32W,5% ,1206,SMT RP44
C
271071472302 RES;4.7K ,1/16W,5% ,0603,SMT PR87,PR88 272001105403 CAP;1U ,10%,10V ,0805,X7R,SMT PC3,PC46
271071478101 RES;4.7 ,1/16W,1% ,0603,SMT PR108,PR109,PR110,PR2,PR3,PR 272001106702 CAP;10U,6.3V,+- 20%,0805,X5R,SMT C110,C112,C114,C121,C122,C127
271071487011 RES;487 ,1/16W,1% ,0603,SMT,MUS R883 272001475701 CAP;4.7U ,CR,10V ,+80-20%,0805,Y C311,C517,C871,C941,C947
271071487811 RES;48.7 ,1/16W,1% ,0603,SMT R900 272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y C921,C961
271071499011 RES;499 ,1/16W,1% ,0603,SMT R764 272003105701 CAP;1U ,CR,25V ,+80%-20%,0805, PC701
271071499311 RES;499K ,1/16W,1% ,0603,SMT R17 272005104402 CAP;.1U ,50V,+/-10%,0805,X7R,SMT PC9
271071563101 RES;56K ,1/16W,1% ,0603,SMT R6 272005104404 CAP;.1U,CR,50V,10%,0805,SMT PC4,PC51,PC52,PC65,PC66,PC7,P
271071622303 RES;620,1/16W,5% ,0603,SMT R786 272005104705 CAP ;1U CR 50V +80-20% 0805 Y5V C14A,C14B,C4A,C4B
140

272010101301 CAP;100P,2KV,5%,1206,NPO,SMT,onl C18 272075222401 CAP;2200P,50V ,10%,0603,X7R,SMT C15A
272010101302 CAP;100P,2KV,5%,1206,NPO,SMT,onl 272075222401 CAP;2200P,50V ,10%,0603,X7R,SMT C5
272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S C166,C174,C238,C271,C355,C772 272075223702 CAP; 0.22U CR 50V +80-20% 0603 C1,C2,C20A,C24,C25
t
272012105401 CAP;1U ,CR,16V ,10%,1206,X7R,S C14A,C14B 272075471401 CAP;470P ,50V,10%,0603,X7R,SMT C15B
272021106501 CAP;10U ,10V ,20%,1210,X7R,SMT C475
t
e e n
272075471409 CAP; 0.0047U CR 50V 10% 0603 X7 C4
r
272023106502 CAP;10U,25V,M,1210,T2.5MM,X5R,SM PC703,PC704,PC705,PC721,PC73 272075473401 CAP;.047U,50V,10%,0603,X7R,SMT C313
272023475502 CAP;4.7U ,CR,25V ,20%,1210,X7R,S C1
ec m 272102104401 CAP;.1U ,CR,10V,10%,0402,X5R,SM PC44,PC80
S u
272030050302 CAP;5P,3KV,5%,1808,NPO,SMT,only C19 272102105701 CAP;1U ,CR,6.3V ,80-20%,0402,Y C1002,C11,C160,C206,C210,C219
272030102401 CAP;1000P,2KV,10%,1808,X7R,SMT
c Do
C148,C327,C806
c 272102224701 CAP;.22U ,10V ,+80-20%,0402,Y5V, C14,C483,C496,C515
272070475701 CAP;4.7U,CR,6.3V,+80-20%,0603,Y5
a
C860,C908 272102334701 CAP;.33U ,CR,10V ,+80-20%,0402,Y C964
iT ial
272071105403 CAP;1U ,10V ,10%,0603,X5R,SMT C10,C4 272102473402 CAP;.047uF ,16V ,+-10%,0402,X7R, C841
M t
272071154401 CAP;.15U ,CR,10V,10%,0603,X7R,SM C482,C490 272103331401 CAP;33P ,25V ,+/-10%,0402,NPO,S C17,C19,C344
n
272071225401 CAP;2.2U ,CR,6.3V ,10%,0603,X5R, C1001,C151,C161,C239,C24,C283 272105100303 CAP;10P ,CR,50V ,5%,0402,NPO,SM C789,C790,C791,C795,C796,C797
e
272071332401 CAP;.33U ,10V ,10%,0603,X7R,SMT C2 272105101401 CAP;100P ,50V ,5%,0402,COG,SMT C150,C18,C20,C503
id
272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM C17 272105101402 CAP;100P ,50V ,+ -10%,0402,NPO,S C10,C330,C455,C498,C520,C521,C
272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM
nf
C12,C6 272105102408 CAP;1000P,CR,50V,10%,0402,X7R,SM C960,C962,PC14,PC17,PC18,PC19
o
272072223401 CAP;.022U,16V ,10%,0603,X7R,SMT C471 272105102501 CAP;1000P,50V ,+/-20%,0402,X7R,S C100,C1006,C1007,C1008,C101,C
C
272072824401 CAP;.082U ,16V ,10%,0603,X7R,SMT C16 272105103702 CAP;.01U ,50V,+80-20%,0402,SMT C106,C117,C120,C128,C132,C137
272073104401 CAP;.1U ,CR,25V,10%,0603,X7R,PR C22,C7 272105104701 CAP;.1U ,16V,+80-20%,0402,SMT C1000,C102,C103,C104,C105,C10
272073223401 CAP;.022U,CR,25V ,10%,0603,X7R,S C9 272105181403 CAP;180P,50V,10%,0402,SMT PC24,PC25,PC61,PC63,PC738
272075101401 CAP;100P ,50V ,10%,0603,COG,SMT C20,C21 272105220402 CAP;22P ,50V ,+ -10%,0402,NPO,S C447,C450,C765,C766,C855,C861
272075101404 CAP; 0.001U CR 50V 10% 0603 X7R C13 272105221403 CAP;220P ,CR,50V ,10%,0402,X7R,S C165,PC11,PC73,PC734,PC75
272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S C13,C8 272105222501 CAP;2200P,50V ,+/-20%,0402,X7R,S C470,C494,C509,C728,C869
272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S C11,C3 272105270303 CAP;27P ,50V ,5%,0402,COG,SMT C794,C804,C914,C915
272075103408 CAP ;0.1U CR 50V 10% 0603 X7R S C10,C11,C12,C15,C3,C5,C6,C7,C8 272105271403 CAP;270P ,50V,+-10%,0402,X7R,SMT C15,C21,C770,C782,C965
141

272105332402 CAP;3300P,50V,10%,0402,SMT PC28,PC56 273000990127 INDUCTOR;IHLP5050CE-01-0.68uH,VI PL711
272105470402 CAP;47P ,50V ,+ -10%,0402,NPO,S C1,C143,C144,C154,C172,C2,C4,C 273000990184 INDUCTOR;3.0UH,30%,CDRH5D28,H3.0 PL717
272105471403 CAP;470P ,50V,10%,0402,X7R,SMT C41,C729,C742,C751 273000990185 INDUCTOR;3.9UH,30%,CDRH8D43,H4.5 PL706,PL707,PL715
t
272431157507 CAP;150U ,TPC,6.3V,20%,H1.9,7343 C701,C713,C743,C768,PC712,PC7 273000990186 INDUCTOR;3.0UH,30%,CDRH6D28,H2.8 PL709,PL713,PL714
272431157512 CAP;150U,6.3V,+/-20%,H2.8,PT,NCC
t
e e n
273001050039 XSFORMER;10/100 BASE,LF-H80P,SMT U717
r
272431227402 CAP;220U,2V,-35/+10%,H1.9,S,SP-C PC775,PC778,PC781,PC784 273001050069 TRANSFORMER;10/100 BASE,NS0013,S
272431227504 CAP;220U ,4V ,20%,7343,POSCAP,SM PC729,PC749
ec m 273001050160 XFMR;CI8.5,25T/2150T,300mH,ONLY T1
S u
272431337506 CAP;330U,4V,20%,7343,SMT PC787,PC788,PC811,PC815 274010800405 XTAL;8Mhz,30PPM,16PF,8*4.5,2P,SM X1
272601107506 EC;100U ,6.3V,M,9.3*3.6,-55~105'
c Do c
C466,C474,C489,C951 274011431414 XTAL;14.318MHZ,32PF,50PPM,8*4.5, X703
272625470401 CP;47P*4 ,8P,50V ,10%,1206,NPO,S CP2
a 274012457406 XTAL;24.576MHZ,16PF,50PPM,8*4.5, X707
iT ial
273000130001 FERRITE CHIP;120OHM/100MHZ,1608, L19,L20,L38,L42,L43,L45,L56,L7 274012500415 XTAL;25MHZ,20PF,30PPM,8.0*4.5,SM X706
M t
273000130006 FERRITE CHIP;600OHM/100MHZ,.2A,1 L13,L14,L16,L50,L52,L53,L55,L5 274012700406 XTAL;27MHZ,20PF,20PPM,8.0*4.5,SM X702
n
273000130015 FERRITE CHIP;220OHM/100MHZ,1608, L58,L59,L60 274013276103 XTAL;32.768KHZ,20PPM,12.5PF,CM20 X704
e
273000130039 FERRITE CHIP;130OHM/100MHZ,1608, L10,L11,L12,L36,L37,L7,L9 281101015001 IC;MP1015EM-Z,CCFL CTRL,TSSOP20, U1
id
273000150002 FERRIET CHIP;120OHM/100MHZ,2012, L41,L732,L735,L737 282574008005 IC;74AHC08,QUAD 2-I/P AND,TSSOP, U9
273000150013 FERRITE CHIP;120OHM/100MHZ,2012,
nf
L15,L17,L18,L24,L27,L46,L47,L5 282574014004 IC;74AHC14,HEX INVERTER,TSSOP,14 U703
o
273000150033 PHASEOUT;FERRITE CHIP,120OHM/100 L743,L746 282574132001 IC;74AHCT1G32,SINGLE OR GAT,SOT2 U17
C
273000150307 FERRITE BEAD;120 OHM/100MHZ,3A,0 L26,L28,L29,L30,L31,L32,L33,L3 283449004001 IC;FLASH,512*8,FWH/LPC,PM49FL004
273000150313 CHOKE COIL;90OHM/100MHZ,20%,2012 L2,L22,L5 283450040001 IC;FLASH,512*8,FWH,M50FW040K1,PL
273000500092 CHOKE COIL;2.2UH ,20%,16A,3.5MM PL719 283467490001 IC;FLASH,512K*8,FWH,SST49LF004A,
273000500115 CHOKE COIL;400uH MIN,120mΩ MAX; L724 283467490002 IC;FLASH,512K*8,FWH,W39V040FAP,P
273000610025 FERRITE ARRAY;120OHM/100MHZ,ONLY FA2 283467530001 IC;EEPROM,S24CC02A,2K,SO8,SMT,ON
273000620001 FERRITE ARRAY;600OHM/100MHZ,2520 L49,L51,L740,L83 283467540001 IC;EEPROM,M24C02-WMN6T,2K,SO8,SM IC2
273000990021 INDUCTOR;33uH,CDRH124,SUMIDA,SMT PL710 283467540002 IC;EEPROM,M93C46-WMN6T,64*16 BIT U722,U723
273000990054 INDUCTOR;10UH,D124C,+/-20%,TOKO, PL702,PL703 283767540001 IC;K4D263238E,DDR SDRAM,4MX32,BG U1,U3,U708,U709
142

283767540002 IC;EM6A9320BI-3.6M,DDR SDRAM,4MX 286301470001 IC;SC1470,PWM CTRL,TSSOP,14P,SMT PU16
283767630002 IC;HY8250128323,DDR SDRAM,4MX32, 286302211006 IC;CP2211,POWER DISTRI SW,REV.C1 U728
284500522001 IC;855GME GMCH,NORTH BRIDGE,BGA, U714 286302951015 IC;LP2951ACM,VOLTAGE REGULATOR,S U11
t
284500655003 IC;ALC655,AUDIO CODEC,LQFP,48P,S U726 286303107001 IC;AMS3107C,3.3V,1%,VOL REGULATO U13
284501014001 IC;ATI MOBILITY M10-P,A14,AGP,BG U710
t n
286303728002 IC;LTC3728LX,PWM CTRL,LTC,5X5 QF
e e
PU14,PU15,PU2,PU703
r
284502779001 IC;P2779A,EMI REDUCTION,SO8 U711 286303734001 IC;LTC3734,PWM CONTROLLER,32-QFN PU3
284506307001 IC;VT6307L,PCI-1394,2PORT,LQFP,1 U724
ec m 286309167001 IC;RT9167-47CB,200MA LDO REGULAT U18
S u
284507460002 IC;ADT7460,TEMPERATURE MTR,QSOP, U706 286309701001 IC;RT9701,POWER DISTRI SW,SOT23- U701,U705
284508100009 IC;RTL8100CL,LAN CONTROLLER,LQFP U719
c Do c286369229301 IC;G692L293T,RESET CIRCUIT,2.93V U21

284582801044 IC;FW82801DBM,ICH4-M,BGA,421P U715
a 288100024002 DIODE;RLZ24D,ZENER,23.63V,5%,SMT PD701
iT ial
284583950002 IC;W83L950D-Ver.C,LPC_KBC,LQFP,8 288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 D24,D7,PD5
M t
284595081201 IC;ICS950812,CK408 CLOCK GEN,TSS U712 288100054001 DIODE;BAT54,30V,200mA,SOT-23 D10,D11,D15,D16,D2
n
286002040001 IC;BQ2040,GAS GAUGE,SO,16P,SMT IC1 288100054002 DIODE;BAT54C,SCHOTTKY DIODE,SOT2 D22,PD4
e
286100212001 IC;TPA0212,AMPLIFIER,TSSOP,24P,S U524 288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM D13
id
286100393004 IC;LMV393,DUAL COMPARTOR,SSOP,8P PU5 288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM ZD3,ZD4
286100822002 IC;LMV822,OP AMP,DUAL,CMOS,MSOP,
nf
U19 288100056017 DIODE;BAW56LT1,70V,215MA,SOT-23, D704,D715,PD1,PD6,PD7,PD705
o
286104173001 IC;MAX4173F,I-SENSE AMP,SOT23,6P PU1 288100070006 DIODE;BAV70LT1,70V,225MW,SOT-23, D12,D18,PD702,PD704
C
286104871002 IC;LM4871LD,AUDIO AMP,4Ohm,2.5W, U725 288100099012 DIODE;BAV99LT1,70V,450MA,SOT-23, PD2,PD3
286300431014 IC;SC431LCSK-.5,.5%,ADJ REG,SOT2 PQ11 288100140007 DIODE;B140,40V,1A,SMA,DIODES,SMT PD706,PD725
286300594001 IC;TL594C,PWM CONTROL,SO,16P PU7 288100340008 DIODE;B340LA,40V,3A,SMA,DIODES,S PD713,PD714,PD718
286300690001 IC;GMT690B,RESET CIRCUIT,2.93V,S U10 288101040006 DIODE;SBM1040,10A,SCHOTTKY,POWER PD703
286300710002 IC;CB710,CARDBUS/CARD READER,LFG U727 288104148001 DIODE;RLS4148,200MA,500MW,MELF,S D17,D19,D21,D27,D703
286300812002 IC;S-812C,DECECTOR,SOT-89,PRC IC3 288105515001 DIODE;BZV55-C15,ZENER,5%,SOD-80, PD709
286301117021 IC;AMS1117,VOL REGULATOR,1A,SOT- U6 288110355001 DIODE;1SS355,80V,100mA,SOD-23,SM D2
286301414001 IC;MM1414,PROTECTION,TSOP-20A,PR IC4 288111544001 DIODE; 1SR-154-400 400V 1.0A D1
143

288200144008 TRANS;DTA144EKA,PNP,SMT Q1 291000013027 CON;HDR,MA,15P*2,ACES,88026-3000 J716
288200301001 TRANS;FDV301N,N-CHANNEL,SOT23 Q42 291000020204 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM
288202215001 TRANS;MUN2215T1,N-MOSFET,SC59,SM Q719,Q720 291000020206 CON;HDR,MA,2P*1,1.25MM,H2.57,R/A J3,J7,J705,J715
t
288202222019 TRANS;MMBT2222ALT1,NPN,TO236AB,O PQ15 291000021105 CON;HDR,MA,11P*1,ACES,87213-1100 CN1
288202237002 TRANS;MUN2237T1,NPN,SOT-23,SMT,O PQ24,Q47
t
e e n
291000021105 CON;HDR,MA,11P*1,ACES,87213-1100 J1
r
288202240001 TRANS;MUN2240T1,NPN,SOT-23,ON Q12,Q23,Q26,Q27,Q29,Q31,Q32,Q 291000023008 CON;HDR,FM,15P*2,0.8MM.H5,R/A,SM J717
288202301001 TRANS;SI2301DS,P-MOSFET,SOT-23
ec m
Q13,Q14,Q24,Q43,Q48,Q51 291000023011 CON;HDR,MA,15P*2,88031-3000,ACES J1
S u
288203904022 TRANS;MMBT3904L,NPN,Tr35NS,TO236 PQ10,PQ9,Q20,Q708,Q718 291000152603 CON;FPC/FFC,26P,1MM,R/A,KBD,SMT J5
288204406001 TRANS;AO4406,N-MOS,.0165OHM,SO8 PU10,PU9
c Do c 291000251246 MINIPCI SOCKET;124P,R/A,0.8MM,H= J713

288204407001 TRANS;AO4407,P-MOS,.01OHM,SO8,SM
a
PQ701,PQ704,PQ707 291000256843 CON;IC CARD,68P,UP,STANDOFF 0.0 J6
iT ial
288204409001 TRANS;AO4409,P-MOSFET,SO-8P,MSL, Q3,Q5 291000614793 IC SOCKET;UPGA479M,479P,MOLEX U713
M t
288204410010 TRANS;AO4410,N-MOSFET,ID=18A,0.0 PU11,PU12,PU13,PU712 291000622007 CON;DIMM,R/A,200P,.6,H9.2,REVERS J711
n
288204435003 TRANS;FDS4435,P-MOSFET,35mOHM,SO Q9,U704,U707 291000811008 CON;PHONE JACK,2 IN 1,7.0MM,ALLT J709
e
288204800001 TRANS;SI4800DY,N-MOS,.0185OHM,SO PU710,U7 291000920605 CON;STEREO JACK,6P,W9.5,33184000 J719,J721
id
288204900001 TRANS;AO4900,DUAL N-MOSFET WITH PU4,PU6,PU702,PU705,PU707,PU 294011200016 LED;GREEN,H0.8,0603,CL-190G,SMT D32,D33,D34,D35,D36,D37,D38
288204914001 TRANS;AO4914,DUAL N-MOSFET,WITH
nf
PU701 294011200034 LED;GREEN,H.8,0603,19-21VGC/TR,S LED4,LED5
o
288221371002 TRANS;MUN2137T1,PNP,SMT,ON PQ13,Q711 294011200034 LED;GREEN,H.8,0603,19-21VGC/TR,S LED3,LED6
C
288227002006 TRANS;2N7002LT1,N-CHANNEL FET,ES PQ1,PQ12,PQ14,PQ16,PQ17,PQ1 294011200043 LED;RE/GR,H0.8,L1.9,W1.6,19-22SR LED1
291000000029 CON;MINI 4 IN 1 SOCKET CONNECTOR J2 294011200043 LED;RE/GR,H0.8,L1.9,W1.6,19-22SR LED2
291000000203 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM J2 294011200069 LED;GREEN,19-21VGC/TR8,LED_CL190
291000000706 CON;BATTERY,7P,MA,2.5MM,R/A,C103 J703 294011200069 LED;GREEN,19-21VGC/TR8,LED_CL190
291000010209 CON;HDR,MA,2P*1,1.25MM,H4.2,ST,S J710 295000010028 FUSE;0.14A/60V,POLY SWITCH,PTC,S F2
291000010303 CON;HDR,MA,3P*1,1.25MM,H4.2,ST,S J707 295000010048 FUSE;0.5A/15V,POLY SWITCH,SMD F701
291000010619 CON;HDR,MA,6P,ACES,87151-0607,SM J4 295000010114 FUSE;FAST,1.75A,63VDC,1206,SMT,P F1
291000013025 CON;HDR,MA,15P*2,ACES,88107-3000 J2 295000010140 FUSE;FAST,2A,63VDC,1206,SMT,0433 F1
144

295000010141 FUSE;FAST,3A,32VDC,1206,SMT,0433 PF703 331870007007 CON;MINI DIN,7P,R/A,W/GROUND,330 J704
295000010163 FUSE;NORMAL,7A/24VDC,0433007,120 PF1,PF2,PF702 331910002006 CON;POWER JACK,2P,20VDC,5A,DIP PJ701
295000010183 FUSE;FAST,1.75A,63VDC,1206,SMT,0 332110020165 WIRE ;#20AWG,UL1007,L=160mm,RED, CN1
t
295000100004 FUSE;FAST,1A,63V,1206,THIN FILM F3 332110020173 WIRE ;#20AWG,UL1007,L=256mm,BLAC CN4
297004010001 SW;PUSH BUTTOM,5P,SPST,12VDC,50m SW2,SW4,SW5
t
e e n
332110026150 WIRE ;#26AWG,UL1007,L=208mm,BLUE CN2
r
297120101007 SW;DIP,SPST,4P,24VDC,.025A,SMT SW701 332110026151 WIRE ;#26AWG,UL1007,L=142mm,YELL CN3
297140200003 SW;COVER SWITCH,0.1A,30V,4P,T-ME SW1
ec m 332810000034 PWR CORD;250V/2.5A,2P,BLK,EU,175
S u
310111103029 THERMISTOR;10K,1%,BN35-3H103F,18 RT1 333050000117 SHRINK TUBE;UL,600V,105'C,ID2.5*
316680900001 PCB;PWA-8050 M BD R01
c Do c 335152000026 CFM-BAT;FUSE,THERMAL,NEC,SF91E
316680900006 PCB;PWA-8050/BATT ,PR AND GA BD
a 335152000085 FUSE; 128 DC-7A/50V 139 ℃only UC F1
iT ial
316680900007 PCB;PWA-8050/Transition BD R00 335152000097 FUSE;LR4-73X,POLY SWITCH,PWR
M t
316681300001 PCB;PWA-INVERTER BD (DA-1A08-A); R0F 338536010052 BATTERY;LI,3.7V/2.2AH,18650,SANY
n
322680900001 CABLE FFC;TP,8050 339115000046 MICROPHONE;-60dB+-2dB,D6.0*H2.7, MIC1
e
323767720004 DDR SODIMM MODULE;256MB,77.10634 340680900002 SPEAKER ASSY;L,8050
id
324180786388 IC,CPU,BANIAS,1.5GHZ,MICRO-FCPGA 340680900003 SPEAKER ASSY;R,8050
331000000302 CON HOLDER;PCMCIA,UP,STANDOFF 0.
f
J6
n
340680900004 COVER ASSY;8050
o
331000004009 CON;IEEE1394,MA,4P*1,0.8MM,R/A J718 340680900005 HOUSING ASSY;8050
C
331000007025 CONNECTOR;7 PIN,DIP,ALLTOP,C1034 CON1 340680900006 BRACKET ASSY;SYSTEM,8050
331000008033 CON;USB,FM,H15.64,R/A,4P*2,2522A J701 340680900008 SHIELDING ASSY;COVER,8050
331030044019 CON;HDR,FM.22P*2,R/A,ST,ACE-1A2, J714 340680900009 BRACKET ASSY;TP,8050
331040004024 CON;HDR,MA,4P*1,H=5.9,R/A,USB,DI J706 340680900010 COVER ASSY;HDD,8050
331040050018 CON;HDR,BTB R/A,0.8MM,S-TECH1507 J708 340680900011 HOUSEING ASSY;LCD,8050
331660020005 DIMM SOCKET;DDR SODIMM 200P, CA0 J712 340680900012 COVER ASSY;LCD,8050
331710015016 CON;D,FM,15P,3ROW,SUYIN,070912FR J702 340680900020 BEZEL ASSY;COMBO,QSI,SBW242,8050
331840010008 CON;STEREO JACK,10P,W/SPDIF,R/A, J720 340680900026 SHIELDING ASSY;HDD,8050
145

340680900027 WLEN ASSY;CABLE,8050 344680900048 DUMMY CARD;PCMCIA,8050
340680900028 WIRE ASSY;INVERTER,8050 344680900049 COVER;HINGE,L,8050
340680900029 COVER ASSY;MINIPCI,8050 345677000018 CONDUCTIVE TAPE;LCD,LYNX
t
340680900034 SPEAKER ASSY;WOOFER,NEW,8050 345677300001 RUBBER;SILICONE RUBBER,T=1.5mm,D
340680900035 HEATSINK ASSY;DESCRETE,UNP,8050
t
e e n
346503100005 INSULATOR;5,BATTERY ASSY,7521Li
r
340683400029 HEATSINK ASSY;NORTHBRIDGE,8050F 346503200202 INSULATOR;BATT ASSY,ONE ROUND,BL
341677000002 SPRING;SCREW,HEATSINK,LYNX
ec m 346677000016 SPONGE;RTC,LYNX
S u
341680900001 SPC SCREW;#4-1/4,8050 346677300001 INSULATOR;FIBER,UL94V-0,D=17.5mm
342502900001 CONTACT PLATE;W4L27T0.15,7068
c Do c 346680900001 INSULATOR;MB,8050
342502900001 CONTACT PLATE;W4L27T0.15,7068
a 346680900002 INSULATOR;CARD READER,8050
iT ial
342503200004 CONTACT PLATE;W4L63T0.15,1/4,T T 346680900005 INSULATOR;INVERTER,LCD,8050
M t
342672200010 BRACKET;CD-ROM,8500 346680900007 INSULATOR;PCB,ASSY,L105,W12T1.0
n
342672400007 FINGER;EMI GROUNDING SMD FINGER TP45,TP48,TP50 346680900009 INSULATOR;PCMCIA,8050
e
342677000014 SMT NUT;A40M20-50,EMI STOP,LYNX MTG701,MTG702 346680900010 INSULATOR;DDR,MINIPCI,8050
id
342680900005 HINGE;R,8050 346680900011 MYLAR;COVER,LCD,8050
342680900006 HINGE;L,8050
nf 346680900017 INSULATOR;L16W8.5T0.05MM,DIALAMY
o
342680900009 SMT NUT;A40M20-55,EMI STOP,8050 MTG703,MTG704 346681800004 INSULATOR;BATT,ASSY,L129W15T0.25
C
342683400005 SPRING;HEATSINK,VGA,8050F 347105015007 GASKET;1,05,015,007
344680900002 cover;battery,8050 347105030025 GASKET;1,05,030,025
344680900003 housing;battery,8050 347105035020 GASKET;1,05,035,020
344680900009 COVER;REAR,R,8050 347108030008 GASKET;1,08,030,008
344680900010 COVER;REAR,L,8050 347110003010 GASKET;1,10,003,010
344680900011 COVER;HINGE,R,8050 347110010010 GASKET;1,10,010,010
344680900015 COVER;CPU,8050 361200001018 CLEANNER;YC-336,LIQUID,STENCIL/P
344680900016 COVER;DDR,8050 361400003003 JET-MELT ADHESIVES;3478-Q,5/8in*
146

361400003005 ADHESIVE;HEAT,TRANSFER,HTA-48(W) 411681300002 PWA;PWA-INVERTER BD,SMT,DA-1A08-
361400003021 SOLDER CREAM;NOCLEAN,P4020870980 411681300003 PWA;PWA-INVERTER BD,SMT TOP,DA-1
361400003021 SOLDER CREAM;NOCLEAN,P4020870980 411681300004 PWA;PWA-INVERTER BD,SMT BOT,DA-1
t
361400003030 ADHESIVE;ABS+PC PACK,G485,CEMIDA 411681710001 PWA-PWA-BATT BD;LI,4.4Ah,2P3S,BL
365350000003 SOLDER WIRE;0.8MM,SN43/PB43/BI14
t n
411681710002 PWA-PWA-BATT BD;SMT,BL3244G095/8
e e
r
370102010201 SPC-SCREW;M2L2,NIW,K-HD,t=0.8,NL 411682700001 PWA;PWA-8050D,ATIM-A14-64M,MOTHE
370102010303 SPC-SCREW;M2L3,NIW,K-HD(+),NYLOK
ec m 411682700002 PWA;PWA-8050D,ATIM-A14-64M,MOTHE
S u
370102010409 SPC-SCREW;M2L4,K-HD(t0.3),NIB/NL 411682700003 PWA;PWA-8050D,ATIM-A14-64M,MOTHE
370102010409 SPC-SCREW;M2L4,K-HD(t0.3),NIB/NL
c Do c412155600047 PCB ASSY;MDM,56K,UNIV,F-PACK,WO/

370102010502 SPC-SCREW;M2 L5,NIB,K-HD,t0.8,NL
a 412673400008 PCB ASSY;MINI-PCI,TYPE IIIB,INTE
iT ial
370102010607 SPC-SCREW;M2L6,K-HD(+),NIW/NLK,H 412681300001 PCB ASSY;D/A BD,DA-1A08-A,PWR
M t
370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK 413000020388 LCD;LTN154X1-L02,TFT15.4",XGA,SA
n
370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK 416268090002 LT PF;SAMSUNG,15.4",LTN154WX,805
e
370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N 422674300071 WIRE ASSY;MDC,E-NOTE
id
370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N 422677000008 WIRE ASSY;BATT TO MB,FOR LYNX,MO J710
370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK
nf 422680900003 WIRE CABLE;SAM LTN154X1,8050
o
370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK 431680900004 CASE KIT;8050D,ATIM
C
370102611601 SPC-SCREW;M2.6*L16,NIB,K-HD 441674800032 CONTACT PLATE ASSY;W4L27T0.15,S-
370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3 441680900031 LCD ASSY;SAMSUNG,XGA,15.4",LTN15
371102010252 SCREW;M2L2.5,K-HEAD(+),NIB/NLK 441681700001 BATT ASS'Y;11.1V,4.4Ah,LI,BL3244
371102010252 SCREW;M2L2.5,K-HEAD(+),NIB/NLK 441681700002 BATT ASSY;11.1V,4.4Ah,LI,CASE CL
371102610603 SCREW;M2.6L6,FLNG/PAN(+),NIW/NLK 441681700003 BATT ASSY;11.1V,4.4Ah,LI,CORE PA
373101712351 T-SCREW;B,M1.7,L2.35,K-HD,2,NIB 441681710031 CONTACT PLATE ASSY;W4L27T0.15,FU
411680900019 PWA;PWA-8050-4 in 1 TRANSITION B 442672600031 AC ADPT ASSY;19V,3.16A,DELTA,706
411681300001 PWA;PWA-INVERTER BD,DA-1A08-A,PW 442680900051 TOUCHPAD MODULE;SYNAPTICS,TM42PU
147

Part Number Description Location(S)
451680900001 LABEL KIT;N-B,8050
451680900031 HDD ME KIT;8050
451680900051 LCD ME KIT;SAMSUNG,15.4",8050
t
451680900072 HOUSING KIT;8050,ATIM10/11
451680900093 HEATSINK ASSY DISCRETE;UNP,8050
t
e e n
r
451680900094 HEATSINK ASSY DISCRETE;MPT,8050
451680900151 ROM ME KIT;8050
ec m
S u
451999900003 HEATSINK DISCRETE OPTION;8050
461680900006 PACKING KIT;N-B BOX,8050
c Do c
481680900001 F/W ASSY;SYS/VGA BIOS,8050,ATIM U15
a
iT ial
481680900002 F/W ASSY;KBD CTRL,8050 U16
M t
523402379038 HD DRIVE,40GB,2.5",MHT2040AT,FUJ
n
523430061010 DVD COMBO DRIVE;24X10X8X24,SBW-2
e
523468090002 HDD ASSY;40GB,MHT2040AT,FUJITSU,
id
523468090029 COMBO ASSY;SBW-242B,QSI,8050
526268270004 LTX;8050DA/5ACB/40H/9UI9/A5D3A/X
nf
o
531020237777 KBD;88,UI,K011818A1,8050,BK
C
600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC
624200010140 LABEL;5*20,BLANK,COMMON
P/N:526268270004
148
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
n
Co
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5 4 3 2 1
REVISION TAPEOUT DAY HISTORY
PCI DEVICE INTERRUPT REQ/GNT IDSEL R00 2003/8/26
8050D R01 LAN
CARDBUS /
PCI_INTE#
PCI_INTB# /
PCI_REQ3# /
PCI_GNT3#
PCI_REQ0# /
AD18
AD20
R0A 2003/10/09 1. CHANGE CARDBUS/CARD READER CONTROLLER FROM
R5C592 TO CB710
PROJECT CODE- G113 PCB P/N 316680900001 CARDREADER PCI_INTC# PCI_GNT0#

2. USE IEEE1394 CONTROLLER VT6307 INSTEAD OF
PRODUCT CODE- 6827 ASSY P/N 411682700001 IEEE1394 PCI_INTG# PCI_REQ1# / AD21
R5C592
PCI_GNT1#
PAGE 1 TITLE 3. ADD SPDIF FUNCTION
PAGE 2 CPU- BANIAS(1/2) MINIPCI PCI_INTD# PCI_REQ2# / AD17

D PCI_GNT2# 4. CHANGE CARDBUS CONNENTOR PLACEMENT FORM D
PAGE 3 CPU-BANIAS(2/2) COMPONENT SIDE TO SOLDER SIDE
PAGE 4 NB-MONTARA-GME(1/2) 5. CHANGE MDC AND MINIPCI CONNECTORS PLACEMENT FROM
PAGE 5 NB-MONTARA-GME(2/2) SOLDER SIDE TO COMPONENT SIDE
PAGE 6 DDR-DIMM EMI 6. CHANGE LVDS ROUTING FAR AWAY POWER SWITCHING
PAGE 7 VGA-M10(1/4) SIGNALS
TP42 TP43 TP44 TP46
TP3
PAGE 8 VGA-M10(2/4) R0B 2003/11/07 1. CHANGE TV CONNECTOR
TOUCHPAD_METAL10 TOUCHPAD_METAL10 TOUCHPAD_METAL10 TOUCHPAD_METAL10
TOUCHPAD_METAL5
PAGE 9 VGA-M10 (3/4) TP48 TP50
2. CHANGE BATTERY CONNECTOR
PAGE10 VGA-M10(4/4) TOUCHPAD_METAL10 TOUCHPAD_METAL10
1
R01 2003/12/16 1. EXCHANGE TV CONNECTOR PIN 6 AND PIN 7
1
PAGE11 CLOCK SYNTHERIZER/TV ENCODER
342672400007 342672400007 2. ADD POWER CONSUMPTION SAVING CIRCUIT BUT RESERVE
1
PAGE12 CRT/LCD GND GND GND GND GND
PAGE13 SOUTHBRIDGE-ICH4-M(1/2) TP47 TP51 TP52 3. CHANGE SOME BEAD TO 0 OHM IN AUDIO REGION
TP4
PAGE14 SOUTHBRIDGE-ICH4-M(2/2) TOUCHPAD_METAL10 TOUCHPAD_METAL10 TOUCHPAD_METAL10 GND GND 4. CHANGE SOME RESISTOR AND CAPACITANCE TO INCREASE
TOUCHPAD_METAL5 TP45 SUBWOOFER GAIN
PAGE15 CDROM/HDD/USB CONNECTOR 5. DELETE SOME COMPONENT AROUND TV ENCODER
TOUCHPAD_METAL10
1
PAGE16 LAN RTL8100CL
1
342672400007
PAGE17 R5C811/841
1
t
GND GND GND GND
PAGE18 IEEE1394
PAGE19 MINI-PCI
t
GND
n
PAGE20 AUDIO CODEC(ALC655)
e e
C
PAGE21 AUDIO AMPLIFIER/SUBWOOFER C
PAGE22 KBC(W83L950D) CARDREADER EC ESD
r
PAGE23 TOUCHP_PAD/FWH/LED MDC
c m
342677000014 342677000014
PAGE24 PULL HIGH MTG702 MTG701
MTG704
MTG/ID1.2/OD4.6
MTG703
MTG/ID1.2/OD4.6 +1.35V
MTG/ID1.2/OD4.6 MTG/ID1.2/OD4.6 C1008
PAGE25 PERPHERIAL TP722 TP723
e
+3V +5V 50V 1 2 0402
C1007 +/-20% 1000P
PAGE26 +2.5VS_DDR_P/+1.25V_DDR_P TOUCHPAD_METAL10 TOUCHPAD_METAL10
u
JS702 50V 1 2 0402
1
S
+/-20% 1000P
1
1 2
PAGE27 +3VS_P/+5VS_P GND
c
SHORT-SMT4 +2.5V_M10
1
PAGE28 +1.5V_P/+1.05V_P GND C1006
c Do
GND GND +3V +5V 50V 1 2 0402
PAGE29 +1.8V_P/1.35V_P C357 +/-20% 1000P
50V 1 2 0402 GND_USB 1394_GND
PAGE30 +1.2V/1.0V_M10 +/-20% 1000P
a
AGND GND
PAGE31 CPUCORE
PAGE32 ADAPTER/VMAIN
iT ial
PAGE33 CHARGER/DISCHARGER
M t
MTG1 MTG2 MTG4 MTG7 MTG8
ID3.0/OD11 ID3.0/OD11 ID3.0/OD11 ID3.0/OD11 ID3.0/OD11 8050N
MTG118NRD433_3016B MTG118-RD433-N-30X16 MTG118-RD433-N-30X16 MTG118NRD433_3016A MTG118NRD433_3016A
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
4 16 4 16 4 16 4 16 4 16 TP58 TP59
n
5 15 5 15 5 15 5 15 5 15 RD080_051/NA RD080_051/NA
6 14 6 14 6 14 6 14 6 14
7 13 7 13 7 13 7 13 7 13
e
B B
8 12 8 12 8 12 8 12 8 12
1
10
11
10
11
10
11
10
11
10
11
9
id
GND GND
f
CHAGND GND GND GND_45 GND
CPU
n
MTG9 MTG11 MTG13 MTG14
ID3.0/OD11 ID3.0/OD11 ID3.0/OD11 ID3.0/OD11
MTG118-RD433-N-30X16 MTG118NRD433_3016A MTG118-RD433-N-30X16 MTG118NRD433_3016B MTG24 MTG27 MTG28 MTG12 MTG32
o
ID5.3/OD7.5 ID5.3/OD7.5 ID5.3/OD7.5 ID5.3/OD7.5 ID5.3/OD7.5
3
2
1
3
2
1
3
2
1
3
2
1
4 16 4 16 4 16 4 16
5 15 5 15 5 15 5 15 光學定位點
C
1
1
6 14 6 14 6 14 6 14
7 13 7 13 7 13 7 13
8 12 8 12 8 12 8 12 FD1 FD2 FD4 FD3
FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK
10
11
10
11
10
11
10
11
GND GND GND GND GND

9
1
GND GND_45 GND CAGND MTG10 MTG22 MTG5 MTG31
ID2.8/OD11 ID2.8/OD11 ID3.0/OD9.0 ID3.0/OD8.0/CP7.5X9.5
FD703 FD704 FD702 FD701

FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK FIDUCIAL-MARK
MTG6 MTG3 MTG15
1
1
ID3.0/OD9.0 ID3.0/OD9.0 ID3.0/OD9.0
MTG118-RD354-N-30X12 MTG118-RD354-N-30X12 MTG118-RD354-N-30X12
1
GND GND GND GND
3
2
1
3
2
1
3
2
1
A A
4 12 4 12 4 12
5 11 5 11 5 11
6 10 6 10 6 10
7
8
9
7
8
9
7
8
9
DRAWN DESIGN CHECK ISSUES

GND GND 1394_GND
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
Date: Wednesday, December 31, 2003 Sheet 1 of 34
5 4 3 2 1

5 4 3 2 1
VCC : PROCESSOR CORE POWER SUPPLY.

VCCA : ISOLATE POWER FOR INTERNAL PLL.
VCCP : PROCESSOR I/O POWER SUPPLY. CPU-BANIAS (1/2)
VCCQ : QUIET POWER SUPPLY FOR ON DIE COMP CKT.
HA#[3..31] HD#[0..63] +VCC_CORE

4 HA#[3..31] U713A HD#[0..63] 4
HA#3 P4 A19 HD#0 U713B
HA#4 A3# D0# HD#1
U4 A25 B15 D6
HA#5 A4# D1# HD#2 +VCCP 11 HCLK_CPU BCLK0 VCC_0
V3 A22 B14 D8
+VCC_CORE HA#6 A5# D2# HD#3 11 HCLK_CPU# BCLK1 VCC_1
R3 B21 D18
HA#7 A6# D3# HD#4 HBPM#0 VCC_2
V2 A24 C8 D20
A7# D4# BPM0# VCC_3
1
HA#8 W1 B26 HD#5 HBPM#1 B8 D22
A8# D5# BPM1# VCC_4
1
HA#9 T4 A21 HD#6 R198 R242 0 1 2 0402 A9 E5

D
R289 HA#10 A9# D6# HD#7 56 R237 0 BPM2# VCC_5 D
W2 B20 1 2 0402 C9 E7
51 HA#11 A10# D7# HD#8 0402 BPM3# VCC_6
Y4 C20 E9
0402 HA#12 A11# D8# HD#9 5% +VCCP HTCLK VCC_7
Y1 B24 A13 E17
5% HA#13 A12# D9# HD#10 HTDI TCK VCC_8
2
U1 D24 C12 E19
HA#14 A13# D10# HD#11 HPROCHOT# HTDO TDI VCC_9
2
AA3 E24 A12 E21

A14# D11# TDO VCC_10
1
HBR0# HA#15 Y3 C26 HD#12 HTMS C11 F6
HA#16 A15# D12# HD#13 R141 HTRST# TMS VCC_11
AA2 B23 B13 F8
HA#17 A16# D13# HD#14 1K HPREQ# TRST# VCC_12
AF4 E23 B10 F18
+VCCP HA#18 A17# D14# HD#15 0402 HPRDY# PREQ# VCC_13
AC4 C25 A10 F20
HA#19 A18# D15# HD#16 1% PRDY# VCC_14
AC7 H23 F22
HA#20 A19# D16# HD#17 VCC_15
2
AC3 G25 G5
A20# D17# VCC_16
1
HA#21 AD3 L23 HD#18 AD26 G21

HA#22 A21# D18# HD#19 GTLREF0 VCC_17
R301 AE4
A22# D19#
M26 Close to CPU as possible. < 0.5" E26
GTLREF1 VCC_18
H6
330 HA#23 AD2 H24 HD#20 G1 H22
A23# D20# GTLREF2 VCC_19
1
0402 HA#24 AB4 F25 HD#21 AC1 J5
A24# D21# GTLREF3 VCC_20
1
5% HA#25 AC6 G24 HD#22 C165 C160 R134 J21
HA#26 A25# D22# HD#23 2K HCOMP0 VCC_21
2
AD5 J23 220P 1U P25 K22

HPWRGD HA#27 A26# D23# HD#24 0402 0402 0402 HCOMP1 COMP0 VCC_22
AE2 M23 P26 U5
HA#28 A27# D24# HD#25 10% +80-20% 1% HCOMP2 COMP1 VCC_23
2
AD6 J25 AB2 V6
HA#29 A28# D25# HD#26 50V 10V HCOMP3 COMP2 VCC_24
2
AF3 L26 AB1 V22
HA#30 A29# D26# HD#27 COMP3 VCC_25
AE1 N24 W5
HREQ#[0..4] HA#31 A30# D27# HD#28 VCC_26
AF1 M25 W21
4 HREQ#[0..4] A31# D28# HD#29 GND VCC_27
H26 AF7 Y6
HREQ#0 D29# HD#30 RSVD_0 VCC_28
R2 N25 Y22
HREQ#1 REQ0# D30# HD#31 VCC_29
P3
REQ1# D31#
K25 HCOMP1 & HCOMP3 should be C14
RSVD_2 VCC_30
AA5
HREQ#2 T2 Y26 HD#32 C3 AA7
HREQ#3 P1
REQ2# D32#
AA24 HD#33 route with 5 mil width RSVD_3 VCC_31
AA9
HREQ#4 REQ3# D33# HD#34 VCC_32
T1 T25 AA11
REQ4# D34# HD#35 CPU_TEST1 VCC_33
U23 C5 AA13
D35# HD#36 CPU_TEST2 TEST1 VCC_34
N2 V23 F23 AA15
t
4 HADS# ADS# D36# HD#37 CPU_TEST3 TEST2 VCC_35
R24 C16 AA17
D37# HD#38 TEST3 VCC_36
U3 R26 AA19
4 HADSTB#0 ADSTB0# D38# HD#39 HDINV#[0..3] VCC_37
AE5 R23 AA21
4 HADSTB#1 ADSTB1# D39# 4 HDINV#[0..3] VCC_38
t
AA23 HD#40 HDINV#0 D25 AB6
n
HBR0# D40# HD#41 HDINV#1 DINV0# VCC_39
N4 U26 J26 AB8
4 HBR0# BR0# D41# HD#42 HDINV#2 DINV1# VCC_40
J3 V24 T24 AB10
4 HBPRI# BPRI# D42# DINV2# VCC_41
e e
L1 U25 HD#43 HDINV#3 AD20 AB12
4 HBNR# BNR# D43# HD#44 DINV3# VCC_42
C J2 V26 AB14 C
4 HLOCK# LOCK# D44# HD#45 VCC_43
Y23 AB16
r
+VCCP R264 56 1 D45# HD#46 VCC_44
2 0402 A4 AA26 AB18
5% IERR# D46# HD#47 VCC_45
K3 Y25 AB20
4 HHIT# HIT# D47# HD#48 VCC_46
K4 AB25 AB22
c m
4 HHITM# HITM# D48# HD#49 +VCC_CORE VCC_47
L4 AC23 AC9
4 HDEFER# DEFER# D49# HD#50 VCC_48
M3 AB24 AC11
4 HTRDY# TRDY# D50# HD#51 VCC_49
AC20 AE11 AC13
e
HRS#0 D51# HD#52 VCC_61 VCC_50
H1 AC22 AE13 AC15
HRS#[0..2] HRS#1 RS0# D52# HD#53 VCC_62 VCC_51
K1 AC25 AE15 AC17
4 HRS#[0..2] RS1# D53# VCC_63 VCC_52
u
HRS#2 L2 AD23 HD#54 AE17 AC19
RS2# D54# VCC_64 VCC_53
S
AE22 HD#55 AE19 AD8
HA20M# D55# HD#56 VCC_65 VCC_54
C2 AF23 AF8 AD10
13 HA20M# A20M# D56# VCC_66 VCC_55
c
D3 AD24 HD#57 AF10 AD12
14 HFERR# FERR# D57# HD#58 VCC_67 VCC_56
C19 AF20 AF12 AD14
4 HDPWR# DPWR# D58# VCC_68 VCC_57
c Do
HDBR# A7 AE21 HD#59 AF14 AD16
HSLP# DBR# D59# HD#60 VCC_69 VCC_58
A6 AD21 AF16 AD18
13 HSLP# HPSI# SLP# D60# HD#61 VCC_70 VCC_59
31 PM_PS 1 2 E1 AF25 AF18 AE9
R292 0/NA5% PSI# D61# HD#62 VCC_71 VCC_60
AF22
a
HIGNNE# D62# HD#63
A3 AF26 BANIAS
13 HIGNNE# HSMI# IGNNE# D63# HDSTBN#[0..3]
B4 HDSTBN#[0..3] 4 BGA479_SKT3
13 HSMI# HPWRGD SMI# HDSTBN#0
E4 C23
13 HPWRGD PWRGOOD DSTBN0# HDSTBN#1
iT ial
K24
HPROCHOT# DSTBN1# HDSTBN#2
22 HPROCHOT# B17 W25
PROCHOT# DSTBN2# HDSTBN#3
AE24
DSTBN3# HDSTBP#[0..3]
HSTPCLK# HDSTBP#0 HDSTBP#[0..3] 4
C6 C22
13 HSTPCLK# HDPSLP# STPCLK# DSTBP0# HDSTBP#1
B7 L24
4,13 HDPSLP# DPSLP# DSTBP1# HDSTBP#2
W24
HINTR DSTBP2# HDSTBP#3
M t
D1 AE25
13 HINTR HNMI LINT0 DSTBP3#
D4
13 HNMI LINT1
M2 HDBSY# 4
HINIT# DBSY#
B5 H2 HDRDY# 4
13,23 HINIT# INIT# DRDY#
B11
4 HCPURST# RESET# CPU_THERMDA
B18
n
THERMDA CPU_THERMDC CPU_THERMDA 22
A18 CPU_THERMDC 22
THERMDC
A16
11 CLK_ITP_CPU ITP_CLK0
A15 C17
e
B 11 CLK_ITP_CPU# ITP_CLK1 THERMTRIP# CPU_THRMTRIP_OUT# 14 B
BANIAS
BGA479_SKT3 +3V
+VCC_CORE +VCCP
id
HCOMP0 & HCOMP2 should be
HDBR# 1 2
R246 10K/NA 0402 5% route with 18 mil width
1
f
1
1
R219 R225 R220 R229
R224 R228 R238 R243 51/NA 39 150 51/NA 1 2 HCOMP0
51 51 51 51 0402 0402 0402 0402 R133 27.4 0402 1%
n
0402 0402 0402 0402 5% 1% 1% 5% +VCCP 1 2 HCOMP1
5% 5% 5% 5% R142 54.9 0402 1%
2
HPREQ# HCOMP2
2
1 2
o
HPRDY# R291 27.4 0402 1%
HBPM#1 HA20M# 1 2 1 2 HCOMP3
HBPM#0 R294 200/NA 0402 5% R300 54.9 0402 1%
HTDO HIGNNE# 1 2
C
HTMS R265 200/NA 0402 5%
HTDI HINTR 1 2 GND
R293 200/NA 0402 5%
4 HCPURST# HNMI 1 2 1 2 CPU_TEST1
HTRST# R302 200/NA 0402 5% R255 1K/NA 0402 5%
HTCLK HSMI# 1 2 1 2 CPU_TEST2
R268 200/NA 0402 5% R143 1K/NA 0402 5%
1
R213 HSTPCLK# 1 2 1 2 CPU_TEST3

27.4 R214 R249 200/NA 0402 5% R204 1K/NA 0402 5%
0402 680 HDPSLP# 1 2
1% 0402 R247 200/NA 0402 5%
5% HSLP# 1 2 GND
R248 200/NA 0402 5%
2
HINIT# 1 2 Close to CPU as possible.

R256 200/NA 0402 5%
GND GND PLACEMENT MAX. 3" FROM CPU.

Don't overlay by CHOKE or vibrating signals.
Place close to CPU socket within 2".
A A
+1.8V +1.5V +VCCA
1 2
1
1
R124 0/NA 0805 C322 C323 C151 C161 C162 C163 C316 C317
2.2U 2.2U 2.2U 2.2U 0.1U 0.1U 0.1U 0.1U
1 2 0603 0603 0603 0603 0402 0402 0402 0402
+/-10% +/-10% +/-10% +/-10% 10% 10% 10% 10%
2
2
R123 0 0805 Title
8050D MOTHER B/D
1.8V, 0.6A, 10uF and 10nF each VCCA pin.
1.5V for future support. GND Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
CPU-BANIAS (2/2) +VCCP 1.05V, 2.4A
1
U713C C256 C257 C220 C187 C188 C189 C203
+VCCP A2 J22 10U 10U 10U 10U 10U 10U 10U
U713D VSS_0 VSS_73 0805 0805 0805 0805 0805 0805 0805
(1.05V) A5
VSS_1 VSS_74
J24
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2
D10 AB19 A8 K2
VCCP_0 VSS_146 VSS_2 VSS_75
D12 AB21 A11 K5
D14 AB23 A14 K21
VCCP_2 VSS_148 VSS_4 VSS_77 GND
D16 AB26 A17 K23
E11 AC2 A20 K26
D
E13
VCCP_5 VSS_151
AC5 A23
VSS_7 VSS_80
L3 0.844V ~ 1.356V, 32A D
E15 AC8 A26 L6 +VCC_CORE
F10 AC10 B3 L22
F12 AC12 B6 L25
F14 AC14 B9 M1
1
F16 AC16 B12 M4 C226 C209 C193 C199 C214 C230 C241
K6 AC18 B16 M5 10U 10U 10U 10U 10U 10U 10U
VCCP_11 VSS_157 VSS_13 VSS_86 0805 0805 0805 0805 0805 0805 0805
L5 AC21 B19 M21
VCCP_12 VSS_158 VSS_14 VSS_87 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2
L21 AC24 B22 M24
M6 AD1 B25 N3
M22 AD4 C1 N6
N5 AD7 C4 N22
1
N21 AD9 C7 N23 C180 C267 C250 C190
P6 AD11 C10 N26 10U 10U 10U 10U
VCCP_18 VSS_164 VSS_20 VSS_93 0805 0805 0805 0805
P22 AD13 C13 P2
VCCP_19 VSS_165 VSS_21 VSS_94 6.3V 6.3V 6.3V 6.3V
2
R5 AD15 C15 P5
R21 AD17 C18 P21
T6 AD19 C21 P24
T22 AD22 C24 R1
+VCCQ VCCP_23 VSS_169 VSS_25 VSS_98 GND
U21 AD25 D2 R4
VCCP_24 VSS_170 VSS_26 VSS_99 +VCC_CORE
AE3 D5 R6
VSS_171 VSS_27 VSS_100
P23 AE6 D7 R22
VCCQ0 VSS_172 VSS_28 VSS_101
W4 AE8 D9 R25
VCCQ1 VSS_173 VSS_29 VSS_102
1
AE10 D11 T3 C320 C321
1
F26 AE12 D13 T5 10U 10U C192 C179 C270 C279 C296
+VCCA VCCA0 VSS_175 VSS_31 VSS_104 0805 0805
B1 AE14 D15 T21 10U 10U 10U 10U 10U
VCCA1 VSS_176 VSS_32 VSS_105 6.3V 6.3V 0805 0805 0805 0805 0805
2
N1 AE16 D17 T23
VCCA2 VSS_177 VSS_33 VSS_106 6.3V 6.3V 6.3V 6.3V 6.3V
2
AC26 AE18 D19 T26
VCCA3 VSS_178 VSS_34 VSS_107
AE20 D21 U2
VID0 VSS_179 VSS_35 VSS_108
E2 AE23 D23 U6
VID1 VID0 VSS_180 VSS_36 VSS_109
F2 AE26 D26 U22
t
1
VID2 F3 AF2 E3 U24 C312 C807 C168 C173 C175 C177 C183
VID3 VID2 VSS_182 VSS_38 VSS_111
G3 AF5 E6 V1 10U 10U 10U 10U 10U 10U 10U
VID4 VID3 VSS_183 VSS_39 VSS_112 0805 0805 0805 0805 0805 0805 0805
G4 AF9 E8 V4
t
VID[0..4] 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2
H4 AF11 E10 V5
n
31 VID[0..4] VID5 VSS_185 VSS_41 VSS_114
AF13 E12 V21
CPUVID5 VSS_186 VSS_42 VSS_115
AF15 E14 V25
e e
AF17 E16 W3
VSS_188 VSS_44 VSS_117 GND +VCC_CORE
C 1 2 AE7 AF19 E18 W6 C
R885 54.9 0402 1% VCCSENSE VSS_189 +5V VSS_45 VSS_118
AF21 E20 W22
r
VSS_190 VSS_46 VSS_119 +VCC_CORE
1 2 AF6 AF24 E22 W23
R899 54.9 0402 1% VSSENSE VSS_191 VSS_47 VSS_120
E25 W26
VSS_48 VSS_121
1
BANIAS F1 Y2 C155 C156 C157 C158 C831
c m
VSS_49 VSS_122
GND BGA479_SKT3 GND 1 RP28 8 VID0 F4 Y5 10U 10U 10U 10U 10U
4.7K*4/NA 7 VID1 VSS_50 VSS_123 0805 0805 0805 0805 0805
2 F5 Y21
VSS_51 VSS_124
1
1206 6 VID2 6.3V 6.3V 6.3V 6.3V 6.3V
2
3 F7 Y24 C1004 C1005
e
VSS_52 VSS_125
4 5 VID3 F9 AA1 + 220U/NA + 220U/NA
VSS_53 VSS_126
R299 1 4.7K/NA 2 0402 VID4 F11 AA4 7343 7343
VSS_54 VSS_127
u
R298 1 4.7K/NA 2 0402 VID5 F13 AA6 4V 4V
VSS_55 VSS_128
1
S
2
F15 AA8 C264 C198 C249 C240 C254
VSS_56 VSS_129
F17 AA10 10U 10U 10U 10U 10U
VSS_57 VSS_130
c
F19 AA12 0805 0805 0805 0805 0805
VSS_58 VSS_131 6.3V 6.3V 6.3V 6.3V 6.3V
2
F21 AA14
VSS_59 VSS_132
c Do
F24 AA16 GND
VSS_60 VSS_133
G2 AA18
VSS_61 VSS_134
G6 AA20
VSS_62 VSS_135 GND
G22 AA22
a
VSS_63 VSS_136 +VCC_CORE
G23 AA25
VSS_64 VSS_137
VID VID G26
VSS_65 VSS_138
AB3
H3 AB5
VSS_66 VSS_139
5 4 3 2 1 0 VCC-Core 5 4 3 2 1 0 VCC-Core
iT ial
H5 AB7
VSS_67 VSS_140
1
H21 AB9 C186 C195 C248 C235 C222 C204 C185
VSS_68 VSS_141
0 0 0 0 0 0 1.708 1 0 0 0 0 0 1.196 H25
VSS_69 VSS_142
AB11 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
J1 AB13 0402 0402 0402 0402 0402 0402 0402
VSS_70 VSS_143 10% 10% 10% 10% 10% 10% 10%
0 0 0 0 0 1 1.692 1 0 0 0 0 1 1.180
2
J4 AB15
VSS_71 VSS_144 16V 16V 16V 16V 16V 16V 16V
J6 AB17
VSS_72 VSS_145
0 0 0 0 1 0 1.676 1 0 0 0 1 0 1.164
M t
BANIAS +VCC_CORE GND
0 0 0 0 1 1 1.660 1 0 0 0 1 1 1.148 BGA479_SKT3
0 0 0 1 0 0 1.644 1 0 0 1 0 0 1.132
1
C268 C251 C280 C191 C178 C236 C200
0 0 0 1 0 1 1.628 1 0 0 1 0 1 1.116 GND 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
n
0402 0402 0402 0402 0402 0402 0402
0 0 0 1 1 0 1.612 1 0 0 1 1 0 1.100 10% 10% 10% 10% 10% 10% 10%
2
16V 16V 16V 16V 16V 16V 16V
e
B B
0 0 0 1 1 1 1.596 1 0 0 1 1 1 1.084
+VCCP GND
0 0 1 0 0 0 1.580 1 0 1 0 0 0 1.068
id
0 0 1 0 0 1 1.564 1 0 1 0 0 1 1.052
1
R193 1 0 2 C319 C318 C181 C266 C259 C182 C242 C194 C196
0 0 1 0 1 0 1.548 1 0 1 0 1 0 1.036 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
f
Q16 0402 0402 0402 0402 0402 0402 0402 0402 0402
0 0 1 0 1 1 1.532 1 0 1 0 1 1 1.020 10% 10% 10% 10% 10% 10% 10% 10% 10%
2
2N7002/NA 16V 16V 16V 16V 16V 16V 16V 16V 16V
VID5
S
D
CPUVID5 S D VID5 31
0 0 1 1 0 0 1.516 1 0 1 1 0 0 1.004
n
GND
0 0 1 1 0 1 1.500 1 0 1 1 0 1 0.988
2
G
o
0 0 1 1 1 0 1.484 1 0 1 1 1 0 0.972 +1.5V
13,24 B/CB#
R400
+VCCP
0 0 1 1 1 1 1.468 1 0 1 1 1 1 0.956 10K/NA +VCCP +VCCQ
2
0402 L41
1
0 1 0 0 0 0 1.452 1 1 0 0 0 0 0.940 R401 Q28 5% C768
1
1 2
1
+ 150U C231 C258
SI2301DS/NA
1
0 1 0 0 0 1 1.436 1 1 0 0 0 1 0.924 1K/NA 120Z/100M C237 C201 C265 7343 10U 10U
0402 D14 GND 2012 6.3V 0805 0805
10U 0.1U 0.1U
5% 6.3V 6.3V
S
D
0 1 0 0 1 0 1.420 1 1 0 0 1 0 0.908 0805 0402 0402

D 1
2
1 3 S D
6.3V 10% 10%
2
0 1 0 0 1 1 1.404 1 1 0 0 1 1 0.892 16V 16V
G
D Q45 BAT54/NA
G
0 1 0 1 0 0 1.388 1 1 0 1 0 0 0.876 11,13,31 STOP_CPU# G S GND

2N7002/NA GND
S
0 1 0 1 0 1 1.372 1 1 0 1 0 1 0.860
0 1 0 1 1 0 1.356 1 1 0 1 1 0 0.844
GND
0 1 0 1 1 1 1.340 1 1 0 1 1 1 0.828
1 0
0 1 1 0 0 0 1.324 1 1 1 0 0 0 0.812
0 1 1 0 0 1 1.308 1 1 1 0 0 1 0.796 B/CB# Banias Celeron
A A
0 1 1 0 1 0 1.292 1 1 1 0 1 0 0.780 GPIO16 CPU Banias CPU
0 1 1 0 1 1 1.276 1 1 1 0 1 1 0.764
power on default = 1
0 1 1 1 0 0 1.260 1 1 1 1 0 0 0.748
0 1 1 1 0 1 1.244 1 1 1 1 0 1 0.732
0 1 1 1 1 0 1.228 1 1 1 1 1 0 0.716 POWER CONSUMPTION SAVING CIRCUIT
0 1 1 1 1 1 1.212 1 1 1 1 1 1 0.700
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
NB-MONTARA-GME(1/2) AGPBUS
AGP_AD[0..31]
855_DVOBHSYNC AGP_AD0 AGP_AD[0..31] 7,24
U714A 855_DVOBVSYNC AGP_AD1
HA#[3..31] U714B HD#[0..63] 855_ADDID0 E5 P3 855_DVOBCLK 855_DVOBD1 AGP_AD2
2 HA#[3..31] HA#3 HD#0 HD#[0..63] 2 855_ADDID1 ADDID[0] DVOBCLK 855_DVOBCLK# 855_DVOBD0 AGP_AD3 855_DVODETECT
P23 K22 F5 P4 AGP_PAR 7
HA#4 HA[3]# HD[0]# HD#1 855_ADDID2 ADDID[1] DVOBCLK# 855_DVOBD3 AGP_AD4 855_MDDCCLK
T25 H27 E3 AGP_STOP# 7
HA#5 HA[4]# HD[1]# HD#2 855_ADDID3 ADDID[2] 855_DVOBD0 855_DVOBD2 AGP_AD5 855_MI2CDATA
HA#6
T28
HA[5]# HD[2]#
K25
HD#3
CHECK 855_ADDID4
E2
ADDID[3] DVOBD[0]
R3
855_DVOBD1 855_DVOBD5 AGP_AD6 855_MDVICLK AGP_DEVSEL# 7
R27 L24 G5 R5 AGP_TRDY# 7
HA#7 HA[6]# HD[3]# HD#4 855_ADDID5 ADDID[4] DVOBD[1] 855_DVOBD2 855_DVOBD4 AGP_AD7 855_MI2CCLK
U23 J27 F4 R6 AGP_IRDY# 7
HA#8 HA[7]# HD[4]# HD#5 +1.5V 855_ADDID6 ADDID[5] DVOBD[2] 855_DVOBD3 855_DVOBD6 AGP_AD8 855_MDVIDATA
U24 G28 G6 R4 AGP_FRAME# 7
D
HA#9 HA[8]# HD[5]# HD#6 855_ADDID7 ADDID[6] DVOBD[3] 855_DVOBD4 855_DVOBD9 AGP_AD9 855_DVOBCLK D
R24 L27 F6 P6 AGP_ADSTB0 7
HA#10 HA[9]# HD[6]# HD#7 ADDID[7] DVOBD[4] 855_DVOBD5 855_DVOBD8 AGP_AD10 855_DVOCCLK
U28 L23 P5 AGP_ADSTB1 7
HA[10]# HD[7]# DVOBD[5]
1
HA#11 V28 L25 HD#8 F7 N5 855_DVOBD6 855_DVOBD11 AGP_AD11 855_DVOBCLK#
HA#12 HA[11]# HD[8]# HD#9 7,13,24 AGPBUSY# AGPBUSY# DVOBD[6] 855_DVOBD7 855_DVOBD10 AGP_AD12 855_DVOCCLK# AGP_ADSTB0# 7
U27 J24 R155 AE29 P2
HA#13 HA[12]# HD[9]# HD#10 1K 11 HCLK_MCH BCLK DVOBD[7] 855_DVOBD8 855_DVOBCCLKINT AGP_AD13 855_DVOBD7 AGP_ADSTB1# 7
T27 H25 11 HCLK_MCH# AD29 N2 AGP_CBE#0 7
HA#14 HA[13]# HD[10]# HD#11 0402 855_DPMS D5 BCLK# DVOBD[8] 855_DVOBD9 855_DVOBFLDSTL AGP_AD14 855_DVOBBLANK#
V27 K23 N3 AGP_CBE#1 7
HA#15 HA[14]# HD[11]# HD#12 5% DPMS DVOBD[9] 855_DVOBD10 855_MDDCCDATA AGP_AD15
U25 G27 2,13 HDPSLP# Y23 M1 5,7 GCBE2# AGP_CBE#2 5,7
HA#16 HA[15]# HD[12]# HD#13 DPSLP# DVOBD[10]
1 0/NA 2 855_DPMS 855_DVOBD11 855_DVOCVSYNC AGP_AD16
D 2
V26 K26 2 HDPWR# AA22 M5
HA#17 HA[16]# HD[13]# HD#14 R156 0402 DPWR# DVOBD[11] 855_DVOCHSYNC AGP_AD17 855_DVOCD5
Y24 J23 11 48M_DREFCLK B7 AGP_CBE#3 7
HA#18 HA[17]# HD[14]# HD#15 DREFCLK 855_DVOBCCLKINT 855_DVOCBLANK# AGP_AD18 855_ADDID0
V25 H26 M3 AGP_SBA0 7
HA#19 HA[18]# HD[15]# HD#16 D Q15 DVOBCCLKINT 855_DVOBCINTR# 855_DVOCD0 AGP_AD19 855_ADDID1
V23 F25 G2 AGP_SBA1 7
HA#20 HA[19]# HD[16]# HD#17 2N7002 IYAM0 DVOBCINTR# 855_DVOBFLDSTL 855_DVOCD1 AGP_AD20 855_ADDID2
W25 F26 13 SUSCLK G S G14 M2 1 R857 2 GND AGP_SBA2 7
HA#21 HA[20]# HD[17]# HD#18 IYAM1 IYAM[0] DVOBFLDSTL 855_DVOBBLANK# 100K 0402 855_DVOCD2 AGP_AD21 855_ADDID3
Y25 B27 E15 L2 AGP_SBA3 7
HA#22 HA[21]# HD[18]# HD#19 IYAM2 IYAM[1] DVOBBLANK# 855_DVOCD3 AGP_AD22 855_ADDID4
S
AA27 H23 C15 AGP_SBA4 7
HA#23 HA[22]# HD[19]# HD#20 IYAM3 IYAM[2] 855_DVOBHSYNC 855_DVOCD4 AGP_AD23 855_ADDID5
W24 E27 C13 T6 AGP_SBA5 7
HA#24 HA[23]# HD[20]# HD#21 GND IYAP0 IYAM[3] DVOBHSYNC 855_DVOBVSYNC 855_DVOCD7 AGP_AD24 855_ADDID6
W23 G25 F14 T5 AGP_SBA6 7
HA#25 HA[24]# HD[21]# HD#22 IYAP1 IYAP[0] DVOBVSYNC 855_DVOCD6 AGP_AD25 855_ADDID7
W27 F28 E14 AGP_SBA7 7
HA#26 HA[25]# HD[22]# HD#23 IYAP2 IYAP[1] 855_DVOCD9 AGP_AD26
Y27 D27 C14
HA#27 HA[26]# HD[23]# HD#24 IYAP3 IYAP[2] 855_DVOCCLK 855_DVOCD8 AGP_AD27
AA28 G24 B13 J3 5,7 GSBSTB# AGP_SBSTBS 5,7
HA#28 HA[27]# HD24]# HD#25 TP38 IYBM0 IYAP[3] DVOCCLK 855_DVOCCLK# 855_DVOCD11 AGP_AD28
W28 C28 1 H12 J2 5,7 GSBSTB AGP_SBSTBF 5,7
HA#29 HA[28]# HD[25]# HD#26 TP26 IYBM1 IYBM[0] DVOCCLK# 855_DVOCD10 AGP_AD29
AB27 B26 1 E12 5,7 GWBF# AGP_WBF# 5,7
HA#30 HA[29]# HD[26]# HD#27 TP21 IYBM2 IYBM[1] 855_DVOCD0 855_DVOBCINTR# AGP_AD30
Y26 G22 1 C12 K5 5,7 GRBF# AGP_RBF# 5,7
HA#31 HA[30]# HD[27]# HD#28 TP32 IYBM3 IYBM[2] DVOCD[0] 855_DVOCD1 855_DVOCFLDSTL AGP_AD31
AB28 C26 1 G11 K1 5,7 GST0 AGP_ST0 5,7
HREQ#[0..4] HA[31]# HD[28]# HD#29 TP31 IYBP0 IYBM[3] DVOCD[1] 855_DVOCD2
E26 1 G12 K3
2 HREQ#[0..4] HREQ#0 R28
HD[29]#
G23 HD#30 TP22 1 IYBP1 E11
IYBP[0] DVOCD[2]
K2 855_DVOCD3 WHEN USE INTEGRATE VGA 5,7 GST1 AGP_ST1 5,7
HREQ[0]# HD[30]# IYBP[1] DVOCD[3] 5,7 GST2 AGP_ST2 5,7
HREQ#1
HREQ#2
P25
HREQ[1]# HD[31]#
B28 HD#31
HD#32
TP20 1 IYBP2
IYBP3
C11
IYBP[2] DVOCD[4]
J6 855_DVOCD4
855_DVOCD5
ADD R798 DEL R857 R1104 5,7 GGNT# AGP_GNT# 5,7
R23 B21 TP36 1 G10 J5
HREQ#3 HREQ[2]# HD[32]# HD#33 IYBP[3] DVOCD[5] 855_DVOCD6 5,7 GREQ# AGP_REQ# 5,7
R25 G21 H2
HREQ#4 HREQ[3]# HD[33]# HD#34 ICLKAM D14 DVOCD[6] 855_DVOCD7
T23 C24 H1
HREQ[4]# HD[34]# HD#35 ICLKAP ICLKAM DVOCD[7] 855_DVOCD8
T26 C23 E13 H3
t
2 HADSTB#0 HADSTB[0]# HD[35]# HD#36 ICLKAP DVOCD[8]
AA26 D22 TP27 1 ICLKBM E10 H4 855_DVOCD9
2 HADSTB#1 HADSTB[1]# HD[36]# HD#37 ICLKBM DVOCD[9]
C25 TP30 1 ICLKBP F10 H6 855_DVOCD10
HD[37]# HD#38 0402 ICLKBP DVOCD[10] 855_DVOCD11 855_MDDCCLK 04021 R235
E24 G3 2 10K +1.5V
HD[38]# DVOCD[11]
t
HXRCOMP B20 D24 HD#39 1 R166 2 D6 855_MDDCCDATA 04021 R236 2 10K
n
HXSWING HXRCOMP HD[39]# HD#40 +3V EXTTS_0 855_DVODETECT 855_MDVICLK
B18 G20 10K 5%Y3 L7 R832 04021 R227 2 10K
HXSWING HD[40]# HD#41 11 66M_MCH DVOVREF GCLKIN DVODETECT 855_MDVIDATA +1.5V
HYRCOMP H28 E23 F1 D1 0402 1 40.2 2 04021 R226 2 10K
HYRCOMP HD[41]# 11 DVOVREF GVREF DVORCOMP GND
e e
HYSWING K28 B22 HD#42 R835 1 0/NA 2 H5 855_DVOCFLDSTL
HYSWING HD[42]# HD#43 7 AGP_VREF DVOCFLDSTL 855_DVOCBLANK# 855_MI2CDATA
C B23 0402 5% L3 0402 1 R1103 2 10K +1.5V C
HDSTBP#[0..3] HD[43]# HD#44 HUB_HI[0..10] DVOCBLANK#
F23
r
HD[44]#
1
2 HDSTBP#[0..3] HDSTBP#0 HD#45 14 HUB_HI[0..10] HUB_HI0 855_DVOCHSYNC 855_MI2CCLK 0402 1 R216
K27 F21 U7 K6 2 10K +1.5V
HDSTBP#1 HDSTBP[0]# HD[45]# HD#46 HUB_HI1 HL[0] DVOCHSYNC 855_DVOCVSYNC R1104
D26 C20 U4 L5
HDSTBP#2 HDSTBP[1]# HD[46]# HD#47 HUB_HI2 HL[1] DVOCVSYNC 100K
E21 C21 U3
c m
HDSTBP#3 HDSTBP[2]# HD[47]# HD#48 HUB_HI3 HL[2] 0402
E18 G18 V3
HDSTBN#[0..3] HDSTBP[3]# HD[48]# HD#49 HUB_HI4 HL[3] 04021 R210 5%
E19 W2 H9 2 10K/NA +3V
2 HDSTBN#[0..3] HDSTBN#0 HD[49]# HD#50 HUB_HI5 HL[4] LCLKCTLA 04021 R799 2 10K/NA
2
J28 E20 W6 C6
WHEN USE INTEGRATE VGA
e
HDSTBN#1 HDSTBN[0]# HD[50]# HD#51 HUB_HI6 HL[5] LCLKCTLB
C27 G17 V6
HDSTBN[1]# HD[51]# HL[6]
HDSTBN#2 E22
HDSTBN[2]# HD[52]#
D20 HD#52 HUB_HI7 W7
HL[7] LIBG
A10 R798 1 1.5K/NA 2 GND
GND DEL R206
u
HDSTBN#3 D18 F19 HD#53 HUB_HI8 T3 0402 5%
HDSTBN[3]# HD[53]# HL[8]
S
HDINV#[0..3] C19 HD#54 HUB_HI9 V5 R206
2 HDINV#[0..3] HDINV#0 HD[54]# HD#55 HUB_HI10 HL[9] 855_MDDCCLK 855_DVODETECT
J25 C17 V4 P7 1 2 +1.5V
DINV[0]# HD[55]# HL[10] MDDCCLK
c
HDINV#1 E25 F17 HD#56 T7 855_MDDCCDATA 1K
HDINV#2 DINV[1]# HD[56]# HD#57 +VCCP MDDCDATA 855_MDVICLK 0402
B25 B19 W3 N7
DINV[2]# HD[57]# 14 HUB_STB HLSTB MDVICLK
c Do
HDINV#3 G19 G16 HD#58 V2 M6 855_MDVIDATA 5%
DINV[3]# HD[58]# HD#59 14 HUB_STB# HLSTB# MDVIDATA 855_MI2CCLK
E16 K7
HD[59]# HD#60
1
HUB_MCH_VREF MI2CCLK 855_MI2CDATA
L28 C16 W1 N6
2 HADS# ADS# HD[60]# HD#61 R209 HUB_RCOMP HLVREF MI2CDATA
M25 E17 T2
a
2 HTRDY# HTRDY# HD[61]# HD#62 49.9 HLRCOMP
N24 D16
2 HDRDY#
M28
DRDY# HD[62]#
C18 HD#63 0402 G8 R202 1 0402 2 0/NA
2 HDEFER# DEFER# HD[63]# PANELBKLTCTL BLADJ 12,22
2 HHITM#
N28
HITM# HDVREF
1%
13 MCH_PCIRST# REFSET
AD28
RSTIN# PANELBKLTEN
F8 R203 1 0402 2 0/NA ENABKL_NB 12
+1.5V ADD R181
R801 1 0402 2 0/NA
2
iT ial
N27 K21 E8 A5 FPVDEN 12
2 HHIT# HIT# HDVREF[0] REFSET PANELVDDEN
P27 J21
HLOCK# HDVREF[1]
1
2 HLOCK# MCH_PSWING R279 8.2K/NA 855_ADDID0

M23 J17 U2 1R175 04022 330/NA 1 R174 2 0402
BREQ0# HDVREF[2] PSWING
1
2 HBR0# R208 855_DDDA RCVENIN# 1 0402 855_ADDID1

N25 C215 C217 C216 G9 AC16 2 0/NA 8.2K/NA 1R177 04022 330/NA 1 R176 2 0402
2 HBNR# BNR# 100 855_DDCK DDCADATA RCVENIN# RCVENOUT# 8.2K/NA 855_ADDID2
P28 0.1U 0.1U 0.1U B6 AC15 1R170 04022 330/NA 1 R169 2 0402
2 HBPRI# BPRI# 0402 0402 0402 0402 R790 1 10K DDCACLK RCVENOUT# 855_ADDID3
M26 +3V 2 0402 B4 8.2K/NA 1R168 04022 330/NA 1 R167 2 0402
2 HDBSY# HRS#0 DBSY# HAVREF +80-20% +80-20% +80-20% 1% R800 1 10K DDCPCLK 855_ADDID4
2 0402 C5 8.2K/NA 1R184 04022 330/NA R183 0402
2
N23 Y22 1 2
HRS#[0..2] HRS#1 RS[0]# HAVREF HCCVREF 50V 50V 50V DDCPDATA 855_ADDID5
M t
8.2K/NA 1R172 04022 330/NA R171 0402
2
P26 Y28 1 2
2 HRS#[0..2] HRS#2 RS[1]# HCCVREF +1.5V 8.2K/NA 855_ADDID6
M27 1R189 04022 330/NA 1 R188 2 0402
RS[2]# 855_RED 8.2K/NA 855_ADDID7
F15 A7 AJ29 1R182 04022 1K/NA 1 R181 2 0402
2 HCPURST# CPURST# RED NC_0
1 0402 2 0 J11 GND A8 AH29
PWROK RED# NC_1
1
12,13,17,25,31 PWROK R217 Maximum length less than 855_GREEN C8 B29
GEEN NC_2 R59 GND
D8 A29
n
855GM/GME 0.5" from pin to voltage GREEN# NC_3
BGA707_25 855_BLUE C9 AJ28 1K ADD ID : 0x7Fh
divider. BLUE NC_4 0402
D9
BLUE# NC_5
A28 RDDP recommend
AA9 5%
e
B NC_6 1K ohm DVOVREF
B
2
AJ4
855_HSYNC
855_VSYNC
H10
J9
HSYNC
NC_7
NC_8
AJ2
A2
resistor M10-P CONNECT TO NB
VSYNC NC_9
1
+1.35V AH1
id
R789 1 0402 2 0 B17
NC_10
B1 R64 WHEN USE INTEGRATE VGA
R898 11 66M_DEFSSCLK DREFSSCLK NC_11
HUB_RCOMP
HXRCOMP & HYRCOMP should be +1.35V
W/ SSC 1K
0402
DEL ALL RESISTOR
1 2 855GM/GME
route with 18 mil width
f
GND BGA707_25 5% IYAM0 R349 1 0/NA 2 0402 R153 1 0 2 0402
855_DDDA TXOUT0-_ATI 7
855_CRT_DDDA R331 1 0/NA 2 0402 IYAP0 R350 1 0/NA 0402 R154 0 0402
2
2 1 2 TXOUT0+_ATI 7
1
37.4 CHANGE TO 0402 CHANGE TO 0402 12 855_CRT_DDDA 855_CRT_DDCK R1166 1 0/NA 855_DDCK
2 0402 IYAM1 R353 1 0/NA 2 0402 R158 1 0 2 0402
TXOUT1-_ATI 7
0603 Less than 0.5" R914 12 855_CRT_DDCK 855_CRT_RED R1167 1 0/NA 855_RED
12 855_CRT_RED 2 0402 IYAP1 R357 1 0/NA 2 0402 R159 1 0 2 0402
TXOUT1+_ATI 7
n
1% 287 855_CRT_GREEN R343 1 0/NA 2 0402 855_GREEN GND IYAM2 R1176 1 0/NA 2 0402 R794 1 0 2 0402
0603 12 855_CRT_GREEN 855_CRT_BLUE TXOUT2-_ATI 7
12 855_CRT_BLUE
R344 1 0/NA 2 0402 855_BLUE IYAP2 R1177 1 0/NA 2 0402 R795 1 0 2 0402
TXOUT2+_ATI 7
Place near to GMCH. 1% IYAM3 R1178 1 0/NA 2 0402 R796 1 0 2 0402
TXOUT3-_ATI 7
1
o
HXRCOMP 1/10W HUB_MCH_VREF IYAP3 R1179 1 0/NA 0402 R797 0 0402
2
1 2 2 1 2 TXOUT3+_ATI 7
R792 27.4 R784 R145 R144
TXOUT0- 12
1
DVOVREF CHANGE TO 0402 C775 C170 C169 75/NA 75/NA 75/NA

TXOUT0+ 12
1
R918 C844 C843 33P/NA 33P/NA 33P/NA 0402 0402 0402
C
TXOUT1- 12
1
C810 1 2 HYRCOMP 100 0.1U 0.01U/NA 0402 0402 0402 1% 1% 1%

0402 +/-10% +/-10% +/-10% TXOUT1+ 12
R839 27.4 0402 0402
2
0.1U
0402 1% +80-20% +80-20% 25V 25V 25V NB CONNECT TO TV ENCORDER TXOUT2- 12
2
+80-20% CHANGE TO 0402 50V 50V TXOUT2+ 12

2
50V
Non SSC TXOUT3- 12
TXOUT3+ 12
GND GND 0402GND GND
GND 855_CRT_HSYNC R345 1 0/NA 2 855_HSYNC
12 855_CRT_HSYNC 855_CRT_VSYNC R348 1 0/NA 2 855_VSYNC +1.35V WHEN USE INTEGRATE VGA
12 855_CRT_VSYNC 0402 ADD ALL RESISTOR R361 1 0/NA 2 0402 ICLKAM
R363 1 0/NA 2 0402 ICLKAP
1
Maximum length less than 0.5" from pin to Less than 0.5" R903 855_DVOCCLK R114 1 0/NA 2 0402 R160 1 0 2 0402
68.1 855_DVOCCLK# DVOCCLK 11 TXCLK-_ATI 7
voltage divider. R128 1 0/NA 2 0402 R161 1 0 2 0402
0603 855_DVOBCCLKINT DVOCCLK# 11 TXCLK+_ATI 7
R147 1 0/NA 2 0402
1% 855_DVOBCINTR# POUT/DET# 11
R117 1 0/NA 2 0402
+VCCP (1.05V) +VCCP +VCCP +VCCP MCH_PSWING 855_MI2CCLK DVOBCINTR# 11
R162 0/NA 0402
2
1 2 MI2CCLK 11 TXCLK- 12
855_MI2CDATA R113 1 0/NA 2 0402
MI2CDATA 11 TXCLK+ 12
1
855_DVOCFLDSTL R150 1 0/NA 2 0402

DVOCFLDSTL 11
1
C836 C837 R910 855_DVOCHSYNC R125 1 0/NA 2 0402

100 855_DVOCVSYNC DVOCHSYNC 11
A R258 R902 R793 R855 0.1U 1U/NA R157 1 0/NA 2 0402 A
49.9 49.9 301 301 0402 DVOCVSYNC 11
0402 0402
0402 0402 0402 0402 +80-20% +80-20% 1% 855_DVOCD0 R146 0/NA 0402DVOCD0
2
1 2
1% 1% 1% 1% 50V 10V 855_DVOCD1 R111 0/NA 0402DVOCD1 DVOCD[0..11]
2
1 2 DVOCD[0..11] 11
HAVREF HCCVREF HXSWING HYSWING 855_DVOCD2 R112 0/NA 0402DVOCD2
2
1 2
855_DVOCD3 R126 1 0/NA 2 0402DVOCD3
1
GND 855_DVOCD4 R127 1 0/NA 2 0402DVOCD4

1
C287 C286 R257 C840 C842 R913 C784 R791 C815 R850 855_DVOCD5 R148 1 0/NA 2 0402DVOCD5
0.1U 1U/NA 100 0.1U 1U 100 0.1U 150 0.1U 150 855_DVOCD6 R129 1 0/NA 2 0402DVOCD6
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 REFSET 1 127 1% 2 R163 855_DVOCD7 R149 1 0/NA 2 0402DVOCD7
+80-20% +80-20% 1% +80-20% +80-20% 1% +80-20% 1% +80-20% 1% 855_DVOCD8 R130 0/NA 0402DVOCD8
2
1 2
50V 10V 50V 10V 50V 50V 855_DVOCD9 R115 0/NA 0402DVOCD9
2
1 2
855_DVOCD10 R131 1 0/NA 2 0402DVOCD10 Title
855_DVOCD11 R116 1 0/NA 2 0402DVOCD11 8050D MOTHER B/D
GND GND GND GND GND
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
6 NB_MA0
6 NB_MA3
NB_MA0
NB_MA3
NB_MONTARA-GME(2/2) +1.35V +2.5VS_DDR
U714D U714E
U714C NB_MD[0..63] W21 AG29 AA29 P16
NB_MA0 NB_MD0 NB_MD[0..63] 6 VCC_0 VCCSM_0 VSS_0 VSS_91
AC18 AF2 AA19 AF29 W29 J16
SMA[0] SDQ[0] VCC_1 VCCSM_1 VSS_1 VSS_92
1
SMA[1..2] SMA1 AD14 AE3 NB_MD1 C243 C282 C293 AA17 AC29 C290 C302 C325 U29 F16
6 SMA[1..2] SMA2 SMA[1] SDQ[1] NB_MD2 VCC_2 VCCSM_2 VSS_2 VSS_93
AD13 AF4 10U 0.1U 0.1U T17 AF27 0.1U 0.1U 10U N29 AG15
NB_MA3 SMA[2] SDQ[2] NB_MD3 0805 0402 0402 VCC_3 VCCSM_3 0402 0402 0805 VSS_3 VSS_94
AD17 AH2 P17 AJ25 L29 AB15
SMA[4..5] SMA4 SMA[3] SDQ[3] NB_MD4 6.3V +80-20% +80-20% VCC_4 VCCSM_4 +80-20% +80-20% 6.3V VSS_4 VSS_95
2
AD11 AD3 U16 AF24 J29 U15
6 SMA[4..5] SMA5 SMA[4] SDQ[4] NB_MD5 10% 50V 50V VCC_5 VCCSM_5 50V 50V 10% VSS_5 VSS_96
AC13 AE2 R16 AB22 G29 R15
NB_MA6 SMA[5] SDQ[5] NB_MD6 VCC_6 VCCSM_6 VSS_6 VSS_97
AD8 AG4 N16 AJ21 E29 N15
6 NB_MA6 NB_MA7 SMA[6] SDQ[6] NB_MD7 VCC_7 VCCSM_7 VSS_7 VSS_98
AD7 AH3 AA15 AF21 GND C29 H15
1
6 NB_MA7 NB_MA8 NB_MD8
AC6 AD6 C288 C218 C255 C273 T15 AB20 AE28 D15
6 NB_MA8 NB_MA9 SMA[8] SDQ[8] NB_MD9 VCC_9 VCCSM_9 VSS_9 VSS_100
AC5 AG5 0.1U 0.1U 0.1U 0.1U P15 AF18 AC28 AC14
1
D 6 NB_MA9 NB_MA10 NB_MD10 0402 0402 0402 0402
D
AC19 AG7 J15 AB18 C309 C301 C324 E28 AA14
6 NB_MA10 NB_MA11 SMA[10] SDQ[10] NB_MD11 +80-20% +80-20% +80-20% +80-20% VCC_11 VCCSM_11 VSS_11 VSS_102
2
AD5 AE8 U14 AJ17 0.1U 0.1U 10U D28 T14
6 NB_MA11 NB_MA12 SMA[11] SDQ[11] NB_MD12 50V 50V 50V 50V VCC_12 VCCSM_12 0402 0402 0805 VSS_12 VSS_103
AB5 AF5 R14 AB16 AJ27 P14
6 NB_MA12 SMAB[1..2] SMA[12] SDQ[12] NB_MD13 VCC_13 VCCSM_13 +80-20% +80-20% 6.3V VSS_13 VSS_104
2
AH4 N14 AF15 AG27 J14
6 SMAB[1..2] SMAB1 SDQ[13] NB_MD14 GND VCC_14 VCCSM_14 50V 50V 10% VSS_14 VSS_105
AD16 AF7 H14 AB14 AC27 AE13
SMAB[4..5] SMAB2 SMAB[1] SDQ[14] NB_MD15 VCC_15 VCCSM_15 VSS_15 VSS_106
AC12 AH6 T13 AJ13 F27 AB13
6 SMAB[4..5] SMAB4 SMAB[2] SDQ[15] NB_MD16 VCC_16 VCCSM_16 VSS_16 VSS_107
AF11 AF8 P13 AA13 GND A27 U13
SMAB5 SMAB[4] SDQ[16] NB_MD17 VCC_17 VCCSM_17 VSS_17 VSS_108
AD10 AG8 AF12 AJ26 R13
SMAB[5] SDQ[17] NB_MD18 VCCSM_18 VSS_18 VSS_109
AH9 +1.35V V9 AB12 AB26 N13
SDQ[18] VCCHL_0 VCCSM_19 VSS_19 VSS_110
1
AD25 AG10 NB_MD19 W8 AA11 C303 C299 C281 W26 H13
SWE# SDQ[19] VCCHL_1 VCCSM_20 VSS_20 VSS_111
1
6 NB_WE# NB_MD20
AC24 AH7 C272 C247 C276 U8 AB10 0.1U 0.1U 10U R26 F13
6 NB_CAS# SCAS# SDQ[20] NB_MD21 VCCHL_2 VCCSM_21 0402 0402 0805 VSS_21 VSS_112
AC21 AD9 10U 0.1U 0.1U V7 AJ9 N26 D13
6 NB_RAS# SRAS# SDQ[21] NB_MD22 0805 0402 0402 VCCHL_3 VCCSM_22 +80-20% +80-20% 6.3V VSS_22 VSS_113
2
AF10 U6 AF9 L26 A13
SDQ[22] NB_MD23 6.3V +80-20% +80-20% VCCHL_4 VCCSM_23 50V 50V 10% VSS_23 VSS_114
2
AD22 AE11 W5 Y9 J26 AJ12
6 NB_BA0 SBA[0] SDQ[23] NB_MD24 10% 50V 50V VCCHL_5 VCCSM_24 VSS_24 VSS_115
AD20 AH10 Y1 AB8 G26 AG12
6 NB_BA1 SBA[1] SDQ[24] NB_MD25 VCCHL_6 VCCSM_25 VSS_25 VSS_116
AH11 V1 AA8 GND AE25 AA12
SDQ[25] NB_MD26 GND VCCHL_7 VCCSM_26 VSS_26 VSS_117
AD23 AG13 Y7 AA25 J12
6 CS#0 SCS[0]# SDQ[26] NB_MD27 VCCSM_27 VSS_27 VSS_118
AD26 AF14 +1.5V P9 AF6 D25 AJ11
SCS[1]# SDQ[27] VCCDVO_0 VCCSM_28 VSS_28 VSS_119
1
6 CS#1 NB_MD28
AC22 AG11 M9 AB6 C291 C300 C314 A25 AC11
SCS[2]# SDQ[28] VCCDVO_1 VCCSM_29 VSS_29 VSS_120
1
6 CS#2 NB_MD29
AC25 AD12 C234 C232 C205 K9 AA6 0.1U 0.1U 10U AG24 AB11
6 CS#3 SCS[3]# SDQ[29] NB_MD30 VCCDVO_2 VCCSM_30 0402 0402 0805 VSS_30 VSS_121
AF13 10U 0.1U 0.1U R8 AJ5 AA24 H11
SDQ[30] NB_MD31 0805 0402 0402 VCCDVO_3 VCCSM_31 +80-20% +80-20% 6.3V VSS_31 VSS_122
2
AC7 AH13 N8 Y4 V24 F11
6 CKE0 SCKE[0] SDQ[31] NB_MD32 6.3V +80-20% +80-20% VCCDVO_4 VCCSM_32 50V 50V 10% VSS_32 VSS_123
2
AB7 AH16 M8 AF3 T24 D11
6 CKE1 SCKE[1] SDQ[32] NB_MD33 10% 50V 50V VCCDVO_5 VCCSM_33 VSS_33 VSS_124
AC9 AG17 L8 AB3 P24 AJ10
6 CKE2 SCKE[2] SDQ[33] NB_MD34 VCCDVO_6 VCCSM_34 VSS_34 VSS_126
AC10 AF19 J8 AG1 GND M24 AE10
6 CKE3 SCKE[3] SDQ[34] NB_MD35 VCCDVO_7 VCCSM_35 VSS_35 VSS_125
AE20 GND H7 AC1 K24 AA10
SDQ[35] NB_MD36 VCCDVO_8 VCCSM_36 VSS_36 VSS_127
AD18 E6 H24 C10
SDQ[36] NB_MD37 VCCDVO_9 VSS_37 VSS_128
6 NB_CLK_DDR0 AB2 AE18 M4 F24 AG9
SCK[0] SDQ[37] NB_MD38 VCCDVO_10 VCCTXLVDS VSS_38 VSS_129
6 NB_CLK_DDR0# AA2 AH18 J4 A12 B24 AB9
SCK[0]# SDQ[38] NB_MD39 VCCDVO_11 VCCTXLVDS_0 VSS_39 VSS_130
AC26 AG19 E4 D10 AJ23 W9
t
6 NB_CLK_DDR1 SCK[1] SDQ[39] NB_MD40 VCCDVO_12 VCCTXLVDS_1 VSS_40 VSS_131
6 NB_CLK_DDR1# AB25 AH20 N1 B10 AC23 U9
SCK[1]# SDQ[40] NB_MD41 VCCDVO_13 VCCTXLVDS_2 VSS_41 VSS_132
6 NB_CLK_DDR2 AC3 AG20 +1.5V J1 F9 AA23 T9
SCK[2] SDQ[41] NB_MD42 VCCDVO_14 VCCTXLVDS_3 VSS_42 VSS_133
6 NB_CLK_DDR2# AD4 AF22 E1 D23 R9
SCK[2]# SDQ[42] VCCDVO_15 VSS_43 VSS_134
1
t
AC2 AH22 NB_MD43 C263 C184 C197 A23 N9
n
6 NB_CLK_DDR3 SCK[3] SDQ[43] NB_MD44 VSS_44 VSS_135
AD2 AF20 10U 0.1U 0.1U B15 V29 VTTHF_0 AE22 L9
6 NB_CLK_DDR3# SCK[3]# SDQ[44] NB_MD45 VCCDLVDS_0 VTTHF_0 VSS_45 VSS_136
AB23 AH19 0805 0402 0402 B14 M29 VTTHF_1 W22 E9
6 NB_CLK_DDR4 SCK[4] SDQ[45] VCCDLVDS_1 VTTHF_1 VSS_46 VSS_137
e e
NB_MD46 6.3V +80-20% +80-20% VTTHF_2
2
6 NB_CLK_DDR4# AB24 AH21 J13 H29 U22 AC8
SCK[4]# SDQ[46] NB_MD47 10% 50V 50V VCCDLVDS_2 VTTHF_2 VTTHF_3 VSS_47 VSS_138
C
6 NB_CLK_DDR5 AA3 AG22 G13 A24 R22 Y8 C
SCK[5] SDQ[47] NB_MD48 VCCDLVDS_3 VTTHF_3 VTTHF_4 VSS_48 VSS_139
6 NB_CLK_DDR5# AB4 AE23 A22 N22 V8
r
SCK[5]# SDQ[48] NB_MD49 VTTHF_4 VSS_49 VSS_140
AH23 GND B9 L22 T8
MCH_SMVSWINGH SDQ[49] NB_MD50 VCCADAC VCCADAC_0 VSS_50 VSS_141
AJ19 AE24 A9 AB29 J22 P8
MCH_SMVSWINGL SMVSWINGH SDQ[50] NB_MD51 VCCADAC_1 VTTLF_0 VSS_51 VSS_142
AJ22 AH25 Y29 F22 K8
c m
+1.25V_DDR SMVSWINGL SDQ[51] NB_MD52 VTTLF_1 VSS_52 VSS_143
AG23 AF1 K29 C22 H8
SDQ[52] NB_MD53 VCCASM VCCASM_0 VTTLF_2 VSS_53 VSS_144
AF23 AD1 F29 AG21 AJ7
SDQ[53] NB_MD54 VCCASM_1 VTTLF_3 VSS_54 VSS_145
AJ24 AF25 A26 AB21 AE7
e
SMVREF_0 SDQ[54] NB_MD55 VTTLF_4 VSS_55 VSS_146
AG25 A4 V22 AA21 AA7
SDQ[55] VCCGPIO_0 VTTLF_5 VSS_56 VSS_147
1
C328 AH26 NB_MD56 VCCGPIO A3 T22 Y21 R7

SDQ[56] VCCGPIO_1 VTTLF_6 VSS_57 VSS_148
u
0.1U MCH_SMRCOMP AB1 AE26 NB_MD57 P22 V21 M7
SMRCOMP SDQ[57] VTTLF_7 VSS_58 VSS_149
S
0402 AG28 NB_MD58 AJ8 M22 T21 J7
+80-20% SDQ[58] NB_MD59 VCCQSM VCCQSM_0 VTTLF_8 VSS_59 VSS_150
2
AF28 AJ6 H22 P21 G7

SDQ[59] VCCQSM_1 VTTLF_9 VSS_60 VSS_151
c
50V AG26 NB_MD60 U21 M21 E7
SDQ[60] NB_MD61 VCCADPLLA VTTLF_10 VSS_61 VSS_152
GND AF26 A6 R21 H21 C7
SDQ[61] VCCADPLLA VTTLF_11 VSS_62 VSS_153
c Do
TP40 1 F12 AE27 NB_MD62 VCCADPLLB B16 N21 D21 AG6
TP35 RSVD_0 SDQ[62] NB_MD63 NB_CB[0..7] VCCADPLLB VTTLF_12 VSS_63 VSS_154
1 D12 AD27 NB_CB[0..7] 6 L21 A21 Y6
TP703 RSVD_1 SDQ[63] NB_CB0 VCCAGPLL VTTLF_13 VSS_64 VSS_155
1 B12 AG14 Y2 H20 AJ20 L6
TP41 RSVD_2 SDQ[64] NB_CB1 VCCAHPLL VCCAGPLL VTTLF_14 VSS_65 VSS_156
1 AA5 AE14 D29 A20 AC20 Y5
a
TP25 RSVD_3 SDQ[65] NB_CB2 VCCAHPLL VTTLF_15 VSS_66 VSS_157
1 D7 AE17 J19 AA20 U5
RSVD_4 SDQ[66] NB_CB3 VCCALVDS VTTLF_16 VSS_67 VSS_158
AG16 +1.5V 1 2 A11 H18 J20 B5
SDQ[67] NB_CB4 L714 VCCALVDS VTTLF_17 +VCCP VSS_68 VSS_159
AH14 A18 F20 AE4
SDQ[68] VTTLF_18 VSS_69 VSS_160
1
NB_CB5 120Z/100M
iT ial
AE15 C777 C343 H16 AE19 AC4
SDQ[69] NB_CB6 VTTLF_19 VSS_70 VSS_161
L4 AF16 0.1U 0.01U B11 G15 AB19 AA4
7 GCBE2# RSVD_5 SDQ[70] NB_CB7 0402 0402 VSSALVDS VTTLF_20 VSS_71 VSS_162
AF17 H19 W4
SDQ[71] VSS_72 VSS_163
1
NB_DQS[0..8] +80-20% +80-20% C271 C238
2
C4 NB_DQS[0..8] 6 B8 C202 C252 D19 T4
7 GST0 GST[0] NB_DQS0 50V 50V VSSADAC 10U 10U VSS_73 VSS_164
C3 AG2 0.1U 0.1U A19 N4
7 GST1 GST[1] SDQS[0] NB_DQS1 0402 0402 16V 16V VSS_74 VSS_165
C2 AH5 855GM/GME AJ18 K4
7 GST2 GST[2] SDQS[1] NB_DQS2 +80-20% +80-20% 1206 1206 VSS_75 VSS_166
2
AH8 BGA707_25 AG18 G4
SDQS[2] NB_DQS3 VSSADAC 50V 50V VSS_76 VSS_167
M t
F2 AE12 GND AA18 D4
7 GSBSTB RSVD_6 SDQS[3] NB_DQS4 VSS_77 VSS_168
F3 AH17 J18 AJ3
7 GSBSTB# RSVD_7 SDQS[4] NB_DQS5 VSS_78 VSS_169
AE21 GND F18 AG3
SDQS[5] NB_DQS6 VSS_79 VSS_170
D3 AH24 AC17 R2
7 GRBF# RSVD_8 SDQS[6] NB_DQS7 VSS_80 VSS_171
D2 AH27 AB17 AJ1
7 GWBF# RSVD_9 SDQS[7] NB_DQS8 VSS_81 VSS_172
AD15 U17 AE1
n
SDQS[8] NB_DM[0..8] VSS_82 VSS_173
B2 NB_DM[0..8] 6 R17 AA1
7 GGNT# RSVD_10 NB_DM0 VSS_83 VSS_174
B3 AE5 N17 U1
7 GREQ# RSVD_11 SDM[0] NB_DM1 VCCADAC VCCASM VSS_84 VSS_175
AE6 1 2 1 2 H17 L1
e
B SDM[1] NB_DM2 +1.5V +1.35V VSS_85 VSS_176 B
AE9 L717 L727 D17 G1
SDM[2] NB_DM3 120Z/100M 120Z/100M VSS_86 VSS_177
AH12 A17 C1
SDM[3] VSS_87 VSS_178
1
AD19 NB_DM4 C779 C786 C852 C850 C851 C848 AE16 J10
SDM[4] NB_DM5 10U 10U VSS_88 VSS_179
AD21 0.1U 0.01U 10U 0.01U AA16 U26
id
SDM[5] NB_DM6 0402 0402 16V 16V 0805 0402 VSS_89 VSS_180
AD24 T16
SDM[6] NB_DM7 +80-20% +80-20%VSSADAC 1206 1206 6.3V +80-20% VSS_90
2
AH28
SDM[7] NB_DM8 50V 50V 10% 50V
AH15 855GM/GME
SDM[8]
f
GND BGA707_25 GND
855GM/GME GND
BGA707_25 GND
n
+1.35V +3V
o
1 2 VCCAHPLL 1 2 VCCAGPLL 1 2 VCCGPIO
+1.35V
L720 L45 L715
1
120Z/100M 120Z/100M 120Z/100M C783 C776
1
1
C808 C297 10U 0.01U
C
0.1U 0.1U 0805 0402
0402 0402 6.3V +80-20%
2
+80-20% +80-20% 10% 50V VTTHF_0 0.1U 0402 C832
2
2
1 2
50V 50V 50V +80-20%
GND GND GND VTTHF_1 0.1U 1 2 0402 C818
50V +80-20%
+1.5V +1.5V VTTHF_2 0.1U 1 2 0402 C814
50V +80-20%
VTTHF_3 0.1U 1 2 0402 C780
1
50V +80-20%
R822 R806 Place within 0.5" with 15-mil wide. 1 2 VCCADPLLA 1 2 VCCADPLLB VTTHF_4 0.1U 1 2 0402 C781
1K 1K/NA +1.35V +1.35V
L38 L713 50V +80-20%
1
1
0402 0402 120Z/100M C166 C171 120Z/100M C772 C785
5% 5% +2.5VS_DDR 10U 0.01U 10U 0.01U
+2.5VS_DDR +2.5VS_DDR 16V 0402 16V 0402
2
GND
1206 +80-20% 1206 +80-20%
2
2
GST0 50V 50V
1
GST1 CHANGE TO 0402 CHANGE TO 0402 C847

R945 R942 R923 0.1U GND GND
A 604 150 60.4 0402 A
0603 0402 0402 +80-20%
2
1% 1% 1% 50V
Clock config bit GST[1,0] MCH_SMVSWINGL MCH_SMVSWINGH MCH_SMRCOMP +2.5VS_DDR
2
2
1
+2.5VS_DDR
1
PSB/Sys Mem Core/GFX Core(CL/CH) R941 C857 R946 C858 R924 C846 1 2 VCCTXLVDS 1 2 VCCQSM
CHANGE TO 0402 150 0.1U 604 0.1U 60.4 0.1U/NA L42 L729
0402 0402 CHANGE TO 0402 0603 0402 0402 0402 120Z/100M +2.5V_M10 120Z/100M
1
1
1% +80-20% 1% +80-20% 1% +80-20% C174 C860
2
C227 C176 C859

00(def): 400/266/200(133/200) 50V 50V 50V 10U 4.7U
2
10U 0.01U 1 2 0.01U

16V 0805 0402 L730 0603 0402
01 : 400/200/200(100/200) 1206 6.3V +80-20% 120Z/100M/NA 6.3V +80-20% Title
2
2
GND GND GND 10% 50V +80-20% 50V 8050D MOTHER B/D
10 : 400/200/133(100/133)
Size Document Rev
GND GND C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
5 NB_MD[0..63]
NB_MD[0..63]
NB_MD0 R1062 1
NB_MD1 R1061 1
NB_MD2 R1059 1
10
10
10
2
2
0402
0402
0402
MD0
MD1
MD2
MD0
MD4
MD1
1
2
RP43
56*8
RPX8
16
15
+1.25V_DDR DDR -SODIMM
+2.5VS_DDR +2.5VS_DDR
2 3 14
NB_MD3 R1058 1 10 2 0402 MD3 MD5 4 13
NB_MD4 R1001 1 10 2 0402 MD4 DQS0 5 12
NB_MD5 R1000 1 10 2 0402 MD5 DM0 6 11 +DDR_VREF +DDR_VREF
NB_MD6 R998 1 10 2 0402 MD6 MD2 7 10
NB_MD7 R997 1 10 2 0402 MD7 MD6 8 9
NB_MD8 R1057 1 10 2 0402 MD8 MD3 1 RP42 16 J711 J712
NB_MD9 R1056 1 10 2 0402 MD9 MD7 2 56*8 15 1 2 1 2
NB_MD10R1054 1 10 2 0402 MD10 MD8 3 RPX8 14 3 4 3 4
NB_MD11R1053 1 10 2 0402 MD11 MD12 4 13 MD0 5 6 MD4 MD0 5 6 MD4
NB_MD13R995 1 10 2 0402 MD13 MD13 6 11 9 10 9 10
NB_MD14R993 1 10 2 0402 MD14 DQS1 7 10 DQS0 11 12 DM0 DQS0 11 12 DM0
NB_MD15R992 1 10 2 0402 MD15 DM1 8 9 MD2 13 14 MD6 MD2 13 14 MD6
NB_MD16R1052 1 10 2 0402 MD16 MD10 1 RP41 16 15 16 15 16
D D
NB_MD17R1051 1 10 2 0402 MD17 MD14 2 56*8 15 MD3 17 18 MD7 MD3 17 18 MD7
NB_MD18R1049 1 10 2 0402 MD18 MD11 3 RPX8 14 MD8 19 20 MD12 MD8 19 20 MD12
NB_MD19R1048 1 10 2 0402 MD19 MD15 4 13 21 22 21 22
NB_MD21R990 1 10 2 0402 MD21 MD20 6 11 DQS1 25 26 DM1 DQS1 25 26 DM1
NB_MD22R988 1 10 2 0402 MD22 MD17 7 10 27 28 27 28
NB_MD24R1047 1 10 2 0402 MD24 DQS2 1 RP40 16 MD11 31 32 MD15 MD11 31 32 MD15
NB_MD25R1046 1 10 2 0402 MD25 DM2 2 56*8 15 33 34 33 34
NB_MD26R1044 1 10 2 0402 MD26 MD18 3 RPX8 14 CLK_DDR0 35 36 CLK_DDR3 35 36
NB_MD27R1043 1 10 2 0402 MD27 MD22 4 13 CLK_DDR0# 37 38 CLK_DDR3# 37 38
NB_MD28R986 1 10 2 0402 MD28 MD19 5 12 39 40 39 40
NB_MD29R985 1 10 2 0402 MD29 MD23 6 11
NB_MD30R983 1 10 2 0402 MD30 MD24 7 10
NB_MD32R1028 1 10 2 0402 MD32 MD25 1 RP39 16 MD17 43 44 MD21 MD17 43 44 MD21
NB_MD33R1027 1 10 2 0402 MD33 MD29 2 56*8 15 45 46 45 46
NB_MD34R1025 1 10 2 0402 MD34 DQS3 3 RPX8 14 DQS2 47 48 DM2 DQS2 47 48 DM2
NB_MD35R1024 1 10 2 0402 MD35 DM3 4 13 MD18 49 50 MD22 MD18 49 50 MD22
NB_MD36R967 1 10 2 0402 MD36 MD26 5 12 51 52 51 52
NB_MD39R963 1 10 2 0402 MD39 MD31 8 9 +2.5VS_DDR 57 58 57 58
NB_MD40R1023 1 10 2 0402 MD40 MD32 1 RP33 16 MD25 59 60 MD29 MD25 59 60 MD29
NB_MD41R1022 1 10 2 0402 MD41 MD36 2 56*8 15 DQS3 61 62 DM3 DQS3 61 62 DM3
NB_MD42R1020 1 10 2 0402 MD42 MD33 3 RPX8 14 63 64 63 64
1
NB_MD43R1019 1 10 2 0402 MD43 MD37 4 13 C868 C331 C347 C369 MD26 65 66 MD30 MD26 65 66 MD30
NB_MD44R962 1 10 2 0402 MD44 DQS4 5 12 0.1U 0.1U 0.1U 0.1U MD27 67 68 MD31 MD27 67 68 MD31
NB_MD45R961 1 10 2 0402 MD45 DM4 6 11 0402 0402 0402 0402 69 70 69 70
NB_MD46R959 1 10 0402 MD46 MD34 +80-20% +80-20% +80-20% +80-20% MCB0 MCB4 MCB0 MCB4
2
2 7 10 71 72 71 72
t
NB_MD47R958 1 10 2 0402 MD47 MD38 8 9 50V 50V 50V 50V MCB1 73 74 MCB5 MCB1 73 74 MCB5
NB_MD48R1018 1 10 2 0402 MD48 MD35 1 RP32 16 75 76 75 76
NB_MD49R1017 1 10 2 0402 MD49 MD39 2 56*8 15 DQS8 77 78 DM8 DQS8 77 78 DM8
1
t
NB_MD50R1015 1 10 2 0402 MD50 MD40 3 RPX8 14 C333 C349 C350 C332 MCB2 79 80 MCB6 MCB2 79 80 MCB6
n
NB_MD51R1014 1 10 2 0402 MD51 MD44 4 13 0.1U 0.1U 0.1U 0.1U 81 82 81 82
NB_MD52R957 1 10 2 0402 MD52 MD41 5 12 0402 0402 0402 0402 MCB3 83 84 MCB7 MCB3 83 84 MCB7
e e
NB_MD53R956 1 10 0402 MD53 MD45 +80-20% +80-20% +80-20% +80-20% CKE1_S1 CKE0_S1
2
2 6 11 85 86 85 86
C NB_MD54R954 1 10 2 0402 MD54 DQS5 7 10 50V 50V 50V 50V 87 88 87 88 C
NB_MD55R953 1 10 2 0402 MD55 DM5 8 9 CLK_DDR2 89 90 CLK_DDR5 89 90
r
NB_MD56R1013 1 10 2 0402 MD56 MD42 1 RP31 16 CLK_DDR2# 91 92 CLK_DDR5# 91 92
NB_MD57R1012 1 10 2 0402 MD57 MD46 2 56*8 15 93 94 93 94
NB_MD58R1010 1 10 2 0402 MD58 MD43 3 RPX8 14 GND CKE1 95 96 CKE0 CKE3 95 96 CKE2
c m
NB_MD59R1009 1 10 2 0402 MD59 MD47 4 13 97 98 CS#0_S1 97 98
NB_MD60R952 1 10 2 0402 MD60 MD48 5 12 MA12 99 100 MA11 NB_MA12 99 100 NB_MA11
e
NB_MD62R949 1 10 2 0402 MD62 MD49 7 10 103 104 103 104
u
DQS6 1 RP30 16 SMA5 107 108 SMA4 SMAB5 107 108 SMAB4
S
NB_DQS[0..7] DM6 2 56*8 15 +1.25V_DDR MA3 109 110 SMA2 NB_MA3 109 110 SMAB2
NB_DQS[0..7] NB_DQS0 DQS0 SMA1 MA0 SMAB1 NB_MA0
R1060 1 10 2 0402 MD50 3 RPX8 14 111 112 111 112
c
NB_DQS1 R1055 1 10 2 0402 DQS1 MD54 4 13 113 114 113 114
NB_DQS2 R1050 1 10 2 0402 DQS2 MD51 5 12 MA10 115 116 BA1 NB_MA10 115 116 NB_BA1
1
1
c Do
NB_DQS3 R1045 1 10 2 0402 DQS3 MD55 6 11 C427 C434 C431 C429 C426 BA0 117 118 RAS# NB_BA0 117 118 NB_RAS#
NB_DQS4 R1026 1 10 2 0402 DQS4 MD56 7 10 0.01U 0.01U 0.01U 0.01U 0.01U WE# 119 120 CAS# NB_WE# 119 120 NB_CAS#
NB_DQS5 R1021 1 10 2 0402 DQS5 MD60 8 9 0402 0402 0402 0402 0402 CS#0 121 122 CS#1 CS#2 121 122 CS#3
NB_DQS6 R1016 1 10 0402 DQS6 MD57 RP29 +80-20% +80-20% +80-20% +80-20% +80-20% CS#1_S1
2
2
2 1 16 123 124 123 124
a
NB_DQS7 R1011 1 10 2 0402 DQS7 MD61 2 56*8 15 50V 50V 50V 50V 50V 125 126 125 126
DQS7 3 RPX8 14 MD32 127 128 MD36 MD32 127 128 MD36
1
1
NB_DM[0..7] DM7 4 13 C433 C430 C428 C425 C432 MD33 129 130 MD37 MD33 129 130 MD37
NB_DM[0..7] NB_DM0 DM0
R999 10 0402 MD58
iT ial
1 2 5 12 0.01U 0.01U 0.01U 0.01U 0.01U 131 132 131 132
NB_DM1 R994 1 10 2 0402 DM1 MD62 6 11 0402 0402 0402 0402 0402 DQS4 133 134 DM4 DQS4 133 134 DM4
NB_DM2 R989 10 0402 DM2 MD59 +80-20% +80-20% +80-20% +80-20% +80-20% MD34 MD38 MD34 MD38
2
2
1 2 7 10 135 136 135 136
NB_DM3 R984 1 10 2 0402 DM3 MD63 8 9 50V 50V 50V 50V 50V 137 138 137 138
NB_DM4 R965 1 10 2 0402 DM4 MD35 139 140 MD39 MD35 139 140 MD39
NB_DM5 R960 1 10 2 0402 DM5 GND MD40 141 142 MD44 MD40 141 142 MD44
NB_DM6 R955 1 10 2 0402 DM6 143 144 143 144
NB_DM7 DM7 MD41 MD45 MD41 MD45
M t
R950 1 10 2 0402 145 146 145 146
NB_CB[0..7] DQS5 147 148 DM5 DQS5 147 148 DM5
NB_CB[0..7] NB_CB0 MCB0 +2.5VS_DDR
R1042 1 10 2 0402 MCB1 1 RP38 16 149 150 149 150
NB_CB1 R1041 1 10 2 0402 MCB1 MCB0 2 56*8 15 MD42 151 152 MD46 MD42 151 152 MD46
NB_CB2 R1039 1 10 2 0402 MCB2 MCB4 3 RPX8 14 MD43 153 154 MD47 MD43 153 154 MD47
NB_CB3 R1038 1 10 2 0402 MCB3 MCB5 4 13 155 156 155 156
n
1
NB_CB4 R981 1 10 2 0402 MCB4 DQS8 5 12 C348 C334 C370 C335 C351 157 158 CLK_DDR1# 157 158 CLK_DDR4#
NB_CB5 R980 1 10 2 0402 MCB5 DM8 6 11 1U 0.1U 0.1U 0.1U 0.1U 159 160 CLK_DDR1 159 160 CLK_DDR4
NB_CB6 R978 1 10 2 0402 MCB6 MCB6 7 10 0402 0402 0402 0402 0402 161 162 161 162
e
B B
NB_CB7 R977 1 10 0402 MCB7 MCB2 +80-20% +80-20% +80-20% +80-20% +80-20% MD48 MD52 MD48 MD52
2
2 8 9 163 164 163 164

10V 50V 50V 50V 50V MD49 165 166 MD53 MD49 165 166 MD53
NB_MA0 R972 1 10 2 0402 MA0 SMAB4 1 RP36 16 167 168 167 168
5 NB_MA0
1
NB_MA3 R1033 1 10 2 0402 MA3 SMAB2 2 56*8 15 DQS6 169 170 DM6 DQS6 169 170 DM6
id
5 NB_MA3 C371 C353 C352 C372 C336
NB_MA6 R973 1 10 2 0402 MA6 SMA5 3 RPX8 14 1U 0.1U 0.1U 0.1U 1U MD50 171 172 MD54 MD50 171 172 MD54
5 NB_MA6 NB_MA7 MA7 SMA2
R1034 1 10 2 0402 4 13 0402 0402 0402 0402 0402 173 174 173 174
5 NB_MA7 NB_MA8 MA8 +80-20% +80-20% +80-20% +80-20% +80-20% MD51 MD55 MD51 MD55
R974 1 10 0402 NB_MA12
2
5 NB_MA8 2 5 12 175 176 175 176
f
NB_MA9 R1035 1 10 2 0402 MA9 NB_MA11 6 11 10V 50V 50V 50V 10V MD56 177 178 MD60 MD56 177 178 MD60
5 NB_MA9 NB_MA10 R1032 1 MA10 NB_MA8
10 2 0402 7 10 179 180 179 180
5 NB_MA10 NB_MA11 R975 1 MA11 MD57 MD61 MD57 MD61
10 2 0402 NB_MA9 8 9 GND 181 182 181 182
5 NB_MA11 NB_MA12 R1036 1 MA12 DQS7 DM7 DQS7 DM7
10 2 0402 NB_BA0 1 RP34 16 183 184 183 184
5 NB_MA12
n
NB_WE# R1030 1 10 2 0402 WE# NB_WE# 2 56*8 15 185 186 185 186
5 NB_WE# CAS# MD58 MD62 MD58 MD62
NB_CAS#R969 1 10 2 0402 NB_CAS# 3 RPX8 14 187 188 187 188
5 NB_CAS# RAS# MD59 MD63 MD59 MD63
NB_RAS#R970 1 10 2 0402 NB_RAS# 4 13 189 190 189 190
5 NB_RAS#
o
NB_BA0 R1031 1 10 2 0402 BA0 CS#1 5 12 191 192 191 192
5 NB_BA0 BA1 SMBDATA
NB_BA1 R971 1 10 2 0402 CS#2 6 11 193 194 SMBDATA 193 194
5 NB_BA1 SMA1 11,14 SMBDATA SMBCLK +3V
CS#3 7 10 195 196 SMBCLK 195 196
5 SMA1 SMA2 11,14 SMBCLK
CS#0 8 9 197 198 197 198
C
5 SMA2 SMA4 +3V +3V
MCB3 1 RP37 16 199 200 199 200
5 SMA4 SMA5 MCB7 CLK_DDR0
2 56*8 15 R338 1 0 0402 2 5%
5 SMA5 SMAB1 5 NB_CLK_DDR0 CLK_DDR0#
CKE1 3 RPX8 14 R337 1 0 0402 2 5% 0.6MM/200P/H9.2 0.6MM/200P/H5.2
5 SMAB1 SMAB2 5 NB_CLK_DDR0# CLK_DDR1
CKE0 4 13 R319 1 0 0402 2 5% QUASAR QUASAR
5 SMAB2 SMAB4 5 NB_CLK_DDR1 CLK_DDR1#
CKE2 5 12 R320 1 0 0402 2 5% CA0145-200N01 CA0115-200N01
5 SMAB4 SMAB5 5 NB_CLK_DDR1# CLK_DDR2
CKE3 6 11 R336 1 0 0402 2 5%
5 SMAB5 5 NB_CLK_DDR2 CLK_DDR2#
CKE0 SMAB5 7 10 R335 1 0 0402 2 5%
5 CKE0 5 NB_CLK_DDR2# CLK_DDR3
CKE1 SMA4 8 9 R354 1 0 0402 2 5%
5 CKE1 CKE2 NB_MA7 5 NB_CLK_DDR3 CLK_DDR3#
1 RP35 16 R352 1 0 0402 2 5% GND GND
5 CKE2 CKE3 5 NB_CLK_DDR3# CLK_DDR4
NB_MA6 2 56*8 15 R359 1 0 0402 2 5%
5 CKE3 CS#0 5 NB_CLK_DDR4 CLK_DDR4#
NB_MA3 3 RPX8 14 R360 1 0 0402 2 5% +1.25V_DDR
5 CS#0 CS#1 5 NB_CLK_DDR4#
SMA1 4 13 R351 1 0 0402 2 5% CLK_DDR5
5 CS#1 CS#2 5 NB_CLK_DDR5
SMAB1 5 12 R347 1 0 0402 2 5% CLK_DDR5#
5 CS#2 CS#3 NB_MA10 5 NB_CLK_DDR5#
6 11 +1.25V_DDR
5 CS#3
1
R979 1 10 2 0402 DM8 NB_MA0 7 10 +2.5VS_DDR C436 C437 C422 C423 C424
5 NB_DM8 DQS8 NB_BA1
R1040 1 10 2 0402 8 9 +1.25V_DDR 10U 10U 0.1U 0.1U 0.1U
5 NB_DQS8
0805 0805 0402 0402 0402
1
6.3V 6.3V +80-20% +80-20% +80-20%
2
C393 C396 C395 C398 C399 C401
1
0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 10% 10% 50V 50V 50V
1
1
A R976 1 0 0402 2 5% CKE0_S1 C387 C388 C389 C390 C392 C391 0402 0402 0402 0402 0402 0402 R340 C337 C346 A
R1037 1 0 0402 2 5% CKE1_S1 +80-20% +80-20% +80-20% +80-20% +80-20% +80-20% 75 +DDR_VREF GND
2
0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.01U 0.1U

R1029 1 0 0402 2 5% CS#0_S1 0402 0402 0402 0402 0402 0402 50V 50V 50V 50V 50V 50V 0402 0402 0402
R968 1 0 0402 2 5% CS#1_S1 +80-20% +80-20% +80-20% +80-20% +80-20% +80-20% 1% +80-20% +80-20%
2
2
1
50V 50V 50V 50V 50V 50V 50V 50V
2
C411 C416 C413 C417 C418 C415
0.01U 0.01U 0.01U 0.01U 0.01U 0.01U
1
C394 C397 C400 C403 C409 C408 0402 0402 0402 0402 0402 0402 1
1
+80-20% +80-20% +80-20% +80-20% +80-20% +80-20% R334
2
0.01U 0.01U 0.01U 0.01U 0.01U 0.01U C386 C366 C338 C384
0402 0402 0402 0402 0402 0402 50V 50V 50V 50V 50V 50V 75 0.01U 0.1U 0.1U 0.1U
+80-20% +80-20% +80-20% +80-20% +80-20% +80-20% 0402 0402 0402 0402 0402
2
50V 50V 50V 50V 50V 50V 1% +80-20% +80-20% +80-20% +80-20%
2
2
C420 C402 C410 C421 C419
50V 50V 50V 50V
2
0.01U 0.01U 0.01U 0.01U 0.01U

1
C404 C405 C406 C412 C407 C414 0402 0402 0402 0402 0402 Title
+80-20% +80-20% +80-20% +80-20% +80-20% 8050D MOTHER B/D
2
0.01U 0.01U 0.01U 0.01U 0.01U 0.01U

0402 0402 0402 0402 0402 0402 50V 50V 50V 50V 50V GND
+80-20% +80-20% +80-20% +80-20% +80-20% +80-20% Size Rev
2
50V 50V 50V 50V 50V 50V Document

GND C PCB 316680900001/ASSY 411682700001 R01
Number
GND Date: Wednesday, December 31, 2003 Sheet 6 of 34
5 4 3 2 1

5 4 3 2 1
+3V
M10_GPIO0 R743 1 10K 2 0402 Bus configuration straps
1.5V, AGP4X, ID=16
ATI M10-P(1/4) R742 1 10K/NA 2 0402 M10_GPIO4
M10_GPIO5
M10_GPIO6
R61 1 10K
R57 1 10K
R735 1 10K
2 0402
2 0402
2 0402
M10_GPIO1 R744 1 10K 2 0402
AGP_VDDQ
GND
AGP MODE R779 R777 R739 1 10K/NA 2 0402
RP715
1
AGP2.0(4X).75V 1.02K 1.02K M10_GPIO2 R738 1 10K/NA 2 0402 M10_GPIO13 1 10

R120 M10_GPIO10 2 9 M10_GPIO11
1.02K M10_GPIO7 3 8 M10_GPIO12
D D
0402 AGP3.0(8X).35V 324 100 AGP_AD[0..31] R737 1 10K/NA 2 0402 M10_GPIO14 4 7 M10_GPIO9
1% 4,24 AGP_AD[0..31] U710A M10_GPIO8
5 6
AGP_AD0 M10_GPIO0
2
H29 AJ5
AGP_AD1 AD0 GPIO0 M10_GPIO1 M10_GPIO3 R734 1 10K/NA 2 0402
H28 AH5 10K*8 1206
AGP_VREF AGP_AD2 AD1 GPIO1 M10_GPIO2
J29 AJ4
AD2 GPIO2
1
AGP_AD3 J28 AK4 M10_GPIO3

AD3 GPIO3
1
1
R110 C146 AGP_AD4 K29 AH4 M10_GPIO4 +3VS R733 1 10K/NA 2 0402
1.02K C149 AGP_AD5 AD4 GPIO4 M10_GPIO5
10U K28 AF4
0402 0805 AGP_AD6 AD5 GPIO5 M10_GPIO6 GND
L29 AJ3
1% 0.01U 6.3V AGP_AD7 AD6 GPIO6 M10_GPIO7 For MEM_ID
2
14
L28 AK3
0402 10% AGP_AD8 AD7 GPIO7 M10_GPIO8 GND +3V
2
N28 AH3 U703A

50V AGP_AD9 AD8 GPIO8 M10_GPIO9
P29 AJ2
10% AGP_AD10 AD9 GPIO9 M10_GPIO10 ZV13 R66
P28 AH2 1 2 SW_1.5V/1.25V 30 1 10K/NA 2 0402
AGP_AD11 AD10 GPIO10 M10_GPIO11
R29 AH1
AGP_AD12 AD11 GPIO11 M10_GPIO12 R67
R28 AG3 1 10K/NA 2 0402
AGP_AD13 AD12 GPIO12 M10_GPIO13
T29 AG1 74AHC14_V
GND AGP_AD14 AD13 GPIO13 M10_GPIO14
7
T28 AG2 TSSOP14
AGP_AD15 AD14 GPIO14 GND
U29 AF3
AGP_AD16 AD15 GPIO15 OSC_SPREAD R83
N25 AF2 1 1K/NA 2 0402
AGP_AD17 AD16 GPIO16
R26
AGP_AD18 AD17 GND R62
P25 AF5 1 1K/NA 2 0402 +3V
AGP_AD19 AD18 ROMCS# +3V
R27
AGP_AD20 AD19 0402
R25 AH6 PANEL_ID0 12,14,24 SW701
AGP_AD21 AD20 ZV_LCDDATA0 R82
T25 AJ6 PANEL_ID1 12,14,24 1 10K 2 ZV11 1 4 R748 1 1K 2 0402
AGP_AD22 AD21 ZV_LCDDATA1 R58
T26 AK6 PANEL_ID2 12,14,24 1 10K 2 ZV12 2 3 R749 1 1K 2 0402
AGP_AD23 AD22 ZV_LCDDATA2 0402
U25 AH7 PANEL_ID3 12,14,24
AGP_AD24 AD23 ZV_LCDDATA3
V27 AK7 HDS402
AGP_AD25 AD24 ZV_LCDDATA4 GND
W26 AJ7 SW_HDS402
AD25 ZV_LCDDATA5
1
AGP_AD26 W25 AH8 C69 C734 C733 C68
AGP_AD27 AD26 ZV_LCDDATA6
Y26 AJ8 0.01U/NA 0.01U/NA 0.01U/NA 0.01U/NA
t
AGP_AD28 AD27 ZV_LCDDATA7 0402 0402 0402 0402
Y25 AH9
AD28 ZV_LCDDATA8 +80-20% +80-20% +80-20% +80-20%
AGP_AD29 ZV11 ZV12 ZV13
2
AA26 AJ9
AGP_AD30 AD29 ZV_LCDDATA9 50V 50V 50V 50V
AA25 AK9
AD30 ZV_LCDDATA10
t
AGP_AD31 AA27 AH10 1 0 0 64M Samsung K4D263238E-GL36
n
AD31 ZV_LCDDATA11
4,5 AGP_CBE#[0..3]
AGP_CBE#[0..3]
ZV_LCDDATA12
AE6 1 TP53 Reserve
AGP_CBE#0 N29
C/BE#0 ZV_LCDDATA13
AG6 1 TP54 64M Infineon HYB25D128323CL3.6
e e
AGP_CBE#1 U28 AF6 TP55 GND
C/BE#1 ZV_LCDDATA14
C FOR M10 AGP_CBE#2 P26
C/BE#2 ZV_LCDDATA15
AE7 1 0 Reserve 64M EtroTech EM6A9320B1-3.6M C
C773 1 2 22P/NA R778 1 5% 2 0402 AGP_CBE#3 U26 AF7 1 TP1
GND
r
C/BE#3 ZV_LCDDATA16
0402 50V +/-10% 33/NA
ZV_LCDDATA17
AE8 1 TP2 0 1 Reserve 64M Hynix
R779 1 0 2 0402 5% AG30 AG8 R77 1 33 5% 2 0402 I2C_DAT
11 66M_AGP PCICLK ZV_LCDDATA18
R105 1 22 2 AG28 AF8 R78 1 33 5% 2 0402 I2C_CLK 1 1 Reserve 128M EtroTech H230904RAT309A
c m
13 ATI_PCIRST# RST# ZV_LCDDATA19
0402 5% AF28 AE9 R76 1 10K 2 0402
5 AGP_REQ# REQ# ZV_LCDDATA20 +3V
1
5 AGP_GNT# AD26 AF9 R405 1 0 2 ZV11
GNT# ZV_LCDDATA21
AGP MODE R794 4 AGP_PAR M25 AG10R406 1 0 0402 25% ZV12 R72 R79
e
PAR ZV_LCDDATA22
4 AGP_STOP# N26 AF10 R407 1 0 0402 25% ZV13 2.21K 2.21K
STOP# ZV_LCDDATA23 0402 5% 0402 0402
4 AGP_DEVSEL# V29
DEVSEL#
u
M9+ 49.9R V28 AJ10 1 RP718 8 1% 1%
4 AGP_TRDY# TRDY# ZV_LCDCNTL0
S
0*4
2
4 AGP_IRDY# W29 AK102 7
IRDY# ZV_LCDCNTL1 1206
4 AGP_FRAME# W28 AJ11 3 6 +3V
FRAME# ZV_LCDCNTL2
c
R122 1 0 2 0402 5% AE26 AH114 5
13,24 PCI_INTA# INTA# ZV_LCDCNTL3 GND
M10 40R 5 AGP_WBF#
R118 1 0 2 0402 5%
c Do
AGP_VDDQ AC26
WBF#
AK16 TXOUT0-_ATI 4
STP_AGP# TXOUT_L0N
13,24 STP_AGP# AH30 AH16 TXOUT0+_ATI 4
R119 AGPBUSY# STP_AGP# TXOUT_L0P
AH29 AH17
a
AGPTEST 4,13,24 AGPBUSY# AGP_BUSY# TXOUT_L1N TXOUT1-_ATI 4
1 2 5 AGP_RBF# AE29 AJ16 TXOUT1+_ATI 4
RBF# TXOUT_L1P
4 AGP_ADSTB0 M28 AH18 TXOUT2-_ATI 4 LVDS CH1
40.2 1% 0402 AD_STBF0 TXOUT_L2N
4 AGP_ADSTB1 V25 AJ17 TXOUT2+_ATI 4
AD_STBF1 TXOUT_L2P
iT ial
5 AGP_SBSTBF AB29 AK19 TXOUT3-_ATI 4
AGP_SBA[0..7] SB_STBF TXOUT_L3N
4 AGP_SBA[0..7] AH19 TXOUT3+_ATI 4
AGP_SBA0 TXOUT_L3P
AD28 AK18 TXCLK-_ATI 4
AGP_SBA1 SBA0 TXCLK_LN
AD29 AJ18 TXCLK+_ATI 4
AGP_SBA2 SBA1 TXCLK_LP TP8
AC28 AG16 1
AGP_SBA3 SBA2 TXOUT_U0N TP7
AC29 AF16 1
AGP_SBA4 SBA3 TXOUT_U0P TP6
AA28 AG17 1
SBA4 TXOUT_U1N
M t
AGP_SBA5 AA29 AF17 1 TP10
AGP_SBA6 SBA5 TXOUT_U1P TP9
Y28 AF18 1
AGP_SBA7 SBA6 TXOUT_U2N TP11
Y29 AE18 1 LVDS CH2
SBA7 TXOUT_U2P TP13
AH20 1
AGP_ST0 TXOUT_U3N TP15
5 AGP_ST0 AF29 AG20 1
AGP_ST1 ST0 TXOUT_U3P TP12
AD27 AF19 1
n
5 AGP_ST1 ST1 TXCLK_UN
AGP_ST2 AE28 AG19 1 TP14
5 AGP_ST2 ST2 TXCLK_UP R752
AB28 AE12 DIGON 1 0 0402 2 5%
e
B 5 AGP_SBSTBS SB_STBS DIGON BLON 1 0 ENABKL ENAVDD 12 B
4 AGP_ADSTB0# M29 AG12 2 ENABKL 12
+3V AD_STBS0 BLON R85 0402 5%
4 AGP_ADSTB1# V26
C145 1 AD_STBS1
2 0.1U AJ13
TX0M
1
AGP_VREF 0402 50V +80-20% M26 AH14
id
4 AGP_VREF AGPREF TX0P
AGPTEST M27 AJ14 R86
R140 AGPTEST TX1M 10K
1 47K 2 0402 5% AC25 AH15
R121 1 10K/NA 2 R762 AGP8X_DET# TX1P 0402
AJ15
TX2M
f
0402 5% 1 2 AK21 AK15 5%
715 ohm is recommanded for R2SET. GND 0603 715 5% R2SET TX2P 2
AH13
GND ATI_TV_CRMA AJ23 TXCM
11 ATI_TV_CRMA AK13
ATI_TV_LUMA AJ22 C_R TXCP
11 ATI_TV_LUMA Y_G
n
ATI_TV_COMP AK22 AE13 GND +3V +3V
11 ATI_TV_COMP COMP_B DDC2CLK
AJ24 AE14
H2SYNC DDC2DATA
AK24
V2SYNC
1
o
AF12 R84 1 100K 2
HPD1 0402 5% L711 R765
AG23
+3V DDC3CLK ATI_CRT_RED 120Z/100M 8.2K
AG24 AK27 ATI_CRT_RED 12
DDC3DATA R ATI_CRT_GREEN GND 2012 0402
AJ27
C
G ATI_CRT_BLUE ATI_CRT_GREEN 12
AJ26 5%
REF_OUT B ATI_CRT_BLUE 12
R770 1 0 2 0402 TP702 +3V
2
1 AK25 AG25 ATI_CRT_HSYNC 12
SSIN HSYNC
2
AJ25 AH25 ATI_CRT_VSYNC 12
R773 1 0 SSOUT VSYNC
2 0402
1
C123 C110 C128 C72 AH26 R764 1 2

RSET GND
1
1000P 10U 0.01U 0.1U 0603 499 1% C757 C755
0402 0805 0402 0402 X1 R775 1 0/NA 2 0402 AH28 B6 R771 1U 0.1U
+/-20% 6.3V +80-20% +80-20% XTALIN TEST_MCLK GND 0 0402 0402
2
E8
50V 10% 50V 50V X2 R774 1 0/NA 2 0402 TEST_YCLK 0402 +80-20% 10%
2
AJ29
R776 XTALOUT 5% 10V 16V
AF25 ATI_CRT_DDDA 12
DDC1DATA U711
1 1M
2
2 AF24 ATI_CRT_DDCK 12
0402 5% R102 1 1K DDC1CLK X1 GND GND
GND 2 AH27 1 8
0402 5% TESTEN R104 X2 XIN/CLKIN VDD R772 REF_OUT
2 7 1 150 2 0402
GND X702 R100 1 0/NA 2 0402 +3V XOUT REF 1% OSC_SPREAD
13 SB_SUSST# AG26 AF26 1 2 3 6
SUS_STAT# AUXWIN R786 2 PD# MODOUT
1 2 1 4 5
LF VSS
1
AGP_VDDQ 10K 0402 5% 620
MOBILITY-M10-P
1
1
27MHZ C774 0603 C770 P2779A R777
BGA644_64_1MM
1
C765 TXC8X4.5 C766 0.1U 270P SO8 180

22P 22P R101 0402 0402 GND 0603
0402 0402 10%5% +/-10% 1%
2
2
A A
+/-10% +/-10% 20K 16V 50V
2
2
1
50V 50V 0402 ATI_CRT_RED

C126 C122 C120 C131 1%
USE 22P 5% ATI_CRT_GREEN GND GND GND
1
1000P 10U 0.01U 0.1U

0402 0805 0402 0402 ATI_CRT_BLUE
+/-20% 6.3V +80-20% +80-20% GND GND +3V
2
50V 10% 50V 50V

R768 R769 R767
1
C761 C760 C759 75 75 75

47P/NA 47P/NA 47P/NA 0402 0402 0402
0402 0402 0402 5% 5% 5%
GND +/-10% +/-10% +/-10%
2
25V 25V 25V Title

8050D MOTHER B/D
GND GND Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
ATI M10-P(2/4)
VGA_1.2/1.0
D +1.8V D
L39 120Z/100M
AGP_VDDQ 1 2
U710D VDD_CORE1.8
2012
1
AC13 AA23 C167 C152 C153
VDDC_0 VDDP_0
AC15 AA24 10U 0.1U 0.1U
VDDC_1 VDDP_1 0805 0402 0402
AC17 AB30
VDDC_2 VDDP_2
1
1
6.3V +80-20% +80-20%
2
C743 AD13 AC23 C114 C164 C769 C132 C147 C767
VDDC_3 VDDP_3
1
1
+ 150U C88 C85 C100 C106 C109 AD15 AC27 10U 10U 0.1U 0.01U 1000P 0.1U 10% 50V 50V
VDDC_4 VDDP_4 0805 0805 0402 0402 0402 0402 L712 120Z/100M
7343 0.1U 0.01U 1000P 0.01U 0.1U M12 AE30
2.5V 0402 0402 0402 0402 0402 VDDC_5 VDDP_5 6.3V 6.3V +80-20% +80-20% +/-20% +80-20% U710E
2
M13 AF27 1 2 VDD_PLL1.8
+80-20% +80-20% +/-20% +80-20% +80-20% VDDC_6 VDDP_6 10% 10% 50V 50V 50V 50V
2
2
M14 J30 A10 N15
VDDC_7 VDDP_7 VSS_0 VSS_76
1
50V 50V 50V 50V 50V M17 M23 2012 C762 C763 C764 A16 N16
M18 M24 10U 0.1U 0.1U A2 N23
VDDC_9 VDDP_9 0805 0402 0402 VSS_2 VSS_78
M19 N30 A22 N24
VDDC_10 VDDP_10 6.3V +80-20% +80-20% VSS_3 VSS_79
2
N12 P23 A29 N27
VDDC_11 VDDP_11 10% 50V 50V VSS_4 VSS_80
N13 P27 AA30 P15
VDDC_12 VDDP_12 GND L29 120Z/100M VSS_5 VSS_81
N14 T23 AB1 P16
N17 T24 1 2 VDD_PNLIO1.8 AB23 P4
N18 T30 AB24 R12
1
1
C82 C89 C107 C91 C101 N19 U27 2012 C98 C86 C124 AB27 R13
10U 10U 0.1U 0.01U 1000P P12 V23 10U 0.1U 0.1U AB7 R14
0805 0805 0402 0402 0402 VDDC_17 VDDP_17 0805 0402 0402 VSS_10 VSS_86
P13 V24 AB8 R15
6.3V 6.3V +80-20% +80-20% +/-20% VDDC_18 VDDP_18 6.3V +80-20% +80-20% VSS_11 VSS_87
2
2
P14 W30 AC12 R16
10% 10% 50V 50V 50V VDDC_19 VDDP_19 VDD_MEM_IO 10% 50V 50V VSS_12 VSS_88
P17 Y27 AC14 R17
VDDC_20 VDDP_20 L710 120Z/100M VSS_13 VSS_89
P18 A15 AC16 R18
VDDC_21 VDDR1_0 VSS_14 VSS_90
P19 A21 1 2 VDD_PNLPLL1.8 AC18 R23
1
U12 A28 C108 C95 C125 C758 AC4 R24
1
VDD_CORE GND U13 A3 1000P 0.01U 0.1U 10U 2012 C739 C746 C747 AD12 R30
t
VDDC_24 VDDR1_3 0402 0402 0402 0805 VSS_17 VSS_93
U14 A9 10U 0.1U 0.1U AD16 R7
VDDC_25 VDDR1_4 +/-20% +80-20% +80-20% 6.3V 0805 0402 0402 VSS_18 VSS_94
2
U17 AA1 AD18 R8
VDDC_26 VDDR1_5 50V 50V 50V 10% 6.3V +80-20% +80-20% VSS_19 VSS_95
2
U18 AA4 AD25 T1
1
t
C111 C119 C80 C83 U19 AA7 10% 50V 50V AD30 T13
n
VDDC_28 VDDR1_7 L32 120Z/100M VSS_21 VSS_97
0.1U 0.1U 0.1U 0.1U V12 AA8 AE27 T14
0402 0402 0402 0402 VDDC_29 VDDR1_8 GND VSS_22 VSS_98
V13 AD4 1 2 A2VDDQ_1.8 AG11 T15
e e
+80-20% +80-20% +80-20% +80-20%
2
V14 B1 AG15 T16

1
C 50V 50V 50V 50V V17 B30 2012 C127 C129 C130 AG18 T17 C
1
V18 D11 C99 C117 C81 10U 0.1U 0.1U AG22 T18
r
VDDC_33 VDDR1_12 0805 0402 0402 VSS_26 VSS_102
V19 D14 1000P 0.01U 0.1U AG27 T19
VDDC_34 VDDR1_13 0402 0402 0402 6.3V +80-20% +80-20% VSS_27 VSS_103
2
GND W12 D17 AG5 T27
VDDC_35 VDDR1_14 +/-20% +80-20% +80-20% 10% 50V 50V VSS_28 VSS_104
2
W13 D20 AG9 U15
c m
VDDC_36 VDDR1_15 50V 50V 50V L34 120Z/100M VSS_29 VSS_105
W14 D23 AJ1 U16
VDD_CORE VDDC_37 VDDR1_16 VSS_30 VSS_106
W17 D26 1 2 AVDD_1.8 AJ30 U4
VGA_1.2/1.0 1.8V for M9 , 1.5V for M10 VDDC_38 VDDR1_17 VSS_31 VSS_107
W18 D5 AK2 U8
e
1
W19 D8 2012 C138 C136 C137 AK29 V15
VDDC_40 VDDR1_19 GND VDD_MEM_IO VSS_33 VSS_109
E27 10U 0.1U 0.01U C1 V16
VDDR1_20 VSS_34 VSS_110
u
VDD_CORE1.5 R94 1 0 2 AC11 F4 0805 0402 0402 C28 V30
VDDC15_0 VDDR1_21 VSS_35 VSS_111
S
0805 6.3V +80-20% +80-20%
2
AC20 G10 C3 W15
1
1
H11 G13 C87 C77 C90 10% 50V 50V C30 W23
1
c
L28 H20 G15 1000P 0.01U 0.1U C78 D12 W24
VDDC15_3 VDDR1_24 0402 0402 0402 VSS_38 VSS_114
L23 G19 10U D15 W27
120Z/100M VDDC15_4 VDDR1_25 VSS_39 VSS_115
c Do
+/-20% +80-20% +80-20% 0805 L35 120Z/100M
2
P8 G22 D18 W7
2012 VDDC15_5 VDDR1_26 50V 50V 50V 6.3V VSS_40 VSS_116
2
Y23 G27 1 2 VDDDI_1.8 D21 W8
VDDC15_6 VDDR1_27 10% VSS_41 VSS_117
Y8 G7 GND D24 Y4
1
2012
2
H10 C141 C139 C140 D27
a
VDDR1_29 VSS_43
1
M15 H13 C74 C60 C58 10U 0.1U 0.1U D4 AE23
VDDCI_0 VDDR1_30 VSS_44 VSS1DI
1
C97 C96 C113 R19 H15 1000P 0.01U 0.01U 0805 0402 0402 D6 AE21
VDDCI_1 VDDR1_31 VSS_45 VSS2DI
1
0402 0402 0402 6.3V +80-20% +80-20%
2
C79 1000P 0.01U 0.1U T12 H17 D9
0402 0402 0402 VDDCI_2 VDDR1_32 +/-20% +80-20% +80-20% 10% 50V 50V VSS_46
2
iT ial
10U W16 H19 F27 F19
0805 +/-20% +80-20% VDD_MEM_IO
+80-20% VDDCI_3 VDDR1_33 50V 50V 50V VSS_47 VSSRH0
2
H22 G12 M6
6.3V 50V 50V 50V VDDR1_34 VSS_48 VSSRH1
2
D13 J1 G16
10% VDDR1_53 VDDR1_35 L709 120Z/100M VSS_49
D19 J23 G18 AG13
VDDR1_54 VDDR1_36 VSS_50 TXVSSR_0
N4 J24 1 2 VDD_MEMPLL1.8 G21 AG14
VDDR1_55 VDDR1_37 GND VSS_51 TXVSSR_1
T4 J4 G24 AH12
VDDR1_56 VDDR1_38 VSS_52 TXVSSR_2
1
AB4 J7 VDD_MEM_IO 2012 C736 C738 C737 G9
VSS_119 VDDR1_39 VSS_53
M t
GND D10 J8 10U 0.1U 0.1U H12 AE16
VSS_120 VDDR1_40 0805 0402 0402 VSS_54 LVSSR_0
D25 L27 H14 AE19
VSS_121 VDDR1_41 6.3V +80-20% +80-20% VSS_55 LVSSR_1
2
E4 L8 H16 AF15
VSS_122 VDDR1_42 10% 50V 50V VSS_56 LVSSR_2
M4 GND H18 AF20
VDDR1_43 VSS_57 LVSSR_3
1
1
VDD_MCLK2.5 F18 N7 C75 C76 C66 C118 C84 H21
VDDRH0 VDDR1_44 VSS_58
N6 N8 0.1U 1000P 0.01U 0.1U 10U H23 AJ19
n
VDDRH1 VDDR1_45 0402 0402 0402 0402 0805 +2.5V_M10 VSS_59 LPVSS
R1 H27 A6
VDDR1_46 +80-20% +/-20% +80-20% +80-20% 6.3V VSS_60 MPVSS
2
2
VDDDI_1.8 AE24 R4 H4 AJ28
VDD1DI VDDR1_47 50V 50V 50V 50V 10% L31 120Z/100M VSS_61 PVSS
AE22 T7 H8 AJ12
e
B VDD2DI VDDR1_48 VSS_62 TPVSS B
T8 1 2 VDD_DAC2.5 H9
VDDR1_49 2012 VSS_63
VDD_PNLIO1.8 AF13 V4 K1 U23
TXVDDR_0 VDDR1_50 VSS_64 VSS_123
1
AF14 V7 +3V C112 C116 C115 K23
TXVDDR_1 VDDR1_51 VSS_65
V8 10U 0.1U 0.1U K24 AH22
id
VDDR1_52 GND 0805 0402 0402 VSS_66 A2VSSN_0
AE15 K27 AJ21
LVDDR_18_0 6.3V +80-20% +80-20% VSS_67 A2VSSN_1
2
AF21 AC19 K30
LVDDR_18_1 VDDR3_0 10% 50V 50V VSS_68
AC21 K7 AF23
VDDR3_1 VSS_69 A2VSSQ
f
AE17 AC22 K8
CONNECT LVDDR_25 TO 1.8V FOR M9 VDD_PNLIO2.5 LVDDR_25_0 VDDR3_2 VSS_70
2
AE20 AC8 C55 C44 L30 120Z/100M L4 AH23

LVDDR_25_1 VDDR3_3 R55 VSS_71 AVSSN
, TO 2.5V FOR M10 AD19 10U 1000P 1 2 VDD_PNLIO2.5 M16
VDDR3_4 0805 0402 VSS_72
AJ20 AD21 M30 AD24
LPVDD VDDR3_5 VSS_73 AVSSQ
1
0
n
6.3V +/-20% 2012
2
VDD_MEMPLL1.8 A7 AD22 C92 C103 C102 M7

MPVDD VDDR3_6 0805 10% 50V VSS_74
VDD_PLL1.8 AK28 AD7 GND 10U 0.1U 0.1U M8
PVDD VDDR3_7 0805 0402 0402 VSS_75
1
VDD_PNLPLL1.8 AK12
TPVDD
o
6.3V +80-20% +80-20%
2
AC10 MOBILITY-M10-P
VDDR4_0 10% 50V 50V
VDD_DAC2.5 AG21 AC9 BGA644_64_1MM
A2VDD_0 VDDR4_1
AH21 AD10
A2VDD_1 VDDR4_2 VDD_MEM_IO
AD9
C
VDDR4_3
AF22 AG7
A2VDDQ_1.8 A2VDDQ VDDR4_4 GND
AH24
AVDD_1.8 AVDD L26 120Z/100M
MOBILITY-M10-P 1 2 GND
VDD_MCLK2.5
BGA644_64_1MM 2012
1
C50 C54 C105
10U 0.1U 0.1U
0805 0402 0402
6.3V +80-20% +80-20%
2
10% 50V 50V
+2.5V_M10 VDD_MEM_IO
L27 120Z/100M GND

1 2
2012
L24 120Z/100M
1 2
2012 +1.5V
A A
L40 120Z/100M
+1.8V 1 2 AGP_VDDQ
2012
L705 120Z/100M/NA
1 2 L33 120Z/100M
2012 1 2 VDD_CORE1.5
2012
1
C121 C134 1 C135

10U 0.1U 0.1U
0805 0402 0402
6.3V +80-20% +80-20% Title
2
10% 50V 50V 8050D MOTHER B/D

Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
GND
5 4 3 2 1

5 4 3 2 1
MEMA_MD0
MEMA_MD1
MEMA_MD2
L25
L26
U710B
DQA0
DQA1
MAA0
MAA1
E22
B22
MEMA_MA0
MEMA_MA1
MEMA_MA2
ATI M10-P(3/4) MEMA_MD0 RP23 VMDA0
VMDA[0..63]
VMDA[0..63] 10
K25 B23 1 8
MEMA_MD3 DQA2 MAA2 MEMA_MA3 MEMA_MD1 24*4 VMDA1
K26 B24 2 7
MEMA_MD4 DQA3 MAA3 MEMA_MA4 MEMA_MD2 1206 VMDA2 VDQMA#[0..7]
J26 C23 3 6 VDQMA#[0..7] 10
MEMA_MD5 DQA4 MAA4 MEMA_MA5 MEMA_MD3 VMDA3
H25 C22 4 5
MEMA_MD6 DQA5 MAA5 MEMA_MA6 MEMA_MD4 RP24 VMDA4 MEMA_DQM#0 R108 24 5% 0402 VDQMA#0
H26 F22 1 8 1 2
MEMA_MD7 DQA6 MAA6 MEMA_MA7 MEMA_MD5 24*4 VMDA5 MEMA_DQM#1 R93 24 5% 0402 VDQMA#1
G26 F21 2 7 1 2
MEMA_MD8 DQA7 MAA7 MEMA_MA8 MEMA_MD6 1206 VMDA6 MEMA_DQM#2 R92 24 5% 0402 VDQMA#2
G30 C21 3 6 1 2
MEMA_MD9 DQA8 MAA8 MEMA_MA9 MEMA_MD7 VMDA7 MEMA_DQM#3 R107 24 5% 0402 VDQMA#3
D29 A24 4 5 1 2
MEMA_MD10 DQA9 MAA9 MEMA_MA10 MEMA_MD8 RP18 VMDA8 MEMA_DQM#4 R719 24 5% 0402 VDQMA#4
D28 C24 1 8 1 2
MEMA_MD11 DQA10 MAA10 MEMA_MA11 MEMA_MD9 24*4 VMDA9 MEMA_DQM#5 R729 24 5% 0402 VDQMA#5
E28 A25 2 7 1 2
MEMA_MD12 DQA11 MAA11 MEMA_MA12 MEMA_MD10 1206 VMDA10 MEMA_DQM#6 R730 24 5% 0402 VDQMA#6
E29 E21 3 6 1 2
MEMA_MD13 DQA12 MAA12 MEMA_MA13 MEMA_MD11 VMDA11 MEMA_DQM#7 R718 24 5% 0402 VDQMA#7 VQSA[0..7]
G29 B20 4 5 1 2 VQSA[0..7] 10
MEMA_MD14 DQA13 MAA13 MEMA_MD12 RP20 VMDA12
G28 C19 1 8
D
MEMA_MD15 DQA14 MAA14 MEMA_MD13 24*4 VMDA13 MEMA_QSA0 R109 24 5% 0402 VQSA0
D
F28 2 7 1 2
MEMA_MD16 DQA15 MEMA_DQM#0 MEMA_MD14 1206 VMDA14 MEMA_QSA1 R91 24 5% 0402 VQSA1
G25 J25 3 6 1 2
MEMA_MD17 DQA16 DQMA#0 MEMA_DQM#1 MEMA_MD15 VMDA15 MEMA_QSA2 R90 24 5% 0402 VQSA2
F26 F29 4 5 1 2
MEMA_MD18 DQA17 DQMA#1 MEMA_DQM#2 MEMA_MD16 RP19 VMDA16 MEMA_QSA3 R106 24 5% 0402 VQSA3
E26 E25 1 8 1 2
MEMA_MD19 DQA18 DQMA#2 MEMA_DQM#3 MEMA_MD17 24*4 VMDA17 MEMA_QSA4 R720 24 5% 0402 VQSA4
F25 A27 2 7 1 2
MEMA_MD20 DQA19 DQMA#3 MEMA_DQM#4 MEMA_MD18 1206 VMDA18 MEMA_QSA5 R731 24 5% 0402 VQSA5
E24 F15 3 6 1 2
MEMA_MD21 DQA20 DQMA#4 MEMA_DQM#5 MEMA_MD19 VMDA19 MEMA_QSA6 R732 24 5% 0402 VQSA6
F23 C15 4 5 1 2
MEMA_MD22 DQA21 DQMA#5 MEMA_DQM#6 MEMA_MD20 RP17 VMDA20 MEMA_QSA7 R717 24 5% 0402 VQSA7
E23 C11 1 8 1 2
MEMA_MD23 DQA22 DQMA#6 MEMA_DQM#7 MEMA_MD21 24*4 VMDA21
D22 E11 2 7
MEMA_MD24 DQA23 DQMA#7 MEMA_MD22 1206 VMDA22
B29 3 6
MEMA_MD25 DQA24 MEMA_QSA0 MEMA_MD23 VMDA23
C29 J27 4 5
MEMA_MD26 DQA25 QSA0 MEMA_QSA1 MEMA_MD24 RP21 VMDA24
C25 F30 1 8
MEMA_MD27 DQA26 QSA1 MEMA_QSA2 MEMA_MD25 24*4 VMDA25 VMA[0..13]
C27 F24 2 7 VMA[0..13] 10
MEMA_MD28 DQA27 QSA2 MEMA_QSA3 MEMA_MD26 1206 VMDA26 RP15
B28 B27 3 6 1 16
MEMA_MD29 DQA28 QSA3 MEMA_QSA4 MEMA_MD27 VMDA27 MEMA_MA12 0*8 VMA12
B25 E16 4 5 2 15
MEMA_MD30 DQA29 QSA4 MEMA_QSA5 MEMA_MD28 RP22 VMDA28 MEMA_MA13 RPX8 VMA13
C26 B16 1 8 3 14
MEMA_MD31 DQA30 QSA5 MEMA_QSA6 MEMA_MD29 24*4 VMDA29 MEMA_MA0 VMA0
B26 B11 2 7 4 13
MEMA_MD32 DQA31 QSA6 MEMA_QSA7 MEMA_MD30 1206 VMDA30 MEMA_MA2 VMA2
F17 F10 3 6 5 12
MEMA_MD33 DQA32 QSA7 MEMA_MD31 VMDA31 MEMA_MA1 VMA1
E17 4 5 6 11
MEMA_MD34 DQA33
D16 A19 MEMA_RAS# MEMA_MD32 1 RP706 8 VMDA32 MEMA_MA10 7 10 VMA10
MEMA_MD35 DQA34 RASA# MEMA_MD33 24*4 VMDA33 MEMA_MA3 VMA3
F16 2 7 8 9
MEMA_MD36 DQA35
E15 E18 MEMA_CAS# MEMA_MD34 3 1206 6 VMDA34 MEMA_MA11 1 RP14 16 VMA11
MEMA_MD37 DQA36 CASA# MEMA_MD35 VMDA35 MEMA_MA4 0*8 VMA4
F14 4 5 2 15
MEMA_MD38 DQA37
E14 E19 MEMA_WE# MEMA_MD36 1 RP709 8 VMDA36 MEMA_MA9 3 RPX8 14 VMA9
MEMA_MD39 DQA38 WEA# MEMA_MD37 24*4 VMDA37 MEMA_MA6 VMA6
F13 2 7 4 13
MEMA_MD40 DQA39
C17 E20 MEMA_CS0# MEMA_MD38 3 1206 6 VMDA38 MEMA_MA5 5 12 VMA5
MEMA_MD41 DQA40 CSA0# C751 1 MEMA_MD39 VMDA39 MEMA_MA7 VMA7
B18 2 470P GND 4 5 6 11
MEMA_MD42 DQA41
B17 F20 MEMA_CS1# 0402 50V 10% MEMA_MD40 1 RP716 8 VMDA40 MEMA_MA8 7 10 VMA8
MEMA_MD43 DQA42 CSA1# R760 1 56 R758 1 56 MEMA_MD41 24*4 VMDA41 MEMA_CKE VCKEA
B15 2 2 2 7 8 9 VCKEA 10
MEMA_MD44 DQA43
C13 B19 MEMA_CKE 0402 5% 0402 5% MEMA_MD42 3 1206 6 VMDA42
t
MEMA_MD45 DQA44 CKEA MEMA_MD43 VMDA43
B14 4 5
MEMA_MD46 DQA45
C14 B21 MEMA_CLK0 R761 1 10 5% 2 0402 VCLKA0
VCLKA0 10
MEMA_MD44 1 RP713 8 VMDA44
MEMA_MD47 DQA46 CLKA0
C16 C20 MEMA_CLK0# R759 1 10 5% 2 0402 VCLKA#0
VCLKA#0 10
MEMA_MD45 2 24*4 7 VMDA45
DQA47 CLKA0#
t
MEMA_MD48 A13 MEMA_MD46 3 1206 6 VMDA46
n
MEMA_MD49 DQA48
A12 C18 MEMA_CLK1 R757 1 10 5% 2 0402 VCLKA1
VCLKA1 10
MEMA_MD47 4 5 VMDA47
MEMA_MD50 DQA49 CLKA1
C12 A18 MEMA_CLK1# R755 1 10 5% 2 0402 VCLKA#1
VCLKA#1 10
MEMA_MD48 1 RP714 8 VMDA48
DQA50 CLKA1#
e e
MEMA_MD51 B12 MEMA_MD49 2 24*4 7 VMDA49 MEMA_CAS# 1 RP16 8 VCASA#
MEMA_MD52 DQA51 DIMA_0 MEMA_MD50 VMDA50 MEMA_RAS# VRASA# VCASA# 10
C C10 D30 R756 1 56 2 R754 1 56 2 3 1206 6 2 0*4 7 C
MEMA_MD53 DQA52 DIMA_0 DIMA_1 MEMA_MD51 VMDA51 MEMA_CS0# VCSA#0 VRASA# 10
C9 B13 0402 5% 0402 5% 4 5 3 1206 6 VCSA#0 10
r
MEMA_MD54 DQA53 DIMA_1 C742 1 MEMA_MD52 VMDA52 MEMA_WE# VWEA#
B9 2 470P GND 1 RP717 8 4 5 VWEA# 10
MEMA_MD55 DQA54 0402 50V 10% MEMA_MD53 24*4 VMDA53
B10 2 7
MEMA_MD56 DQA55 TP17 MEMA_MD54 1206 VMDA54
E13 AE25 1 3 6
c m
MEMA_MD57 DQA56 PLLTEST MEMA_MD55 VMDA55
E12 4 5
MEMA_MD58 DQA57 R787 1 0 MEMA_MD56 VMDA56
E10 AG29 2 5% GND 1 RP708 8
MEMA_MD59 DQA58 RSTB_MSK 0402G_DFS MEMA_MD57 24*4 VMDA57 DIMA_0 R89 1 0/NA 2 0402 VDIMA_0
F12 2 7 VDIMA_0 10
e
MEMA_MD60 DQA59 R45 MEMA_MD58 VMDA58 DIMA_1 VDIMA_1
F11 AG4 1 1K 1% 2 0402 +3V 3 1206 6 R746 1 0/NA 2 0402
VDIMA_1 10
MEMA_MD61 DQA60 VREFG MEMA_MD59 VMDA59 MEMA_CS1# R80 1 0/NA 2 0402 VCSA#1
E9 4 5 VCSA#1 10
DQA61
u
MEMA_MD62 F9 AE10 R81 1 0 2 0402 R44 1 1K 1% 2 0402 MEMA_MD60 1 RP705 8 VMDA60
DQA62 DVOVMODE GND GND
S
MEMA_MD63 F8 AE11 VGA_THERMDC MEMA_MD61 2 24*4 7 VMDA61
DQA63 DMINUS VGA_THERMDA VGA_THERMDC 22 MEMA_MD62 VMDA62
AF11 3 1206 6
DPLUS VGA_THERMDA 22
c
MEMA_MD63 4 5 VMDA63
AB26 R98 1 0 2 5%
DBI_LO AGP_VDDQ
c Do
AB25 0402G_DFS
DBI_HI R97 0
1 2 5%
MOBILITY-M10-P 0402G_DFS
BGA644_64_1MM
a
VMDB[0..63]
U710C VMDB[0..63] 10
MEMB_MD0 MEMB_MA0 MEMB_MD0 RP9 VMDB0
iT ial
D7 N5 1 8
MEMB_MD1 DQB0 MAB0 MEMB_MA1 MEMB_MD1 24*4 VMDB1
F7 M1 2 7
MEMB_MD2 DQB1 MAB1 MEMB_MA2 MEMB_MD2 1206 VMDB2
E7 M3 3 6
MEMB_MD3 DQB2 MAB2 MEMB_MA3 MEMB_MD3 VMDB3
G6 L3 4 5
MEMB_MD4 DQB3 MAB3 MEMB_MA4 MEMB_MD4 RP11 VMDB4 VDQMB#[0..7]
G5 L2 1 8 VDQMB#[0..7] 10
MEMB_MD5 DQB4 MAB4 MEMB_MA5 MEMB_MD5 24*4 VMDB5
F5 M2 2 7
MEMB_MD6 DQB5 MAB5 MEMB_MA6 MEMB_MD6 1206 VMDB6 MEMB_DQM#0 R40 24 5% 0402 VDQMB#0
E5 M5 3 6 1 2
MEMB_MD7 DQB6 MAB6 MEMB_MA7 MEMB_MD7 VMDB7 MEMB_DQM#1
M t
C4 P6 4 5 R29 1 24 5% 2 0402 VDQMB#1
MEMB_MD8 DQB7 MAB7 MEMB_MA8 MEMB_MD8 RP4 VMDB8 MEMB_DQM#2 R38 24 5% 0402 VDQMB#2
B5 N3 1 8 1 2
MEMB_MD9 DQB8 MAB8 MEMB_MA9 MEMB_MD9 24*4 VMDB9 MEMB_DQM#3 R35 24 5% 0402 VDQMB#3
C5 K2 2 7 1 2
MEMB_MD10 DQB9 MAB9 MEMB_MA10 MEMB_MD10 1206 VMDB10 MEMB_DQM#4 R724 24 5% 0402 VDQMB#4
A4 K3 3 6 1 2
MEMB_MD11 DQB10 MAB10 MEMB_MA11 MEMB_MD11 VMDB11 MEMB_DQM#5 R710 24 5% 0402 VDQMB#5
B4 J2 4 5 1 2
MEMB_MD12 DQB11 MAB11 MEMB_MA12 MEMB_MD12 RP3 VMDB12 MEMB_DQM#6 R722 24 5% 0402 VDQMB#6
C2 P5 1 8 1 2
n
MEMB_MD13 DQB12 MAB12 MEMB_MA13 MEMB_MD13 24*4 VMDB13 MEMB_DQM#7 R716 24 5% 0402 VDQMB#7 VQSB[0..7]
D3 P3 2 7 1 2 VQSB[0..7] 10
MEMB_MD14 DQB13 MAB13 MEMB_MD14 1206 VMDB14
D1 P2 3 6
MEMB_MD15 DQB14 MAB14 MEMB_MD15 VMDB15 MEMB_QSA0 R41 24 5% 0402 VQSB0
D2 4 5 1 2
e
B
MEMB_MD16 DQB15 MEMB_DQM#0 MEMB_MD16 RP12 VMDB16 MEMB_QSA1 R30 24 5% 0402 VQSB1
B
G4 E6 1 8 1 2
MEMB_MD17 DQB16 DQMB#0 MEMB_DQM#1 MEMB_MD17 24*4 VMDB17 MEMB_QSA2 R39 24 5% 0402 VQSB2
H6 B2 2 7 1 2
MEMB_MD18 DQB17 DQMB#1 MEMB_DQM#2 MEMB_MD18 1206 VMDB18 MEMB_QSA3 R33 24 5% 0402 VQSB3
H5 J5 3 6 1 2
MEMB_MD19 DQB18 DQMB#2 MEMB_DQM#3 MEMB_MD19 VMDB19 MEMB_QSA4 R723 24 5% 0402 VQSB4
J6 G3 4 5 1 2
id
MEMB_MD20 DQB19 DQMB#3 MEMB_DQM#4 MEMB_MD20 RP13 VMDB20 MEMB_QSA5 R709 24 5% 0402 VQSB5
K5 W6 1 8 1 2
MEMB_MD21 DQB20 DQMB#4 MEMB_DQM#5 MEMB_MD21 24*4 VMDB21 MEMB_QSA6 R721 24 5% 0402 VQSB6
K4 W2 2 7 1 2
MEMB_MD22 DQB21 DQMB#5 MEMB_DQM#6 MEMB_MD22 1206 VMDB22 MEMB_QSA7 R715 24 5% 0402 VQSB7
L6 AC6 3 6 1 2
DQB22 DQMB#6
f
MEMB_MD23 L5 AD2 MEMB_DQM#7 MEMB_MD23 4 5 VMDB23
MEMB_MD24 DQB23 DQMB#7 MEMB_MD24 RP5 VMDB24
G2 1 8
MEMB_MD25 DQB24 MEMB_QSA0 MEMB_MD25 24*4 VMDB25 VMB[0..13]
F3 F6 2 7 VMB[0..13] 10
MEMB_MD26 DQB25 QSB0 MEMB_QSA1 MEMB_MD26 1206 VMDB26 RP8
H2 B3 3 6 1 16
DQB26 QSB1
n
MEMB_MD27 E2 K6 MEMB_QSA2 MEMB_MD27 4 5 VMDB27 MEMB_MA12 2 0*8 15 VMB12
MEMB_MD28 DQB27 QSB2 MEMB_QSA3 MEMB_MD28 RP7 VMDB28 MEMB_MA13 RPX8 VMB13
F2 G1 1 8 3 14
MEMB_MD29 DQB28 QSB3 MEMB_QSA4 MEMB_MD29 24*4 VMDB29 MEMB_MA0 VMB0
J3 V5 2 7 4 13
DQB29 QSB4
o
MEMB_MD30 F1 W1 MEMB_QSA5 MEMB_MD30 3 1206 6 VMDB30 MEMB_MA2 5 12 VMB2
MEMB_MD31 DQB30 QSB5 MEMB_QSA6 MEMB_MD31 VMDB31 MEMB_MA1 VMB1
H3 AC5 4 5 6 11
MEMB_MD32 DQB31 QSB6 MEMB_QSA7 MEMB_MD32 RP707 VMDB32 MEMB_MA10 VMB10
U6 AD1 1 8 7 10
MEMB_MD33 DQB32 QSB7 MEMB_MD33 24*4 VMDB33 MEMB_MA3 VMB3
U5 2 7 8 9
C
MEMB_MD34 DQB33 MEMB_RAS# MEMB_MD34 1206 VMDB34 MEMB_MA11 RP6 VMB11
U3 R2 3 6 1 16
MEMB_MD35 DQB34 RASB# MEMB_MD35 VMDB35 MEMB_MA4 0*8 VMB4
V6 4 5 2 15
MEMB_MD36 DQB35 MEMB_CAS# MEMB_MD36 RP712 VMDB36 MEMB_MA9 RPX8 VMB9
W5 T5 1 8 3 14
MEMB_MD37 DQB36 CASB# MEMB_MD37 24*4 VMDB37 MEMB_MA6 VMB6
W4 2 7 4 13
MEMB_MD38 DQB37 MEMB_WE# MEMB_MD38 1206 VMDB38 MEMB_MA5 VMB5
Y6 T6 3 6 5 12
MEMB_MD39 DQB38 WEB# MEMB_MD39 VMDB39 MEMB_MA7 VMB7
Y5 4 5 6 11
MEMB_MD40 DQB39 MEMB_CS0# MEMB_MD40 RP701 VMDB40 MEMB_MA8 VMB8
U2 R5 1 8 7 10
MEMB_MD41 DQB40 CSB0# C729 1 MEMB_MD41 VMDB41 MEMB_CKE VCKEB
V2 2 470P GND 2 24*4 7 8 9 VCKEB 10
MEMB_MD42 DQB41 MEMB_CS1# 0402 50V 10% MEMB_MD42 1206 VMDB42
V1 R6 3 6
MEMB_MD43 DQB42 CSB1# R726 1 56 R725 1 56 MEMB_MD43 VMDB43
V3 2 2 4 5
MEMB_MD44 DQB43 MEMB_CKE 0402 5% 0402 5% MEMB_MD44 RP702 VMDB44
W3 R3 1 8
MEMB_MD45 DQB44 CKEB MEMB_MD45 24*4 VMDB45 MEMB_CAS# RP10 VCASB#
Y2 2 7 1 8 VCASB# 10
MEMB_MD46 DQB45 R728 1 10 5% 2 0402 VCLKB0 MEMB_MD46 1206 VMDB46 MEMB_RAS# 0*4 VRASB#
Y3 N1 VCLKB0 10 3 6 2 7 VRASB# 10
MEMB_MD47 DQB46 CLKB0 R727 1 10 5% 2 0402 VCLKB#0 MEMB_MD47 VMDB47 MEMB_CS0# 1206 VCSB#0
AA2 N2 VCLKB#0 10 4 5 3 6 VCSB#0 10
MEMB_MD48 DQB47 CLKB0# MEMB_MD48 RP711 VMDB48 MEMB_WE# VWEB#
AA6 1 8 4 5 VWEB# 10
MEMB_MD49 DQB48 R50 MEMB_MD49 VMDB49
AA5 T2 1 10 5% 2 0402 VCLKB1
VCLKB1 10 2 24*4 7
MEMB_MD50 DQB49 CLKB1 R51 MEMB_MD50 VMDB50
AB6 T3 1 10 5% 2 0402 VCLKB#1
VCLKB#1 10 3 1206 6
MEMB_MD51 DQB50 CLKB1# R42 R43 MEMB_MD51 VMDB51 DIMB_0 R31 1 0/NA 2 0402 VDIMB_0
AB5 4 5 VDIMB_0 10
MEMB_MD52 DQB51 DIMB_0 MEMB_MD52 VMDB52 DIMB_1 VDIMB_1
AD6 E3 1 56 2 1 56 2 1 RP710 8 R711 1 0/NA 2 0402
VDIMB_1 10
MEMB_MD53 DQB52 DIMB_0 DIMB_1 0402 5% 0402 5% MEMB_MD53 24*4 VMDB53 MEMB_CS1# R36 1 0/NA 2 0402 VCSB#1
A AD5 AA3 2 7 VCSB#1 10
A
MEMB_MD54 DQB53 DIMB_1 C41 1 VMDB54
AE5 2 470P GND
MEMB_MD54 3 1206 6
MEMB_MD55 DQB54 0402 50V 10% VDD_MEM_IO MEMB_MD55 VMDB55
AE4 4 5
MEMB_MD56 DQB55 MEMB_MD56 VMDB56
AB2 B7 1 R740 2 1 RP703 8
MEMB_MD57 DQB56 MVREFD MEMB_MD57 VMDB57
AB3 B8 R747 1 0 2 5% 1 R741 2 VDD_MEM_IO
1K 0402 1% 2 24*4 7
MEMB_MD58 DQB57 MVREFS 0402G_DFS 0402 5% 1K 0402 1% MEMB_MD58 VMDB58
AC2 1 R736 2 3 1206 6
MEMB_MD59 DQB58 R69 MEMB_MD59 VMDB59
AC3 C6 1 4.7K 2 VDD_CORE1.8 1 R745 2 1K 0402 1% 4 5
MEMB_MD60 DQB59 MEMVMODE0 R74 MEMB_MD60 VMDB60
AD3 C7 1 4.7K/NA 2 1K 0402 1% C732 1 2 0.1U GND 1 RP704 8
MEMB_MD61 DQB60 MEMVMODE1 0402 5% C735 MEMB_MD61 VMDB61
AE1 1 2 0.1U GND
0402 50V +80-20% 2 24*4 7
MEMB_MD62 DQB61 0402 50V +80-20% MEMB_MD62 1206 VMDB62
AE2 3 6
DQB62
1
MEMB_MD63 AE3 C8 C730 6.3V MEMB_MD63 4 5 VMDB63

DQB63 MEMTEST
1
R75 R70 C731 6.3V 1 2

R750 4.7K 4.7K/NAFOR 2.5V VDDR1 1 2 10U 0805 10% Title
MOBILITY-M10-P 0402 0402 MEMVMODE=1.8V
47 10U 0805 10% 8050D MOTHER B/D
BGA644_64_1MM 5% 5% MEMVMODE1=GND
0402
5% FOR 1.8V VDDR1(ELPIDA) Size Rev
2
Document
MEMVMODE=GND C PCB 316680900001/ASSY 411682700001 R01
2
MEMVMODE1=1.8V Number
GND GND Date: Wednesday, December 31, 2003 Sheet 9 of 34
5 4 3 2 1

5 4 3 2 1
VMDA[0..63]
VMDA[0..63] 9 VMDB[0..63]
VMDB[0..63] 9
VDQMA#[0..7]
VQSA[0..7]
VDQMA#[0..7]
VQSA[0..7]
9
9
VRAM VDQMB#[0..7]
VQSB[0..7]
VDQMB#[0..7] 9
VMA[0..13] VQSB[0..7] 9
VMA[0..13] 9 VMB[0..13]
VMB[0..13] 9
U3 U709 U1 U708
VMA0 M4 A6 VMDA0 VMA0 M4 A6 VMDA32 VMB0 M4 A6 VMDB0 VMB0 M4 A6 VMDB32
VMA1 A0 DQ0 VMDA1 VMA1 A0 DQ0 VMDA33 VMB1 A0 DQ0 VMDB1 VMB1 A0 DQ0 VMDB33
M5 B5 M5 B5 M5 B5 M5 B5
L5 A5 L5 A5 L5 A5 L5 A5
M6 A4 M6 A4 M6 A4 M6 A4
M7 B1 M7 B1 M7 B1 M7 B1
L8 C2 L8 C2 L8 C2 L8 C2
M8 C1 M8 C1 M8 C1 M8 C1
D
VMA7 A6 DQ6 VMDA7 VMA7 A6 DQ6 VMDA39 VMB7 A6 DQ6 VMDB7 VMB7 A6 DQ6 VMDB39 D
M9 D1 M9 D1 M9 D1 M9 D1
VMA8 A7 DQ7 VQSA0 VMA8 A7 DQ7 VQSA4 VMB8 A7 DQ7 VQSB0 VMB8 A7 DQ7 VQSB4
M10 A1 M10 A1 M10 A1 M10 A1
VMA12 A8/AP DQS0 VMA12 A8/AP DQS0 VMB12 A8/AP DQS0 VMB12 A8/AP DQS0
M3 M3 M3 M3
VMA13 BA0 VMDA8 VMA13 BA0 VMDA40 VMB13 BA0 VMDB8 VMB13 BA0 VMDB40
L4 J12 L4 J12 L4 J12 L4 J12
VMA9 BA1 DQ8 VMDA9 VMA9 BA1 DQ8 VMDA41 VMB9 BA1 DQ8 VMDB9 VMB9 BA1 DQ8 VMDB41
L7 J11 L7 J11 L7 J11 L7 J11
K5 H12 K5 H12 K5 H12 K5 H12
L6 H11 L6 H11 L6 H11 L6 H11
VDQMA#0 A11 DQ11 VMDA12 VDQMA#4 A11 DQ11 VMDA44 VDQMB#0 A11 DQ11 VMDB12 VDQMB#4 A11 DQ11 VMDB44
A2 F12 A2 F12 A2 F12 A2 F12
VDQMA#1 DQM0 DQ12 VMDA13 VDQMA#5 DQM0 DQ12 VMDA45 VDQMB#1 DQM0 DQ12 VMDB13 VDQMB#5 DQM0 DQ12 VMDB45
G11 F11 G11 F11 G11 F11 G11 F11
G2 E12 G2 E12 G2 E12 G2 E12
A11 E11 A11 E11 A11 E11 A11 E11
VRASA# DQM3 DQ15 VQSA1 VRASA# DQM3 DQ15 VQSA5 VRASB# DQM3 DQ15 VQSB1 VRASB# DQM3 DQ15 VQSB5
9 VRASA# L1 G12 9 VRASA# L1 G12 9 VRASB# L1 G12 9 VRASB# L1 G12
VCASA# RAS DQS1 VCASA# RAS DQS1 VCASB# RAS DQS1 VCASB# RAS DQS1
9 VCASA# K1 9 VCASA# K1 9 VCASB# K1 9 VCASB# K1
VWEA# CAS VMDA16 VWEA# CAS VMDA48 VWEB# CAS VMDB16 VWEB# CAS VMDB48
9 VWEA# K2 E2 9 VWEA# K2 E2 9 VWEB# K2 E2 9 VWEB# K2 E2
VCSA#0 WE DQ16 VMDA17 VCSA#0 WE DQ16 VMDA49 VCSB#0 WE DQ16 VMDB17 VCSB#0 WE DQ16 VMDB49
9 VCSA#0 M1 E1 9 VCSA#0 M1 E1 9 VCSB#0 M1 E1 9 VCSB#0 M1 E1
VCLKA0 CS DQ17 VMDA18 VCLKA1 CS DQ17 VMDA50 VCLKB0 CS DQ17 VMDB18 VCLKB1 CS DQ17 VMDB50
9 VCLKA0 L10 F2 9 VCLKA1 L10 F2 9 VCLKB0 L10 F2 9 VCLKB1 L10 F2
VCLKA#0 CK DQ18 VMDA19 VCLKA#1 CK DQ18 VMDA51 VCLKB#0 CK DQ18 VMDB19 VCLKB#1 CK DQ18 VMDB51
9 VCLKA#0 L11 F1 9 VCLKA#1 L11 F1 9 VCLKB#0 L11 F1 9 VCLKB#1 L11 F1
VCKEA CK# DQ19 VMDA20 VCKEA CK# DQ19 VMDA52 VCKEB CK# DQ19 VMDB20 VCKEB CK# DQ19 VMDB52
9 VCKEA M11 H2 9 VCKEA1 M11 H2 9 VCKEB M11 H2 9 VCKEB M11 H2
CKE DQ20 VMDA21 CKE DQ20 VMDA53 CKE DQ20 VMDB21 CKE DQ20 VMDB53
H1 H1 H1 H1
VDD_MEM_IOREFM12 DQ21 VMDA22 VDD_MEM_IOREFM12 DQ21 VMDA54 VDD_MEM_IOREFM12 DQ21 VMDB22 VDD_MEM_IOREFM12 DQ21 VMDB54
J1 J1 J1 J1
VREF DQ22 VMDA23 VREF DQ22 VMDA55 VREF DQ22 VMDB23 VREF DQ22 VMDB55
L12 J2 L12 J2 L12 J2 L12 J2
MCL DQ23 VQSA2 MCL DQ23 VQSA6 MCL DQ23 VQSB2 MCL DQ23 VQSB6
M2 G1 M2 G1 M2 G1 M2 G1
NC1 DQS2 NC1 DQS2 NC1 DQS2 NC1 DQS2
B3 B3 B3 B3
GND NC2 VMDA24 GND NC2 VMDA56 GND NC2 VMDB24 GND NC2 VMDB56
B10 D12 B10 D12 B10 D12 B10 D12
NC3 DQ24 VMDA25 NC3 DQ24 VMDA57 NC3 DQ24 VMDB25 NC3 DQ24 VMDB57
G3 C12 G3 C12 G3 C12 G3 C12
G10 C11 G10 C11 G10 C11 G10 C11
9 VDIMA_0 K11 B12 9 VDIMA_1 K11 B12 9 VDIMB_0 K11 B12 9 VDIMB_1 K11 B12
K12 A9 K12 A9 K12 A9 K12 A9
L2 A8 L2 A8 L2 A8 L2 A8
VCSA#1 NC8 DQ29 VMDA30 VCSA#1 NC8 DQ29 VMDA62 VCSB#1 NC8 DQ29 VMDB30 VCSB#1 NC8 DQ29 VMDB62
L3 B8 L3 B8 L3 B8 L3 B8
t
9 VCSA#1 NC9 DQ30 VMDA31 9 VCSA#1 NC9 DQ30 VMDA63 9 VCSB#1 NC9 DQ30 9 VCSB#1 NC9 DQ30 VMDB63
A7 A7 A7 VMDB31 A7
DQ31 VQSA3 DQ31 VQSA7 DQ31 VQSB3 DQ31 VQSB7
G7 A12 G7 A12 G7 A12 G7 A12
VSS/TH1 DQS3 VSS/TH1 DQS3 VSS/TH1 DQS3 VSS/TH1 DQS3
G8 G8 G8 G8
VSS/TH2 VSS/TH2 VSS/TH2 VSS/TH2
t
H5 K8 H5 K8 H5 K8 H5 K8
n
VSS/TH3 A12/RFU1 VSS/TH3 A12/RFU1 VSS/TH3 A12/RFU1 VSS/TH3 A12/RFU1
H6 L9 H6 L9 H6 L9 H6 L9
VSS/TH4 BA2/RFU2 VSS/TH4 BA2/RFU2 VSS/TH4 BA2/RFU2 VSS/TH4 BA2/RFU2
H7 H7 H7 H7
e e
H8 H8 H8 H8
C G5 G5 G5 G5 C
G6 G6 G6 G6
r
E5 E5 E5 E5
E6 E6 E6 E6
E7 E7 E7 E7
c m
E8 E8 E8 E8
F5 F5 F5 F5
F6 F6 F6 F6
e
F7 F7 F7 F7
F8 F8 F8 F8
u
+2.5V_M10 +2.5V_M10 +2.5V_M10 +2.5V_M10
S
D6 D6 D6 D6
VSS_0 VSS_0 VSS_0 VSS_0
D7 C6 D7 C6 D7 C6 D7 C6
VSS_1 VDD_0 VSS_1 VDD_0 VSS_1 VDD_0 VSS_1 VDD_0
c
D9 C7 D9 C7 D9 C7 D9 C7
J5 D3 J5 D3 J5 D3 J5 D3
c Do
J6 D10 J6 D10 J6 D10 J6 D10
J7 K3 J7 K3 J7 K3 J7 K3
J8 K6 J8 K6 J8 K6 J8 K6
K4 K7 K4 K7 K4 K7 K4 K7
a
K9 K10 K9 K10 K9 K10 K9 K10
VSS_8 VDD_7 VDD_MEM_IO VSS_8 VDD_7 VDD_MEM_IO VSS_8 VDD_7 VDD_MEM_IO VSS_8 VDD_7 VDD_MEM_IO
D4 D4 D4 D4
VSS_9 VSS_9 VSS_9 VSS_9
C8 B2 C8 B2 C8 B2 C8 B2
VSSQ_0 VDDQ_0 VSSQ_0 VDDQ_0 VSSQ_0 VDDQ_0 VSSQ_0 VDDQ_0
iT ial
C9 B4 C9 B4 C9 B4 C9 B4
C10 B6 C10 B6 C10 B6 C10 B6
D5 B7 D5 B7 D5 B7 D5 B7
D8 B9 D8 B9 D8 B9 D8 B9
E4 B11 E4 B11 E4 B11 E4 B11
E9 D2 E9 D2 E9 D2 E9 D2
F4 D11 F4 D11 F4 D11 F4 D11
M t
F9 E3 F9 E3 F9 E3 F9 E3
G4 E10 G4 E10 G4 E10 G4 E10
G9 F3 G9 F3 G9 F3 G9 F3
H4 F10 H4 F10 H4 F10 H4 F10
H9 H3 H9 H3 H9 H3 H9 H3
J4 H10 J4 H10 J4 H10 J4 H10
n
J9 J3 J9 J3 J9 J3 J9 J3
A3 J10 A3 J10 A3 J10 A3 J10
C3 C3 C3 C3
e
B VSSQ_16 VSSQ_16 VSSQ_16 VSSQ_16 B
C4 C4 C4 C4
VSSQ_17 VSSQ_17 VSSQ_17 VSSQ_17
C5 C5 C5 C5
A10 A10 A10 A10
id
HY5DU2832222F HY5DU2832222F HY5DU2832222F HY5DU2832222F
BGA144F_08MM_1 BGA144F_08MM_1 BGA144F_08MM_1 BGA144F_08MM_1
GND GND GND GND
+2.5V_M10 +2.5V_M10
nf +2.5V_M10 +2.5V_M10
o
1
1
C750 C753 C744 C745 C59 C62 C45 C47 C724 C723 C720 C727 C32 C28 C36 C33
10U 1U 0.1U 0.01U 10U 1U 0.1U 0.01U 10U 1U 0.1U 0.01U 10U 1U 0.1U 0.01U
0805 0402 0402 0402 0805 0402 0402 0402 0805 0402 0402 0402 0805 0402 0402 0402
C
6.3V +80-20% 10% +80-20% 6.3V +80-20% 10% +80-20% 6.3V +80-20% 10% +80-20% 6.3V +80-20% 10% +80-20%
2
2
10% 10V 16V 50V 10% 10V 16V 50V 10% 10V 16V 50V 10% 10V 16V 50V
GND GND GND GND
VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO

1
1
C756 C748 C754 C752 C749 C49 C48 C63 C46 C51 C716 C721 C718 C725 C726 C37 C30 C35 C29 C34
10U 1U 0.1U 0.1U 0.01U 10U 1U 0.1U 0.1U 0.01U 10U 1U 0.1U 0.1U 0.01U 10U 1U 0.1U 0.1U 0.01U
0805 0402 0402 0402 0402 0805 0402 0402 0402 0402 0805 0402 0402 0402 0402 0805 0402 0402 0402 0402
6.3V +80-20% 10% 10% +80-20% 6.3V +80-20% 10% 10% +80-20% 6.3V +80-20% 10% 10% +80-20% 6.3V +80-20% 10% 10% +80-20%
2
2
10% 10V 16V 16V 50V 10% 10V 16V 16V 50V 10% 10V 16V 16V 50V 10% 10V 16V 16V 50V
GND GND GND GND

VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO
A A
1
1
R751 R65 R713 R34
1K 1K 1K 1K
0402 0402 0402 0402
1% 1% 1% 1%
VDD_MEM_IOREF VDD_MEM_IOREF VDD_MEM_IOREF VDD_MEM_IOREF
2
2
1
1
1
1
R753 C741 C740 R60 C65 C57 R712 C719 C722 R32 C27 C25
1K 0.1U 10U 1K 0.1U 10U 1K 0.1U 10U 1K 0.1U 10U
0402 0402 0805 0402 0402 0805 0402 0402 0805 0402 0402 0805
1% 10% 6.3V 1% 10% 6.3V 1% 10% 6.3V 1% 10% 6.3V Title
2
2
16V 10% 16V 10% 16V 10% 16V 10% 8050D MOTHER B/D
2
Size Document Rev

GND GND GND GND C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
FS2
X
FS1
0
FS0
0
CPU
166.66
3V66[5:0]
66.66
PCI*
33.33
CLOCK SYNTHERIZER ITP_CPU#
HCLK_CPU#
HCLK_MCH#
R871
R893
R891
1
1
1
2 49.9/NA 0402
2 49.9 0402 1%
2 49.9 0402 1%
ITP_CPU R870 1 2 49.9/NA 0402
001 X 0 1 100.00 66.66 33.33 HCLK_CPU R892 1 2 49.9 0402 1%
HCLK_MCH R890 1 2 49.9 0402 1% GND
X 1 0 200.00 66.66 33.33 C834 1 2 0402
10P/NA 50V +/-10%
X 1 1 133.33 66.66 33.33 Layout note: Place crystal within C833 1 2 0402
500 mils of CLK Gen. 10P/NA 50V +/-10%
Mid 0 0 Tristate Tristate Tristate C830 1 2 0402 GND
10P/NA 50V +/-10%
Mid 0 1 TCLK/2 TCLK/2 TCLK/2 U712 R895 2 33 10402 5% +3V +3VCLKCPU
SIO_48M 19
2 39 R877 2 33 10402 5%
X1 48MHZ_USB USBCLK_ICH 14
D
Mid 1 0 Reserved Reserved Reserved X703
48MHZ_DOT
38 R878 2 33 10402 5% 48M_DREFCLK 4
L43 1 2 120Z/100M 1608
D
1 2 3 C825 1 2 0402
X2 GND
Mid 1 1 Reserved Reserved Reserved 3V66_1/VCH_CLK
35 DEFSSCLK 10P/NA 50V +/-10%
1
C804 14.318MHZ C794 29 R859 1 33 2 0402 C262 C820 C819 C239
6,14 SMBDATA SDATA 14M_CODEC 20
0:0V UNIT: MHz 27P 27P 30
SCLK REF
56 1 2 5%
14M_ICH 13 0.1U 0.1U 0.1U 2.2U
1:3.3V 0402 TXC8X4.5 0402 6,14 SMBCLK R858 33 0402 5% 0402 0402 0402 0603
5% 5% FS0 10% 10% 10% +/-10%
2
54
FS1 FS0 R861 33/NA 1 16V 16V 16V
55 52 2 0402 ITP_CPU 1 R888 2 0402 5%
CLK_ITP_CPU 2
+3V FS2 FS1 CPUCLKT0 R872 33
40 49 1 2 0402 HCLK_MCH 0/NA
HCLK_MCH 4
GND 0402 FS2 CPUCLKT1 R874 33
45 1 2 0402 HCLK_CPU
HCLK_CPU 2
GND GND
CLK_PD# CPUCLKT2
1 R830 2 8.2K/NA 25
CLK_PCI_STOP# 34 *PD#
+3V 1 R882 2 8.2K/NA 51 R862 33/NA 1 2 0402 ITP_CPU# 1 R889 2 0402 5%
CLK_ITP_CPU# 2
+3V +3VCLKPCI
0402 2 8.2K/NA CLK_CPU_STOP#53 PCI_STOP# CPUCLKC0 R873 33
1 48 1 2 0402 HCLK_MCH# 0/NA
HCLK_MCH# 4
CPU_STOP#* CPUCLKC1
1
R886 0402 44 R875 33 1 2 0402 HCLK_CPU# L718 1 2 120Z/100M 1608

CPUCLKC2 HCLK_CPU# 2
R864 R853 R860 1 R863 2 8.2K 0402 43
+3V VTT_PWRGD# 28 MULTSEL0*
4.7K/NA 4.7K/NA 4.7K 5% 10 R825 33 1 2 0402
VTT_PWRGD# PCICLK0 PCICLK_FWH 23
1
0402 0402 0402 11 R816 33 1 2 0402 C778 C801 C800 C788
PCICLK1 PCICLK_MINIPCI 19
5% 5% 5% 1 12 R826 33 1 2 0402 0.1U 0.1U 0.1U 2.2U
VDDREF PCICLK2 PCICLK_CARD 17
FS0 R827 33 0402 0402 0402 0402 0603
2
+3VCLKANA 37 13 1 2 PCICLK_LAN 16
FS1 VDD48 PCICLK3 PCICK_1394 C796 C789 C797 C790 10% 10% 10% +/-10%
2
26 16
VDDA PCICLK4
1
FS2 19 17 PCICK_KBC 10P 10P 10P 10P 16V 16V 16V
VDD3V66_0 PCICLK5 0402 0402 0402 0402
+3VCLK66 32 18
VDD3V66_1 PCICLK6
1
+/-10% +/-10% +/-10% +/-10% GND GND

R894 R848 R869 50V 50V 50V 50V
2
46
4.7K 4.7K 4.7K/NA VDDCPU0 +3V +3VCLK66
+3VCLKCPU 50 5
0402 0402 0402 VDDCPU1 PCICLK_F0
6
5% 5% 5% PCICLK_F1 R824 33
8 7 1 2 0402 GND
PCICLK_ICH 13
L726 1 2 120Z/100M 1608
VDDPCI0 PCICLK_F2
2
+3VCLKPCI 14
VDDPCI1
1
4 21 R829 33 1 2 0402 C827 C802 C822 C823
GND0 66MHZ_OUT0/3V66_2 66M_MCH 4
9 22 R818 33 1 2 0402 0.1U 0.1U 0.1U 2.2U
t
GND1 66MHZ_OUT1/3V66_3 66M_ICH 14
15 23 R819 33 1 2 0402 0402 0402 0402 0603
GND2 66MHZ_OUT2/3V66_4 66M_AGP 7 10% 10% 10% +/-10%
GND +3V C793 C792 C799 C795
2
20
GND3
1
27 33 10P/NA 10P/NA 10P/NA 10P 16V 16V 16V
GND4 3V66_0
t
31 24 0402 0402 0402 0402
n
GND5 66MHZ_IN/3V66_5
1
36 +/-10% +/-10% +/-10% +/-10% GND GND

R831 GND6 50V 50V 50V 50V
2
41 R876
GND7
e e
10K 47 42 1 2 +3V +3VCLKANA
C 0402 GND8 IREF C
5% ICS950810 GND L722 1 2 120Z/100M 1608
r
GND 390 GND
2
TSSOP56
1 2 VTT_PWRGD# 284595081201 0402
1
31 CORE_CLKEN# R821 0 0402 5% 1% C812 C821 C803 C809 C811
c m
DEFSSCLK R865 1 33 2 0402 0.1U 0.1U 0.1U 0.1U 2.2U
66M_DEFSSCLK 4
0402 0402 0402 0402 0603
PCICK_1394 R828 1 33 2 0402 10% 10% 10% 10% +/-10%
2
PCICLK_1394 18
e
16V 16V 16V 16V
PCICK_KBC R817 1 33 2 0402 PCICLK_KBC 22
u
1 2 CLK_PD# C826 C798 C791 GND GND
1
S
13 SUSA# R820 0 0402 5% 10P/NA 10P 10P
WHEN USE INTEGRATE VGA R887/NA 0402 0402 0402
c
1 2 CLK_CPU_STOP# +/-10% +/-10% +/-10%
3,13,31 STOP_CPU# R887 0 0402 5% 50V 50V 50V
2
c Do
1 2 CLK_PCI_STOP#
13 STOP_PCI# R881 0 0402 5% GND GND GND
a
iT ial
TV ENCODER +1.5V
1
+3V +3V R63
+3VA_TV +3V 0/NA
M t
+3V 0805
2
DVOVREF R807
2
10K/NA
33
18
44
12
49
45
n
G
1
0402 U2 DVOCD[0..11]
DVOCD[0..11] 4
1
Place near 5% DVOCD0

1
C67 3 63
AVDD_0
AVDD_1
DVDD_0
DVDD_1
DVDD_2
DVDDV
VDD
TV_DDCK 4 DVOVREF VREF D[0] DVOCD1
0.1U S D 62
e
B to 7011. 4 MI2CCLK D[1] B
S
D
0402 57 61 DVOCD2
+80-20% 855_TV_COMP 4 DVOCCLK XCLK D[2] DVOCD3
2
56 60
50V Q702 CVBS1 4 DVOCCLK# XCLK* D[3] DVOCD4
59
2N7002/NA D[4] DVOCD5 +3V
4 58
id
H D[5]
1
SOT23_FET 4 DVOCHSYNC DVOCD6 +3V

5 55
288227002006 R48 R46 XIN 4 DVOCVSYNC V D[6] DVOCD7
54
D[7]
1
GND 75/NA 75/NA 855_TV_CRMA 38 53 DVOCD8
C/R D[8]
1
f
+3V +3V 0402 0402 R52 1 1M/NA 2 XOUT 855_TV_LUMA 37 52 DVOCD9 R53
5% 5% 0402 5% Y/G D[9] DVOCD10 8.2K/NA R68
51
+3V X701 855_TV_COMP39 D[10] DVOCD11 0402 8.2K/NA
2
50
CVBS1 CVBS/B D[11] 5% 0402
1 2 36
CVBS
2
n
5%
2
8
R935 GND GND TV_DDCK GPIO[0] R56 1 0/NA
2
14.318MHZ/NA 15 7 2 DVOBCINTR# 4
SPC GPIO[1]
1
USE 20P 5% C52 C56 TV_DDDA 14 0402 5%
G
SPD
1
1
10K/NA
o
20P/NA TXC8X4.5 20P/NA 2 C64 C53
NC0
2
1
D719 0402 0402 0402 XIN R54
42 9 0.1U/NA 0.1U/NA
5%TV_DDDA +/-10% +3V +/-10% XI/FIN NC1 0402 0402 330/NA R71
1
2
S D 19
4 MI2CDATA 50V NC2 +80-20% +80-20% 0402 330/NA
S
D
TV_GND TV_GND 50V XOUT
2
43 20
C
XO NC3 50V 50V 5% 0402
21
WHEN USE INTEGRATE VGA GND NC4
1
D3 TV_GND D4 Q712 GND 5%
3
2
46 22 GND GND
4 POUT/DET# P-OUT NC5
BAV99/NA BAV99/NA BAV99/NA 2N7002/NA ADD R763 R766 U2 R1240 R47
3
2
23
SOT23_FET 8.2K/NA NC6
13 TV_PCIRST# 13 24 GND
288227002006 0402 RESET* NC7
48 25 GND
5% C/HSYNC NC8
C344 1 2 33P
NC9
26 Default NTSC
0402 25V +/-10%
2
10 27
L56 1 R37 1 140/NA 2 AS NC10
2 ATI_TV_COMP 7 GND 35 28
J704 120Z/100M R73 1 0/NA ISET NC11
4 DVOCFLDSTL 2 47 29
BCO NC12
1
DGND_0
DGND_1
DGND_2
AGND_0
AGND_1
AGND_2
1 C17 1 2 33P 0/NA 1 R1240 2 0402855_TV_COMP 0402 5% 30
GND_0
GND_1
1 0402 25V +/-10% R49 NC13
2 ATI_TV_LUMA 7 31
2 L19 330/NA NC14
3 1 2 32
3 NC15
4 120Z/100M 0/NA 1 R763 2 0402855_TV_LUMA 0402
4 L20 5%
5 1 2 ATI_TV_CRMA 7 CH7011A/NA
34
40
16
17
41
11
64
5 120Z/100M
2
6
6 PQFP64_0.5MM
6
7 C19 1 2 33P 0/NA 1 R766 2 0402855_TV_CRMA
7 0402 25V +/-10%
4
3
2
1
GND1 GND
GND1
GND2 RP2
GND2
1
A C782 C15 C21 C20 C18 75*4 GND A

270P 270P 270P 100P 100P 1206
7P/RA 0402 0402 0402 0402 0402
SUYIN +/-10% +/-10% +/-10% R704 10% 10% +3V +3V +3VA_TV
2
33007S-07T1-C 50V 50V 50V 1 2 50V 50V L25

331870007007 0
5
6
7
8
+3V 1 2
120Z/100M/NA 2012
1
C70 C43 C71 C42
1
TV_GND GND GND C38 0.1U/NA 0.1U/NA 0.1U/NA 0.1U/NA C73 C40 C61
0402 0402 0402 0402 C39 0.1U/NA 0.1U/NA
10U/NA +80-20% +80-20% +80-20% +80-20% 10U/NA 0402 0402
2
6.3V 50V 50V 50V 50V 6.3V 10U/NA +80-20% +80-20%
2
0805 0805 6.3V 50V 50V Title
10% 10% 0805
GND GND 10% 8050D MOTHER B/D
GND Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
Pannel ID
Display (CRT / LCD) LCD_ID0 LCD_ID1 LCD_ID2 PANEL TYPE
0 0 1
1
C339 C340 1 0 1
0.01U 1000P
0402 0402
INVERTER 0 1 1
1
+80-20% +/-20%
2
C8 C7
50V 50V 0.1U/NA 0.1U GND 0 1 0
L17 1 2 0402 0402
DVMAIN +80-20% +80-20%
2012 120Z/100M 1 1 0
2
50V 50V J1
+5V_H L8 1 2 2012 1
120Z/100M/NA 2
ENABKL_VGA_C L10 1 2 120Z/100M 3
D +5V_H +3V R16 D
Inverter
BLADJ 0 1 R5 2 0402 L9 1 2 1608 4 +3VS F1
4,22 BLADJ
1608 120Z/100M 5 1 1M 2 1 2
1
0402 5% +3V
C6 6
2
4.7U/NA 7 FPVEDEN R22 1 0/NA 2 2A
4 FPVDEN
0805 8 R398 R365 R370 0402 5% FUSE_1206
+80-20% 0/NA 0/NA
2
9
10K/NA 0402 0402 +5V_H
10
1
2
3
GND 120OHM/100MHZ 0402 5% 5% Q9
11
G
FA2 273000610025 5% S
SI4835DY
2
BATT_R# 8 1 GND1 R20 1 0 2 SO8
22,23 BATT_R# BATT_G# 7 ENAVDD
7 2 GND2 R4 0402 5% S D R19 1 10K 2 4
22,23 BATT_G#
2
AC_POWER#
S
D
6 3 0402 5%
22,23 AC_POWER# BATT_POWER# 10K/NA
5 4 MA/11PX1/RA R399 G
23 BATT_POWER#
1
0402 GND
L18
ACES 20K/NA 5% WHEN USE INTEGRATE VGA Q11 C14 D
1
1 2 0.22U
R1
VDD3S 87213-1100 0402
ADD R22 0402
1
120Z/100M 1% ENABKL_VGA ENABKL_VGA_C 2N7002 +80-20%
5
6
7
8
1 3
2012
C12
0.1U
DEL R20 SOT23_FET 16V
Q4 NEED USE X7R ?
0402
+80-20% DTC144TKA/NA
2
GND
1
50V 288202240001 C11
1U L15
R323 0402 1 2
+80-20% 120Z/100M
2
GND 2 1
0402 5% 10V 2012
0
GND J2
R383 1 2
H8_ENABKL 1 2
When inverter use +5V ADD 3 4 To SB
22 H8_ENABKL
Q4,R398,R399,R4 and DEL R323 5 6
t
PANEL_ID2 7,14,24
7 8
WHEN USE INTEGRATE VGA 0 7,14,24 PANEL_ID3
9 10
ADD R384 +3V 0402 +3VS +3V When inverter use +3V ADD R323 11 12
PANEL_ID1 7,14,24
Cover Switch and DEL Q4,R398,R399,R4
t
5% 13 14
DEL R386
n
4 TXCLK+ PANEL_ID0 7,14,24
D1 4 TXCLK- 15 16
2
D2 1 2 17 18
1
e e
4 ENABKL_NB
R384 1 0/NA 2 3 1 ENABKL_VGA R380
4 TXOUT3+ 19 20 TXOUT1+ 4
C 0402 5% R373 R2 ESD0805A/NA 21 22 C
10K 470K 470K/NA 4 TXOUT3- TXOUT1- 4
23 24
r
R386 1 0 BAT54 0402 0402 0402
7 ENABKL 2 4 TXOUT2+ 25 26 TXOUT0+ 4
0402 5% 5% D16 R379 5% 5% R3
1
SW1 4 TXOUT2- 27 28 TXOUT0- 4

2
2
1 3 1 2 1 2 1 3 29 30
c m
+3V 2 4
1K 0402 5% GND1
2
1
BAT54 0/NA C385 30V/0.1A GND2
e
R372 0402 0.1U DT006-P11AA-A
5% 0402 MA/15PX2/ST
10K
u
H8_LIDSW# +80-20%
2
ACES
S
0402 22 H8_LIDSW# 50V GND
5% D15 88107-300X
1
c
4,13,17,25,31 PWROK 3 1
GND
c Do
BAT54 GND
a
Check Power Plane is 3VS or 5VS
iT ial
R6 1 4.7K 2
+5V_H
R1 CRT +5V_H
0402
R10 1
0402
5%
4.7K 2
5%
G
1 2
855_CRT_DDCK 4 U702
M t
0 D702 2N7002 D S R785 1 0 2 0402 CON_DDDA 1 6
ATI_CRT_DDCK 7
0805 1 2 L12 1 2 120Z/100M 1608
D
S
CHAGND GND Q6 2 5
G
R703 3 4 3 4
1 2 2N7002 D S R138 1 0 2 0402
n
ATI_CRT_DDDA 7
SMS05C/NA
D
S
855_CRT_DDDA 4 CHAGND
0 5 6 Q5 SSOT6
0805
e
B B
CHAGND GND
CHAGND 7 8
+5V_H
Q2
1
id
ESD41A/NA
G
L13 3 CON_BLUE
R9 1 1K 2 1 2 2
CRT_IN# 13,24 855_CRT_VSYNC 4
0402 5% L11 1 2 120Z/100M 1608 2N7002 D S R136 1 0 2 0402 ATI_CRT_VSYNC 7
f
D
S
SLVU2.8/NA
G
1
C10 BEAD_600Z/100M Q7 SOT23N

R8 100P 0603D
1 0/NA 2 0402 L7 1 2 120Z/100M 1608 2N7002 D S R137 1 0 2 0402 CHAGND
ATI_CRT_HSYNC 7
n
+/-10% Q1
2
D
S
855_CRT_HSYNC 4
5
6
7
8
0402 50V Q8 1
5% CP2 3 CON_GREEN
J702
o
CHAGND 2
47PX4
17
CON_DDCK 1206 WHEN USE INTEGRATE VGA DEL SLVU2.8/NA
15 R785 R138 R136 R137 R139 R135 SOT23N
C
5 CON_VSYNC
R783
4
3
2
1
10 CHAGND
14 CON_HSYNC Q3
4 1
9 CON_DDDA CHAGND 3 CON_RED
CON_BLUE CRT_BLUE 855_CRT_BLUE 4
13 R139 1 0 2 0402 2
CON_GREEN ATI_CRT_BLUE 7
3
8 SLVU2.8/NA
12 L58 CRT_GREEN R135 1 0 2 0402 SOT23N
ATI_CRT_GREEN 7
2 1 2 220Z/100M 855_CRT_GREEN 4
7 1 L59 2 220Z/100M CHAGND
11 1 L60 2 220Z/100M CRT_RED R783 1 0 2 0402 ATI_CRT_RED 7
1 CON_RED 1 2 855_CRT_RED 4
6 L74 1608 120Z/100M
4
3
2
1
16
RP1
5
6
7
8
D701 75*4/NA
15P/3R-FM 1 2 CP1 C1 1 2 0402 1206
A 7312S-15G2T-DC 47P 25V +/-10% A
SUYIN 47PX4/NA C2 1 2 0402
3 4 1206 47P 25V +/-10%
C4 2 0402
5
6
7
8
1
47P 25V +/-10%
5 6
4
3
2
1
CHAGND
GND
7 8 CHAGND
GND
ESD41A/NA
CHAGND
Title
8050D MOTHER B/D
CLOSE TO CRT CONNECTOR
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
JL1
SOUTHBRIDGE-ICH4-M(1/2) +3V
1
JP_NET10
2 ATI_PCIRST# 7
+3V
JL2
U715A
1 2 1394_PCIRST# 18
JP_NET10
14
A5 D22
U715B PCI_AD[0..31] VCC3_3 VSS
PCI_AD[0..31] 16,17,18,19 U9A B2 AC23
PCI_INTA# R195 1 0 5% D5 PCI_AD31 VCC3_3 VSS
2 P4 1 JL3 H6 AC18
7,24 PCI_INTA# PCI_INTB# R854 10402G_DFS
0 5% C2 PIRQA# AD31 PCI_AD30 VCC3_3 VSS
2 D2 3 1 2 PCIRST#0 15,25 J1 AC14
17,24 PCI_INTB# PCI_INTC# R805 10402G_DFS
0 5% B4 PIRQB# AD30 PCI_AD29 JP_NET10 VCC3_3 VSS
2 R1 2 K6 AC10
17,24 PCI_INTC# PCI_INTD# R823 10402G_DFS
0 5% A3 PIRQC# AD29 PCI_AD28 +1.5V VCC3_3 VSS
2 D3 M10 AC5
19,24 PCI_INTD# PCI_INTE# R192 10402G_DFS
0 5% C8 PIRQD# AD28 PCI_AD27 VCC3_3 VSS
2 P2 74AHC08_V P6 AC1
16,24 PCI_INTE# PCI_INTF# R199 10402G_DFS
0 5% D7 PIRQE#/GPI0 2 AD27 PCI_AD26 VCC3_3 VSS
7
2 E1 TSSOP14 U1 AB20
17,19,24 PCI_INTF# PCI_INTG# R844 10402G_DFS
0 5% C3 PIRQF#/GPIO 3 AD26 PCI_AD25 VCC3_3 VSS
2 P1 P12 AB7
18,24 PCI_INTG# ICH_GPI50402G_DFS PIRQG#/GPIO 4 AD25 PCI_AD24 VCC3_3 VSS
C4 E2 V10 AA22
PIRQH#/GPIO 5 AD24 VCC3_3 VSS
1
24 ICH_GPI5 PCI_AD23 C294 C278 C246
M5 V16 AA16
D
PCI_REQ4# AD23 PCI_AD22 C292 0.1U 0.1U 0.1U VCC3_3 VSS D
B6 E4 GND V18 AA12
24 PCI_REQ4# REQ# 4 AD22 PCI_AD21 0402 0402 0402 VCC3_3 VSS
C7 N3 AC8 AA9
16,24 PCI_REQ3# REQ# 3 AD21 PCI_AD20 10U 16V 16V 16V VCC3_3 VSS
2
B3 E3 AC17 AA3
19,24 PCI_REQ2# REQ# 2 AD20 PCI_AD19 +3V 6.3V VCC3_3 VSS
A2 N2 H18 Y19
18,24 PCI_REQ1# PCI_REQ0# REQ# 1 AD19 PCI_AD18 0805 VCC3_3 VSS
B1 E5 J18 Y7
17,24 PCI_REQ0# REQ# 0 AD18 PCI_AD17 10% +LAN_3V VCC3_3 VSS
N1 JL4 W22
SB_CARD_PME# AD17 PCI_AD16 VSS
A6 F4 1 2 MCH_PCIRST# 4 W8
24 SB_CARD_PME# CRT_IN# REQB#/REQ5#/GPIO 1 AD16 PCI_AD15 JP_NET10 VDD3S VSS
14
B5 F5 E9 W5
12,24 CRT_IN# REQA#/GPIO 0 AD15 PCI_AD14 VCCLAN3_3/VCCSUS3_3 VSS
L3 U9B F9 V17
PCI_GNT4# AD14 PCI_AD13 VCCLAN3_3/VCCSUS3_3 VSS
D6 H2 4 JL5 E11 V15
24 PCI_GNT4# GNT# 4 AD13 PCI_AD12 VCCSUS3_3 VSS
B7 L2 6 1 2 KBC_PCIRST# 22 F10 V3
GNT# 3 AD12 VCCSUS3_3 VSS
1
16,24 PCI_GNT3# PCI_AD11 PCIRST# JP_NET10 C253 C244
A7 G4 5 V9 U20
19,24 PCI_GNT2# GNT# 2 AD11 PCI_AD10 0.1U 0.1U VCCSUS3_3 VSS
E6 L1 V8 T23
18,24 PCI_GNT1# PCI_GNT0# GNT# 1 AD10 PCI_AD9 0402 0402 VCCSUS3_3 VSS
C1 G2 74AHC08_V JL6 V7 T19
17,24 PCI_GNT0# TP34 GNT# 0 AD9 PCI_AD8 16V 16V VCCSUS3_3 VSS
2
1 C5 K2 TSSOP14 1 2 LAN_PCIRST# 16 F15 T1
R409 1 GNTB#/GNT5#/GPIO 17 AD8 PCI_AD7 JP_NET10 VCCSUS3_3 VSS
2 E8 J5 F16 R21
3,24 B/CB# 0/NA GNTA#/GPIO 16 AD7 PCI_AD6 VCCSUS3_3 VSS
H4 F17 R18
AD6 PCI_AD5 VCCSUS3_3 VSS
F1 J4 F18 R5
16,17,18,19,24 PCI_FRAME# FRAME# AD5 PCI_AD4 VCCSUS3_3 VSS
L5 G5 GND K14 P22
16,17,18,19,24 PCI_IRDY# IRDY# AD4 PCI_AD3 +1.5V VCCSUS3_3 VSS
F2 K1 P20
16,17,18,19,24 PCI_TRDY# TRDY# AD3 PCI_AD2 VSS
M3 H3 P13
16,17,18,19,24 PCI_DEVSEL# DEVSEL# AD2 PCI_AD1 +3V GND VSS
F3 J3 K10 P11
16,17,18,19,24 PCI_STOP# STOP# AD1 PCI_AD0 VCC1_5 VSS
G1 H5 K12 P3
16,17,18,19 PCI_PAR PAR AD0 PCI_C/BE#[0..3] VCC1_5 VSS
L4 PCI_C/BE#[0..3] 16,17,18,19 JL7 K18 N23
16,17,18,19,24 PCI_PERR# PCI_LOCK# PERR# PCI_C/BE#3 VCC1_5 VSS
M2 N4 1 2 CARD_PCIRST# 17 K22 N21
24 PCI_LOCK# PLOCK# C/BE#3 PCI_C/BE#2 JP_NET10 VCC1_5 VSS
14
K5 M4 P10 N19
16,17,19,24 PCI_SERR# SB_PME# SERR# C/BE#2 PCI_C/BE#1 VCC1_5 VSS
W2 K4 U9C T18 N14
14,16 SB_PME# PCIRST# PME# C/BE#1 PCI_C/BE#0 +VHI_ICH VCC1_5 VSS
U5 J2 9 JL8 V14 N13
PCIRST# C/BE#0 VCC1_5 VSS
P5 8 1 2 MINIPCI_PCIRST# 19 U19 N12
11 PCICLK_ICH PCICLK JP_NET10 VCC1_5 VSS
10 1 2 L23 N11
t
+1.5V VCCHI0 VSS
ICH4-M M14 N10
R867 0/NA VCCHI1 VSS
BGA360_25_36 74AHC08_V JL9 P18 N5
0805C_DFS VCCHI2 VSS
7
TSSOP14 1 2 FWH_PCIRST# 23 T22 M13
VCCHI3 VSS
t
JP_NET10 +LAN_1.5V M12
n
VSS
M11
PCI_PME# R920 1 0 CARDBUS_PME# VDD1.5 VSS
2 5% CARDBUS_PME# 17 JL10 F6 M1
VCCLAN1_5/VCCSUS1_5 VSS
e e
0402G_DFS GND 1 2 F7 M22
TV_PCIRST# 11 VCCLAN1_5/VCCSUS1_5 VSS
C JP_NET10 E12 L21 C
SB_CARD_PME# 1 0/NA 2 R921 VCCSUS1_5 VSS
R6 L14
r
VCCSUS1_5 VSS
1
0402 C223 C211 C212 C224 T6 L13
C285 0.1U 0.1U 0.1U 0.1U VCCSUS1_5 VSS
U6 L12
0402 0402 0402 0402 VCCSUS1_5 VSS
G18 L11
c m
+3V 10U 16V 16V 16V 16V VCCSUS1_5 VSS
2
E13 L10
6.3V VCCSUS1_5 VSS
F14 K23
U715D 0805 VCCSUS1_5 VSS
E20 M20
e
R240 1 0 10% VCCSUS1_5 VSS
2 J19 R2 1 2 R880 0 0402
AGPBUSY# 4,7,24 GND K19
APICCLK AGPBUSY#/GPIO 6 V5REF VSS
H19 R3 KBD_US/JP# 22,24 E7 K13
APICD_0 GPIO 7 V5REF1 VSS
u
R222 1 2 10K K20 V4 V6 K11
APICD_1 GPIO 8 EXTSMI# 22,24 V5REF2 VSS
S
C3_STAT# 0402 1 R904 2 8.2K/NA 0402 5% K3
HSTPCLK# +VCCP V5REF_SUS VSS
V23 V5 SCI# 22,24 E15 J6
2 HSTPCLK# STPCLK# GPIO 12 V5REF_SUS VSS
c
GND AB23 W3 H1
2 HA20M# A20M# GPIO 13 WAKE_UP# 22,24 VSS
U21 P14 G21
2 HSLP# CPUSLP# V_CPU_IO VSS
c Do
1 R934 2 0 Y23 Y21 STOP_PCI# 11 U18 G19
2 HPWRGD CPUPWRGD STP_PCI/GPIO 18 SUSA# +1.5V V_CPU_IO VSS
AB22 W18 SUSA# 11 AA23 G6
INTR SLP_S1#/GPIO 19 V_CPU_IO VSS
1
2 HINTR
V21 W19 STOP_CPU# 3,11,31 C304 C853 G3
2 HNMI NMI STP_CPU#/GPIO 20 C3_STAT# VSS
W23 T3 1 2 R896 0 0402 C274 0.1U 0.1U C22 F8
a
2 HSMI# SMI# C3_STAT#/GPIO 21 STP_AGP# 7,24 VCCPLL VSS
W21 Y20 0402 0402 E22
IGNNE# CPUPERF#/GPIO 22 CPUPERF# 24 VSS
1
2 HIGNNE#
A20_GATE TP705 10U 10% 10% C219
2
Y22 J21 1 D1 E21
+3V A20GATE SSMUXSEL/GPIO 23 6.3V 16V 16V 1U VSS VSS
U22 AC2 PCLKRUN# 16,17,19,24 C23 E19
22 HRCIN# RCIN# CLKRUN#/GPIO 24 0805 0402 VSS VSS
iT ial
AA21 V2 SPK_OFF 21,24 C21 E18
14 CPU_FERR# 0 FERR# GPIO 25 GPIO27 10% 10V VSS VSS
2
1 2 V22 W1 GPIO27 24 C19 E17
INIT# GPIO 27 VSS VSS
2
2,23 HINIT# R928 0402G_DFS 5% GPIO28

W4 GPIO28 24 C17 E16
GPIO 28 VSS VSS
J22 C15 E14
DTC144TKA 14,17,19,22 SERIRQ SERIRQ VSS VSS
GND C6 E10
SOT23AN_1 VSS VSS
T5 Y4 B22 D23
R1
19,22,23 LFRAME# LFRAME#/FWH4 SLP_S3# SLP_S4# SUSB# 17,22,23,25 VSS VSS

288202240001 U3 Y2 B20 D21
SB_PME# PCI_PME# 19 LRDQ0# LDRQ1# LDRQ0# SLP_S4# SLP_S5# VSS VSS
M t
3 1 PCI_PME# 18 U4 AA2 B18 D19
LDRQ1# SLP_S5# VSS VSS
Q704 Y1 ICH_RI# 16 B16 D17
0 RI# VSS VSS
1 2 R915 MINIPCI_PME# 19
LAD0 T2 AA1 ICH_PWRBTN# 22 B12 D15
0402G_DFS 5% LAD1 LAD0/FWH0 PWRBTN# +3V VSS VSS
R4 Y3 ICH_SYS_RESET# 14 B9 D12
0/NA 2 R908 LAD[0..3] LAD2 LAD1/FWH1 SYS_RESET# VSS VSS
1 T4 Y5 ICH_LAN_RST# 14 A22 D8
0402 19,22,23 LAD[0..3] LAD3 LAD2/FWH2 LANRST# VSS VSS
U2 AB2 A20 D4
n
LAD3/FWH3 BATLOW#/TP[ 0 ] SB_SUSST# ICH_BATLOW# 14 VSS VSS
AB3 SB_SUSST# 7
R939 1 2 10K/NA SB_SUSST# A18
SUSCLK SUS_STAT#/LPCPD ICH_VGATE 0402 5% VSS
AA4 V19 A16
4 SUSCLK INTRUDER# SUSCLK VGATE/VRMPWRGD R270 1 VSS
W6 W20 2 10K/NA LDRQ1# A4
e
B
RTC_RST# INTRUDER# THERMTRIP# CPU_THRMTRIP# 14 VSS B
W7 V1 0402 5% A1 GND
RTCRST# THRM# SB_THRM# 22 VSS
AB6
4,12,17,25,31 PWROK PWROK
AA6 AC3 SMLINK0 14 ICH4-M
22,25 RSMRST# RSMRST# SMILINK 0 +VCC_RTC
AB5 AB1
id
+VCC_RTC VCCRTC SMLINK 1 SMLINK1 14 BGA360_25_36
RTC_VBIAS Y6 AB4 GND
RTC_X1 VBIAS SMBDATA SMB_DATA 14
AC7 AC4 SMB_CLK 14
VDD3S RTC_X2 RTCX1 SMBCLK INTRUDER#
AC6 AA5 SMBALERT# 24 1 2
RTCX2 SMBALERT#/GPIO 11
f
H23 SBSPKR 14,20
R274 1 0 SPKR +5V +3V VDD5S VDD5 VDD3S
2 5% V20 J23 14M_ICH 11
R287 10K 0402 5%
DPRSLPVR CLK14
1
14,31 DPRSLPVR 0402G_DFS U23

R276 2,4 HDPSLP# DPSLP#
1
n
0 +3V +LAN_3V
ICH4-M
0805_DFS R252 D11 R397 R164 D10
U5 +VCC_RTC BGA360_25_36
VDD5S 1K 1K 1K/NA
BAT54 BAT54
o
2 R223 0402 0402 0402
2
3 4 1 1
VOUT NC1 0 5% 5% 5%
2 3
VIN
1
VDD3S 0805C_DFS V5REF V5REF_SUS
3
1 5 2 C228 C225
GND0 NC0
1
C856 10U 0.1U
1
AME8800AEEV/NA D12 1U 1 2 R233 0805 0402 C298 C207 C210 C221
+3VS
1
1
SOT25 BAV70LT1 0402 0805 0/NA 6.3V 10% 1U 1U
2
C289 C311 0.1U 0.1U
R917 288100070006 +80-20% R926 0805C 10% 16V 0402 0402 0402 0402
2
2.2U/NA 4.7U
0603 0805 1K 10V 4.7K 10V 10% 10V 10%
2
+/-10% +80-20% 0402 0402 GND 16V 16V
2
D704
5% R288 SLP_S4# 2 5%
GND
RTC_RST#
2
1 2 3 SUSC# 22,26,27 GND GND

SLP_S5# 1
1
GND GND GND 180K C315 +3V +3V

1
C841 0402 0.1U BAW56

0.047U 5% 0402 288100056017 VDD3S
0402 10%
2
1
J710 10% 16V Spacing other signal 25 mils
2
14
C261 C305 C275 C277

1 25V GND U9D C233 0.1U 0.1U 0.1U 0.1U
1
2 12 R306 0402 0402 0402 0402
31 VRMPWRGD 10U C245 C206 C213 C306 C307 C308
RTC_VBIAS ICH_VGATE 10% 10% 10% 10%
2
11 1 2 1U 1U 0.1U 0.1U 0.1U 0.1U
PWROK 6.3V 16V 16V 16V 16V 0402 0402 0402 0402 0402 0402
13
1.25MM/ST/MA-2 22 0805 10V 10V 10% 10% 10% 10%
2
1
ACES 0402 10% 16V 16V 16V 16V

74AHC08_V
85205-0200 R296 5% GND
7
A TSSOP14 A
10M
0402 GND
5% +VHI_ICH
GND C855 22P 0402
2
1 2 RTC_X1 GND +1.5V +LAN_1.5V

+3V
1
1
50V +/-10% R311 1 2 0/NA C260 C824 C269
4
R938 1 2 R234 1U 0.1U 0.1U

X704 10M 0 0402 0402 0402
1
0402 VDD1.5 0805C_DFS 10V 10% 10%
2
32.768KHZ C208
5% R932 1 2 R245 C229 0.1U 16V 16V
C861 22P 0402 10K 0805 0/NA 0402 Title
1
RTC_X2 0402 0805C 10U 10% 8050D MOTHER B/D

2
1 2
5% 6.3V 16V GND
50V +/-10% 0805 Size Rev
2
10% GND Document

R931 1 2 0 A20_GATE C PCB 316680900001/ASSY 411682700001 R01
22 A20GATE Number
GND
5 4 3 2 1

5 4 3 2 1
SOUTHBRIDGE-ICH4-M(2/2)
+VCCP +3V
U715E HUB_HI[0..10]
HUB_HI0 HUB_HI[0..10] 4
R185 1 0/NA 2 5% 0402G_DFS C20 L19 VDD3S
USBP_0 HI 0
1
15 USBP0+ R190 0/NA 5% 0402G_DFS HUB_HI1 R392 1
1 2 D20 L20 2 8.2K
15 USBP0- R173 0/NA 5% 0402G_DFS USBP_0# HI 1 HUB_HI2 R936 13,17,19,22 SERIRQ 0402 5%
1 2 A21 M19
15 USBP1+ R178 0/NA 5% 0402G_DFS USBP_1 HI 2 HUB_HI3 56
1 2 B21 M21
15 USBP1- R196 0/NA 5% 0402G_DFS USBP_1# HI 3 HUB_HI4 0402
1 2 C18 P19
15 USBP2+ R205 0/NA 5% 0402G_DFS USBP_2 HI 4 HUB_HI5 5% R307 1
1 2 D18 R19 2 5% 13,16 SB_PME#
R907 1 2 10K
15 USBP2- TP23 USBP_2# HI 5 HUB_HI6 R937 0402 10K/NA 0402 5%
2
1 A19 T20
TP29 USBP_3 HI 6 HUB_HI7
1 B19 R20 1 2 CPU_FERR# 13
TP33 USBP_3# HI 7 HUB_HI8 2 HFERR# ICH_LAN_RST#
1 C16 P23 1 2
TP37 USBP_4 HI 8 HUB_HI9 56 5% 13 ICH_LAN_RST#
1 D16 L22
TP24 USBP_4# HI 9 HUB_HI10 0402 R308 10K 0402 5% VDD3S
1 A17 N22
D
TP28 USBP_5 HI 10 R856 1
D
1 B17 K21 2 56 GND
GND
USBP_5# HI 11 0402 5% R929 1 SMLINK1
2 47K SMLINK1 13
USBOC0# B15 N20 0402 5%
15 USB_OC0# OC#0 HI_STB#/HI_STBF HUB_STB# 4 SMLINK0
C14 P21 R940 1 2 47K
USBOC1# OC#1 HI_STB/HI_STBS HUB_STB 4 +VCCP SMLINK0 13
A15 0402 5%
15 USB_OC1# OC#2 HI_COMP
B14 R23
USBOC4# OC#3 HI_COMP HI_VSWING
A14 R22
WHEN USE INTEGRATE VGA OC#4 HIVSWING
1
USBOC5# D14 M23 HI_VREF R933 1 2 10K ICH_BATLOW#
OC#5 HIREF ICH_BATLOW# 13
ADD RP26 CLK66
T21 66M_ICH 11
R269
56
0402 5%
ICH_SYS_RESET#
J20 R310 1 2 10K
19,24 WIRELESS_PD# GPIO 32 0402 ICH_SYS_RESET# 13
1 RP26 8 G22 A10 0402 5%
7,12,24 PANEL_ID0 0*4/NA 7 GPIO 33 LANRXD0 5%
2 F20 A9
7,12,24 PANEL_ID1 1206 GPIO 34 LANRXD1 R273
2
3 6 G20 A11
7,12,24 PANEL_ID2 GPIO 35 LANRXD2 R261 1 0
4 5 F21 B10 2 5% 1 2 CPU_THRMTRIP# 13
VDD3S +3V
7,12,24 PANEL_ID3 MB_ID2 GPIO 36 LANTXD0 2 CPU_THRMTRIP_OUT# 0402G_DFS
24 MB_ID2 H20 C10
GPIO 37 LANTXD1 56 5%
F23 A12
15,24 IDERST# GPIO 38 LANTXD2 TP704 0402
H22 B11 1
GPIO 39 LANRSTSYNC
1
19,24 MINIPCI_ACT# MB_ID0 R811 1
24 MB_ID0 G23 C11 2 10K
MB_ID1 GPIO 40 LANCLK 0402 5% Q20 +VCCP R315 R318 R316 R317
24 MB_ID1 H21
GPIO 41 288203904022 2.2K 2.2K 10K 10K
F22 D11
G
C
24 GPIO42 GPIO 42 EE_DIN
GPIO43 E23 D10 GND MMBT3904L R266 0402 0402 0402 0402
24 GPIO43 GPIO 43 EE_CS 5% 5% 5% 5%
C12 B 1 2
EE_SHCLK EE_DOUT
2
F19 A8 D S SMBDATA 6,11
11 USBCLK_ICH CLK48 EE_DOUT R812 0 0402 5% 1K 5% 13 SMB_DATA
D
S
E
C9 1 2 0402 1Q21 2
ACSYNC ACSYNC 20
B23 D9 2N7002
USBRBIAS# ACSDOUT ACSDOUT 20
B8 R313 0/NA 0402 5%
ACBITCLK ACBITCLK 20
1
A23 C13 C787
G
USBRBIAS ACRST# ACRST# 20
D13 10P/NA R290
ACSDIN0 ACSDIN0 20 0/NA
A13 0402
t
ACSDIN1 ACSDIN1 20
1
+/-10% 0402
2
B13 D S SMBCLK 6,11
R838 ACSDIN2 50V 5% 13 SMB_CLK
D
S
1
18.2 1 Q22
2
ICH4-M THERM_ERR# 22,25 2
t
0402 R810 GND 2N7002
BGA360_25_36
n
1% 10 R314 0/NA 0402 5%
271061180101 0402
2
e e
5%
VDD3S
2
C C
GND
r
GND
GPIO CHARACTERISTIC LIST
c m
1
NAME TYPE POWER PLANE CURRENT DEFINE
R197 R809
10K 10K B5 GPI[0] I MAIN POWER WELL CRT_IN#
e
0402 0402
5% 5% A6 GPI[1] I MAIN POWER WELL SB_CARD_PME#
2
S
C8 GPI[2] I MAIN POWER WELL PCI_INTE#
USBOC4#
c
D7 GPI[3] I MAIN POWER WELL PCI_INTF#
USBOC5#
c Do
C3 GPI[4] I MAIN POWER WELL PCI_INTG#
+1.5V
+1.5V C4 GPI[5] I MAIN POWER WELL ICH_GPI5
a
STRAPPING R2 GPI[6] I MAIN POWER WELL AGPBUSY#
2
1
R883 R911 R3 GPI[7] I MAIN POWER WELL KBD_US/JP#
+1.5V 487 130
iT ial
1% 0603 +3V V4 GPI[8] I RESUME POWER WELL EXTSMI#
R900 1%
HI_COMP HI_VREF HI_VSWING R1113 0402 AA5 GPI[11] I RESUME POWER WELL SMBALERT#(Pull high only)
1
2
1 2
ACSDOUT 1 2
1
1
4.7K/NA 5% V5 GPI[12] I RESUME POWER WELL SCI#
1
1
48.7 C829 C828 R884 C838 C839 R912
150 150 EE_DOUT
M t
0.01U 0.1U 0.01U 0.1U 1 2 W3 GPI[13] I RESUME POWER WELL WAKE_UP#
0402 0402 0402 0402 0402 0402
10% 10% 1% 10% 10% 1% R813 4.7K/NA 0402 5% E8 GPO[16] O MAIN POWER WELL X
2
50V 16V 50V 2 16V GND

2
2
C5 GPO[17] O MAIN POWER WELL X
n
GND GND Y21 GPO[18] O MAIN POWER WELL STOP_PCI#
+VHI_ICH
R275 0402 W18 GPO[19] O MAIN POWER WELL SUSA#
e
B B
1 2
4.7K/NA 5% W19 GPO[20] O MAIN POWER WELL STOP_CPU#
1 2
PD_D[0..15] U715C SD_D[0..15] 13,31 DPRSLPVR T3 GPO[21] O MAIN POWER WELL C3_STAT#
id
15 PD_D[0..15] PD_D15 SD_D15 SD_D[0..15] 15
Y11 Y17 R286 4.7K 0402 5%
PD_D14 PDD 15 SDD 15 SD_D14
W11
PDD 14 SDD 14
AA17 GND Y20 GPO[22] OD MAIN POWER WELL CPUPERF#
PD_D13 W10 Y16 SD_D13
PDD 13 SDD 13
f
PD_D12 AB10 AB16 SD_D12 J21 GPO[23] O MAIN POWER WELL X
PD_D11 PDD 12 SDD 12 SD_D11 +3V
W9 Y15
AC9
PDD 10 SDD 10
AA15 R852 0402 AC2 GPIO[24] I/O RESUME POWER WELL PCLKRUN#
PD_D9 Y9 AC15 SD_D9 1 2
PDD 9 SDD 9 13,20 SBSPKR
n
PD_D8 AB9 Y14 SD_D8 4.7K/NA 5% V2 GPIO[25] I/O RESUME POWER WELL SPK_OFF
AA8 AA14
Y8
PDD 6 SDD 6
W14 W1 GPIO[27] I/O RESUME POWER WELL X
o
PD_D5 AB8 AB15 SD_D5
AA7
PDD 4 SDD 4
W15 W4 GPIO[28] I/O RESUME POWER WELL X
PD_D3 AA10 AC16 SD_D3
Y10 W16 J20 GPIO[32] I/O MAIN POWER WELL WIRELESS_PD#
C
AC11 AB17
AB11
PDD 0 SDD 0
W17 G22 GPIO[33] I/O MAIN POWER WELL PANEL_ID0
W12
PDIOW# SDIOW#
AA18 SDIOW# 15
F20 GPIO[34] I/O MAIN POWER WELL PANEL_ID1
15 PDIOW#
Y12 AB19 SDDACK# 15
15 PDDACK# PDDACK# SDDACK#
AA11
PDDREQ SDDREQ
AB18 SDDREQ 15
G20 GPIO[35] I/O MAIN POWER WELL PANEL_ID2
15 PDDREQ
15 PDIOR#
AC12
PDIOR# SDIOR#
Y18 SDIOR# 15 STRAPPING AT RISING EDGE OF PWROK
AB12
PIORDY SIORDY
AC19 SIORDY 15
F21 GPIO[36] I/O MAIN POWER WELL PANEL_ID3
15 PIORDY
STRAPPING PINS FUNCTIONS H20 GPIO[37] I/O MAIN POWER WELL MB_ID2
AA13 AC21 SDA2 15
15 PDA0 PDA0 SDA2
AB13
PDA1 SDA1
AC20 SDA1 15
ACSDOUT SAFE MODE F23 GPIO[38] I/O MAIN POWER WELL IDERST#
15 PDA1
W13 AA20 SDA0 15
15 PDA2 PDA2 SDA0
EEDOUT RESERVED H22 GPIO[39] I/O MAIN POWER WELL MINIPCI_ACT#
Y13 AB21 SDCS1# 15
15 PDCS1# PDCS1# SDCS1#
AB14
PDCS3# SDCS3#
AC22 SDCS3# 15
GNTA# OP-BLOCK SWAP OVERRIDE G23 GPIO[40] I/O MAIN POWER WELL MB_ID0
15 PDCS3#
DPRSLPVR HUB INTERFACE TERMINATION SCHEME H21 GPIO[41] I/O MAIN POWER WELL MB_ID1
AC13 IRQ14 15
IRQ14
A
IRQ15
AA19 IRQ15 15
HUB_ICH_COMP HUB INTERFACE SCHEME(1.0 OR 1.5) F22 GPIO[42] I/O MAIN POWER WELL X A
ICH4-M SBSPKR NO REBOOT E23 GPIO[43] I/O MAIN POWER WELL X

BGA360_25_36
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
HDD- PRIMARY IDE CONNECTOR CDROM- SECONDARY IDE CONNECTOR

J714
GND2 +5V R922
GND2
GND1 GND 1 10K 2
GND1 0402 5%
R436 RSTDRV1# 44 43 1 R901 2 RSTDRV2# J708
44 43
1 2 PD_D7 42 41 PD_D8 10K/NA CDROM_LEFT 1 2 CDROM_RIGHT
CDROM_RIGHT 20
42 41 1 2
1
PD_D[0..15] PD_D6 PD_D9 0402 20 CDROM_LEFT CDROM_COM M
14 PD_D[0..15] 40 39 3 4
PD_D0 10K/NA PD_D5 40 39 PD_D10 R919 5% 20 CDROM_COM M RSTDRV2# 3 4 SD_D8
38 37 5 6
PD_D1 0402 PD_D4 38 37 PD_D11 10K/NA R927 110K/NA SD_D7 5 6 SD_D9
36 35 GND 2 7 8
PD_D2 GND 5% PD_D3 36 35 PD_D12 0402 Q703 SD_D[0..15] 0402 5% SD_D6 7 8 SD_D10
34 33 14 SD_D[0..15] 9 10
34 33 9 10
3
PD_D3 PD_D2 32 31 PD_D13 5% DTC144TKA/NA SD_D0 SD_D5 11 12 SD_D11
32 31 11 12
2
D D
PD_D4 PD_D1 PD_D14 R1 SD_D1 SD_D4 SD_D12
2
30 29 2 13 14
PD_D5 PD_D0 30 29 PD_D15 R909 SD_D2 SD_D3 13 14 SD_D13
28 27 15 16
PD_D6 28 27 SD_D3 SD_D2 15 16 SD_D14
26 25 17 18
26 25 17 18
3
PD_D7 PDDREQ 0 SD_D4 SD_D1 SD_D15
1
24 23 19 20
PD_D8 PDIOW# 24 23 R1 0402 SD_D5 SD_D0 19 20 SDDREQ
22 21 14,24 IDERST# 2 21 22
PD_D9 PDIOR# 22 21 R1085 5% SD_D6 21 22 SDIOR#
1
20 19 23 24
PD_D10 PIORDY 20 19 Q705 SD_D7 SDIOW# 23 24
18 17 1 2 25 26
PD_D11 PDDACK# 18 17 DTC144TKA/NA SD_D8 SIORDY 25 26 SDDACK#
1
16 15 27 28
PD_D12 IRQ14 16 15 470 5% SD_D9 IRQ15 27 28
14 13 29 30
PD_D13 PDA1 14 13 0402 GND +5V SD_D10 SDA1 29 30 TP706
12 11 31 32 1
PD_D14 PDA0 12 11 PDA2 GND SD_D11 SDA0 31 32 SDA2
10 9 33 34
PD_D15 PDCS1# 10 9 PDCS3# SD_D12 SDCS1# 33 34 SDCS3#
8 7 35 36
HDD_LED# 8 7 SD_D13 35 36
6 5 1 R492 2 RSTDRV1# CD_LED# 37 38
23 HDD_LED# 6 5 10K SD_D14 23 CD_LED# 37 38
+5V_HDD 4 3 +5V_HDD 39 40 +5V_CDROM
4 3 39 40
1
2 1 0402 SD_D15 41 42
2 1 +5V_CDROM 41 42
R476 5% 43 44
10K R836 43 44
45 46
HDR/FM/22PX2/2MM 0402 45 46
GND 1 2 47 48
47 48
3
SPEED 5% 49 50
ACE-1A2-0216 R1 Q41 470/NA 49 50
2
2
GND GND 0402 GND R/A-25PX2/0.8
DTC144TKA 5% GND
SPEED
3
288202240001
1
K22-102-150X
PCIRST#0 2 R1 Q37
13,25 PCIRST#0
DTC144TKA
+5V_HDD +5V 288202240001
1
L733 SDDREQ R879 1 5.6K/NA 2
PDDREQ 14 SDDREQ SDIOW# +3V
R295 1 5.6K/NA 2 1 2 0402 5% +5V_CDROM +5V
14 PDDREQ PDIOW# +3V 14 SDIOW# SDIOR# L723
0402 5% 120Z/100M 2012 GND
t
14 PDIOW# 14 SDIOR#
1
1
PDIOR# C872 C877 C878 SIORDY R833 1 4.7K 2 1 2
14 PDIOR# PIORDY 14 SIORDY SDDACK# +3V
R1081 1 4.7K 2 0.1U 0.1U 10U 0402 5%
14 PIORDY +3V 14 SDDACK#
1
PDDACK# 0402 5% 0402 0402 0805C IRQ15 R834 1 8.2K 2 C813 C816 C817 120Z/100M
14 PDDACK# 14 IRQ15 +3V
t
IRQ14 R1074 1 8.2K 10% 10% 10V SDA1 0402 5% 10U 2012
2
2 0.1U 0.1U
n
14 IRQ14 PDA1 +3V 16V 16V 14 SDA1 SDA0
0402 5% 0402 0402 0805C
14 PDA1 PDA0 14 SDA0 SDA2 10% 10% 10V
2
14 PDA0 14 SDA2 16V 16V
e e
PDA2 GND GND GND SDCS1#
14 PDA2 PDCS1# 14 SDCS1# SDCS3#
C GND GND GND C
14 PDCS1# PDCS3# 14 SDCS3#
14 PDCS3#
r
c m
e
USB CONNECOTR
S cu
c Do
+5VS +5VS
U701 L702 U705 L708
3 1 1 2 +VCC_USB_0 3 1 1 2 +VCC_USB_2
VIN0 VOUT0 120Z/100M VIN0 VOUT0 120Z/100M
GND
GND
a
1
1
4 5 2012 C5 4 5 2012 C31
VIN1 VOUT1 VIN1 VOUT1
1
1
0.1U 0.1U
1
1
C703 RT9701-CBL R701 0402 C709 RT9701-CBL R706 0402
1
1
33K C701 C702 +80-20% 33K C713 +80-20%
2
2
iT ial
1U SOT25 1U SOT25
0402 0402 + 150U + 150U/NA 50V 0402 0402 + 150U 50V
+80-20% 5% +80-20% 5%
2
2
7343 7343 7343
10V 6.3V 6.3V L701 GND_USB 10V 6.3V GND_USB1
2
2
GND GND +VCC_USB_1 GND GND
2
2
1 2
USB_OC0# 120Z/100M USB_OC1#
1
14 USB_OC0# 2012 14 USB_OC1#

C3
1
1
M t
0.1U
1
1
C704 R702 0402 C711 R708
47K +80-20% 47K
2
1000P 1000P
0402 0402 50V 0402 0402
+/-20% 5% GND_USB +/-20% 5%
2
2
50V 50V
2
2
n
GND GND
e
B B
L21
L3 0603D BEAD/NA
0603D BEAD/NA
1 2
id
14 USBP2+
14 USBP0+ 1 2
3
f
2
L22 J706
L2 J701 +VCC_USB_2 1
+VCC_USB_0 90Z/100M VCC
1 2
90Z/100M 1 CHOKE_ACM2012 P-
n
1
4
2 3
CHOKE_ACM2012 2 P+
1
3 4
3 GND
4
4
o
14 USBP2- 1 2 GND1
+VCC_USB_1 GND1
14 USBP0- 1 2 A1 GND2
A1 L23 GND2
A2
L1 A2 0603D BEAD/NA
A3 GND1 USB/4PX1
C
0603D BEAD/NA A3 GND1
A4 GND2 SUYIN
A4 GND2
2545A-04GXT
USB/4PX2/DIP
2
SUYIN
2
2522A-08G1T-K GND_USB1
JO16 JO15 JO14

L6 JO4 JO5 JO6 JO3 JO7 JO8
0603D BEAD/NA
GND_USB
1
14 USBP1+ 1 2
1
1
2
JO13
L5 1 2
90Z/100M JO9 GND_USB1 SHORT-SMT4
CHOKE_ACM2012 GND_USB GND_USB JO17
1
1 2
A 1 2 A
SHORT-SMT4
1 2 JO702 SHORT-SMT4
14 USBP1-
1 2
L4 GND GND_USB1
0603D BEAD/NA SHORT-SMT4
GND GND_USB
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
+2.5VS_DDR
L732
DVDD
LAN-RTL8100CL/RTL8110S
1 2 120Z/100M DVDD
2012 Close to RTL8100C
1
C904 C894 C905 C879 C873
+1.8VS 0.1U 0.1U 0.1U 0.1U 0.1U +3VS
0402 0402 0402 0402 0402
L731 10% 10% 10% 10% 10% MDI0+ MDI1+
2
1 2 120Z/100M/NA 16V 16V 16V 16V 16V USED IN 93C56 MDI0- MDI1-
1
2012 C876 C862 C865 C874 C886 C891 C906 +3VS
1
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U R1108
0402 0402 0402 0402 0402 0402 0402 1 2 10K/NA R1087 R1090 R1082 R1086
1
+3VS 10% 10% 10% 10% 10% 10% 10% 0402 49.9 49.9 49.9 49.9
2
C863 C864 C866 C880
0.1U 0.1U 0.1U 0.1U 16V 16V 16V 16V 16V 16V 16V R1110 0402 0402 0402 0402
D D
0402 0402 0402 0402 1 2 3.6K 1% 1% 1% 1%
E
Q707 10% 10% 10% 10% ADD if use RTL8110S 0603
2
CTRL18 B +1.8VS 16V 16V 16V 16V GND U723
1
EECS 1 8 C900 C896
DVDD CS VCC
Change DVDD to +1.8VS, DVDD_A EECK 2
SK NC1
7 C911 0.01U 0.01U
1
R1100
1C
2SB1188/NA GND EEDI 3 6 1U 0402 0402

when use RTL8110S DI NC0
1
C870 C867 +3VS AVDDL AVDDH EEDO 0402 +80-20% +80-20% MDI2+ MDI3+
2
1 2 4 5
10U 0.1U DO GND +80-20% 50V 50V MDI2- MDI3-
16V 0402 +5V 0/NA 0402 10V GND GND
2
93C46
1
1206 16V
2
SO8
10% 1 283467540002 GND R1067 R1071 R1063 R1066
49.9/NA 49.9/NA 49.9/NA 49.9/NA
GND R1006 0402 0402 0402 0402
110
116
126
107
120
1K 1% 1% 1% 1%
24
32
45
54
64
78
99
26
41
56
71
84
94
16
20
10
3
7
R1008 0402 U719
2
15K 0402 31 111 EECK
NC_18
VDD25_0
NC_19
VDD25_1
NC_20
VDD25_2
VDD25_3
NC_21
NC_22
NC_23
VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
AVDD33_0
AVDD33_1
NC_24
AVDD33(REG)
NC_25
NC_26
13,14 SB_PME# PMEB EESK
1
ISOLATEB EEDI
2
2 1 23 109 C882 C884

GND LAN_WAKE ISOLATEB AUX/EEDI EEDO
105 108 0.01U/NA 0.01U/NA
LANWAKE EEDO EECS 0402 0402
106
PCI_AD[0..31] PCI_AD0 EECS +80-20% +80-20%
2
104
+3VS 13,17,18,19 PCI_AD[0..31] PCI_AD1 AD0 50V 50V
103
L737 PCI_AD2 AD1 GND GND
102
AD2
1 2 120Z/100M PCI_AD3 98 1 MDI0+
AD3 TX+
+2.5VS_DDR
2012
AVDDL
PCI_AD4 97
AD4 TX-
2 MDI0- ADD if use RTL8110S
PCI_AD5 96
L738 PCI_AD6 AD5 MDI1+
95 5
AD6 RX+
1 2 120Z/100M/NA AVDDL PCI_AD7 93 6 MDI1-
2012 PCI_AD8 AD7 RX- R305 0/NA 0603 R303 0/NA 0603 R285 0/NA 0603 R272 0/NA 0603
90
AD8
1
C895 C893 C887 C883 PCI_AD9 89 14 MDI2+ MDI0+ 1 2 PMDI0+ MDI1+ 1 2 PMDI1+ MDI2+ 1 2 PMDI2+ MDI3+ 1 2 PMDI3+
AD9 NC_9
Change AVDDL to 0.1U 0.1U 0.1U 0.1U PCI_AD10 87 15 MDI2-
t
0402 0402 0402 0402 PCI_AD11 AD10 NC_10
86
+2.5VS_DDR , when 10% 10% 10% 10% PCI_AD12 AD11 MDI3+
2
85 18
16V 16V 16V 16V AD12 NC_11
use RTL8110S PCI_AD13 83
AD13 NC_12
19 MDI3- 1.50/8/8/8/50
1
t
PCI_AD14 82 L51 L49 L48 L44
n
AD14
PCI_AD15 79
AD15 2.Parallel and
GND PCI_AD16 59
+3VS AVDDH AD16 equal length
e e
PCI_AD17 58
L736 AD17
PCI_AD18 LAN_XTAL1 3.Not to use via 120Z/100M 120Z/100M 120Z/100M/NA 120Z/100M/NA
4
C 57 121 C
PCI_AD19 AD18 XTAL1 CORE_ACM2520U CORE_ACM2520U CORE_ACM2520U CORE_ACM2520U
1 2 55
r
PCI_AD20 AD19 LAN_XTAL2
53 122
AD20 XTAL2
1
120Z/100M/NA C903 C890 PCI_AD21 50 MDI0- 1 2 PMDI0- MDI1- 1 2 PMDI1- MDI2- 1 2 PMDI2- MDI3- 1 2 PMDI3-
2012 PCI_AD22 AD21
0.1U/NA 0.1U/NA 49
c m
AD22
ADD if use RTL8110S 0402 0402 PCI_AD23 47
AD23
R304 0/NA 0603 R297 0/NA 0603 R278 0/NA 0603 R263 0/NA 0603
10% 10% PCI_AD24
2
43
16V 16V AD24
PCI_AD25 42 ADD if use RTL8110S
e
PCI_AD26 AD25 CTRL18
40 125
PCI_AD27 AD26 NC_13
39 8
AD27 CTRL25
u
GND PCI_AD28 37 R1099
AD28
S
PCI_AD29 36 127 1 2 5.6K
PCI_AD30 AD29 RSET 0402 GND
34
AD30
c
PCI_AD31 33 1%
AD31
Change to 2.49K when use
c Do
PCI_C/BE#[0..3] PCI_C/BE#0 92
13,17,18,19 PCI_C/BE#[0..3] PCI_C/BE#1 77
CBEB0 RTL8110S
PCI_C/BE#2 CBEB1 LED0
60 117
PCI_C/BE#3 CBEB2 LED0 LED1
44 115
a
CBEB3 LED1 LED2
114
LED2 LED3
28 113
11 PCICLK_LAN PCICLK NC_14 JO718
65 2 1
13,17,19,24 PCLKRUN# CLKRUNB
iT ial
68
13,17,18,19,24 PCI_DEVSEL# DEVSELB
13,17,18,19,24 PCI_FRAME#
61
FRAMEB
It's should be NA when 2 1 JO719
13,24 PCI_GNT3#
29
GNTB change to RTL8110S GND_45
30 DVDD Use H1285 for RTL8100C 2 1 JO720
PCI_AD18 13,24 PCI_REQ3# R947 100 REQB
1 2 0402 46 11 L735
IDSEL NC_15 V_12P U716
25 12 2 1 2 1
13,24 PCI_INTE# INTAB AVDD25 PMDI0+ PJTX+
63 72 12 13
IRDYB NC_16
1
13,17,18,19,24 PCI_IRDY# J709
M t
67 74 120Z/100M JO721
13,17,18,19,24 PCI_TRDY# TRDYB NC_17 C889 2012 PMDI0- PJTX1- MDO3-
76 11 14 8
13,17,18,19 PCI_PAR PAR C845 MDO3+ 8
88 7
NC_8 0.1U 0.01U/NA 2 V_DAC MCT4 PJRX- 7 RJ45
2
70 1 10 15 6
13,17,18,19,24 PCI_PERR# PERRB 0402 6
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
75 0402 MDO2- 5
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
13,17,19,24 PCI_SERR# SERRB 16V 5

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
69 PMDI1+ 9 16 PJRX+ MDO2+ 4
n
13,17,18,19,24 PCI_STOP# STOPB GND 10% GND PJRX+ 4
27 3
13 LAN_PCIRST# PCIRSTB PMDI1- PJRX- PJTX1- 3
8 17 2
C835 PJTX+ 2
100
112
118
101
119
123
124
128
e
RTL8100CL
22
35
48
52
62
73
80
21
38
51
66
81
91
13
17
1
1
B B
0.1U 2 V_DAC MCT3
9
4
PQFP128A_0.5MM 1 7 18
R1070 0402 MODEMP A2
1K/NA 20 MODEMP MODEMN A2 RJ11
Crystal should be placed PMDI2+ 6 19 MDO2+
20 MODEMN A1
A1
0402 GND
id
far away from I/O port and 5% PMDI2- 5 20 MDO2- GND1
C849 GND1
Tx,Rx,power,magnetics. ADD if use RTL8110S
2
GND2
GND2
2
0.01U/NA 2 1 V_DAC 4 21 MCT2
f
GND GND 0402 RJ11-2P/RJ45-8P
LAN_XTAL1 GND PMDI3+ 3 22 MDO3+ C10037-102XX
GND JO717 JO716 JO715 JO714
LAN_XTAL2 PMDI3- 2 23 MDO3- GND_45 GND_45
n
R1101 C854
2 1 0.01U/NA 2 1 V_DAC 1 24 MCT1
0402
1
R943
o
1M
0402 1% AVDDL 2 1 0/NA V_DAC GND H5007/NA
X706
R944
0805 Add thease caps when H500X
1 2
C
DVDD 2 1 0/NA use RTL8110S, and
25MHZ 0805 C879 change to 0.01U GND_45
1
C914 TXC8X4.5 C915

27P 274012500415 27P Add AVDDL to V_DAC, when
0402 0402 change to RTL8110S
5% 5%
2
1 2
L719
GND GND +3V 0
+3VS 0603
U717
PMDI0- 7 10 PJTX1- GND GND_45
TD+ TX+
1
V_DAC 6 11 MCT4 PJTX-

PJTX+
R1115 PMDI0+ TDC TXC PJRX-
8 9 1 2
A
10K TD- TX- PJRX+

D707 D708 D709 D710 0402 PMDI1- 1 16 L728
R1111 5% V_DAC RD+ RX+ MCT3
3 14 1 8 RP27MDO2+ 0
PMDI1+ RDC RXC
7 0*4 MDO2- 0603
2
1 2 ICH_RI# 13 2 15 2
0 5% RD- RX-
3 6 1206MDO3+ GND GND_45
3
A CL-190G/NA CL-190G/NA CL-190G/NACL-190G/NA 0402 4 12 4 5 MDO3- A

LAN_WAKE 2 NC0 NC2
1K
1K
1K
1K
R1 Q709 R1114 5 13 R271

R1097 R1102 R1107 R1109 NC1 NC3 75
1 2 KBC_RI# 22 1 2
510/NA 510/NA 510/NA 510/NA DTC144TKA 0/NA R277 0402
288202240001 LF-H80P
0402 0402 0402 0402 0402 5% 75
1
SOX16 1 2
1% 1% 1% 1% 0402
Pull high at EC side. MCT4 R152 1 2 75
LED0 0402 C327
2
1
LED1 MCT3 R930 1 2 75 1000P
LED2 0402 2KV
LED3 GND MCT2 R262 1 2 75/NA 1808
0402 10%
2
MCT1 R254 1 2 75/NA Title
0402 8050D MOTHER B/D
GND_45 Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
JS5
CardBus &
1 2
+CARD_VCC
SHORT-SMT4
CB710 +CARD_VCC
Reader(CB710)
GND_C1 JS7
IDSEL: AD20 1 2
PCI REQ0# SHORT-SMT4

GND_C2 GND
PCI GNT0#
2
+CARD_VCC
1
R1187 R1188 R1189 C983 JS4
PCI INTB# +3V 43.2K 10K 43.2K 0.1U 1 2
INTC# VPPD1 0402 0402 0402 0402
1
VPPD0 1% 1% 10% SHORT-SMT4
2
C984
16V GND_C3 JS8
1
0.1U
0402 J6 1 2
CARD_PCIRST# R1190 1 0 2 5% 10% GND
2
1 35
D
0402G_DFS 16V GND CRST# CAD0 1 35 CCD1# SHORT-SMT4 D
2 36
GND CAD1 2 36 CAD2 GND_C4 GND
3 37
W12
M17
G19
R13
A11
B14
E11
P17
K18
E18
B10
F12
F17
F18
F19
3 37
M5
G2
CCLKRUN# CAD3 CAD4
D1
U7
C9
C5
E7
P2
P9
E8
E5
U727
F3
L3
4 38
J5
CAD5 4 38 CAD6
5 39
CAD11 CAD7 5 39 R2_D14
6 40
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCCA
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
VPPD2
VPPD1
VPPD0
G_RST
NC
CCBE0# 6 40 CAD8
7 41
CAD9 7 41 CAD10
8 42
CAD11 8 42 CVS1
9 43
+SD_MSVDD CAD12 9 43 CAD13
10 44
PCI_AD[0..31] CAD14 10 44 CAD15
11 45
13,16,18,19 PCI_AD[0..31] PCI_AD0 CCBE1# 11 45 CAD16
H5 V15 12 46
PCI_AD1 AD0 VCC_SD SD_PWREN# CPAR 12 46 R2_A18
G1 P13 13 47
PCI_AD2 AD1 SD_PWREN# R1191 1 0 CPERR# 13 47 CBLOCK#
G3 V14 2 5% 14 48
PCI_AD3 AD2 SD_CLKIN SD_CLK1 0402G_DFS CGNT# 14 48 CSTOP#
H6 P14 15 49
PCI_AD4 AD3 SD_CLK SD_CMD +VPPOUT CINT# 15 49 CDEVSEL#
F1 R14 16 50
PCI_AD5 AD4 SD_CMD SD_WP# GND 16 50
G5 V13 17 51
PCI_AD6 AD5 SD_WP SDCD# 17 51
F2 U13 18 52 +VPPOUT
PCI_AD7 AD6 SD_CD# SD_LED# CCLK 18 52 CTRDY#
E1 W14 19 53
AD7 SD_LED# 19 53
1
PCI_AD8 G6 W15 SD0 C985 C986 CIRDY# 20 54 CFRAME#
PCI_AD9 AD8 SD_DAT0 SD1 CCBE2# 20 54 CAD17
F5 U14 0.1U 0.1U 21 55
PCI_AD10 AD9 SD_DAT1 SD2 0402 0402 CAD18 21 55 CAD19
E3 W16 22 56
PCI_AD11 AD10 SD_DAT2 SD3 10% 10% CAD20 22 56 CVS2
2
C12 U15 23 57
PCI_AD12 AD11 SD_DAT3 16V 16V CAD21 23 57 CRST#
A4 24 58
PCI_AD13 AD12 CAD22 24 58 CSERR#
E6 25 59
PCI_AD14 AD13 SM_PWR5EN# R1192 2 10K CAD23 25 59 CREQ#
B5 J15 1 0402 26 60
PCI_AD15 AD14 SM_PWR5EN# SM_PWR3EN# R1241 2 10K CAD24 26 60 CCBE3#
F6 H19 1 0402 GND 27 61
PCI_AD16 AD15 SM_PWR3EN# SM_WPD# CAD25 27 61 CAUDIO
B8 H18 28 62
PCI_AD17 AD16 SM_WPD# SM_WP# TP707 CAD26 28 62 CSTSCHG
A8 K17 1 29 63
PCI_AD18 AD17 SM_WP# SM_CE# CAD27 29 63 CAD28
E9 J14 30 64
PCI_AD19 AD18 SM_CE# SM_RE# CAD29 30 64 CAD30
F9 J18 31 65
t
PCI_AD20 AD19 SM_RE# SM_LED# R1242 2 10K R2_D2 31 65 CAD31
B9 H17 1 0402 32 66
PCI_AD21 AD20 SM_LED# SM_CD# CCLKRUN# 32 66 CCD2#
A9 N19 33 67
PCI_AD22 AD21 SM_CD# SM_R/B# 33 67
F10 K14 34 68
AD22 SM_R/B# 34 68
t
PCI_AD23 E10 K15 SM_W E#
n
PCI_AD24 AD23 SM_WE# SM_ALE TP708 GND
F11 J19 1 GND1
PCI_AD25 AD24 SM_ALE SM_LVD GND1
E13 K19 GND2
AD25 SM_LVD GND2
e e
PCI_AD26 C11 J17 SM_CLE 1 TP709 GND3
PCI_AD27 AD26 SM_CLE SM_SD0 TP16 GND3
C B11 L14 1 GND4 C
PCI_INTB# R1193 1 0 AD27 SM_D0 SM_SD1 GND4
2 5% PCI_AD28 A12 L17 1 TP711 GND5
r
13,24 PCI_INTB# 0402G_DFS PCI_AD29 AD28 SM_D1 SM_SD2 TP712 GND5
B12 L19 1 GND6
PCI_AD30 AD29 SM_D2 SM_SD3 TP713 GND6
E12 M18 1 GND7
PCI_INTC# 0 AD30 SM_D3 SM_SD4 GND7
1 2 5% PCI_AD31 A13 M15 1 TP18 GND8
c m
13,24 PCI_INTC# R1194 0402G_DFS AD31 SM_D4 SM_SD5 TP715 GND8
F15 M19 1
PCI_INTF# MFUNC0 SM_D5 SM_SD6
1 0/NA 2 0402 CARD_MF1 E17 L18 1 TP716 GND_C1 GND_C3 FM/34PX2/1.27MM
13,19,24 PCI_INTF# R1238 5% MFUNC1 SM_D6 SM_SD7 TP19
A16 L15 1 ACECON
e
SERIRQ R1195 1 0/NA 2 MFUNC2 SM_D7
C15 MF-291000000008
0402 5% RI# MFUNC3 GND_C2 GND_C4
E14
MFUNC4
u
CARD_ACT F13 N14 291000256843 GND
MFUNC5 VCC_SC
S
PCLKRUN# B15 N15 SC_PWR5EN# 1 R1196 2
13,16,19,24 PCLKRUN# MFUNC6 SC_PWR5EN# SC_PWR3EN# 1 10K/NA 20402 GND
VCC5_EN# E19 P18
VCCD0# SC_PWR3EN#
c
VCC3_EN# F14 R17 R1197 10K/NA 0402 R1198
VCCD1# SC_CLK +3V SD_CLK1 1 SD_CLK
T19 2
SC_IO
c Do
A10 P15 10
11 PCICLK_CARD PCLK SC_RST# 0402
G15 P19 1 2
SPKROUT SC_CD#
1
20 CARDSPK# R1199 10K 0402 5%
C14 M14 C987
13 CARDBUS_PME# R1200 RI_OUT#PME# SC_LED#
1 4.7K 2 0402 D19 N18 1 2 10P
a
13,22,23,25 SUSB# CARD_PCIRST# SUSPEND# SC_OC#
A14 R19 R1201 10K 0402 0402
13 CARD_PCIRST# PRST# SC_C8 5%
2
13,24 PCI_GNT0# C13 R18
GNT# SC_C4 50V
13,24 PCI_REQ0# B13
PCI_AD20 R1202 REQ#
1 100 GND
iT ial
2 C10
0402 5% IDSEL MS_PWREN# R1203
13,16,18,19,24 PCI_FRAME# F8 P12 J716
FRAME# MS_PWREN# MS_CLK1 MS_CLK1 1 MS_SCLK SDCD# MS_INS#
13,16,18,19,24 PCI_IRDY# A7 U12 2 1 2
IRDY# MS_SCLK R1204 1 0 10 SD_WP#
13,16,18,19,24 PCI_TRDY# B7 W13 2 GND 3 4
TRDY# MS_CLKIN MS_BS 0402_DFS 5% 0402 MS_SCLK SD_CMD
13,16,18,19,24 PCI_DEVSEL# C7 P11 5 6
DEVSEL# MS_BS
1
F7 R12 MS_LED# 5% C988 SD_CLK 7 8 SD0
13,16,18,19,24 PCI_STOP# STOP# MS_LED# MS_INS# SD1 SD2
13,16,18,19,24 PCI_PERR# A6 V12 10P 9 10
PERR# MS_INS# SD3 MS_BS
M t
B6 R11 MS_SDIO 0402 11 12
13,16,19,24 PCI_SERR# SERR# MS_SDIO 5% MS_SDIO
2
13,16,18,19 PCI_PAR C6 13 14
PAR 50V +SD_MSVDD
E2 15 16
13,16,18,19 PCI_C/BE#0 C/BE0# +SD_MSVDD GND
A5 G17 17 18
13,16,18,19 PCI_C/BE#1 C/BE1# GPIO5 R431 1 0 5% 2 0402
C8 G18 19 20
13,16,18,19 PCI_C/BE#2 C/BE2# GPIO6 43.2K
A15 H15 1 R1205 2 0402 1% SM_W E# R440 1 0 5% 2 0402 21 22
n
13,16,18,19 PCI_C/BE#3 C/BE3# GPIO7 43.2K
H14 1 R1206 2 0402 1% SM_RE# R435 1 0/NA5% 2 0402 23 24
SERIRQ GPIO8 43.2K +SD_MSVDD
13,14,19,22 SERIRQ G14 N17 1 R1207 2 0402 1% SM_CE# R444 1 0/NA5% 2 0402 25 26
IRQSER GPIO9
U11 27 28
e
B GPIO10 B
V11 29 30
GPIO11 43.2K R1208 0402 1% MS_BS
1 2
43.2K 1 R1209 2 0402 1% MS_SDIO GND1
1
43.2K 1 R1210 2 0402 1% MS_SCLK GND2
D14/RSVD (R_D14)
id
C465 C463
A18/RSVD (R_A18)
+3VS 43.2K 1 R1211 2 0402 1% SM_LVD 0.1U 10U GND3 GND

D2/RSVD (R_D2)
BVD1/CSTSCHG
INPACK/CREQ#
WAIT#/CSERR#
WP/CCLKRUN#
A21/CDEVSEL#
RESET/CRST#
0402 0805
REG#/CCBE3#
A23/CFRAME#
IOWR#/CAD15
BVD2/CAUDIO
GND4
A19/CBLOCK#
CE1#/CCBE0#
READY/CINT#
IORD#/CAD13
CD1#/CCD1#
CD2#/CCD2#
A14/CPERR#
A22/CTRDY#
A20/CSTOP#
CE2#/CAD10
A12/CCBE2#
+80-20% 6.3V
WE#/CGNT#
A15/CIRDY#
2
GND5
OE#/CAD11
A8/CCBE1#
D10/CAD31
VS1#/CVS1
VS2#/CVS2
A11/CAD12
A17/CAD16
A24/CAD17
A25/CAD19
f
50V 10%
A13/CPAR
D11/CAD2
D12/CAD4
D13/CAD6
D15/CAD8
D0/CAD27
D8/CAD28
D1/CAD29
D9/CAD30
A10/CAD9
A9/CAD14
A7/CAD18
A6/CAD20
A5/CAD21
A4/CAD22
A3/CAD23
A2/CAD24
A1/CAD25
A0/CAD26
A16/CCLK
GND GND6
D3/CAD0
D4/CAD1
D5/CAD3
D6/CAD5
D7/CAD7
2
2
R1212 GND MA/15PX2/ST

10K/NA ACES
n
0402 GND 88025-3000
W10
W11
+SD_MSVDD
U10
R10
V10
P10
W4
W6
W7
W9
W8
W5
M1
M3
M2
M6
291000013027
H2
H1
U5
R6
U6
R8
H3
R9
U8
N1
N2
N6
N5
R1
R2
N3
U9
R7
CFRAME# R3
K1
K3
K5
V5
V6
V7
P7
K6
P8
K2
P3
CSTSCHG V9
V8
P5
P1
P6
T1
CB710
L1
L2
L6
L5
J1
J3
J2
J6
C989 GND
1
BGA_GHK_209
o
RI#
CDEVSEL#
3 1 1 2
1
CBLOCK#
CSERR#
CPERR#
CTRDY#
CCBE0#
CCBE1#
CCBE2#
CCBE3#
CSTOP#
CAUDIO
R2_D14
CIRDY#
2
R2_A18
CREQ#
CGNT#
CAD10
CAD11
CAD12
CAD13
CAD14
CAD15
CAD16
CAD17
CAD18
CAD19
CAD20
CAD21
CAD22
CAD23
CAD24
CAD25
CAD26
CAD27
CAD28
CAD29
CAD30
CAD31
CCD1#
CCD2#
CRST#
Q714 L54
R2_D2
CINT#
CPAR
CVS1
CVS2
CAD0
CAD1
CAD2
CAD3
CAD4
CAD5
CAD6
CAD7
CAD8
CAD9
DTC144WK/NA 0.1U/NA R1213 Q24 120Z/100M R552
C
0402 33 SI2301DS 2012 K A 1 0402 2 5% +3V
16V 0402 273000150013 220
10% D36
D
2
S
D
Multi Function pin need pull up. CL-190G
1
2
+3V S D
R1214 D Q716
1
G S
1
0 4,12,13,25,31 PWROK 2N7002
G
+3VS CCLK R376 C341
5%
2S
100K 0.1U
R1216 CARD_MF1 0402G_DFS
1 4.7K/NA 2 0402 0402 0402
1
+3V 5% 10% R1217
2
R1218 1 4.7K/NA 2 0402 RI# +3V CCLKRUN# 16V
2
0
2
2
R1220 CARD_ACT 5%
1 4.7K/NA 2 0402
R1221 43.2K R1224 0402 1% SDCD# R377 R378 0402G_DFS
1
1 2
10K 43.2K 1 R1225 2 0402 1% SD_WP# SD_PWREN# 10K
0402 43.2K R1226 0402 1% MS_INS# 0402 1K SD_LED#
1 2
8.2K R1228 0402 SM_CD# MS_PWREN# 0402
1 2
+3V +5V +3V U728 8.2K R1230 0402 SM_WPD# (43K) 5% MS_LED#
1
1
1 2
VCC5_EN# 1 16 8.2K 1 R1231 2 0402 SM_R/B#
VCC3_EN# VCCD0 SHDN VPPD0
A 2 15 A
VCCD1 VDDP0
2
3 14 VPPD1 +CARD_VCC
R1229 3.3VA VDDP1
4 13
10K 3.3VB AVCCA +VPPOUT GND
5 12
0402 5VA AVCCB +3V
6 11
5VB AVCCC
7 10
GND AVPP +SD_MSVDD
1
8 9
OC 12V
1
1
C991 C992 TPS2211A SSOP16 43.2K 1 R388 2 0402 1% SD3 C993 C994 C995 C996 C997 C998 C999 C1000
1
0.1U 0.1U C1001 C1002 43.2K 1 R1233 2 0402 1% SD_CMD 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
0402 0402 286302211006 2.2U 1U 43.2K/NA 1 R1234 2 0402 1% SD_CLK 0402 0402 0402 0402 0402 0402 0402 0402
10% 10% 0603 0402 10% 10% 10% 10% 10% 10% 10% 10%
2
2
16V 16V GND +/-10% +80-20% 43.2K 1 R1235 2 0402 1% SD0 16V 16V 16V 16V 16V 16V 16V 16V Title
2
10V 43.2K 1 R389 2 0402 1% SD1 8050D MOTHER B/D

GND GND GND GND 43.2K 1 R1237 2 0402 1% SD2
GND Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
1394_AVCC:Because of
IEEE1394(VT6307L)
suspend then resume 1394_AVCC
unknow, us suspend
power +3V ALL Capacator must close to power pin
VT6307L
1
C956 C957 C936
IDSEL: AD21 0.1U 0.1U 0.1U
0402 0402 0402
PCI REQ1# +80-20% +80-20% +80-20% +PHYVDD +PHYVDD 1394_AVCC
1
50V 50V 50V C919 C918 C917 +3V +3VS
PCI GNT1# +3V 0.1U 0.1U 0.1U L743 L746
0402 0402 0402 1 2 1 2
PCI INTG# GND
+80-20% +80-20% +80-20% 120Z/100M 120Z/100M
1
D 50V 50V 50V D
C923 C922 C925 2012 +3V 2012
1
C931 C954 C924 C920 C916 0.1U 0.1U 0.1U +3VS C921
0.1U 0.1U 0.1U 0.1U 0.1U +PHYVDD GND 0402 0402 0402 L742 2.2U
1
0402 0402 0402 0402 0402 +80-20% +80-20% +80-20% +80-20%
2
1 2 1 2 C961 C955
+80-20% +80-20% +80-20% +80-20% +80-20% 50V 50V 50V 120Z/100M/NA L739
2
0805C 2.2U 0.1U
50V 50V 50V 50V 50V 2012 120Z/100M/NA +80-20% 0402
+80-20%
2
0805C
GND GND 50V
GND
102
113
114
125
20
33
35
65
75
89
62
76
90
24
39
49
8
PCI_AD[0..31] U724
13,16,17,19 PCI_AD[0..31]
PCI_AD0 28 54 1394_AGND
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCCARX0
VCCARX1
VCCARX2
VCCATX0
VCCATX1
VCCATX2
VCCRAM
VCCSUS[0]
VCCSUS[1]
PCI_AD1 AD0 PHYPC0
27 55
PCI_AD2 AD1 PHYPC1
23 53
PCI_AD3 AD2 PHYPC2
22
PCI_AD4 AD3
21 52
PCI_AD5 AD4 PHYCMC
19
PCI_AD6 AD5 R1112
18
PCI_AD7 AD6
17 46 1 2
PCI_AD8 AD7 12CEEENA 4.7K/NA 0402 5% +3V
14 48
PCI_AD9 AD8 I2CFAST
13
PCI_AD10 AD9
12 47
PCI_AD11 AD10 CARDBUSENA
11
PCI_AD12 AD11
10
PCI_AD13 AD12 TPA-_6307
7 72
PCI_AD14 AD13 XTPA0M TPA+_6307
6 73
PCI_AD15 AD14 XTPA0P TPB+_6307
5 71
PCI_AD16 AD15 XTPB0P TPB-_6307
120 70
PCI_AD17 AD16 XTPB0M
119
AD17
1
PCI_AD18 118 80
t
PCI_AD19 AD18 XTPA1P R1144 R1143 R1141 R1142
117 79
PCI_AD20 AD19 XTPA1M 54.9 54.9 54.9 54.9
116 78
PCI_AD21 AD20 XTPB1P 0402 0402 0402 0402
112 77
AD21 XTPB1M
t
PCI_AD22 110 1% 1% 1% 1%
n
PCI_AD23 AD22 TPBIAS
2
109 87
PCI_AD24 AD23 XTPA2P
106 86
AD24 XTPA2M
1
e e
PCI_AD25 105 85
AD25 XTPB2P
1
C PCI_AD26 104 84 R1148 C965 C964 C
PCI_AD27 AD26 XTPB2M 4.99K
101 270P 0.33U
r
PCI_AD28 AD27 TPBIAS 0402 0402 0402
100 74
PCI_AD29 AD28 XTPBIAS0 1% +/-10% +80-20%
2
99 81
PCI_AD30 AD29 XTPBIAS1 50V 16V
2
98 88
c m
PCI_AD31 AD30 XTPBIAS2
97
AD31
63
XCPS GND
13,16,17,19 PCI_C/BE#0 15 66 GND
e
CBE0# XRES
13,16,17,19 PCI_C/BE#1 4
CBE1#
1
122 60 XI
13,16,17,19 PCI_C/BE#2 CBE2# XI
1
u
107 61 XO R1145 C958
13,16,17,19 PCI_C/BE#3 CBE3# XO
S
6.34K 47P R1146 1 1K/NA 2
EECS_1394 0402 0402 0402 5% +3V
29
EECS/EEAUTO#
1
c
EEDO_1394 1% +/-10%
2
13,16,17,19,24 PCI_FRAME# 123 30
FRAME# EEDO EEDI_1394 50V R1147 +3V
2
13,16,17,19,24 PCI_DEVSEL# 127 31
DEVSEL# EEDI/SDA
c Do
126 32 EECK_1394 1K U722
13,16,17,19,24 PCI_TRDY# TRDY# EECK/SCL/EEFAST 0402 EECS_1394
124 GND 1 8
13,16,17,19,24 PCI_IRDY# IRDY# 5% EECK_1394 CS VCC
13,24 PCI_GNT1# 95 37 PCI_PME# 13 2 7
PGNT# PME# SK NC1
1
EEDI_1394
2
96 3 6 C907
a
13,24 PCI_REQ1# PREQ# EEDO_1394 DI NC0
PCI_AD21 R1117 1 100 2 108 43 4 5 1U
0402 1% IDSEL MODE0 DO GND 0402
13,24 PCI_INTG# 91 42
INTA# MODE1 GND +80-20%
2
11 PCICLK_1394 93 93C46
PCICLK 10V
iT ial
13 1394_PCIRST# 92 38 SO8
PCIRST# NC0 XI
13,16,17,19 PCI_PAR 3 40 283467540002 GND
PAR NC1
13,16,17,19,24 PCI_PERR# 2 44
PERR# NC2
128 45
GNDSUS[0]
GNDSUS[1]
13,16,17,19,24 PCI_STOP# STOP# NC3 R1116
GNDARX0
GNDARX1
GNDARX2
GNDATX0
GNDATX1
GNDATX2
58 GNDRAM 51
PHYRST# NC4 XO
56 1 2
GND10
NC5
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
57 1M
NC6 Configuration Straps
1
M t
C928 67 0402
NC7 5%
0.1U
0402
103
111
115
121
VT6307L
16
26
34
36
94
64
68
82
59
69
83
25
41
50
+80-20% I2CEEENA I2C EEPROM.

2
1
9
PQFP128A_0.5MM X707
50V 1 2
0: 4-wire EEPROM interface(Default)
n
GND 24.576MHZ
TXC8X4.5 1: 2-wire I2C EEPROM interface
274012457406 using SCL/SDA
e 1
1
B B
GND 1394_AGND GND C932 C929 I2CFAST I2C EEPROM Fast Mode
10P 10P
0402 0402 0: Disable (Default)
5% 5%
2
id
50V 50V 1: Enable
GND GND CARDBUSENA CardBus Mode
f
0: Disable (PCI)(Default)
1: Enable
n
PHYCMC Programmable Contender / Bus Manager Capable
o
High specifies that the node is capable of
being a bus manager.
R1149 1 0/NA 2 0402 5%
C
3
L740
TPB-_6307 120Z/100M
J718
TPB- CORE_ACM2520U
2
1
TPB+_6307 TPB+ 1
2
2
3
R1139 3
1 0/NA 2 0402 5% 4
4
R543 1 0/NA 2 0402 5% 5
GND0
6
A
GND1
2
TPA-_6307 TPA- L747

TPA+ D28 D711 D30 D706 4PX1/0.8MM-MA 1 2
TPA+_6307 MOLEX 120Z/100M
3
JO53 JO48 JO52 JO49 54030-0411 2012

A L83 ESD0805A/NA ESD0805A/NA 331000004009 A
ESD0805A/NA ESD0805A/NA
120Z/100M L87
K
CORE_ACM2520U GND 1394_AGND

2
1 2
120Z/100M
2012 Because of EMC notice, change
R534 1 0/NA 2 0402 5%
1394_GND GND L547 to 0 ohm 0805
1394_GND
1394_GND
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
MINI-PCI FROM LYNX-AMD

+3V
PCI_AD[0..31]
MINI-PCI 13,16,17,18 PCI_AD[0..31]
J713
AD17 1 2
TIP RING
3 4
PCI_INTD# +3V 5
RX+ TX+
6 +5V
R1007 1 10K RX- TX-
2 7 8
D REQ2#/GNT2# 0402 5% 9
PJ7 PJ4
10
D
PJ8 PJ5
11 12
MINIPCI_PD R1003 1 0 LED1_GRNP LED2_YELP
2 13 14
0402 5% LED1_GRNN LED2_YELN MINIPCI_LPCAD1
15 16
CHSGND RESERVED4
17 18 TP721
INTB# 5V[1] R1068 1 0
19 20 2 0402 5%
PCI_INTD# 13,24 TOUCHPAD_10
R1064 1 0/NA 3.3V[0] INTA# MINIPCI_LPCAD2
13,17,24 PCI_INTF# 2 21 22
0402 5% MINIPCI_LPCDRQ# RESERVED0 RESERVED5 R1077 1 0 5% MINIPCI_PCIRST#
23 24 2 0402 MINIPCI_PCIRST# 13
PCICLK_MINIPCI R1079 1 0 GROUND0 3.3VAUX[0] R1078 1 0/NA
11 PCICLK_MINIPCI 2 25 26 2 0402 5% MINIPCI_GPORESET#
0402 5% C885 CLK RST#
1
27 28
GROUND1 3.3V[4]
1
10P/NA R1083 1 0 2 MINI_REQ2# 29 30 R1080 1 0 2 0402 5%
13,24 PCI_REQ2# REQ# GNT# PCI_GNT2# 13,24
0402 0402 5% 31 32
+/-10% PCI_AD31 3.3V[1] GROUND9 PCI_PME#
33 34 MINIPCI_PME# 13
+3V 50V PCI_AD29 AD[31] PME# MINIPCI_LPCAD3
2
35 36
AD[29] RESERVED6 PCI_AD30
37 38
GND PCI_AD27 GROUND2 AD[30]
39 40
PCI_AD25 AD[27] 3.3V[5] PCI_AD28
41 42
AD[25] AD[28]
1
C875 C888 C898 C901 MINIPCI_LPCFRAME# 43 44 PCI_AD26

PCI_CBE#3 RESERVED1 AD[26] PCI_AD24
2.2U 0.1U 0.1U 0.1U 13,16,17,18 PCI_C/BE#3 45 46
0603 0402 0402 0402 PCI_AD23 C/BE[3]# AD[24] R1092 1 100 2 PCI_AD17
47 48
+/-10% +80-20% +80-20% +80-20% AD[23] IDSEL 0402 1%
2
49 50
50V 50V 50V PCI_AD21 GROUND3 GROUND10 PCI_AD22
51 52
PCI_AD19 AD[21] AD[22] PCI_AD20
53 54
+3V GND AD[19] AD[20] PCI_PAR
55 56 PCI_PAR 13,16,17,18
PCI_AD17 GROUND4 PAR PCI_AD18 +5V
57 58
PCI_CBE#2 AD[17] AD[18] PCI_AD16
13,16,17,18 PCI_C/BE#2 59 60
PCI_IRDY# C/BE[2]# AD[16]
13,16,17,18,24 PCI_IRDY# 61 62
IRDY# GROUND11
1
C910 C892 C899 C909 63 64 PCI_FRAME#

3.3V[2] FRAME# PCI_FRAME# 13,16,17,18,24
1
0.1U 0.1U 0.1U 0.1U PCLKRUN# 65 66 PCI_TRDY#
13,16,17,24 PCLKRUN# CLKRUN# TRDY# PCI_TRDY# 13,16,17,18,24
0402 0402 0402 0402 PCI_SERR# 67 68 PCI_STOP# R558
t
+80-20% +80-20% +80-20% +80-20% 13,16,17,24 PCI_SERR# SERR# STOP# PCI_STOP# 13,16,17,18,24 470
2
69 70
50V 50V 50V 50V PCI_PERR# GROUND5 3.3V[6] PCI_DEVSEL# 0402
13,16,17,18,24 PCI_PERR# 71 72 PCI_DEVSEL# 13,16,17,18,24
PCI_CBE#1 PERR# DEVSEL# 5%
73 74
2A
13,16,17,18 PCI_C/BE#1 C/BE[1]# GROUND12
t
GND PCI_AD14 75 76 PCI_AD15
n
AD[14] AD[15] PCI_AD13 D38
77 78
PCI_AD12 GROUND6 AD[13] PCI_AD11
79 80
AD[12] AD[11] CL-190G
e e
PCI_AD10 81 82
AD[10] GROUND13 PCI_AD9 LED_CL190
C 83 84 C
PCI_AD8 GROUND7 AD[9] PCI_CBE#0
85 86 PCI_C/BE#0 13,16,17,18
r
PCI_AD7 AD[8] C/BE[0]#
K
87 88
AD[7] 3.3V[7] PCI_AD6 R1095
89 90 1 0/NA 2 0402 5%
PCI_AD5 3.3V[3] AD[6] PCI_AD4
91 92
c m
AD[5] AD[4] PCI_AD2
93 94
RESERVED2 AD[2]
3
PCI_AD3 95 96 PCI_AD0
AD[3] AD[0] R1094 1 0 R1
97 98 2 0402 MINIPCI_PD 2 Q710
e
PCI_AD1 5V[0] RESERVED_WIP4[0] 5%
99 100
AD[1] RESERVED_WIP4[1] DTC144TKA
101 102
+5V GROUND8 GROUND14 288202240001
u
MINIPCI_LPCAD0
1
103 104
AC_SYNC M66EN
S
105 106 WIRELESS_PD# 14,24
AC_SDATA_IN AC_SDATA_OUT
2
107 108
AC_BIT_CLK AC_CODEC_ID0#
c
R1093 109 110
AC_CODEC_ID1# AC_RESET# MINIPCI_PCISERIRQ
111 112
0/NA MOD_AUDIO_MON RESERVED7
c Do
113 114 GND
0402 AUDIO_GND0 GROUND15
115 116
5% SYS_AUDIO_OUT SYS_AUDIO_IN
1
117 118
SYS_AUDIO_OUT_GND SYS_AUDIO_IN_GND
119 120
a
MINIPCI_SIO48M AUDIO_GND1 AUDIO_GND2 R1138
121 122 1 0 2 0402 5%
MINIPCI_ACT# 14,24
RESERVED3 MPCIACT#
123 124
VCC5VA 3.3VAUX[1] R1076 1 0/NA 2 0402 +3V
5%
iT ial
GND1
GND1 R1072 1 0
GND2 2 5% +3VS
GND2 0402G_DFS
124P/0.8MM/H6
SPEED 291000251246
1
R1096 1 0 2 0402 5% MINIPCI_LPCAD0 SPEED-B27-101-0038 C881
13,22,23 LAD0 MINIPCI_LPCAD1
R1065 1 0 2 0402 5% 0.1U PIN24, 124 ARE AUX_POWER
13,22,23 LAD1 MINIPCI_LPCAD2
M t
R1069 1 0 2 0402 5% 0402
13,22,23 LAD2 MINIPCI_LPCAD3 +80-20%
R1088 0 0402 5%
2
13,22,23 LAD3 1 2
50V
R1075 1 0 2 0402 5% MINIPCI_LPCDRQ#
13 LRDQ0# MINIPCI_PCISERIRQ
R1118 1 0 2 0402 5% GND GND GND
13,14,17,22 SERIRQ MINIPCI_LPCFRAME#
R1091 1 0 2 0402 5% GND
n
13,22,23 LFRAME# MINIPCI_SIO48M
R1137 1 0 2 0402 5%
11 SIO_48M
e
B B
fid
on
C
A A
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
AUDIO CODEC(ALC655)
VA +5V BEAD_600Z/100M MIC1
C460 0.1U 10% VA 120Z/100M/NA L7341 2 0603D 1 +
10% L64 2 1 2012 L70 1 2 0603D 2 -
1
16V 1 2 C942 BEAD_600Z/100M
0402 U18 47P/NA D5.8/H2.0
0.1U 5 1 0402 EM147TK
OUT IN
2
C457 0402 16V +/-10%
2
2 339115000046
GND
1
SBSPKR 1 2 GND 4 3 50V JO724
13,14 SBSPKR R484 ADJ EN D705
U17
1 5 R438 C456 180K/NA ESD0805A/NA SPARKGAP_6
CARDSPK#1 A VCC PC_BEEP 0603 MIC5205BM5 0603B_0805C
2 2 4 1 2 1 2
D 17 CARDSPK# B Y 1% SOT25
D
3
GND
1
C458 10K 1U C475 AGND AGND
2
1
1
0.1U 0402 0402 10U R1150 1 0
1
NC7S32 2
1
0402 R442 R443 SOT25 5% R437 C455 10V 1210 0603
1
16V 47K 47K 1K +80-20% 10V R452
2
100P C467 C509
10% 0402 0402 0402 0402 L66 470K/NA 0.01U 2200P
5% 5% 5% +/-10% 120Z/100M AGND 0402 0402 AGND L741 0402
4
50V 2012 5% +80-20% +/-20%
2
2
50V 120Z/100M/NA 50V
2
CORE_ACM2520U CAGND
AGND +3V
1
GND AGND
1
5 J719
4
BEAD_600Z/100M 3
R1151 R1154 R1153 MIC_INT L57 1 2 0603D 6
1
C491 C501 C481 AVDD 1 2 MIC_VREF 1 2 1 2 MIC_EXT 2
10U 0.1U 0.1U 0402 4.7/NA 5% 4.7K 1
0805 0402 0402 0402 5% 0 0402 R1155 1 0 2
2
6.3V 10% 10% 5% C973 0603
2
C968 C938 C972 C948
1
ACBITCLK 10% 16V 16V 0.1U 0.1U 4.7U/NA 0.1U/NA C971 100P/NA L744 RA/D6/6P
0402 0402 0603 0402 0.1U/NA 0402 2SJ-SB2014D3
1
C476 GND GND GND +80-20% +80-20% 6.3V +80-20% 0402 +/-10% BEAD_600Z/100M CAGND CONN_JACK_SB2014
2
22P/NA 50V 50V +80-20% 50V +80-20% 50V 0603D 291000920605
2
0402 AGND AGND 50V
+/-10% U726 AGND AGND JO725
2
1
25
38
1
9
50V AGND 2 1
GND 23 C974 1 2 1U LINE_IN/L 1 R1164 2
DVDD1
DVDD2
AVDD1
AVDD2
LINE-L 0402 10V +80-20% 22K/NA 0402 1%
t
24 C969 1 2 1U LINE_IN/R D718 SPARKGAP_6
LINE-R 0402 10V +80-20% R1157 AGND 1 2
ACRST# 11 21 MIC1 C975 1 2 1U MIC 1 2
14 ACRST# RESET# MIC1
t
ACSDOUT 5 0402 10V +80-20% 5% 0 0402 ESD0805A/NA
n
14 ACSDOUT ACSDIN0 R530 1 SDATA-OUT MIC2 C970
2 22 8 22 1 2 1U AGND 0603B_0805C CAGND
14 ACSDIN0 ACSYNC 0402 5% SDATA-IN MIC2 0402 10V +80-20%
10
14 ACSYNC SYNC
e e
ACBITCLK 1 2 R498 1 2 22 6 20 C513 1 2 1U R547 1 2 6.8K 0402 5% CDROM_RIGHT
14 ACBITCLK BIT-CLK CD-R CDROM_RIGHT 15
C L69 0 1608 0402 5% 0402 10V +80-20% C
18 C507 1 2 1U R538 1 2 6.8K 0402 5% CDROM_LEFT FOR EMI REQUEST CHANGE TO 0 OHM
CDROM_LEFT 15
r
CD-L 0402 10V +80-20%
2
R472 1 0 XTL-IN C515 CDROM_COM M L73 L88
2 19 1 2 0.22U R550 1 2 0 0402 5%
CDROM_COM M 15
11 14M_CODEC 0402 5% CD-GND 0402 16V +80-20%
3 1 2 1 2
c m
XTL-OUT
1 R516 2 16 C979 1 2 1U/NA
JD2
1
PC_BEEP 12 0402 10V +80-20%
1M/NA 0402 PC-BEEP C980
17 1 2 1U/NA R546 R537 R549 120Z/100M 120Z/100M
e
JD1/GPIO1 0402 10V +80-20% 6.8K 6.8K GND 2012 GND 2012
0 AGND AGND
X2 14 C976 1 2 1U 0402 0402
AUX-L 0402
u
1 2 0402 10V +80-20% 5% 5%
S
C959 5%
2 1U C516 2 1U
2
1 31 15 1
24.576MHZ/NA 0402 10V +80-20% VRDA AUX-R 0402 10V +80-20% L65 L62
c
TXC8X4.5 C953 1 2 1U 32 35 AOUT_L 1 2 1 2
FRONT-MIC2 LINE-OUT-L
1
C477 274012457406 C504 0402 10V +80-20% AGND AGND AGND
c Do
22P/NA 22P/NA C952 1 2 1U/NA 33 36 AOUT_R
0402 0402 0402 10V +80-20% NC_0 LINE-OUT-R 120Z/100M 120Z/100M
+/-10% +/-10% C945 2 0.1U/NA C519 1 2 0.1U/NA R559 1 10K/NA2 MODEM_SPK GND 2012 GND 2012
2
1 34 13 AGND AGND
50V 50V 0402 16V 10% FRONT-MIC1 PHONE 0402 16V 10% 0402 5%
a
37 C937 1 2 0.1U MONO_OUT
MONO-OUT 0402 16V 10%
40
NC_1
1
GND GND 43 C933
CEN-OUT
1
AGND C939 2 1U R560
iT ial
44 39 1 1000P/NA C518
LFE-OUT S-OUT-L +80-20% 0402 10V 0402 1K/NA SUB_OUTL R497 1 0/NA 2
45 0.1U/NA 21 SUB_OUTL
JD0/GPIO0 C940 10%
2 1U 0402 0402 0402 5%
2
46 41 1
XTLSEL S-OUT-R +80-20% 0402 10V 50V 5% 10% SUB_OUTR R503 1 0/NA 2
2
47 21 SUB_OUTR
SPDIFI/EAPD C962 16V
2 1000P 0402 5%
2
48 29 1
SPDIFO AFILT1 0402 50V 10%
30 C960 1 2 1000P
AFILT2 AOUT_L
M t
0402 50V 10% AGND AGND R1130 1 4.42K 2 R1135 1 0 2 AMP_LEFT 21
27 20mil 0402 5% 0402 5%
DVSS1
DVSS2
AVSS1
AVSS2
VREF AOUT_R R1127 1 4.42K 2 R1128 1 0 2 AMP_RIGHT 21

28 0402 5% 0402 5%
R1123 2 0/NA JD0 VREFOUT
GND 1 SUB_LEFT 21
1
0402 5%
n
C967 C966 SUB_RIGHT 21
26
42
1
ALC655 R1126 R1129
4
7
0.1U 1U AGND
1
PQFP48_0.5MM C963 R542 0402 0402 27K/NA 27K/NA

R1124 2 0 1U 5.6K 10% +80-20% 0402 0402
2
1
e
B GND 16V 10V B
0402 5% 0402 0402 5% 5%
+80-20% 5%
2
2
10V
2
21 EAPD GND
id
AGND AGND AGND
21 SPDIFOUT AGND
R535 1 0 2 MIC_VREF AGND
f
0402 5%
R532 1 0 2 2464_VREF
2464_VREF 21
0402 5% 273000130006
n
R324 BEAD_600Z/100M 5 J721
LINE_IN/L 1 2 L53 1 2 0603D 4
5% 0 0402 R.CH 3
o
6
LINE_IN/R 1 R519 2 L76 1 2 0603D L.CH 2
5% 0 0402 1
BEAD_600Z/100M
C
1
1
C159 C499
1
100P/NA 100P/NA R325 R520 C498 C330 RA/D6/6P
0402 0402 22K 22K 100P 100P 2SJ-SB2014D3
+/-10% +/-10% 0402 0402 0402 0402 CONN_JACK_SB2014
2
50V 50V 1% 1% +/-10% J11 J10 +/-10% 291000920605
2
MDC 50V 50V
2
CAGND CAGND
+3V +5V L751
J717
2
2 1
MONO_OUT 1 2 AGND
3 4 R1134 1 2 MODEM_SPK
5 6 0/NA 0402 5% 120Z/100M
7 8 CAGND 1608 AGND
1
9 10 C913 CAGND
+3V +3VS 11 12 0.1U
13 14 R1132 0402 0402
10%
2
15 16 1 2
17 18 4.7K 5% 10V 120Z/100M/NA
19 20 GND L725 2 1 2012
A 21 22 ACSYNC A
ACSDOUT 23 24 R1131 1 22 5% 2 0402 ACSDIN1
ACSDIN1 14
ACRST# 25 26 R1121 1 22/NA
5% 2 0402 C148 1 2 1808 1000P 2KV 10%
1
27 28
29 30 R1120 1 22 5% 2 0402ACBITCLK J715 R849 C806 1 2 1808 1000P 2KV 10%
1
C927 C926 2 560-2010/NA

0.1U 0.1U FM/0.8MM/H2.4 1 L724 0805 MODEMP
MODEMP 16
1
0402 0402 AMP C-179373 50UH MODEMN

MODEMN 16
1
10% 10% R1133 R1136 CHOKE_WLT04020201 GND_45

2
C912
10V 10V 0/NA 1K HDR/MA-2
1
291000023008 10P/NA
0402 0402 0402 ACES
CLOSE TO MDC 5% +/-10% 5% 85204-0200 120Z/100M/NA F2 JP, use 4pcs of 2kV 1000P cap
2
50V 291000020206 L721 1 2012 1 Title

2
2 2
US, use 2pcs of 2kV 1000P cap 8050D MOTHER B/D
MINISMDC014-2
GND GND GND GND GND POLYSW_MINISMDC110 UK, use 4pcs of 3kV 1000P cap Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
+3V +5V
AUDIO AMPLIFIER DEVICE_DECT# DECT_HP#/OPT REMARK
1
2
R477
100K +5V +5V 0 0 HP in
0402
D22 5%
R1
1
0 1 OPT in
2
1
20 EAPD
3 AMP_OFF 1 3 AMP_SHUTDOWN R1239 R1158
2 4.7K 1.3M
13,24 SPK_OFF Q38 0402 1 0
0402 no this condition
1
BAT54C 5% D715 1%
DTC144TKA
2
2
R454 288202240001 SPK_OFF# 1 1
3 on device
D27 A K 1K OPTIN# 1
D 22 KBC_MUTE L67 D
0402 C977 +5V
1
5% 1U AMPVDD
2
RLS4148 BAW56 1 2
AMP_OFF 2 R1 Q52 288100056017 0402 120Z/100M 2012 VA
1
10V
1
GND DTC144TKA + C466
2
C949 C934
288202240001
1
0.1U 0.1U
2
0402 0402 100U
GND 10% 10% 6.3V L752 R322 R1183
2
GND 16V 16V 20% J7 4.7K 10K R1302 1 0
1 2 2 CAGND
120Z/100M 2012 1 0402 0402 0402
2 5%
600Z/100M J720
1
AGND CAGND L52 DEVICE_DECT# L754 1 2 1608 5
1 2 600Z/100M 1608 HDR/MA-2 AGND L755 1 2 1608 4
AMP_RIGHT C492 1 2 1U 1 2 600Z/100M 1608 ACES 600Z/100M 2
20 AMP_RIGHT
0402 10V +80-20% U524 L50 85204-0200 3
20 21 ROUT+ 291000020206 DECT_HP#OPT L55 1 2 1608 1
C497 1 RHPIN ROUT+ ROUT-
2 1U 23 16 600Z/100M
0402 10V +80-20% RLINEIN ROUT- J3 1608 8 LED
C935 2 1 1U 8 7 L14 1 2 600Z/100M 1608 1 L757 1 2 7 Drive
RIN PVDD0 20 SPDIFOUT IC
0402 10V +80-20% 18 L16 1 2 600Z/100M 1608 2 600Z/100M 9
C950 2 1U PVDD1
1 14
PC-BEEP
1
AGND 0402 10V +80-20% 19 C1003
VDD
1
R1159 1 2 100K 0402 5% 2 HDR/MA-2 100P/NA GP1FD310TP
R1160 GAIN0 + C474 + C489
1 2 100K/NA 0402 5% 3 11 C485 1 2 1U ACES 0402 SHARP
GAIN1 BYPASS
2
AMPVDD R1161 2 100K 0402 5% 0402 10V +80-20% 85204-0200 +/-10% CONN_GP1FD310TP
2
1
AMPVDD R391 100U 100U 50V
1 2 100K/NA 0402 5% 15 22 291000020206 L758
AGND SEBTL SHUTDOWN SPK_OFF# 6.3V 6.3V 600Z/100M
2
VA 20% 20% GND 1608
17 1
HP/LINE GND0 AGND L759
12
t
AMP_LEFT C484 1 GND1
20 AMP_LEFT 2 1U 13 600Z/100M
0402 10V GND2 R329 2 22 1 0402 5% L80 2 600Z/100M 1608 1608
1
5 24 1
LLINEIN GND3
2
C480 1 2 1U 6 R528 2 22 1 0402 5% L78 1 2 600Z/100M 1608 +3V

LHPIN
t
R367 0402 10V 4
n
10K C493 1 LOUT+
2 1U Q711
1
10 9
0402 0402 10V LIN LOUT- 288221371002
1
e e
30 25 DTA144WK
G6 G1
1
DEVICE_DECT AGND R529 R328 C354 AGND CAGND
1
C 31 26 C150 C503 C356 1 SOT23AN_1 3 C

G7 G2 1K 1K 100P/NA
32 27 100P 100P 100P/NA
r
G8 G3
3
1
33 28 0402 0402 0402 0402 0402 0402
DEVICE_DECT# R1 Q23 G9 G4 1% 1% 10% 10% 10% 10% R1185 C978
2
2 34 29
G10 G5 50V 50V 50V 50V 10K
2
c m
DTC144TKA 0402 1U/NA
2
288202240001 TPA0212_GND 0402
AGND
1
TSSOP24_TPA0102 10V
AGND OPTIN#
2
e
AGND AGND AGND AGND GND +80-20%
u
CAGND CAGND Q713
3
S
AGND DTC144TKA
R1 288202240001
2 DECT_HP#OPT
c Do c
1
DEVICE_DECT#
a SUBWOOFER AMP(LM4871)
iT ial +5VS_SUBAMP
L63
+5V
M t
1 2
C471 1 2 0603 120Z/100M
1
1000P 10% 2012 D6
C496 0.22U + C951 2 1
SUB_OUTR 1 2 R502 1 10.2K 2
n
0402 +80-20% 16V 0402 1% 100U ESD0603/NA
6.3V
2
C483 0.22U R1122 1 22.1K 20%
2
e
B JO12 B
USE 3K 1% SUB_OUTL 1 2 R496 1 10.2K 2 0603 1%
0402 +80-20% 16V 0402 1% AGND 1 2
GND
U725
USE 2200P R506 C487 3 5
id
R521 1 0 +IN VO1 JO10
2 10% 1 2 1 2 4 8
0402 3K/NA Q35 -IN VO2
2 1 2
D
BYPASS GND
1
0402 5% 2N7002/NA AMP_SHUTDOWN D17 A K R1125 1 0 2 1

SHDWN
1
f
C494 R507 1U/NA R471 D 0402 7 6
VA 18K 10V 1M/NA S 5% 1 0402 GND VDD D5
2200P G 2 RLS4148 9
0402 0402 0805 0402 R451 10K/NA DEVICE_DECT D19 GND1
A K 10 13 2 1
GND2 GND5
1
+/-20% 1% 5%
S
2
11 14 C930
GND3 GND6
n
50V ESD0603/NA J705
2
RLS4148 12 15 1U
GND4 GND7
1
1
C469 SUB_OUTL C345 0402 1
1
AGND AGND VA C941 +80-20%
2
0.1U 1U/NA LM4871 2
o
0402 0402 4.7U LLP8A 10V
+80-20% +80-20% +80-20%
2
2
50V 10V 0805 R26 0 2 0805 HDR/MA-2
2
1
1
AGND R27 1 0 2 0805 ACES
C
8
R460 85204-0200
2464VREF1 3 47K/NA 291000020206
C490 R509 +
1 SUB_OUTL 0402 AGND
1 2 1 2 2 5% AGND AGND
20 SUB_LEFT -
2
22.1K 0402 1% U19A

1
0.15U LMV822
4
C462
3
0603 MSOP8 0.1U/NA Q30 TP49

0402 R1 2 1
AGND +80-20%
2
50V R510
DTC144TKA/NA R511 100 2 0402 2464VREF1
1
20 2464_VREF 1 1 2
AGND 1%
1
USE 3K 1% 22.1K 0402 1%
USE 2200P C479 C500
10% R461
R478 1 0 10U
2
2 1 2 1 2
1
0402 3K/NA Q36 AGND 6.3V R463

D
1
R462 0402 5% 2N7002/NA AGND 0805 2464VREF2

C470 1 2
18K 1U/NA R489 D 10%
A 2200P A
0402 0402 10V 1M/NA S G 2 5% 1 0402 22.1K 0402 1%
VA +/-20% 1% 0805 0402 R459 10K/NA
2
50V 5%
S
2
SUB_OUTR
2
8
SUB_LEFT R491 1 0/NA 2 0402 5% SUB_OUTL

2464VREF2 SUB_OUTL 20
5 + AGND
C482 R479 7 SUB_OUTR AGND
1 2 1 2 RIN_2464 6 SUB_RIGHT R512 1 0/NA 2 0402 5% SUB_OUTR
20 SUB_RIGHT - SUB_OUTR 20
22.1K 0402 1% U19B
0.15U LMV822
4
0603 MSOP8 Title

8050D MOTHER B/D
AGND
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
J5
KO0 C543 1 2 0402 1 KO0
KO1 100P 50V C542 1 2 0402 2 KO1 VDD3 20MIL VDD3_AVREF Pull HIGH at Other End
KO2 C541 1 2 0402 100P 50V 3 KO2 L61
KO3 100P 50V C540 1 2 0402 4 KO3 1 2
KO4 C539 1 2 0402 100P 50V 5 KO4
KO5 100P 50V C538 2 0402 KO5 120Z/100M/NA +3V +3V
1 6 PULL HIGH at SB END RSMRST# 13,25
KO6 C537 1 2 0402 100P 50V 7 KO6 0805C
WINBOND KBC
D
KO7 100P 50V C536 1 2 0402 8 KO7
2
KO8 C535 1 2 0402 100P 50V 9 KO8
13,24 SCI#
KO9 100P 50V C534 1 2 0402 10 KO9 R395 DTC144TKA D
KO10 C533 1 2 0402 100P 50V 11 KO10 10K SOT23AN_1 H8_RSMRST G S
3
KO11 100P 50V C532 1 2 0402 12 KO11 +KBC_CPUCORE +VCC_CORE 0402 288202240001 Q32
R1
KO12 C531 1 2 0402 100P 50V 13 KO12 R1 2 H8_SCI Q42
KO13 100P 50V C530 2 0402 KO13 H8_THRM# FDV301N
2
1 14 13 SB_THRM# 3 1
S
KO14 C529 1 2 0402 100P 50V 15 KO14 R424 1 22 2 SOT23_FET
BATT_DEAD# Q27
KO15 100P 50V C528 2 0402 KO15 0402 5% DTC144TKA
1
1 16
1
KI7 C527 1 2 0402 100P 50V 17 KI7 C453 R394 1 0/NA 2 SOT23AN_1
D +3V +3V D
KI6 100P 50V C526 1 2 0402 18 KI6 0.1U 0402 288202240001
KI5 C525 1 2 0402 100P 50V 19 KI5 0402 GND
3
KI4 100P 50V C524 2 0402 KI4 +80-20%
2
1 20
2
KI3 C523 1 2 0402 100P 50V 21 KI3 50V 2 R1 Q39 +3VS GND VDD3S
33 BATT_DEAD
KI2 100P 50V C522 1 2 0402 22 KI2 GND R925 DTC144TKA
KI1 C521 DTC144TKA
1 2 0402 100P 50V 23 KI1 10K SOT23AN_1
1
KI0 100P 50V C520 SOT23AN_1
2 0402 KI0 0402 288202240001
1
1 24
R1
100P 50V 288202240001 Q26 R453
25 KBD_US/JP# 13,24 H8_HRCIN# DTC144TKA
2
26 13 HRCIN# 3 1
GND GND SOT23AN_1 10K
R1
Q706 0402
288202240001
WAKE_UP# 5%
FPC/FFC/1MM/26P R267 0/NA 2 1 H8_WAKE_UP#
2
1 13,24 WAKE_UP# 3
ACES 0402 5%
11 PCICLK_KBC 13 ICH_PWRBTN#
+5V 85202-26-00 R381 1 0/NA 2
13,14,17,19 SERIRQ U16
291000152603 0402 5%
3
70 16 Q31
GP80/SD0 GP51/INT20#/S0 H8_PWRON H8_LIDSW# 12 R1
GND LAD[0..3] 69 18 2 ICH_PWRBTN
13,19,23 LAD[0..3] GP81/SD1 GP47/SRDY1#/S1 H8_PWRON 26,27
LAD3 68
GP82/SD2
1
C93 C94 LAD2 67 21 R439 1 0 2 H8_HRCIN#

GP83/SD3 GP44/RXD
10U R88 LAD1 0402 A A20GATE DTC144TKA
1
0.1U 66 20 K A20GATE 13
16V 0402 10K LAD0 GP84/SD4 GP45/TXD RLS4148/NA D20 SOT23AN_1
65
1206 +80-20% 0402 R393 1 0 GP85/SD5 T_DATA 288202240001
2
13 KBC_PCIRST# 2 64 9 T_DATA 23
50V 5% 0402 GP86/SD6 GP70/SIN2 H8_RSMRST
63 8
S
FAN# 13,19,23 LFRAME# GP87/SD7 P71/SOUT2 ICH_PWRBTN

12
G 1 2 7
GND
S G
SW_VDD3 GP72/SCLK2 T_CLK
J707 D C104
0.1U R87
3V LEVEL 25 SW_VDD3 BATT_DEAD#
17
15
GP50/A0 GP73/SRDY2#/INT21
6
5
T_CLK 23
GND
H8_ADEN# GP52/INT30#/R GP74/INT31 H8_PWRON_SUSB# 25
1 Q14 0402 0 D21 K A RLS4148 14 4
25,32 ADEN# GP53/INT40#/W GP75/INT41 SUSC# 13,26,27
FAN
SI2301DS +80-20% 0402 LEARNING

2
2 23
50V 5% 32 LEARNING H8_SUSB GP42/INT0/OBF00 H8_THRM#
3 22 38
H8_SCI GP43/INT1/OBF01 GP20/FD0/LPCEN H8_WAKE_UP# H8_SUSB
D703 19 37
t
+3V GP46/SCLK1/OBF1 GP21/FD1 BATT_G#
A K 36 BATT_G# 12,23
1.25MM/ST/MA-3 GP22/FD2/SDA1/RXD1 BATT_R#
10MIL GP23/FD3/SCL1/TXD1
35 BATT_R# 12,23
3
ACES RLS4148 BAT_DATA 3 34 EXTSMI# Q49
GP76/SDA GP24/FD4 EXTSMI# 13,24
1
t
85205-0300 BAT_CLK 2 33 CAP# R1 2
n
GP77/SCL GP25/FD5 NUM# CAP# 23 SUSB# 13,17,23,25
291000010303 R95 32
10K H8_ENABKL GP26/FD6 SCROLL# NUM# 23
GND 27 31
12 H8_ENABKL GP40/XOUT/PWM2 GP27/FD7 SCROLL# 23
e e
0402 CHARGING DTC144TKA
1
33 CHARGING 26
C 5% GP41/XCIN/PWM3 VDD3_AVREF SOT23AN_1 C
FAN_SPEED BLADJ 288202240001
2
1 2 23 BATT_LED# 13 11
r
GP54/CNTR0 GP56/DA1/PWM01
3
12 10 H8_I_CTR GND
25 KBC_PWRON_VDD3S GP55/CNTR1 GP57/DA2/PWM11
1
R99
1
R96 33 C133 KO0 54 1 PWRBTN# D18
c m
1M/NA 0402 KO1 GP0/P3REF/FA0 GP60/AN0/INT5 KBC_RI# BAV70LT1
0.1U 53 80
0402 5% 0402 KO2 GP1/FA1 GP61/AN1/INT6 AC_POWER# SOT23N
52 79 AC_POWER# 12,23 RP45
5% +80-20% KO3 GP2/FA2 GP62/AN2/INT7 288100070006 BAT_VOLT
2
2
51 78 8 1 BAT_V 32
e
50V KO4 GP3/FA3 GP63/AN3/INT8 BAT_TEMP
2
50 77 7 2 BAT_T 32
KO5 GP4/FA4 GP64/AN4/INT9 H8_I_LIMIT BAT_CLK
49 76 6 3 BAT_C 32
GP5/FA5 GP65/AN5/INT10
u
GND GND KO6 48 75 H8_PROCHOT# BAT_DATA 5 4
GP6/FA6 GP66/AN6/INT11 BAT_D 32
1
S
KO7 47 74 C454 C459
KO8 GP7/FA7 GP67/AN7/INT12 +KBC_CPUCORE
46 0.1U 0.1U 22*4
GP10/FA8
c
KO9 45 0402 0402 RPSOA_8C
KO10 GP11/FA9 H8_RESET# +80-20% +80-20%
2
44 25
Processor Hot Protection GP12/FA10 RESET# H8_RESET# 25
c Do
KO11 43 50V 50V
KO12 GP13/FA11 KBC_X+ H8AGND H8AGND
42 28
+VCC_CORE KO13 GP14/FA12 XIN
41
KO14 GP15/FA13 KBC_X- VDD3_AVREF
40 29
a
GP16/FA14 XOUT
2
KO15 39
GP17/FA15 VDD3 VDD3
KI0 62
GP30/PWM0/FCTRL0 VREF
72 R414 1 0 2 5% For External
DTC144TKA KI1 0402G_DFS flash BAT_CLK R448 1 2.7K 2 1% 0402
iT ial
61
R1
288202240001 KI2 GP31/PWM10/FCTRL1 BAT_DATA R449 1 2.7K

60 71 2 1% 0402
GP32/FCTRL2 VCC
1
H8_PROCHOT# 3 1 HPROCHOT# KI3 59 C449 C448 C445
HPROCHOT# 2 KI4 GP33/FCTRL3#
Q29 58 0.1U 0.1U 10U
KI5 GP34/BANK0 0402 0402 0805 VDD3 VDD5
57 30
KI6 GP35/BANK1 VSS +80-20% +80-20% 6.3V
2
56 73
KI7 GP36/CE# AVSS 50V 50V 10% BAT_CLK R419 1 2.7K/NA 2 1% 0402
55 24
GP37/OE# CNVSS
R0A
2
M t
BAT_DATA R455 1 2.7K/NA 2 1% 0402
W83L950D R447
C Version 284583950002 GND GND
0/NA add
PQFP80_0.5MM 0402
Closed to KB CONN
11
5% +3V
+5VS +5VS KBC IC :284583950002
n
R446
F/W 150 H8_THRM# R390 1 10K/NA 2
G
2N7002 ASSY:481677700002 0402 0402 5%
e
B B
1% H8_ENABKL R425 1 10K/NA 2
H8_THRM_DATA R473 1 0 BAT_DATA ADD-->R0B 0402 5%
2
2 S D
S
D
0402
G
2
Q33 2N7002 +5V
id
KBC_X- R430
H8_THRM_CLK R486 1 0 2 S D BAT_CLK T_DATA R482 2 10K 5% 1 0402
KBC_X+ 10K
S
D
0402 KBC_RI# R445 1 0 2 T_CLK R481 2 10K 5% 1 0402

KBC_MUTE 21 0402
f
Q40 0402 R404
1M 5%
1
KBC_RI# 16 1 2
0402 5% KI5 R385 1 0/NA 2
R450 2 10K/NA 1 X1 GND 0402 5%
+3VS
n
I_LIMIT R428 1 0 2 0402 H8_I_LIMIT 0402 1 2 0:for external flash
32 I_LIMIT I_CTRL
33 I_CTRL
R483 1 0 2 0402 H8_I_CTR 0:internal flash GND
1
BLADJ C450 8MHZ C447 1:external flash
4,12 BLADJ
o
22P TXC8X4.5 22P
BEAD_600Z/100M 0402 0402
1
L68 0603D +/-10% +/-10% H8_SCI R475 1 10K
2
C478 1 2 2 VDD3
0.1U 50V 50V 0402 5%
C
0402 GND GND
+80-20%
2
GND 50V
H8AGND GND +3VS
H8_PROCHOT# R413 2 10K 5% 1 0402
THERMAL SENSOR / FAN CONTROLLER VDD3

10
9
RP46
1 H8_ADEN#
2 BATT_DEAD#
5 10K*4 4 1206
+3VS POWER BUTTON H8_RSMRST
H8_SUSB
8
7
3
4 PWRBTN#
6 3 +2.5VS_DDR ICH_PWRBTN 6 5 VDD3
7 2
8 1 SW2 RP10KX8
2
RP719 R1002 +3VS PWRBTN# R7 1 1K 2 1 2 RPSOE_10

0402 5% 3 4 RP44
1
0 C9 5 10 1 KI0
U706 VDD3 KI4 KI1
1000P 9 2
H8_THRM_DATA 16 14 0402 KI5 8 3 KI2
H8_THRM_CLK SDA +2.5VIN/SMBALERT +/-20% TC010-PSS11CET KI6 KI3
1
A 1 7 4 A
SCL 50V KI7
VCC
3 CPU_THERMDA 2 X7R 297004010001 6 5 VDD3
1
C869 GND GND

TP720 1 15 13 2200P 1206 4.7K*8
FAN# PWM1 D1+ 0402
5 12 CPU_THERMDC 2
PWM2/SMBALERT D1- +/-20%
2
8 11 VGA_THERMDA 9
PWM3/ADDRESS ENABLE D2+
1
D2-
10 C728 50V
2200P
TP718 1 6 2 0402
TACH1 GND +/-20% VGA_THERMDC 9
FAN_SPEED
2
7
TACH2
1
TP719 1 4 C871 50V

THERM_ERR# TACH3 4.7U
14,25 THERM_ERR# 9
TACH4/ADDRESS SELECT/THERM 0805 Title
+80-20% 8050D MOTHER B/D
2
ADT7460
QSOP16B
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
GND
5 4 3 2 1

5 4 3 2 1
FWH
TOUCH_PAD +3V
D D
11 PCICLK_FWH
13 FWH_PCIRST#
+5V R402 1 8.2K 5% 2 0402
1
R411 1 8.2K 5% 2 0402 R387 1 8.2K 5% 2 0402 C908 C897 C902
L716 F701 4.7U 0.1U 0.1U
2 1 1 2 0603 0402 0402
GND GND 6.3V 10% 10%
2
120Z/100M 0.5A/POLYSW +80-20% 10V 10V
32
31
30
4
3
2
1
2012
C771
miniSMDC050 U15
0.1U
A8/RSV
A9/RSV
RESET#
VPP
R-C#/CLK
A10/GPI4
VDD
1 2 GND GND GND
0402 GND
50V +80-20%
L36 1 2 J4 +3V
22 T_DATA TP_VDD
120Z/100M 6
1608 TP_DATA 5
4 R427 1 8.2K 5% 2 0402 5 29 R364 1 4.7K 2 0402
L37 TP_CLK R422 1 8.2K 5% 2 0402 A7/RSV MODE 5%
22 T_CLK 1 2 3 6 28
120Z/100M R417 1 4.7K 5% 2 0402 A6/RSV GNDA
2 7 27
1608 R132 1 0 TP_LEFT A5/RSV VCCA
SW_LEFT 2 5% 1 R408 1 4.7K 5% 2 0402 8 26 GND
SW4 0402G_DFS R403 1 8.2K 5% 2 0402 A4/RSV GND
9 25
R151 1 0 A3/RSV VDD INIT#
1 2 2 5% TP_RIGHT R412 1 8.2K 5% 2 0402 10 24
0402G_DFS HDR/MA-6 R418 1 8.2K 5% 2 0402 A2/RSV OE#/INIT#
3 4 11 23 LFRAME# 13,19,22
ACES R423 1 8.2K 5% 2 0402 A1/RSV WE#/LFRAME#
5 12 22
87151-0607 A0/RSV NC
13 21
LAD0/DQ0 DQ7/RSV
TC010-PSS11CET GND
1
297004010001 C143 C144 C154 C172 +3V
DQ1/LAD1
DQ2/LAD2
DQ3/LAD3
D29 47P 47P 47P 47P
DQ4/RSV
DQ5/RSV
DQ6/RSV
t
1 2 0402 0402 0402 0402
1
+/-10% +/-10% +/-10% +/-10%
2
GND
2
ESD0805A/NA 50V 50V 50V 50V GND
t
R1089
n
1
1
SW_RIGHT JO18 JO20 SST49LF004A
14
15
16
17
18
19
20
1
SW5 GND LAD0 330
13,19,22 LAD0 0402
e e
1 2 LAD1 R1084
13,19,22 LAD1 LAD2 1.5K 5% INIT#
JO19 JO21
C 1
C 3 4 13,19,22 LAD2
C
LAD3 0402
2
2
5 13,19,22 LAD3
r
5%
Q718
C 2
B
TC010-PSS11CET MMBT3904L
2
c m
GND 297004010001 SYS BIOS Vendor List: GND R1073 288203904022
E
1 2 B Q708
SST49LF004A : 283467490001 2,13 HINIT# MMBT3904L
D23 330
e
1 2 0402 288203904022
E
GND 5%
u
ESD0805A/NA
S c
GND
c Do
J8
TP_RIGHT 1
TP56 1 2
a
TP57 1 3
TP_LEFT 4
5 LED
iT ial
6
TP_CLK 7
8
TP_DATA 9 D721
10 R415 R433 1 0402 2 2
TP_VDD VDD3S 15 CD_LED# IDE_LED#
11 AC_BATT_LED# 1 2 0402 220/NA 5% 3
12 0/NA 1
15 HDD_LED#
M t
R416 1 2 0402 K A R553 1 0402 2 5%
15 HDD_LED# +5V
HDR/MA-12/NA 0 470 BAW56/NA
GND ACES D32 R434 1 0402 2 VDD3S
87151-1207 CL-190G 220/NA 5%
291000141204 R458 1 2 0402 K A R554 1 0402 2 5%
15 CD_LED# +5V
0 470
n
R465 1 2 0402 D33
12,22 BATT_G#
When 8050N ADD J722 and DEL J4 0/NA CL-190G
e
B B
When 8050 ADD J4 and DEL J722 D31
VG
4 3
id
R466 1 2 0402 2 1 R467 1 0402 2 5%
12,22 BATT_R# VDD3S
f
0/NA 220/NA
SR
19-22SRVGC/TR8/NA
on R441
1 0402
470/NA
2 5% +5V
C
R420 R555
NUM# 1 2 0402 K A 1 0402 2 5%
22 NUM# +3V
0 220
IDE_LED# D34
CL-190G
R421
CAP# 1 2 0402 K A R556 1 0402 2 5%
22 CAP#
0 220
R426 1 2 0402 D35
22 NUM# 0/NA CL-190G
R429
SCROLL# 1 2 0402 K A R557 1 0402 2 5%
22 SCROLL#
0 220
D37
R432 1 2 0402 CL-190G
22 CAP# 0/NA
R457 +3VS +3VS +3VS

A AC_BATT_LED# 1 2 0402 A
0/NA
R468 U703B U703C U703D
BATT_POWER# 2 0402 Q720
14
14
14
1
12 BATT_POWER# 0 DTC114TKA 74AHC14_V 74AHC14_V 74AHC14_V
3
288202215001 TSSOP14 TSSOP14 TSSOP14

3
R1 2 4 3 6 5 8 9 1 2 0402
2 R1 Q719 R1152 1M 5%
13,17,22,25 SUSB# DTC114TKA
1
BATT_LED# 288202215001
1
7
22 BATT_LED#
1
C947
R1303 4.7U Title
12,22 AC_POWER# 1 2 0402 0805 8050D MOTHER B/D
0/NA GND +80-20% GND GND
2
Size Document Rev

C PCB 316680900001/ASSY 411682700001 R01
Number
1 2
R1140 180K 0402 5% Date: Wednesday, December 31, 2003 Sheet 23 of 34
5 4 3 2 1

5 4 3 2 1
PULL -HIGH
PCI PULL HIGH AGP PULL HIGH
+3V
8.2K 1 R187 2 0402

PCI_INTA# 7,13
GPIO PULL HIGH
8.2K 1 R847 2 0402
PCI_INTB# 13,17
8.2K 1 R1119 2 0402
PCI_INTC# 13,17
8.2K 1 R808 2 0402
PCI_INTD# 13,19 +3V
D D
+3V
CRT_IN# 0402 1 R804 2 8.2K
12,13 CRT_IN#
8.2K 1 R191 2 0402 PCI_INTE# 13,16 DEL ALL RESISTOR
8.2K 1 R194 2 0402 0402 1 R916 2 10K
PCI_INTF# 13,17,19 13 SB_CARD_PME#
8.2K 1 R841 2 0402 5%
PCI_INTG# 13,18 ICH_GPI5
8.2K 1 R868 2 0402 0402 1 R815 2 8.2K
PCI_LOCK# 13 13 ICH_GPI5 +1.5V
+3V AGPBUSY# 0402 2 R788 1 20K
4,7,13 AGPBUSY#
1%
8.2K 1 R180 2 0402 KBD_US/JP# 0402 1 R165 2 10K 100K 1 R837 2 0402 5%
PCI_REQ0# 13,17 13,22 KBD_US/JP# AGP_AD30 4,7
8.2K 1 R1005 2 0402 5%
PCI_REQ1# 13,18 STP_AGP#
8.2K 1 R179 2 0402 0402 2 R780 1 20K/NA VDD3S 100K 1 R866 2 0402 5%
PCI_REQ2# 13,19 7,13 STP_AGP# AGP_AD13 4,7
8.2K 1 R814 2 0402 1%
PCI_REQ3# 13,16
8.2K 1 R803 2 0402 0402 1 R410 2 8.2K/NA
PCI_REQ4# 13 3,13 B/CB#
+3V
8.2K 1 R186 2 0402 0402 1 R396 2 10K GND

PCI_GNT0# 13,17 13,22 EXTSMI#
8.2K 1 R207 2 0402 5%
PCI_GNT1# 13,18 SMBALERT#
8.2K 1 R802 2 0402 0402 2 R309 1 10K
PCI_GNT3# 13,16 13 SMBALERT#
8.2K 1 R201 2 0402 5%
PCI_GNT4# 13
8.2K 1 R200 2 0402 0402 1 R464 2 10K
PCI_GNT2# 13,19 13,22 SCI#
5% +2.5VS_DDR +2.5VS_DDR_P
0402 1 R382 2 10K
13,22 WAKE_UP#
+3V 5% JS708
1 2
8.2K 1 R211 2 0402
PCI_FRAME# 13,16,17,18,19 SHORT-SMT4
8.2K 1 R231 2 0402
PCI_SERR# 13,16,17,19 +VCCP
8.2K 1 R230 2 0402 JS709
PCI_IRDY# 13,16,17,18,19
8.2K 1 R241 2 0402 1 2
t
PCI_PERR# 13,16,17,18,19
8.2K 1 R244 2 0402
PCI_DEVSEL# 13,16,17,18,19 SHORT-SMT4
8.2K 1 R212 2 0402 0402 1 R280 2 200
PCI_TRDY# 13,16,17,18,19 13 CPUPERF#
8.2K 1 R218 2 0402 5% JS710
PCI_STOP# 13,16,17,18,19
t
0402 1 R1004 2 8.2K 1 2
n
13,16,17,19 PCLKRUN# +3V
5%
SHORT-SMT4
e e
C +3VS +3VS_P C
R284 1 0 2 5% VDD3S
r
0402G_DFS +1.25V_DDR +1.25V_DDR_P
GPIO27 0402 1 R282 2 8.2K R283 1 0/NA 2 0402 JS711
13 GPIO27 GPIO28 0402 1 R281 +3V
2 8.2K 1 2 JS11
c m
13 GPIO28
1 2
SHORT-SMT4
SPK_OFF 0402 1 R905 2 8.2K R897 1 0/NA 2 0402 JS713 SHORT-SMT4
+3VS
e
13,21 SPK_OFF JS12
1 2
R906 1 0 2 0402 1 2
VDD3S
u
SHORT-SMT4
S
JS715 SHORT-SMT4
1 2
c
+3V
SHORT-SMT4 +1.8V +1.8V_P
c Do
R1098 1 10K 2 JS716
14,19 WIRELESS_PD#
0402 5% 1 2
+3V +5VS +5VS_P
a
SHORT-SMT4
JS717
JS718 1 2
R843 10K 0402 5%
iT ial
2 1 1 2
14,15 IDERST# R851 10K 0402 5% SHORT-SMT4
2 1
14,19 MINIPCI_ACT# R840 10K 0402 5% SHORT-SMT4
14 GPIO43 2 1
R842 2 10K 1 0402 5% JS719
14 GPIO42
1 2 +1.35V +1.35V_P
+3V SHORT-SMT4 JS720
M t
JS721 1 2
PANEL_ID0 10K 1 R11 2 0402 1 2
7,12,14 PANEL_ID0 PANEL_ID1 10K 1 SHORT-SMT4
R12 2 0402
7,12,14 PANEL_ID1 PANEL_ID2 10K 1 SHORT-SMT4
R13 2 0402 JS722
7,12,14 PANEL_ID2 PANEL_ID3 10K 1 R14 2 0402 1 2
7,12,14 PANEL_ID3
n
SHORT-SMT4
+3V
e
B +1.2V/1.0V_M10 VGA_1.2/1.0 B
+1.5V +1.5V_P
R845 1 2 10K/NA 0402 MB_ID0 R846 1 2 10K 0402
R232 1 2 10K 0402 MB_ID1 R239 1 2 10K/NA 0402 JS723
R215 1 2 10K/NA 0402 MB_ID2 R221 1 2 10K 0402 JS724 1 2
id
1 2
SHORT-SMT4
14 MB_ID0 SHORT-SMT4 JS725
14 MB_ID1
f
JS726 1 2
14 MB_ID2
GND 1 2
SHORT-SMT4
SHORT-SMT4
n
JS727
1 2 +VCCP +1.05V_P
o
SHORT-SMT4 1.05V
JS728
1 2
C
SHORT-SMT4
JS729
1 2
SHORT-SMT4
JS730
1 2
SHORT-SMT4
A A
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
PWR_VDDIN VDD3_AVREF
POWER ON PERPHERIAL CIRCUIT
F3 Q48 Q43
U14
1 2 8 6 SI2301DS SI2301DS
IN 5VTAP VDD3 +3VS
2 1
FUSE_1206 SENSE OUT VDD3S VDD1.5
7 5
F/B ERR-
S
D
3216FF-1 3 4 D S S D
D
S
1A-1206 SHUTDN GND PWR_VDDIN VDD5 U6
K
1
1
LP2951-3.3/NA C383 C381 U11 3
K
VIN
G
G G
R374 SO8 10U 0.1U D25 8 6
IN 5VTAP
1
G
10K/NA 0805 0402 RLZ3.6B/NA D26 C517 R525 2 1 C310 2
0402 6.3V +80-20% MLL34B UDZS3.6B/NA 100K SENSE OUT VOUT
2
4.7U 7 5 0.1U
5% 10% 50V SOD323 0805 0402 F/B ERR- 0402
3 4 1
K
SHUTDN GND GND/ADJ
1
+80-20% 5% 10%
A
2
2
C295
1
10V
A
D13
2
D
LP2951-02 C342 2.2U D
R321 SO8 10U AME1117 0603
GND GND GND GND GND 10K UDZ5.6B 0805 SOT223 +/-10%
2
SOD323
GND 0402 6.3V GND
2
3
5% 10%
A
GND R259 1 2 0402
U13 Q47 1K 1%
2
1 3 SW_VDD3 R523 1 2 0402 2 GND
INPUT OUTPUT
1
22 SW_VDD3 0 5% DTC144WK
GND
288202237002 GND GND GND GND R253

200
1
C355 AMS3107 R522 1 2 0402 0402

13,15 PCIRST#0 0/NA 5% 1%
2
10U SOT223
1206
2
286303107001
10V
2
GND
GND GND
GND U10
+3V MAX809
H8 RESET# / RSMRST# PWROK

3
SOT23N
286300690001
VCC RESET#
2 PWROK 4,12,13,17,31
PWROK 4,12,13,17,31
GND
Q51
1
Q13 C326
1
VDD3 SI2301DS 0.1U
VDD5 SI2301DS VDD5S 0402 R312
L71 10% 809S 100K
1
R1
R501 10V
S
D
S D 1 2 VDD3S
DTC144TKA 2.93V 0402
2 THERM_ERR#
S
D
S D 120Z/100M 2882022400013 1 1 5%
t
THERM_ERR# 14,22
2012 GND
2
Q44
1
G
L72 +3VS VDD3 VDD3S
1
1
G
VDD5
G
R561 C508 1 2 VDD3 0
+3VS
1
t
G
R28 C24 100K 2.2U 120Z/100M/NA 0402 GND GND
n
100K 2.2U 0402 0603 2012 5%
1
0402 0603 5% +/-10%
2
1
2
+/-10%
e e
5% R456 R358
2
R375 R531 4.7K/NA 4.7K

2
C C
10K 10K 0402 0402
r
0402 0402 5% 5%
R1
5% 5% U21 Q34
2
D24
ADEN#
2
2
D7 A K 3 2 1 3
c m
ADEN# MN RESET RSMRST# 13,22
A K ADEN# 22,32
BAS32L 4 1 DTC144TKA/NA
VCC GND
1
BAS32L
e
H8_RESET# R474
H8_RESET# 22
3
1
+3VS Q50 C506 IMP811 294K/NA C486
3
u
Q12 R1 2 R551 1 0 2 5% 0.01U SOT143 R508 0402 10U/NA
KBC_PWRON_VDD3S 22
S
R1 2 R25 1 0 2 5% 0402G_DFS 0402 100K 1% 0805
0402G_DFS +80-20% 0402 6.3V
2
c
DTC144TKA 50V 5% 10% +3VS +5VS
1
DTC144TKA 288202240001
1
2
c Do
288202240001 GND GND
GND VDD3S VDD3
1
2
GND R366
1
GND 10K/NA
GND R362 R368 0402
10K 10K/NA 5%
R1
0402 0402
2
iT ial
5% 5% PWRON_SUSB# 1 3 R355 1 2 0402 VCC_ON
0/NA 5%
2
PWRON_SUSB# Q25
R480 1 0 2 5%
22 H8_PWRON_SUSB# PWRON_SUSB# 26,28,29,30,31
0402G_DFS DTC144TKA/NA
R548 1 0/NA 2 0402
13,17,22,23 SUSB# 5%
M t
n
+5VS U704 +3VS U707 +2.5VS_DDR +2.5V_M10
+5V_H +5V +3V For ATI VRAM
AO4403 For Lan AO4403
U8
8 L703
120Z/100M SO8 8 L707120Z/100M L46
e
B SO8 B
3 7 1 2 3 7 1 2 4 5 1 2
2012 2012 SOURCE3 DRAIN3 120Z/100M
2 6 2 6 3 6
L704 120Z/100M L706 120Z/100M SOURCE2 DRAIN1 2012
1 5 1 5 2 7
SOURCE1 DRAIN2
D
VCC_ON
S
1 2 1 2 1 8
id
VIN GND
1
1
G
C706 C13 C705 C707 2012 C710 C712 2012 C717 C329 L47 C283
1U 0.1U 10U 2.2U 1U 0.1U C715 2.2U 1U 1 2 C284 2.2U
1
0402 0402 0805C 0603 0402 0402 0603 0402 SI4788CY/NA 120Z/100M 0603
4
1
10U 10U
f
+80-20% R15 +80-20% R1248 10V +/-10% +80-20% R705 +80-20% +/-10% +80-20% SO8 2012 +/-10%
2
2
10V 50V 0/NA 10V 50V R1249 6.3V 10V 6.3V
1 2 1 2
0805 0/NA 0805 U7 SI4800DY 0805
GND GND 0805 10% GND SO8 GND 10%
1
n
100K GND GND 100K GND GND GND GND
2
8
0402 R21 0402 R707
2
7 3
5% 1K 5% 1K 6 2
D
o
0402 0402 5 1
5% 5%
D
D Q721
S
D
G
2
GG S
SI2301DS/NA D Q722 DVMAIN
Q10
C
S
C313
4
GG S
D
SI2301DS/NA DVMAIN
2N7002 1 2
S
D Q701 Q18
1
S G OD5 0.047U 0603 DTA144WK/NA
D
GND 2N7002 SOT23AN_SC70_1

1
1
S
C16 D R2501 1M 2
0.1U S G OD3 GND R251 0402 5%
0402 220K 2
1
+80-20% 0402
S
2
C708 Q17
50V 0.1U 5% GND R260
D
0402 1 22K/NA 2
D 2
2N7002/NA
+80-20% 0402 1%
2
3
D
GND 50V S G PWRON_SUSB#
D Q19
S
G S
OD3 +3VS 2N7002
R17 1 0 2 0402 GND
S
5%
PWRON_SUSB# GND
PWRON_SUSB# R18 1 0 2 0402 OD5
A 5% A
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
DVMAIN +2.5VS_DDR_P/+1.25V_DDR_P
JS703 PL716
1 2 1 2
2012
SHORT-SMT4 120Z/100M
1
PC791
0.01U
0402
10%
2
50V
D D
2
GND
1
PC799 PJL1
10U
1
1210 JP_NET20
PC801
25V
2
0.01U
1
0402 20%/X5R
1
10%
2
PC792 PC794 PC795
1
0.01U 10U PC796 50V 1000P
0402 1210 10U GND 0402
10% 25V 1210 10%
2
GND
50V 20%/X5R 25V PR109 PR110 50V
2
20%/X5R 1 2 288100056017 1 2
1
4.7 4.7
GND 0603 PD7 0603 GND
1% 1%
BAW56
SOT23N
PR111 PC67
3
1 2 INTVCC12 1
+5VS_P
2
PJL2 PU708A 0
0402 10U
6
5
JP_NET20 5% 16V
AO4900
1
D 1206
1
SO8 PC68
0.1U
1
G PC65 0402 PC66
1
5
6
+80-20% PU709A
2
PC793 4 0.1U 0.1U
1000P 0805 50V 0805 D
0402 10% 10%
2
PU15
t
10% GND
2
24
23
22
21
20
19
18
17
LTC3728L G
50V 4
HVQFN32_1
BOOST1
BG1
BG2
BOOST2
VIN
EXTVCC
INTVCC
PGND
t n
GND S
PR742 PL715 AO4900
e e
+2.5VS_DDR_P
3
SO8
C 1 2 1 2 25 16 PL717 PR744 C
SW1 NC1
26 15 1 2 1.25V_2 1 2 +1.25V_DDR_P
r
TG1 SW2
PU708B 27 14
0.008 3.9UH PGOOD TG2 3.0UH
28 13
RUN/SS1 RUN/SS2
8
7
2512 SPC-08045 AO4900 29 12 SPC-05703 .012
c m
1% 30% D NC2 SENSE2+ 30% 2010
SO8 30 11
SENSE1+ SENSE2-
1
7
8
PC789 31 10 PU709B 1%
SENSE1- NC0
1
+ 330U/NA G 32 9 D PC797
e
NC3 VOSENSE2
7343 2 33 10U
VOSENSE1
K
4V SGND1 1210
34 G
PLLFLTR
K
3.3VOUT
SGND2
1
u
10V PD724
2
2
PC788 35 2
SGND3
1
1
S
SGND
PLLIN
PD723 + 330U PC790 S PC70 36 PC800
ITH1
ITH2
FCB
PC71 SGND4 BZV55C2V4/NA
7343 0.1U 1000P 37 0.1U
SGND5
1
c
BZV55C3V3/NA 4V 0402 0402 1 0402
1
2 S PC798
+80-20% 10% +80-20%
A
+ 150U
2
2
AO4900
1
c Do
50V 50V 50V
A
1
2
3
4
5
6
7
8
1
PC787 SO8 7243
+ 330U 1000P GND 6.3V
0402 PC72
2
7343
4V 50V 1 2 SENSE1.25+
a
SENSE2.5+ 10%
2
1 2 SENSE1.25-
SENSE2.5- 1000P
1
PC76 PR116 0402
iT ial
PC75
1
1 2 PC73 220P 100P 11.8K 50V
1
220P 0402 0402 0402 10%
1
PR118 PR124 0402 10% +/-10% 1%
2
1
1
43.2K 2K PC74 10% 50V 50V
1
GND 0402 0402 47P 50V PR113 PC69
1
1
1% 1% 0402 PR122 20.5K
2
1000P
15K 0402
M t
PR117 10% PR121 0402
2
2
20K 50V 1K 0402 1% 10%
2
0402 0402 1% 50V
2
1% 1%
2
JS6
2
2
1 2
n
SHORT-SMT1
1
GND
e
B B
PR120 SGND1
0
0402
VDD5 5%
id
2
VDD5
1 2 INTVCC1
1
f
PR114 PR119
1
100K 10K
0402 0402 PR112
D
n
1% 1% 100K
PQ22 0402
2
D
G S 2N7002 1%
o
PQ20
2
D
2N7002
S
G S
D
S
D PQ23
C
R369 1 0 2 G S 2N7002
22,27 H8_PWRON
0402 5%
1
S
1
R371 1 0/NA 2 C382 PR123 SGND1

D
13,22,27 SUSC# 1M
0402 5% 0.1U/NA
0402 0402 D PQ21
+80-20% 1% R356 0 2N7002
2
1 2 G S
50V 25,28,29,30,31 PWRON_SUSB#
0402 5%
2
S
1
C367
SGND1 0.1U/NA PR115
0402 1M
+80-20% 0402
2
50V 1%
2
SGND1
A A
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
DVMAIN
+3VS_P/+5VS_P
JS704 PL701
1 2 1 2
2012
1
PC710
0.01U
0402
10%
2
50V
D D
2
GND
1
PC703 PJL3
1
10U PC704
1
1210 10U JP_NET20
PC708
25V 1210
2
0.01U
1
0402 20%/X5R 25V
2
1
1
10% 20%/X5R
2
PC709 PC705 PC706
0.01U 10U 50V 1000P
0402 1210 GND 0402
10% 25V 10%
2
GND
50V 20%/X5R PR3 PR2 50V
1 2 288100056017 1 2
1
4.7 4.7
GND 0603 PD1 0603 GND
1% 1%
BAW56
SOT23N
PR11 PC8
3
1 2 INTVCC02 1
+5VS_P
2
0
PJL4 PU702A 0402
10U
6
5
JP_NET20 5% 16V
AO4900
1
1 D PC10 1206
SO8
0.1U
1
G PC4 0402 PC7
1
5
6
+80-20%
2
PC707 4 0.1U 0.1U
1000P 0805 50V 0805 D PU701A
0402 10% 10%
2
PU2
t
10% GND AO4914
2
24
23
22
21
20
19
18
17
LTC3728L G SO8
50V 4
HVQFN32_1
3
BOOST1
BG1
BG2
BOOST2
VIN
EXTVCC
INTVCC
PGND
t n
GND S
PR711
e e
3
C 1 2 1 2 25 16 PR707 C
SW1 NC1
+3VS_P 26 15 1 2 5V_21 2 +5VS_P
r
PL703 TG1 SW2
PU702B 27 14
.012 10UH PGOOD TG2 PL702
28 13
RUN/SS1 RUN/SS2
8
7
2010 D124C AO4900 29 12 10UH .012
c m
1% 20% D NC2 SENSE2+ D124C 2010
SO8 30 11
SENSE1+ SENSE2-
7
8
1
31 10 20% 1% PC713
SENSE1- NC0
1
1
PC719 G 32 9 D PU701B PC721 + 150U/NA
e
+ 150U NC3 VOSENSE2
2 33 10U 7343
VOSENSE1
K
SGND1 AO4914 1210 6.3V
7343 34 G
PLLFLTR
K
3.3VOUT
SGND2 SO8
u
PD708 6.3V 10V PD707
2
35 2
SGND3
1
1
S
SGND
PLLIN
2
PC737 S PC17 36 PC717
ITH1
ITH2
FCB
BZV55C4V3/NA PC20 SGND4 BZV55B5V6/NA
0.1U 1000P 37 0.1U
SGND5
1
c
0402 0402 1 0402
1
2 S PC712
1
+80-20% 10% +80-20%
A
+ 150U
2
2
PC725
c Do
50V 50V 50V
A
+ 150U/NA
1
2
3
4
5
6
7
8
1
7343
7343 1000P GND 6.3V
6.3V 0402 PC19
2
50V SENSE5V+
2
1 2
a
SENSE3+ 10% PR35
1 2 SENSE5V-
SENSE3- 1000P
1
0402
iT ial
PC25
1
1 2 PC24 180P 107K 50V
1
180P 0402 PC26 0402 10%
PR42 PR46 0402 10% 47P 1%
2
63.4K 2K 10% 50V 0402
12
1
GND 0402 0402 50V 10%
2
PC14
1
1
5% 1% PC23 PR54 PR55 50V 1000P
200K 200K
M t
PR41 47P 0402
2
20K 0402 0402 0402 PR36 10%
2
0402 10% 1% 1% 19.6K 50V
2
1% 50V 0402
2
JS1
1%
2
1 2
n
SHORT-SMT1
1
GND
e
1
B B
PR48 SGND0
PR47 0/NA
10K 0402
0402 5%
id
D
1%
2
D
PQ3
2
D
G S 2N7002 INTVCC0 D PQ4
f
G S 2N7002
S
S
VDD5
VDD5
n
1
PR9 SGND0 SGND0
o
100K PR10
0402 100K
1% 0402
1%
2
C
2
PQ2
D
2N7002
D PQ1 D
R24 1 0 2 G S 2N7002 S G PR25 1 0 2
22,26 H8_PWRON H8_PWRON 22,26
0402 5% 0402 5%
S
S
1
C23 R23 1 0/NA 2

SUSC# 13,22,26
1
0.1U/NA PR26 PR27 C22 0402 5%

0402 1M 1M 0.1U/NA
+80-20% 0402 0402 0402
2
50V 1% 1% +80-20%
2
50V
2
A SGND0 A
SGND0
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
+1.5V_P/+1.05V_P
DVMAIN
JS10 PL3
1 2 1 2
2012
1
PC31
D
0.01U D
0402
2 10%
50V
GND
2
1
PC739 PJL5
10U
1
1210 JP_NET20
PC38
25V
2
0.01U
1
0402 20%/X5R
1
10%
2
PC32 PC743 PC744 PC40
0.01U 10U 10U 50V 1000P
0402 1210 1210 GND 0402
10% 25V 25V 10%
2
GND
50V 20%/X5R 20%/X5R PR709 PR708 50V
1 2 288100056017 1 2
1
4.7 4.7
GND 0603 PD705 0603 GND
1% 1%
BAW56
SOT23N
PR713 PC716
3
1 2 INTVCC32 1
+5VS_P
2
0
PJL6 PU4A 0402
5% 10U
6
5
JP_NET20 16V
AO4900
1
D 1206
1
SO8 PC718
t
0.1U
1
G PC715 0402 PC714
1
5
6
+80-20% PU6A
2
PC30 4 0.1U 0.1U
t
1000P 0805 50V 0805 D
n
0402 10% 10%
2
PU703
10% GND
2
24
23
22
21
20
19
18
17
LTC3728L G
50V
e e
HVQFN32_1 4
3
C C
BOOST1
BG1
BG2
BOOST2
VIN
EXTVCC
INTVCC
PGND
r
GND S
PR719 PL706 AO4900
+1.5V_P
3
SO8
c m
1 2 1 2 25 16 PL707 PR732
SW1 NC1
26 15 1 2 1 2 +1.05V_P
TG1 SW2
PU4B 27 14
e
.012 3.9UH PGOOD TG2
28 13
RUN/SS1 RUN/SS2
8
7
2010 SPC-08045 AO4900 29 12 3.9UH .012

NC2 SENSE2+
u
1% 30% D 30 11 SPC-08045 2010
SO8 SENSE1+ SENSE2-
7
8
1
S
31 10 PU6B 30% 1% PC749
SENSE1- NC0 D + 220U
G 32 9
NC3 VOSENSE2
c
2 33 7343
VOSENSE1
K
SGND1 4V
34 G
PLLFLTR
K
3.3VOUT
SGND2
1
c Do
PD716
2
PC728 PC729 35 2
SGND3
1
1
SGND
PLLIN
PD710 + 220U/NA + 220U PC730 S 36 PC746
ITH1
ITH2
FCB
PC726 PC731 SGND4 PC727 BZV55C2V4/NA
7343 7343 0.1U 37 0.1U
SGND5
1
4V 4V 0402 1000P 0402
1
1 2 S PC742
a
+80-20% 1000P +80-20%
A
BZV55C2V4/NA 0402 + 220U/NA
2
2
0402 AO4900
50V 50V
A
50V
1
2
3
4
5
6
7
8
1
SO8 7343
50V 1000P GND PR721 10% 4V
10% 0402 6.49K
2
iT ial
50V 0402 2 1 SENSE1.05+
SENSE1.5+ 10% 1%
1 2 SENSE1.05-
SENSE1.5-
1
PC734
1
1 2 1 PC738 220P PC735
M t
180P 0402 100P
PR718 PR725 0402 10% 0402
1
+3VS_P 18K 2K 10% 50V +/-10%
12
2
1
1
GND 0402 0402 25V 50V PR722 PC724
1
1
1% 1% PC736 PR728 PR727 20K 1000P
1
PR726 100P 15K 15K 0402 0402

2
n
PR715 20K 0402 0402 0402 1% 10%
2
100K 0402 +/-10% 1% 1% 50V
2
2
0402 1% 50V
2
JS701
e
B B
1%
2
1 2
PR717
2
1 2 SHORT-SMT1
31 VCCP_PWRGD
id
1
0 GND
0402 PR723 SGND3
5% 0/NA
D
f
0402
D PQ705 5%
2N7002
2
G S
VDD5
n
INTVCC3
S
1 2
PR724
o
10K
1
SGND3 0402
PR733 1%
100K
C
0402
D
1%
PQ703
2
D
G S 2N7002
S
D
D PQ706
R714 1 0 2 G S 2N7002 SGND3
25,26,29,30,31 PWRON_SUSB#
0402 5%
1
S
1
C714 PR730
0.1U/NA 1M
0402 0402
+80-20% 1%
2
50V
2
SGND3
A A
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
DVMAIN
+1.8V_P/+1.35V_P
JS706 PL712
1 2 1 2
2012
1
PC765
0.01U
0402
2 10%
D 50V D
GND
2
PJL7
1
JP_NET20
PC766
0.01U
1
0402
1
10%
2
PC50 PC774 PC779 PC777
0.01U 10U 10U 50V 1000P
0402 1210 1210 0402
10% 25V 25V 10%
2
GND
50V 20%/X5R 20%/X5R PR91 PR90 50V
1 2 288100056017 1 2
1
4.7 4.7
GND 0603 PD6 0603 GND
1% 1%
BAW56
SOT23N
PR92 PC53
3
1 2 INTVCC22 1
2 +5VS_P
PJL8 PU705A 0
0402 10U
6
5
JP_NET20 5% 16V
AO4900
1
D 1206
1
SO8 PC54
0.1U
1
G PC51 0402 PC52
t
1
5
6
+80-20% PU707A
2
PC776 4 0.1U 0.1U
1000P 0805 50V 0805 D
0402 10% 10%
2
PU14
t
10% GND
2
24
23
22
21
20
19
18
17
LTC3728L G
n
50V 4
HVQFN32_1
3
BOOST1
BG1
BG2
BOOST2
VIN
EXTVCC
INTVCC
PGND
e e
C GND S C
AO4900
r
+1.8V_P PR739 PL713
3
SO8
1 2 1 2 25 16 PL714 PR741
SW1 NC1
26 15 1 2 1.2V_2
1 2
c m
TG1 SW2 +1.35V_P
PU705B 27 14
.012 3.0UH PGOOD TG2
28 13
RUN/SS1 RUN/SS2
8
7
2010 SPC-06703 AO4900 29 12 3.0UH .012
e
1% 30% D NC2 SENSE2+ SPC-06703 2010
SO8 30 11
SENSE1+ SENSE2-
7
8
1
31 10 PU707B 30% 1% PC783
SENSE1- NC0
u
G 32 9 D + 150U/NA
NC3 VOSENSE2
S
2 33 7343
VOSENSE1
K
SGND1 6.3V
34 G
PLLFLTR
K
3.3VOUT
SGND2
1
c
PD722
2
PC770 35 2
SGND3
1
1
SGND
PLLIN
PD719 + 150U PC767 S PC56 36 PC780
ITH1
ITH2
FCB
PC59 SGND4 BZV55C2V4/NA
c Do
7343 0.1U 3300P 37 0.1U
SGND5
1
6.3V 0402 0402 1 0402
1
2 S PC782
+80-20% 10% +80-20%
A
+ 150U
2
2
AO4900
50V 50V 50V
A
BZV55C2V4/NA
1
2
3
4
5
6
7
8
1
SO8 7343
a
1000P GND 6.3V
0402 PC57
2
50V 1 2 SENSE1.2+
SENSE1.8+ 10%
iT ial
1 2 SENSE1.2-
SENSE1.8- 1000P
1
PC63 PR96 0402
1
1 2 PC61 180P 13.7K 50V
1
180P 0402 0402 10%
1
PR98 PR101 0402 10% PC62 1%
2
1
1
2K 10% 50V
M t
24.9K
12
100P
1
GND +3VS_P 0402 0402 50V 0402 PC55
1
1% 1% PC60 PR105 PR107 +/-10%
2
1000P
100P 15K 15K 50V 0402
2
PR99 0402 0402 0402 PR97 10%
2
19.6K +/-10% 1% 1% 19.6K 50V
2
2
n
0402 50V 0402
2
2
JS3
1
1% 1% 1 2
PR93
e
B B
100K SHORT-SMT1
0402
1
1% GND
PR103
2
id
SGND2
PR94 0
1 2 0402
31 MCH_PG 5%
f
2
0
0402 1 2 INTVCC2
5%
n
PR102
10K
0402
o
1%
VDD5
C
D
D PQ17
G S 2N7002
1
PR95
100K
0402
D
1% SGND2
PQ16
2
D
G S 2N7002
A A
S
D
D PQ18
R103 1 0 2 G S 2N7002
25,26,28,30,31 PWRON_SUSB#
0402 5%
1
S
1
C142 PR106
0.1U/NA 1M
0402 0402
+80-20% 1% SGND2
2
50V
2
Title
8050D MOTHER B/D
SGND2 Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
+1.2V/1.0V_M10
DVMAIN
JS707 PL718
D D
1 2 1 2
2012
1
2
PC802
0.01U PJL10
1
0402 PC803 PC804 PC805
1
10% JP_NET20
2
PC806 10U 10U 10U

50V 0.01U 1210 1210 1210
1
0402 25V 25V 25V
2
GND
1
10% 20%/X5R 20%/X5R 20%/X5R
2
PC807
50V 1000P
0402
10%
2
GND
50V
1
PR72
1M GND
0402 GND
5% +5VS_P
PR100
2
1 2
A
10
0402 PD725
5%
1
EC10QS04
PC37
0.1U
1
K
0402
+80-20% PC64
2
t
50V
2
10U
2
PR108 16V
GND 1206
t n
4.7
0603
1%
e e
PR125 GND
1
C 0402 C
1 0 2
25,26,28,29,31 PWRON_SUSB#
5
6
7
8
5% PC81
0.1U D PU710
1
PC77 0805
c m
10% G SI4800DY
2
0.1U/NA
0402 PU16 SO8
4
+80-20%
2
1 14
e
50V EN/PSV BST +1.2V/1.0V_M10
2 13
VIN DH S
3 12
VOUT LX
u
4 11
VCCA ILIM
1
2
3
5 10
FB VDDP
6 9
PGOOD DL
c
SGND7 7 8 PL719
AGND PGND
1 2 1 2
c Do
SC1470
TSSOP14 PR126
5
6
7
8
8.2K 2.2UH
0402 D PU712 IHLP5050CE-01
1
5% 20% PC811
K
1
G AO4410 + 330U
PC78 PC79
1
SO8 PD726
0.01U 0.1U 4 PC814 7343
0402 0402 288204410010 + 330U/NA 4V
iT ial
10% +80-20%
2
2
7343
1
50V 50V S 4V PC815 PC816 BZV55C2V4/NA
A
+ 330U
2
0.1U
0402
1
2
3
7343
K
PD727 4V +80-20%
2
EC31QS04-TE12L/NA 50V
2
M t
DC2010
A
JS9
1 2
n
SHORT-SMT1
e
B B
GND
SGND7
fid
n
1 2
o
PR127
1
10K
1
PR128 0402
24.9K PR129 1%
C
0402 10K
1% 0402
1%
D 2
D PQ19
1 2 G S 2N7002
7 SW_1.5V/1.25V
S
PR130
1
100K PC80
0402 0.1U
1% 0402
10%
2
10V
SGND7 SGND7
A A
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
+5VS_P
CPU_CORE
1
PR4 PR5
10K 10
MCH_PG 29
0402 0402
1% 1%
2
PR6
1 2
PC6 VRMPWRGD 13
2.2K
D D
1 2 0402
1
1% PR7
0 PR712
1
1U 0402 0 DVMAIN PL5
0402 5% 0402 PR710 120Z/100M
GND_A 10V 5% 1.96K 2012 DD_CPU
+80-20% 0402
2
1 2
PR14 1%
+5VS_P +3V
2
13,14 DPRSLPVR 1 2 PF2
1 2 1 2
A
0 1 2 7A/24VDC PL4
2 PM_PS
0402 PD706 120Z/100M
2
5% PR13 2012 PC755 PC750 PC754 PC753 PC757 PC752 PC751
1
0 EC10QS04 PJL9
3,11,13 STOP_CPU# 1 2 PC41 10U 10U 10U 10U 10U 10U 0.01U
0402 1000P 1210 1210 1210 1210 1210 1210 0402 JP_NET20
25V 25V 25V 25V 25V 25V 10%
K
PR32 5% 0402
2
1 2
0 +/-20% 20% 20% 20% 20% 20% 20% 50V
1
1
0402 PC9 50V
5% PR8 0.1U
1
4.7 0805 PC58
1 2 1 2 0603 X7R GND 1000P
1
PC15 1% GND 0402

PR30 PC18 +/-20%
2
100P
0402 100K 1000P 50V
+/-10% 0402 0402 GND_A
2
33
32
31
30
29
28
27
26
25
PU3
1
50V VOS-1% 1 50V

2 PC11
5
6
7
8
5
6
7
8
5
6
7
8
+80-20% 220P GND
SGND1
PSIB
VFB
MCH_PG
FREQSET
DPRSLPVR
SVCC
PGOOD
BOOST
1
PR28 0402 D PU9 D PU8 D PU10

PR18 576K 10% FDS6694 FDS6694/NA FDS6694
2
t
1 0402 50V G SO8 G SO8 G SO8
0402 1% 1 24 4 4 4
1% VOA+ TG
t
2
2 23
n
PR29 VOA- SW S S S
1 2 3 22
OAOUT PVCC
e e
GND_A
1
2
3
1
2
3
1
2
3
C 13.3K 4 21 PR740 +VCC_CORE C
S1+ 0402 STP_CPUB BG .001
1 2
r
PR37 1% 5 20 2512C
GND_A SGND PGND
1
10 PC21 1%
0402 1000P 6 19 PL711
c m
1% 0402 SENSE+ VID5
1 2 1 2
S1- 10%
2
1 2 7 18
50V SENSE- VID4
e
PR38 8 17 GND 0.68UH
RDPRSLP VID3
1
10 IHLP-5050CE
1
RDPSLP
u
15%
RUN/SS
0402 PR39 S1+

RBOOT
PC778 PC773
5
6
7
8
5
6
7
8
5
6
7
8
1
S
1% 2.32K S1- PC785 + 220U 0.1U
VID0
VID1
VID2
ITH
0402
NC
D PU12 D PU13 D PU11 + 220U/NA 7243 0402

1
c
1% FDS7788 FDS7788 FDS7788 2V +80-20%
2
7243
G SO8 G SO8 G SO8 50V
2
PR31 2V
2
1
LTC3734
10
11
12
13
14
15
16
c Do
0
9
2
HVQFN32 4 4 4 PC784
0402 + 220U
K
5% 7243
GND_A S S S PD718 2V
2
2
PR15 +5VS_P EC31QS04-TE12L
1
2
3
1
2
3
1
2
3
K
DC2010
1 2
1
1
1
PR12
A
PD720
iT ial
PC786 PC775 PC781
1
1 2 56.2K + 220U/NA + 220U + 220U

0402 PR44 BZV55C2V4/NA
7243 7243 7243
1
1 1% 2 0 PC12 2V 2V 2V
1
0402
A
PC5 100K
2
0.1U
2
1
1000P0402 PR16 5% 0402

1
0402 1% 1.3M PR33 +80-20%

2
+80-20% 0 50V
M t
04021 PC13
2
2
1
50V 1% 0402 10U

PR17 PR52 5% 1206
2
GND_A 12.7K 0 10V

2
1
PR19 0402 0402

1 2 1 1%
2 5% PR34
n
1
0
2
PR43 PR40 0402 JS2 1 2 VOS-

13.3K 499K 0 5% 1 2
e
B B
0402 0402 RUN/SS 0402 VID5 PR104
2
GND
1% 1% 5% SHORT-SMT1 0
VID4 0402
2
GND_A 5%
id
VID3
1
PR53 1 2 VCCP_PWRGD 28
f
1K VID2 +3V
0402 +3VS VDD3 PR57
1% 1 PR731 2 0
VID1 2K 0402
2
1
n
PC22 VDD3 0402 5%
100P/NA 1%
1
0402 PC29 VID0 1 2 1 2 CORE_CLKEN# 11
1
o
+/-10%
2
1000P
1
50V 0402 PR729 PR64 PR51 PR56
10% 249K 249K/NA PR59 2K/NA VDD3 0
2
50V 0402 0402 1M 0402 0402
C
1% 1% 0402 1% 5%
1
1%
2
PQ8 PR58 PR68
2
D
GND_A G S 2N7002 4.12K 1.91K/NA
VID[0..5] VDD5 SOT23_FET 0402 0402
C
3 VID[0..5] VID0 1% 1%
S
VID1 PQ9
2
B 1 2 PWROK 4,12,13,17,25
VID2 MMBT3904L
VID3 288203904022 PR73
C
1
VID4 PR60
E
0/NA
VID5 PR49 RUN/SS 1 1 2 B PQ10 0402
100K PR66 MMBT3904L 5%
0402 80.6K GND_A 288203904022
1% 0402
E
43.2K
D
1% 0402
2
PQ5 PR50 1%
2
1
G S 2N7002 1M PC35
SOT23_FET 0402 1U
1%
S
GND_A 0402 GND_A

D
+80-20%
2
2
A A
PR61 D PQ7 10V
1 2 G S 2N7002
25,26,28,29,30 PWRON_SUSB#
1
SOT23_FET PC27
1
1
S
100P PC28 GND_A

1
0 C26 PR62 0402 3300P

0402 1M +/-10% 0402
2
0.1U/NA
5% 0402 0402 50V 10%
2
+80-20% 1% 50V
2
50V
2
GND_A PD4 Title

2 8050D MOTHER B/D
3
1 Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
BAT54C Date: Wednesday, December 31, 2003 Sheet 31 of 34
5 4 3 2 1

5 4 3 2 1
VMAIN/DISCHARGE PWR_VDDIN
PD702 PD704
1 2
3 3
2 1
D D
BAV70LT1 BAV70LT1
288100070006 288100070006
PL1
120Z/100M
2012 JO701
2 1 2 1 PQ701 DVMAIN
AO4407 ADINP 33
SO8 PD703
PJ701 OPEN-SMT4 8 1
2DC-S107B200 PF1 7A/24VDC 3 7 3
1 A1 1 2 A2 2 1 A3 1 2 A4 2 6 2
1 5
1
D
S
2 PL2 PR701 SBM1040 PC82 PC83 PC84 PC85 PC711 PC740 PC86
1
G
120Z/100M .01 PC818 PC819 PC820 PC821 PR706 0.01U 0.01U 1000P 1000P 1000P 0.01U 0.01U
1
1
JACK-2P PC2 2012 2512 PR702 PR704 4.7K 0402 0402 0402 0402 0402 0402 0402
3
4
PC701 PC702 0.01U 0.01U 1000P 1000P

331910002006 PD701 1% 470K 0402 0402 0402 0402 4.7K 0805 +80-20% +80-20% +/-20% +/-20% +/-20% 10% +80-20%
2
0.01U 1U 0.01U
0402 0805 0402 RLZ24D 0402 +80-20% +80-20% +/-20% +/-20% 0805 PR720 50V 50V 50V 50V 50V 50V 50V
2
10% 25V 10% MLL34B 5% 50V 50V 50V 50V
2
2
1 2
50V 50V
2
PQ704
1
100K AO4407 GND
2
1
2
3
PR703 0402 SO8
JO1 JO2 100K PR71 5%
S
0402 226K
SPARKGAP_6 SPARKGAP_6 GND 5% 0402 4
1%
2
t
GND
2
G
1
D
1
2
t
D PQ702 PR45
n
LEARNING 2N7002 PJO701 33K
5
6
7
8
G S
22 LEARNING 0402
1
OPEN-SMT4
e e
5%
S
ADEN# 22,25
GND PR705
D 2
C C
PU1 1M
r
4 3 0402
RS+ VCC 5% D PQ6
1
5
RS- S 2N7002
2
2 G
c m
GND1 SOT23_FET
6 1 BATT 33
OUT GND0
1
S
PC1
0.01U
e
1
MAX4173FEUT-T 0402
PR1 SOT26 10%
2
u
10 50V GND
S
0402 GND
1
5% PC733 PC732
c
2
0.01U 1000P
3
0402 0402
c Do
GND PQ24 +80-20% +/-20%
2
2 50V 50V
I_LIMIT 22 DTC144WK
288202237002
a
1
PC3 PL705
1U 120Z/100M
0805 2012
10V GND
2
1
iT ial
2 1
PF702 7A/24VDC
GND 1 2 B2 2 1 B3
BATT 33
GND
1
PL704
1
PC720 120Z/100M PR716

499K
M t
0.01U 2012
0402 0402
VDD3S 10% 1%
2
50V
2
1
PC722 VDD5
BAT_V 22
0.01U
n
1
8
J703 GND 0402
1
PR20 10% PR714

2
7 PC723 3 +
7 4.99K 50V 100K
6 0.1U 1
e
B 6 0402 0402 0402
B
5 2 -
5 GNDB 1% 1% +80-20%
2
4
4 50V PU5A
2
3 BAT_T 22
3 LMV393M
4
2
id
2
1
1 B1 SSOP8
1
1
PR21 PC16 GND

20K 0.1U
f
R/A-7P-2.5MM 0402 0402
SUYIN 1% +80-20%
2
250233-MR007G123ZU 50V GND

2
n
GND
PR23
o
1 2 BAT_C 22
0
0402
C
5% PR24
1 2 BAT_D 22
0 PD2
0402 2 VDD3
5% 3
1
PD3 BAV99
2 288100099012 VDD3
3
1
2
BAV99
288100099012
JO11 JP1
A SPARKGAP_6 SPARKGAP_6 A
GND GND
1
GND GND
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
CHARGING
PQ707
AO4407
SO8
D D
8
3 7
PF703 PL708 2 6 PL710 PL709 PD713 12.65V
1 2 L2 1 2 L3 1 5 L4 1 2 L5 1 2 A K
32 ADINP BATT 32
D
S
BEAD_120Z/100M
G
TR/3216FF-3A 0805D 33UH EC31QS04
K
CDRH124 3.0UH DC2010
K
1
1
PC758 SPC-06703 PD709
4
PC747 PC748 PC745 PC756
1
0.01U 0.01U 10U PR87 PR88 10U 0.01U 30% PC741 PD711
1
0402 0402 1210 4.7K 4.7K 1210 0402 BZV55C15V RLZ20C/NA
10U
K
1
10% 10% 25V 0603 0603 25V 10% 1210 PC39 PR75 MLL34B
2
2
50V 50V 50V 25V 20K
A
PR89 PD714
2
C
100K 1000P 0402
A
2
2
PQ15 0402 EC31QS04 0402 0.1%
B
MMBT2222A 5% DC2010 50V
2
10% 2IN+
A
288202222019 GND
2
E
GND GND
1
1
PD5 GND PR76
1 2 K A PR74 249K
13.7K 0402
PR86 BAS32L 0402 1%
1
0 MLL34B 0.1%
2
1206
2
5%
2 PQ13
DTA144WK PC49
SOT23AN_1 0.01U/NA
t
0402
2
50V
3
D
PQ14 +80-20% PJ1
t
D 2N7002 1 2
n
S SOT23_FET OPEN-SMT4
G
D
22 CHARGING PU7 PQ12
1
e e
S
PC48 9 8 D 2N7002
E1 C1 S SOT23_FET
C 0.01U 10 7 1 2 G C
0402 E2 GND 22 CHARGING
1
11 6
r
10% C2 RT
S
PR85
2
12 5
50V VCC CT PC43 0
13 4
OUTPUTCTRL DTC 0402
14 3 1 2
c m
REF FEEDBACK 5%
15 2
2IN+ 2IN- 1IN-
16 1
2IN+ 1IN+ 0.01U
e
GND TL594C 0402
SO16 50V
1
1
u
+80-20%
1
S
PC46 PR83 PC47 PR84
1
1U 100K 1000P 7.5K
c
PC42 0805 0402 0402 0402 PR79
10V 5% 10% 5% 124K
2
2
1 2
c Do
50V 0402
2
2
1%
1
0.01U
2
PR82 0402 PR22
a
10K 50V 1 2
0402 +80-20%
1% PC44 PR81 .02
PC45 2512
2
iT ial
1 2 1 2
REF 1 2 1%
1
0.1U 6.19K PR77
0.1U 0402 0402 2.49K GND GNDB
0402 16V 1% 0402
50V 10% 1%
PR80
M t
+80-20%
2
1 2
63.4K/NA
0402 PJS1
n
5% 2 1
PR78
1 2
e
B 22 I_CTRL B
SHORT-SMT3
0
0402
id
5%
f
VDD5 DVMAIN
on
1
PR70
1
3.3K PC34
C
1
0402 0.01U PR65
5% 0402 590K PR69
10% 0402 100K
2
50V 1% 0402
GND 5%
2
1.25V 5 +
7 BATT_DEAD 22
6 -
2
PQ11 PU5B =8.56V

LMV393M
1
SCK431LCSK-.5 SSOP8
4
1 PC36
1
PC33 PR63 0.01U

SOT23N 0.1U 80.6K 0402
0402 0402 10%
3
+80-20% 5% 50V
2
50V
2
A A
GND GND
Title
8050D MOTHER B/D
Size Document Rev
C PCB 316680900001/ASSY 411682700001 R01
Number
5 4 3 2 1

5 4 3 2 1
VGA_THRMDA/VGA_THRMDC
8050 BLOCK DIAGRAM
CPU_THRMDA/CPU_THRMDC LCD PANEL
CLK_ITP_CPU+/- 100MHZ (XGA)
SIO_48M CPU
HCLK_CPU+/- 100MHZ
(DEBUG CARD ONLY) LVDS
INTEL
14.318MHZ BANIAS/DOTHAN
D D
CLOCK GENERATOR
HOST BATT-Adapter
14M_CODEC 400MHZ D/D Power
ICS950810 RGB CRT LTC3728L
D/D Charger
LVDS/NA +2.5V/+1.25V TL-594C
HCLK_NB+/- 100MHZ
RGB/NA
North Bridge
D/D CPU Core
66M_MCH I-LIMIT OP LTC3734
DREFCLK_48MHZ MAX4173F
DIMM1 DIMM0 CLK_DDR2+/-
CLK_DDR1+/- 855GME AGP D/D Power
CH7011 LTC3728L
CLK_DDR0+/- VGA_M10 TV +3V/+5V
CLK_DDR3+/- 27MHZ
I -LIMIT
t
CLK_DDR4+/-
CLK_DDR5+/- D/D Power
LTC3728L
t n
DDR 266 PCICLK_FWH
+1.5V/+1.05V
e e
C C
66M_AGP
r
D/D Power D/D Power
c m
66M_ICH 66MHZ SC1470 LTC3728L
66MHZ CDROM +1.2V/1.0V +1.8V /+1.35V
e
USBCLK_ICH 48MHZ
32.768KHZ
u
PCICLK_ICH 33MHZ
S
USB 0~2 AC-Adapter
c
14M_ICH Sourth Bridge VRAM
c Do
x3 16MBx4 D/D
33MHZ
SECONDARY IDE
a
ICH4-M
33MHZ
33MHZ
HDD
iT ial
PRIMARY IDE
PCICLK_MINIPCI
PCI_1394_CLK
PCI_CRAD_CLK
14M_CODEC (CLK GEN)
M t AC97
LPC BUS
en
B B
PCI
ADT7460
24.576MHZ / NA
id
25MHZ AUDIO
PCICLK_LAN RTL8100CL MDC
f
CODEC
MODULE
SMBUS
Fan ALC655
on
C
PH163112
PCMCIA AMPLIFIER
Keyboard BIOS MINIPCI
IEEE1394 CARD READER
SYSTEM CP2211 TPA0212 EXT LINE
WINBOND BIOS INT
VIA MIC. IN
MIC
W83L950D VT6307L CB710
8MHZ 512K
LM4871
KEY MATRIX
SPEAKER SPEAKER
PS/2
A
HP JACK A
NA
24.576MHZ RJ45/ RJ11 SUB WOOFER
I -LIMIT
CABLE CARD
REARDER
TOUCH Internal SOCKET
Keyboard
PAD PCMCIA/ CardReader Title
CARDBUS Transition 8050D MOTHER B/D
Board Size Rev
SLOT C
Document
Number
PCB 316680900001/ASSY 411682700001 R01

5 4 3 2 1

REFERENCE MATERIAL
Intel Mobile Pentium-M Processor/BANIAS Processor Intel, INC.
“Intel 855GME North Bridge” Intel, INC.
“Intel ICH-4 South Bridge” Intel, INC.
WINBOND KBC WINBOND, LTD.
Clock Syntherizer ICS,INC
VT6307L IEEE1394 Host Controller AMPRO Computers, INC
System Explode View Technology Corp / MiTAC
8050D Hardware Specification Technology Corp / MiTAC

SERVICE MANUAL FOR 8050D
Sponsoring Editor : Jesse Jan
Author : Grass Ren
Assistant Editor : Ping.Xie
Publisher : MiTAC International Corp.
Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C.
Tel : 886-3-5779250 Fax : 886-3-5781245
First Edition : Mar.2004
E-mail : Willy.Chen @ mic.com.tw
Web : http: //www.mitac.com http: //www.mitacservice.com

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SERVICE MANUAL FOR

1. Hardware Engineering Specification ………………………………………………………………….. 3

6. System Block DiagramC

7. Maintenance Diagnostics ……………………………………………………………………………….. 93

10. System Exploded View ……………………………………………………………………………...….. 148

11. Circuit Diagram ……………………………………………………………………………………….... 149

12. Reference Material …………………………………………………………………………………..…. 183

1. Engineer Hardware Specification

VGA CRT with the input data.

1.2 System Overview

CPU Mobile Pentium-M Processor 1.5G ~ 1.9GHz/Dothan 2.0GHz and above

1.3 System Hardware Parts

1.3.1 Intel Banias Processors in Micro-FCPGA Package

Intel Banias Processors with 478 pins Micro-FCPGA package.

Provides standard frequencies and additional 5% and 10% over-clocked frequencies

Processor/Host Bus Support

All supported devices have 4 banks.

Supports up to 16 simultaneous open pages.

UMA support only.

From IOxAPIC in ICH4-M

Dynamic Bob and Weave support for Video Streams

Software DVD at 60 fields/second and 30 frames/second full screen

Multiple overay functionality provided via Arithmetic Stretch Blt

Direct YUV from Overlay to TV-out

Independent Gamma Correction

each display device

DVO (DVOB) support

Variety of DVO devices channel

Introducing MOBILITY M10

SMARTSHADER™ 2.0 — Advanced Shader Technology

Adaptive algorithm with programmable sample patterns

2x/4x/8x/16x anisotropic filtering modes

Adaptive algorithm with bi-linear (performance) and tri-linear (quality) options

High Performance Memory Support

Incorporates support for DDR SDRAM/SGRAM.

Dual Display Support

provides sharper image quality.

1.3.6 CardBus: CB710

Advanced Configuration and Power Interface Specification, Revision 1.0

Support CardBay PC card interface

Smart Card Interface

Compliant with PC/SC Specification 1.0

Support ISO7816 T=0 and T=1 asynchronous communication protocols

Two power enable pins to support 5V and 3V smart cards

Support Write Protect Switch

Support Card Detect either by DAT3 or by dedicated Card Detect Switch

One Traffic LED pin

One power enable pin.

Memory Stick Interface

Compliant with Memory Stick Standard Format Specification Version 1.3

One traffic LED pin

Supports Zoomed Video port.

Power Switch Interface

Misc Control Logic

Supports socket activity LED

Supports 12 GPIOs and GPE#

Supports PCI LOCK

Meets performance requirements for audio on PC99/2001 systems

Meets Microsoft WHQL/WLP 2.0 audio requirements