DISCRETE SEMICONDUCTORS

DATA SHEET

BST120
P-channel enhancement mode
vertical D-MOS transistor
Product specification April 1995
File under Discrete Semiconductors, SC13b
Philips Semiconductors Product specification

P-channel enhancement mode vertical

BST120
D-MOS transistor

DESCRIPTION QUICK REFERENCE DATA

P-channel vertical D-MOS transistor Drain-source voltage −VDS max. 60 V
in SOT89 envelope and intended for Gate-source voltage (open drain) ±VGSO max. 20 V
use in relay, high-speed and
Drain current (DC) −ID max. 0,3 A
line-transformer drivers, using SMD
technology. Total power dissipation up to Tamb = 25 °C Ptot max. 1 W
Drain-source ON-resistance
−ID = 200 mA; −VGS = 10 V RDS(on) typ. 4,5 Ω
FEATURES
max. 6 Ω
• Very low RDS(on)
Transfer admittance
• Direct interface to C-MOS
−ID = 200 mA; −VDS = 15 V  Yfs typ. 200 mS
• High-speed switching
• No second breakdown
PINNING - SOT89
1 = source
2 = drain
3 = gate

PIN CONFIGURATION

handbook, halfpage d

1 2 3 s
Bottom view MAM354

marking: LM

Fig.1 Simplified outline and symbol.

April 1995 2
Philips Semiconductors Product specification

P-channel enhancement mode vertical

BST120
D-MOS transistor

RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage −VDS max. 60 V
Gate-source voltage (open drain) ±VGSO max. 20 V
Drain current (DC) −ID max. 0.3 A
Drain current (peak) −IDM max. 0.8 A
Total power dissipation up to Tamb = 25 °C (note 1) Ptot max. 1 W
Storage temperature range Tstg −65 to + 150 °C
Junction temperature Tj max. 150 °C

THERMAL RESISTANCE
From junction to ambient (note 1) Rth j-a = 125 K/W
Note
1. Transistor mounted on ceramic substrate: area = 2,5 cm2 and thickness = 0,7 mm.

April 1995 3
Philips Semiconductors Product specification

P-channel enhancement mode vertical

BST120
D-MOS transistor

CHARACTERISTICS
Tj = 25 °C unless otherwise specified
Drain-source breakdown voltage
−ID = 10 µA; VGS = 0 −V(BR)DSS min. 60 V
Drain-source leakage current
−VDS = 48 V; VGS = 0 −IDSS max. 1 µA
Gate-source leakage current
−VGS = 20 V; VDS = 0 −IGSS max. 100 nA
Gate threshold voltage
min. 1.5 V
−ID = 1 mA; VDS = VGS −VGS(th)
max. 3.5 V

Drain-source ON-resistance
typ. 4.5 Ω
−ID = 200 mA; −VGS = 10 V RDS(on)
max. 6 Ω

Transfer admittance
−ID = 200 mA; −VDS = 15 V  Yfs typ. 200 mS
Input capacitance at f = 1 MHz
typ. 55 pF
−VDS = 10 V; VGS = 0 Ciss
max. 70 pF

Output capacitance at f = 1 MHz

typ. 30 pF
−VDS = 10 V; VGS = 0 Coss
max. 45 pF

Feedback capacitance at f = 1 MHz

typ. 8 pF
−VDS = 10 V; VGS = 0 Crss
max. 12 pF

Switching times (see Figs 2 and 3)

ton typ. 4 ns
−ID = 200 mA; −VDD = 50 V; −VGS = 0 to 10 V
toff typ. 20 ns

April 1995 4
Philips Semiconductors Product specification

P-channel enhancement mode vertical

BST120
D-MOS transistor

handbook, halfpage 10 %
handbook, halfpage VDD = −50 V
INPUT

90 %

10 %
0V OUTPUT
ID
−10 V
90 %
50 Ω

ton toff
MBB689
MBB690

Fig.2 Switching times test circuit. Fig.3 Input and output waveforms.

MDA776 MDA777
−103 −1
handbook, halfpage
V GS = −10 V handbook, halfpage
ID
−7.5 V
(A)
ID −6 V −0.8
(mA)
−5 V

−4.5 V −0.6

−102

−0.4

−0.2

−10 0
4 6 8 10 12 14 16 0 −2 −4 −6 −8 −10
RDSon (Ω) VGS (V)

Fig.4 Drain current vs ON-resistance; Fig.5 Transfer characteristics; Tj = 25 °C;

Tj = 25 °C; typical values. −VDS = 10 V; typical values.

April 1995 5
Philips Semiconductors Product specification

P-channel enhancement mode vertical

BST120
D-MOS transistor

MDA778
−1
handbook, halfpage
ID
(A) VGS = −10 V
−0.8
−7.5 V

−0.6
−6 V

−0.4
−5 V

−4.5 V
−0.2

0
0 −2 −4 −6 −8 −10
VDS (V)

Fig.6 Output characteristics; Tj = 25 °C;

typical values.

April 1995 6
Philips Semiconductors Product specification

P-channel enhancement mode vertical

BST120
D-MOS transistor

PACKAGE OUTLINES

Plastic surface mounted package; collector pad for good heat transfer; 3 leads SOT89

D B

b3

E
HE

L
1 2 3

b2 c

w M b1

e1

0 2 4 mm

scale

DIMENSIONS (mm are the original dimensions)

L
UNIT A b1 b2 b3 c D E e e1 HE w
min.
1.6 0.48 0.53 1.8 0.44 4.6 2.6 4.25
mm 3.0 1.5 0.8 0.13
1.4 0.35 0.40 1.4 0.37 4.4 2.4 3.75

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

SOT89 97-02-28

April 1995 7
Philips Semiconductors Product specification

P-channel enhancement mode vertical

BST120
D-MOS transistor

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Application information
Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

April 1995 8
Philips Semiconductors Product specification

P-channel enhancement mode vertical

BST120
D-MOS transistor

NOTES

April 1995 9
Philips Semiconductors Product specification

P-channel enhancement mode vertical

BST120
D-MOS transistor

NOTES

April 1995 10
Philips Semiconductors Product specification

P-channel enhancement mode vertical

BST120
D-MOS transistor

NOTES

April 1995 11
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Printed in The Netherlands 137107/00/01/pp12 Date of release: April 1995 Document order number: 9397 750 02494
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