SN54/74LS279

QUAD SET-RESET LATCH

VCC S1 R Q S1 S2 R Q
16 15 14 13 12 11 10 9 QUAD SET-RESET LATCH
LOW POWER SCHOTTKY

1 2 3 4 5 6 7 8
R S1 S2 Q R S1 Q GND
J SUFFIX
CERAMIC
CASE 620-09
TRUTH TABLE 16
1
INPUT OUTPUT
S1 S2 R (Q)
N SUFFIX
L L L h PLASTIC
L X H H 16 CASE 648-08
X L H H
1
H H L L
H H H No Change
L = LOW Voltage Level
H = HIGH Voltage Level D SUFFIX
X = Don’t Care SOIC
16
h = The output is HIGH as long as 1 CASE 751B-03
h = S1 or S2 is LOW. If all inputs go
h = HIGH simultaneously, the output
h = state is indeterminate; otherwise,
h = it follows the Truth Table
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0

FAST AND LS TTL DATA

5-452
 SN54/74LS279

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input LOW Voltage for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table

20 µA VCC = MAX, VIN = 2.7 V

IIH Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX
ICC Power Supply Current 7.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tPLH 22
Propagation Delay, S to Output ns VCC = 5.0 V
tPHL *21*
CL = 15 pF
tPHL Propagation Delay, R to Output 27 ns
* Add 0.6 ns to spec limit for each 1.0 ns input rise time less than 15 ns.

FAST AND LS TTL DATA

5-453
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FAST AND LS TTL DATA

5-454
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◊ FAST AND LS TTL DATA

5-455
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