APPLICATION NOTE

APPLICATION NOTE
0


Virtex Synthesizable Delta-Sigma DAC

XAPP154 September 23, 1999 (Version 1.1) 0 13* Application Note by John Logue

Summary
Digital to analog converters (DACs) convert a binary number into a voltage directly proportional to the value of the binary number. A variety of
applications use DACs including waveform generators and programmable voltage sources. This application note describes a Delta-Sigma DAC
implemented in a Virtex FPGA. The only external circuitry required is a low pass filter comprised of just one resistor and one capacitor. Internal
resource requirements are also minimal. For example, a 10-bit DAC uses only three Virtex CLBs. The speed and flexible output structure of the Virtex
series FPGAs make them ideal for this application.
Xilinx Family: Virtex Family

Introduction Delta-Sigma DACs are used extensively in audio applications. They are
suited for low frequency applications that require relatively high
Figure 1 is a top-level schematic diagram of a typical Virtex DAC accuracy.
implementation. As shown in this diagram, the inputs include reset and
clock signals, in addition to the binary number bus. As is standard practice, the DAC binary input in this implementation is
an unsigned number with zero representing the lowest voltage level. The
DACoutDrvr (Virtex output pin) drives an external low-pass filter. VOUT analog voltage output is also positive only. A zero on the input produces
can be set from 0V to VCCO, where VCCO is the supply voltage applied to zero volts at the output. All ones on the input cause the output to nearly
the FPGA I/O bank driving the resistor-capacitor filter. reach VCCO. For AC signals, the positive bias on the analog signal can
be removed with capacitive coupling to the load. Though the low pass
filter can be driven with any of the Virtex SelectIOTM output standards
Virtex FPGA that both sink and source current, this application note emphasizes the
LVTTL standard.
OBUF_F_24
3.3k
VOUT Figure 2 is a block diagram of a Delta-Sigma DAC. The width of the
DACout
Verilog dac binary input in the implementation described below is configurable. For
module DACoutDrvr
DACin [7:0]
DACin [7:0] 0.0047 µF simplicity, the block diagram depicts a DAC with an 8-bit binary input.
100 MHz
The term “Delta-Sigma” refers to the arithmetic difference and sum,
Reset Reset
respectively. In this implementation, binary adders are used to create
both the difference and the sum. Although the inputs to the Delta adder
990709001 are unsigned, the outputs of both adders are considered signed
numbers. The Delta Adder calculates the difference between the DAC
Figure 1: Top-level DAC Implementation input and the current DAC output, represented as a binary number.
Since the DAC output is a single bit, it is “all or nothing”; i.e., either all
The classic current summing digital to analog converter uses matched zeroes or all ones. As shown in Figure 2, the difference will result when
resistors to convert a binary number to a corresponding voltage level. adding the input to a value created by concatenating two copies of the
This technique works well for high-speed DACs when the binary number most significant bit of the Sigma Latch with all zeros. This also
is up to ten bits wide. However, it is difficult to maintain accuracy over a compensates for the fact that DACin is unsigned. The Sigma Adder
range of temperatures as the number of bits increases. sums its previous output, held in Sigma Latch, with the current output of
the Delta Adder.
Delta-Sigma Architecture In most cases, the Delta adder is optimized out when the high level
A Delta-Sigma DAC uses digital techniques. Consequently, it is design is synthesized. This is because all bits on either the A or B inputs
impervious to temperature change, and may be implemented in are zero, so A and B are simply merged, rather than added.
programmable logic. Delta-Sigma DACs are actually high-speed single-
As noted below, the DAC input can be widened by one bit to allow the full
bit DACs. Using digital feedback, a string of pulses is generated. The
analog range of 0V to VCCO. In this case, the Delta adder is needed.
average duty cycle of the pulse string is proportional to the value of the
binary input. The analog signal is created by passing the pulse string The interface to Verilog module dac in Figure 1 includes one output and
through an analog low-pass filter. While an in-depth discussion of Delta- three input signals as defined in Table 1. All signals are active high.
Sigma conversion is beyond the scope of this application note, the basic
architecture, implementation, and trade-offs are covered.
Table 1: DAC Interface Signals

Signal Direction Description

DACout Output Pulse string that drives the external low pass filter (via an output driver such as OBUF_F_24).
DACin Input Digital input bus. Value must be setup to the positive edge of CLK. For high-speed operation, DACin should
be sourced from a pipeline register that is clocked with CLK. For full resolution, each DACin value must be
averaged over 2(MSBI+1) clocks, so DACin should change only on intervals of 2(MSBI+1) clock cycles.
CLK Input Positive edge clock for the SigmaLatch and the output D flip-flop.
Reset Input Reset initializes the SigmaLatch and the output D flip-flop. In this implementation, SigmaLatch is initialized
to a value that corresponds to 0V in and 0V out. If DACin starts at zero, there is no discontinuity.

XAPP154 September 23, 1999 (Version 1.1) 1

 Implementation

Implementation
The DAC can be implemented in a single Verilog module, as shown
below. The width of the input bus is configurable with defined constant
MSBI .

‘timescale 100 ps / 10 ps
‘define MSBI 7 // Most significant Bit of DAC input

//This is a Delta-Sigma Digital to Analog Converter

module dac(DACout, DACin, Clk, Reset);

output DACout; // This is the average output that feeds low pass filter
reg DACout; // for optimum performance, ensure that this ff is in IOB
input [‘MSBI:0] DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;

reg [‘MSBI+2:0] DeltaAdder; // Output of Delta adder

reg [‘MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [‘MSBI+2:0] SigmaLatch; // Latches output of Sigma adder
reg [‘MSBI+2:0] DeltaB; // B input of Delta adder

always @(SigmaLatch) DeltaB = {SigmaLatch[‘MSBI+2], SigmaLatch[‘MSBI+2]} << (‘MSBI+1);

always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;

always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;

always @(posedge Clk or posedge Reset)

begin
if(Reset)
begin
SigmaLatch <= #1 1’bl << (‘MSBI+1);
DACout <= #1 1‘b0;
end
else
begin
SigmaLatch <== #1 SigmaAdder;
DACout <= #1 SigmaLatch[‘MSBI+2];
end
end
endmodule

Delta Sigma Sigma

Adder Adder Latch
8 10
DACin
A A

10 DACout
D S L
SUM SUM D Q
L [9]
D Q
DeltaB
B B Init
10

10
{ L [9] , L [9] , 0, 0, 0, 0, 0, 0, 0, 0 } L [9]
CLR

Clk

Reset

990709002

Figure 2: Delta-Sigma DAC Internal Block Diagram

2 XAPP154 September 23, 1999 (Version 1.1)

Implementation
For the implementation in Figure 1, the output voltage (VOUT) as a • Time Constant. The filter time constant (τ = RC) must be high
function of the DAC input may be expressed as follows: enough to greatly attenuate the individual pulses in the pulse string.
VOUT = (DACin/(2(MSBI+1))) x VCCO Volts On the other hand, a high time constant may also attenuate the
desired low-frequency output signal. These potentially conflicting
For example, for an 8-bit DAC (MSBI = 7) the lowest VOUT is 0V when
requirements are analyzed separately.
DACin is 0. The highest VOUT is 255/256 VCCO volts when DACin is
FF16. Pulse String Filtering
For some applications, it may be important for VOUT to swing through the In the midrange voltages, signal DACoutDrvr is switching rapidly making
entire voltage range: 0V to VCCO (rail-to-rail). This is accomplished by it relatively easy to filter. When the DAC input is at 1 or the highest
increasing the DACin bus width by one bit and leaving all other bus possible value, the signal DACoutDrvr is at the same level for all but one
widths the same. For an 8-bit DAC with an input value of 256, VOUT = CLK cycle for each sample period. These are the most difficult output
VCCO. Note that all DACin values greater than 256 are illegal and should strings to filter; i.e., they are the "worst-case".
not be used.
Although the filter noise may be calculated as an absolute peak-to-peak
As outlined in this application note, it is often advantageous to use a voltage, it is more useful to consider it as a fraction of the step voltage.
high-frequency clock. The desired clock may be faster than that which The step voltage (VS) is defined as the absolute change in VOUT when
can be practically sourced externally. One or two Virtex Delay Locked the DAC input is incremented or decremented. For an 8-bit DAC, VS
Loops (DLLs) can be used to double or quadruple the frequency of an equals (1/256) x VCCO.
external clock source. See Application note XAPP132 - Using the Virtex
Delay-Locked Loop. The worst-case peak-to-peak filter noise for an 8-bit DAC can be
expressed as follows:
Low-Pass Filter PPNFS = (1-e-(1/fτ)) x ((1-e-(255/fτ) )/(1-e-(256/fτ))) x 256
The resistor/capacitor low-pass filter shown in Figure 1 is adequate for
where:
most applications. A 24 mA LVTTL output buffer is used to provide
maximum current drive. PPNFS - peak-to-peak noise expressed as a fraction of step voltage
f is the DAC clock frequency
There are three primary considerations in choosing values for the
resistor and capacitor: τ is the filter time constant, RC.
• Output Source and Sink Current. Unlike normal digital For simplicity, we did not generalize this equation to handle any width
applications, it is important that signal DACoutDrvr always switch the DAC. For other widths, change the constants 256 and 255 to the
entire voltage range from 0 V to VCCO (rail-to-rail). If the value of R is appropriate power of 2, and (power of 2) minus 1, respectively.
too low and signal DACoutDrvr can not switch rail-to-rail, the analog This equation was used to create Figure 3, Figure 4, and Figure 5.
output is non-linear; i.e., the absolute output voltage change These charts may be used to determine the value of RC for the desired
resulting from incrementing or decrementing DACin is not constant. worst-case noise voltage and operating frequency. For example, for an
The worst-case output impedance of the 24 mA LVTTL buffer is 8-bit DAC with a clock frequency of 80 MHz, the user might choose an
about 25 Ω. R must be 2.5 KΩ or greater to ensure rail-to-rail RC value of 13.0x10-6, corresponding to a peak-to-peak noise voltage of
switching, with an error of 1% or less. about 0.25VS. This leaves 0.75VS noise margin between steps. Part of
• Load Impedance. Keep the value of R low relative to the impedance this noise margin is needed to handle other noise sources such as noise
of the load so that the current change through the capacitor due to on VCCO.
loading becomes negligible.

XAPP154 September 23, 1999 (Version 1.1) 3

 Implementation

10-bit DAC, Static Input of Binary 1, Peak-to-Peak Noise as Fraction of a Step

1.00
0.90
0.80
0.70
Peak-to-Peak Filter Noise Voltage as a Fraction of a Step

40.0
0.60
0.50

60.0
0.40

80.0
0.30

100.0

120.0
0.20
0.10
0.00

2.0 4.0 6.0 8.0 10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00 26.00 28.00 30.00 32.00 34.00 36.00 38.00 40.00
RC (x 10E - 6)

Note: The number at the end of each curve is the DAC clock frequency in MHz. 99063002

Figure 3: Peak-to-Peak Filter Noise as a Function of RC and Frequency (10-bit DAC)

4 XAPP154 September 23, 1999 (Version 1.1)

Implementation

8-bit DAC, Static Input of Binary 1, Peak-to-Peak Noise as Fraction of a Step

1.00
0.90
0.80
0.70
Peak-to-Peak Filter Noise Voltage as a Fraction of a Step
0.60
0.50
0.40
0.30
0.20

40.0

60.0
0.10

80.0
100.0
120.0
0.00

2.0 4.0 6.0 8.0 10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00 26.00 28.00 30.00 32.00 34.00 36.00 38.00 40.00
RC (x 10E - 6)

Note: The number at the end of each curve is the DAC clock frequency in MHz. 99063004

Figure 4: Peak-to-Peak Filter Noise as a Function of RC and Frequency (8-bit DAC)

XAPP154 September 23, 1999 (Version 1.1) 5

 Implementation

6-bit DAC, Static Input of Binary 1, Peak-to-Peak Noise as Fraction of a Step40

1.00
0.90
0.80
0.70
Peak-to-Peak Filter Noise Voltage as a Fraction of a Step
0.60
0.50
0.40
0.30
0.20
0.10

40.0
60.0
80.0
100.0
120.0
0.00

2.0 4.0 6.0 8.0 10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00 26.00 28.00 30.00 32.00 34.00 36.00 38.00 40.00
RC (x 10E - 6)

Note: The number at the end of each curve is the DAC clock frequency in MHz. 99063003
Figure 5: Peak-to-Peak Filter Noise as a Function of RC and Frequency (6-bit DAC)

Output Attenuation Figure 6 may be used in conjunction with Figure 3, Figure 4, or Figure 5
to choose the RC time constant that is optimum for a particular
By convention, the cutoff frequency of a low pass filter is defined as the application. All figures cover the same RC range.
half-power point. The cutoff frequency of the simple RC filter may be
expressed as: Figure 4 shows an RC value of 13.0 x 10-6 results in a peak-to-peak
noise voltage of 0.25V when a DAC clock frequency of 80 MHz is used
fC = 1/(2πτ) on a 8-bit DAC. From Figure 6, it can be determined that the filter cutoff
frequency for this RC value is about 12 KHz. If the expected output is
where:
essentially a DC level, e.g., a programmable voltage generator, then RC
fC is the filter cutoff frequency may be increased to reduce the clock noise. On the other hand, if the
τ is the filter time constant, RC. fundamental frequency of the analog output is high, or it has sharp
edges, then a lower RC may be needed. When determining the actual
The above equation was used to create Figure 6. component values, remember that R should be at least 2500 Ω.
The user may implement a more sophisticated filter if the simple RC filter
has inadequate cutoff or drive characteristics for the application.

6 XAPP154 September 23, 1999 (Version 1.1)

Implementation

Filter Cutoff Frequency vs. RC

30.00
27.50
25.00
22.50
20.00
Filter Cutoff Frequency (KHz)
17.50
15.00
12.50
10.00
7.50
5.00
2.50

2.0 4.0 6.0 8.0 10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00 26.00 28.00 30.00 32.00 34.00 36.00 38.00 40.00
RC (x 10E - 6)
99063001

Figure 6: Filter Cutoff Frequency as a Function of RC

Sampling Rate This section lists some of the ways this DAC can be used in real-world
applications.
To resolve each DACin sample to the full precision of a Delta-Sigma
DAC, the sample rate, i.e., the rate that DACin changes, must be less • Programmable Voltage Generator. A variable voltage between 0V
than or equal to 1/(2(MSBI+1)) of the CLK frequency. In some and VCCO can be generated with a granularity determined by the bus
applications, such as a programmable voltage source, this is not an width of DACin. In these applications, the voltage typically does not
issue. change quickly, so RC may be large to minimize noise.
• Virtex VREF Generator. This is a specific application of a
As DAC width and the desired sample frequency increases, it may not
be possible to meet the above criterion. In practice, the sample rate Programmable Voltage Generator. For some Virtex SelectIOTM
sometimes exceeds 1/(2(MSBI+1)) of the CLK frequency. Though this receivers standards, a reference voltage is required for each bank of
compromises precision at higher frequencies, it is often possible to get receivers. If a DAC is used to generate this voltage, VREF can be
satisfactory results. For example, the 16-bit audio DACs in a CD system dynamically changed to verify operating margins when conducting
would require a clock frequency of 2.9 GHz for full resolution of the system tests. See XAPP133 for more information on SelectIO.
highest frequencies. In practice, a much lower clock frequency is used. • Waveform Generator. Various analog waveforms, such as sine,
One reason this is acceptable is because the sensitivity of the human sawtooth, triangle, etc., can be created by sequentially feeding the
ear to noise becomes lower as the frequency increases. proper values to DACin. The values are normally pre-stored in

XAPP154 September 23, 1999 (Version 1.1) 7

 Conclusion
SRAM. Virtex Block SelectRAM+ is ideal for this purpose. See Since each DAC requires only a few CLBs and one output pin, many
XAPP130 for more information on Block SelectRAM+. DACs may be implemented in even the smallest Virtex FPGA.
• Sound Generator. Delta-Sigma DACs are widely used in sound When the same VCCO source is used for multiple DACs on the same
reproduction, speech synthesis, etc. Since the analog output is FPGA, the analog outputs will track each other very accurately. This is
changing rapidly, RC must be chosen with an acceptable trade-off important, for example, when three DACs are used to generate Red-
between noise and frequency response. Green-Blue color signals.
• RGB Color Generator. Although Delta-Sigma DACs are too slow to
directly generate Red-Green-Blue signals for a raster display, they Table 2 provides some typical resistor and capacitor values for 6-, 8-,
are applicable in some color generation systems that do not operate and 10-bit DACs. This table also lists the approximate maximum DAC
in real time. clock frequency for a Virtex XCV300-6. The parts cost per DAC is based
• Analog to Digital Conversion. This DAC may be used as a voltage on the following:
reference in an ADC. See XAPP155 for a complete discussion of this • Virtex Slice $0.03
application. • Resistor $0.015
• Capacitor $0.07

Table 2: Typical DAC Implementations

No. bits No. slices Max. Freq. Typical R Typical C Cost/DAC

6 4 223 MHz 3.3 KΩ 0.0047 µF $0.205

8 5 219 MHz 3.3 KΩ 0.0047 µF $0.235

10 6 215 MHz 6.8 KΩ 0.0047 µF $0.265

Conclusion Bibliography
The Delta-Sigma DAC is an example of how high speed FPGAs may be 1. “Analog Devices Data Converter Reference Manual, Volume I”, 1992
used in mixed-signal systems to minimize the number of components. 2. "High Performance Stereo Bit-Stream DAC with Digital Filter", R.
The speed and density of the Virtex family of FPGAs makes them ideal Finck, IEEE Transactions on Consumer Electronics, Vol. 35, No. 4, Nov.
for a wide range of analog signal generating and processing 1989.
applications.

Revision History
Date Revision # Activity
7/9/99 Version 1.0 Initial release
9/23/99 Version 1.1 Updated for Virtex-E designs

8 XAPP154 September 23, 1999 (Version 1.1)