Nic LD PDF

Digital Logic
+ Write the truth tables for, and draw the symbols for, 2-input OR, AND, NOR, and
NANO gates.
+ Write Boolean equations for logic circuits and draw logic circuits for Boolean
equations.
+ Use DeMorgan's first and second theorems to create equivalent circuits.
+ Understand the operation of AND-OR-INVERT gates and expanders.
A digital circuit having one or more input signals but only one output signal is called a gate. In Chapter 1, the
most basic gates-the NOT gate (inverter), the OR gate and the AND gate-were introduced. Connecting the
basic gates in different ways makes it possible to produce circuits that perform arithmetic and other functions
associated with the human brain (an ALU). Because they simulate mental processes, gates are often called
logic circuits. A discussion of both positive and negative logic leads to the important concept of assertion-
/eve/ logic.
Hardware description languages (HDL) are an alternative way of describing logic circuits. This uses a set
of textual codes that is machine (computer) readable. The concept is relatively new and is useful for design,
testing and fabrication of complex digital circuits. We'll have a soft introduction ofHDL towards the end of
this chapter. We'll learn it in detail in later part of this book introducing features relevant to each chapter.
2.1 THE BASIC GATES-NOT, OR, AND
Is an action right or wrong? A motive good or bad? A conclusion true or false? Much of our thinking involves
trying to find the answer to two-valued questions like these. Two-state logic had a major influence on Aristotle,
Digital Logic
who worked out precise methods for getting to the truth. Logic next attracted mathematicians, who intuitively
sensed some kind of algebraic process running through all thought.
Augustus De Morgan came close to finding the link between logic and mathematics. But it was George
Boole (1854) who put it all together. He invented a new kind of algebra that replaced Aristotle's verbal
methods. Boolean algebra did not have an impact on technology, however, until almost a century later. In
1938 Shannon applied the new algebra to telephone switching circuits. Because of Shannon's work, engineers
soon realized that Boolean algebra could be used to analyze and design computer circuits.
Three logic circuits, the inverter, the OR gate, and the AND gate, can be used to produce any digital
system. The function of each of these gates was introduced in Chapter 1. Let's look more closely at the
operation of each circuit and-also at their Boolean expressions.
The Inverter (NOT Gate)

Figure 2.1 is the symbol and truth table for an
inverter. In one truth table, the symbols Hand L are
used, while the binary numbers O and 1 are used .in
the other. The information in each table is identical,
however, since we know L = 0 and H = 1. In this
A-{>-Y
(a) (b)
W0 1
1 0
Y
text, both symbols are used, hence since there is no (a) Inverter symbol, (b) Truth
chance for confusion. You will find both symbols
tables
used in other texts, as well as in manufacturers' data
sheets. The important idea is that there are only two
possible voltage levels (low and high) associated
with a digital circuit. This fits nicely with the binary
number system, since it has only two values (0 and
1). This is often referred to as two-state operation. 7404
By definition, this is positive logic, since the higher
voltage level is assigned binary 1. Later in this
chapter, we will consider negative logic, where the
higher voltage level is assigned binary (zero).
Figure 2.2 shows the pinout diagram of a 7404 Pinoutdiagram of a 7404
hex inverter. This IC contains six inverters. After ap-
plying +5 V de (the supply voltage for all TTL devices) to pin 14 and grounding pin 7, you can connect any or
all inverters to other TTL devices. For instance, if you only need one inverter, you can connect an input signal
to pin 1 and take the output signal from pin 2; the other inverters can be left unconnected.
In Boolean algebra a variable can be either O or 1. The output Yofnot gate is always complement of input
A. In equation f01m
Y=notA 1.e. Y=A' sothat,ifA=O,Y=O'=l andif A=l,Y=l'=O
The truth tables in Fig. 2.1 illustrate signal levels that do not change with time. However,
almost all digital signals do in fact change with time, as illustrated by the waveforms in Chapter 1
(Sec. 1.2). Here are two examples that illustrate how to use the truth table information with signals that vary
with time.
A I-kHz square wave drives pin 1 of a 7404 (see Fig. 2.2). What does the voltage waveform
at pin 2 look like?
Digital Principles and Applications
Solution Figure 2.3a shows what you will see on a dual-trace oscilloscope. Assuming you have set the sweep
timing to get the upper waveform (pin I), then you would see an inverted square wave on pin 2.
If a 500-Hz square wave drives pin 3 of a 7404, what is the waveform on pin 4?
Solution Pins 3 and 4 are the input and output pins of an inverter (see Fig. 2.2). A giance at Fig. 2.3b shows the
typical waveforms on the input (pin 3) and output (pin 4) of a 7404. Again, the output waveform is the complement of
the input waveform, Because of two-state operation, rectangular wavefonns like this are the normal shape of digital
signals. Incidentally, a timing diagram is a picture of the input and output waveforms of a digital circuit. Examples of
timing diagrams are shown in Figs. 2.3a and b.
Pin 1 Pin 3
A B C D E F G H I A C E G I
Pin2 Pin4
A B C D E F G H I A C E G I
(a) (b)
Cfl F.i;:rI::)
OR Gates
An OR gate has two or more input signals but only A B y
one output signal. It is called an OR gate because 0 0 0
the output voltage is high if any or all of the input B~y 0 I I
voltages are high. For instance, the output of a 2-in- 1 0 I
1 l l
put OR gate is high if either or both inputs are high.
Figure 2.4a shows the logic symbol of a 2-input OR (a) (b)
gate and Fig. 2.4b its truth table.
(a) OR gate, (b) Truth table
In Boolean equation form
Y = A ORB. 1.e. Y = A + B
so that Y=O+O=O, Y=O+ I= 1, Y= I +O= I and Y= I+ l = 1.
The '+' sign here represents logic operation OR and not addition operation of basic arithmetic. Note that
in arithmetic 1 + 1 = 2 in decimal and l + 1 = l O in bi- A B C Y
nary number system (Table 1.1 of Chapter I). Binary
0 0 0 0
addition is discussed in detail in Chapter 6. 0 0 I l
0 1 0 I
Three Inputs Figure 2.5 shows a 3-input OR gate.
DA~ 0 l I l
The inputs are A, B, and C. When all inputs are low, Y C~y
is low. If A or B or C is high, Y will be high. The truth 0 0
table summarizes all input possibilities. In equation 0 1
form, the three input OR gate is represented as: Y = I 0
I 1
A+B+C.
(a) (b)
The truth table (Fig. 2.5b) allows us to check that
all input possibilities are included. Why? Because (a) Three-input OR gate,
every possibility is included when the input entries (b) Truth table
Digital Logic
follow a binary sequence. For example, the first ABC entry is 000, the next is 001, then 010, and so on, up to
the final entry of 111. Since all binary numbers are present, all input possibilities are included.
Incidentally, the number of rows in a truth table equals 2", where n is the number of inputs. For a 2-input
OR gate, the truth table has 22, or 4 rows. A 3-input OR gate has a truth table with 23, or 8 rows, while a
4-input OR gate results in 24, or 16 rows, and so on.
An OR gate can have as many inputs as desired. No matter how many inputs, the action of any OR gate
is summarized like this: One or more high inputs produce a high output.
logic Symbols Figure 2.6a shows the symbol for a 2-input OR gate of any design. Whenever you see this
symbol, remember the output is high if either input is high.
Shown in Fig. 2.6b is the logic symbol for a 3-input OR gate. Figure 2.6c is the symbol for a 4-input OR
gate. For these gates, the output is high when any input is high. The only way to get a low output is by having
all inputs low.
(a) (b) (c) (d)
OR gate symbols: (a) Two-input, (b) Three-input, (c) Four input,

(d) Twelve-input
When there are many input signals, it's common drafting practice to extend the input side as needed to
allow sufficient space between the input lines. For instance, Fig. 2.6d is the symbol for a 12-input OR gate.
The same idea applies to any type of gate; extend the input side when necessary to accommodate a large
number of input signals.
TTL OR Gates Figure 2.7 shows the pinout diagram of a 7432, a TTL quad 2-input OR gate. This digital
IC contains four 2-input OR gates inside a 14-pin DIP. After connecting a supply voltage of +5 V to pin 14
and a ground to pin 7, you can connect one or more of the OR gates to other TTL devices.
Timing Diagram Figure 2.8 shows an example of a timing diagram for a 2-input OR gate. The input
voltages drive pins 1 and 2 of a 7432. Notice that the output (pin 3) is low only when both inputs are low. The
output is high the rest of the time because one or more input pins are high.
Pin 1
B D F H
7432 Pin 2
A B C D E F G H I
Pin3 L L
A D E H I
GND
Pinout diagram of a 7432 Timing diagram
Work out the truth table for Fig. 2.9a.
Solution With two input signals (A and B), four input cases are possible: low-low, low-high, high-low, and high-
high. For convenience, let L stand for low and Hfor high. Then, the input possibilities are LL, LH, HL, and HH, as
listed in Fig. 2.9b. Here is what happens for each input possibility.
CASE l A is !ow and Bis low. With. both input voltages in the low state, each inverter has a high output This means
that the OR gate has a high output, the first entry of Fig. 2.9b.
CASE 2 A is low and B is high. With these inputs the upper inverter has a high output, while the lower inverter has
a low output. Since the OR gate still has a high input, the output Y is high.
CASE 3 A is high and B .is low. Now, the upper.inverter has a low output and the lower inverter has a high output
Again, the OR gate produces a high output, so that Y is high.
CASE 4 A is high and B is high. With both inputs high, each inverter has a low output. This time, the ORgate has
all inputs in the low state, so that Y is low, as shown by the final entry of Fig. 2.9b.
7404
2
A A B y
L L H
y L H H
H L H
B H H L
(a) {b)
Logic circuit and truth table of Example 2.3
Incidentally, the circuit of Fig. 2.9a uses only one-third of a 7404 and one-fourth ofa 7432. The other gates in these
digital ICs are not connected, which is all right because you don't have to use all of the available gates.
AND Gates
The AND gate has a high output only when all inputs are
A B Y
high. Figure 2.1 Oa shows a 2-input AND gate. The truth
table (Fig. 2.1 Ob) summarizes all input-output possibili- 0 0 0
0 1 0
ties for a 2-input AND gate. Examine this table carefully B~y
1 0 0
and remember the following: the AND gate has a high 1 l l
output only when A and B are high. In other words, the (a) (b)
AND gate is an all-or-nothing gate; a high output occurs
only when all inputs are high. This truth table uses Is and (a) Two-input AND gate,
Os, where 1 = Hand O = L. (b) Truth table
In Boolean equation fonn
Y =A AND B, i.e. Y=A.B or Y=AB
so that, Y = 0.0 = 0, Y = 0.1 = 0, Y = 1.0 = 0 and Y = 1.1 = 1
The '.' sign here represents logic AND operation and not multiplication operation of basic arithmetic
though the result are same for both.
Digital Logic
Three Inputs Figure 2.11 a shows a 3-input AND A B C y

gate. The inputs are A, B, and C. When all inputs are 0 0 0 0
low, Y is low. If even one input is low, Y is in the low 0 0 I 0
state. The only way to get a high output is to raise all 0 I 0 0
inputs to the high state ( +5 V) The truth table (Fig. 0 I I 0
C~y
2.11 b) summarizes all input-output possibilities. In 0 0 0
equation form, the three input AND gate is represented 0 I 0
as: Y=A.B.C=ABC. 1 0 0
I I I
Logic Symbols Figure 2.12a shows the symbol (a) (b)
for a 2-input AND gate of any design. Shown
in Fig. 2.12b is the logic symbol for a 3-input (a) Three-input AND gate,
AND gate. Figure 2.12c is the symbol for a 4- (b) Truth table
input AND gate. Remember: For any of these
gates, the output is high only if all inputs are high. As before, it's common drafting practice to
extend the input sides when there are many input signals. For instance, Fig. 2.12d is the symbol for a
12-input AND gate.
(a) (b) (c) (d)
AND gate symbols: (a) Two-input, (b) Three-input, (c) Four-input,

(d) Twelve-input
TTL AND Gates Figure 2.13 shows the pinout diagram of a 7408, a TTL quad 2-input AND gate. This
digital IC contains four 2-input AND gates. After connecting a supply voltage of +5V to pin 14 and a ground
to pin 7, you can connect one or more of the AND gates to other TTL devices. TTL AND gates are also
available in triple 3-input and dual 4-input packages. (See Appendix 3 for pinout diagrams.)
Timing Diagram Figure 2.14 shows an example of a timing diagram for a 2-input AND gate. The input
voltages drive pins 1 and 2 of a 7408. Notice that the output (pin 3) is high only when both inputs are high
(between C and D, G and H, etc.). The output is low the rest of the time.
Pin I
B F
7408 Pin2
A B C D F G H I
Pin3 H
C D G H
GND
Pinout diagram of a 7408 Timing diagram
Work out the truth table for Fig. 2.15a.
A A B A' B' Y=A~B'

0 0 1 I 1
y 0 I 1 0 0
r 0 0 1 0
1 1 0 0 0
(a) (b)
logic circuit and truth table of Example 2.4
Solution We get the final truth table here in slightly different way. Consider, one logic gate at as shown in
Fig. 2:15b; The NOT gate connected to A gives A I at its output and is shown in column 3. The NOT gate connected to
B gives B' at its output and is shown in column 3. Finally, the 4'" column shows OR operation on column 3and 4 to
give the final output Y. Here is what happens for each input possibility.
CASE 1 A is low and B is low. With both input voltages in the low state, each inverter has a A B y
high output This means the AND gate has a high output, the first entry of Fig. 2.16.
L L H
CASE 2 A is low and B is high. With these inputs the upper inverter has a high output, while L H L
the lower inverter has a low output Since the AND gate produces a low output, Y is low. H L L
CASE 3 A is high and B is low. Now, the upper inverter has a low output and the lower H H1L
inverter has a output Again, the AND gate produces a low output, so Y is low.
CASE 4 A is high and B is high. With both inputs high, each inve1ter has a low output Again,
the AND gate has a low as shown bythe final.entry of Fig. 2.16.
Note that input-output relations described i11 Fig. 2.15b and Fig. 2.16 are same.
What is the Boolean equation for the logic circuit of Fig. 2. l 7a?
Solution This circuit is called an AND-OR network because input AND gates drive an output OR gate~
The intermediate outputs are
=AB =CD
The :final output is
f8 Y3 +Y,,
Y=AB+CD
An equation in this form is referred to as a sum-ofproducts equation. AND-OR networks always produce sum-of-
products equations.
Write the Boolean equation for Fig. 2.17b.
Solution Thislogic circuit u,ic.,u«;u an OR-AND network because input OR gates drive an output AND gate. The
intem1ediate outputs are Y8 =A and Y11 = C + D.
Digital Logic
The :final output is
or B)(C+D)
A
B
y y
C
D
(a) AND-OR, {b) OR-AND network
As shown in this equation, parentheses may be used to indicate a logical product (ANDing), Also notice that the final
answer is a product of sums. OR-AND networks always produce product-of-sums equations.
What is the logic circuit whose Boolean equation is

Y= ABC+ABC
Solution This is ,i ~um-of-products equati9n with some of the inputs in complemented fonn. Figure.2.18a shows an
.AND-OR circuit with the foregoing Boolean equation. upper AND gate. produces a logical product of
=ABC
The lower AND gate proi:luces
7411 7411
A A -----~•.:;:,o.----2,,.t__
B B ----,-+---------+ 7432
C 13
y
3
A
3 4 4
B
5
C
(a) (b)
(a) Intermediate, (b) Final logic circuit of Example 2.7
I. A system in which H= 1 and L = 0 is (positive, negative) logic.

2. A gate whose output is H if any input is His an gate.
3. A gate whose output is H only when all inputs are His an ____ gate.
The final output therefore equals the sum of the f 12 and Y6 products:
Y= ABC+ABC
The complemented inputs A and B may be produced by other circuits (discussed later). Alternatively,
inverters on the A and B input lines may produce the complemented variables, as shown in
Fig. 2.I8b.
4. Write an expression for an inverter, or NOT gate equivalent to Y = not A.

5. Write a Boolean expression for an OR gate having A and Bas inputs and Yas the output.
6. Write the Boolean expression for an AND gate with A and B as inputs and Y as the output.
This example illustrates one method oflogic design. Whenever you are given a sum-of-products equation,
you can draw the corresponding AND-OR network using AND gates to produce the logical products and an
OR gate to produce the sum.
2.2 UNIVERSAL LOGIC GATES-NOR, NANO
In the previous section we have seen how AND, OR and NOT gates can be connected together to realize
any logic function. Here, we address an interesting question. Is it possible to use only one type of gate for
this purpose? If possible, one needs to procure only one type of gate for his design. And more importantly,
fabrication of Integrated Circuit that perfonns a logic operation becomes easier when gate of only one kind
is used. Gates, which can perform this task, are called universal logic gates. Clearly, basic gates like AND,
OR and NOT don't fit into this category for the simple reason that conversion among themselves itself are not
possible. As for example, one cannot gate OR operation by using any number or combination of AND gates.
In this section, we discuss two universal logic gates NOR and NAND.
NOR Gates
The logic circuit of Fig. 2.19a used to be called a NOT-OR gate because the output is
Y=A+B
Read this as "Y equals NOT A ORB" or "Y equals the complement of A ORB." Because the circuit is an
OR gate followed by an inverter, the only way to get a high output is to have both inputs low, as shown in
the truth table of Table 2.1.
NOR Gate Symbol

The logic circuit of Fig. 2.19a has become so popular that the abbreviated symbol of Fig. 2.19b is used for
it. The bubble (small circle) on the output is a reminder of the inversion that takes place after the ORing.
Furthermore, the words NOT-OR are contracted to the word NOR. So from now, we will call the circuit a
NOR gate and will use the symbol of Fig. 2.19b. Whenever you see this symbol, remember that the output is
NOT the OR of the inputs. With a NOR gate, all inputs must be low to get a high output. If any input is high,
the output is low.
Digital Logic
~=D-{)»-r ~=[>-r ~=§-r

(a) (b) (c)
2
3
5 4
7402 6
8 10
9
11 13
7 12
(GND)
(d) (e)
NOR logic gate
Figure 2.19c shows the new IEEE rectangular symbol for the NOR Gate
NOR gate. The small triangle on the output is equivalent to the
bubble used on the standard symbol. The indicator~ inside the box A B y
means "if one or more of the inputs are high, the output is high." 0 0 l
The 7402 is a quad 2-input NOR gate in a 14-pin DIP as illus- 0 I 0
trated in Fig. 2.19d. The new rectangular symbol for the 7402 is l 0 0
shown in Fig. 2.19e. l 0
Bubbled AND Gate

Figure 2.20a shows inverters on the input lines
of an AND gate. This logic circuit is often drawn
in the abbreviated form shown in Fig. 2.20b.
The bubbles on the inputs are a reminder of the (a)
inversion that takes place before the AND operation.

We will refer to the abbreviated drawing of
Fig. 2.20b as a bubbled AND gate. We have already (b)
analyzed this circuit in Example 2.4 and obtained

(a) AND gate with inverted
its truth table as shown in Fig. 2.15b. We find that
inputs, (b) Equivalent symbol
output Y and inputs A, B are identical for bubbled
AND gate and NOR gate. Therefore, these two circuits are equivalent and thus interchangeable. Given any
logic circuit with NOR gates, we can replace it by bubbled AND gates and converse is also true.
De Morgan's First Theorem

The Boolean equation for Fig. 2.19b is
Y=A+B
Y=AB
The first equation describes a NOR gate, and the second equation a bubbled AND gate. Since the outputs
are equal for the same inputs, we can equate the right~hand members to get
A+B = AB (2.1)
This identity is known as De M01gan ~, first theorem. In words, it says the complement of a sum
equals the product of the complements. This can also be proved by comparing the truth tables shown
in Fig. 2.4(b) and NOR gate truth table of Table 2.1. A similar exercise that compares truth tables of
three input NOR gate and three input bubbled AND gate show they are identical and we can write,
(A+ B + C)' = A'B'C'. Note that this equivalence can be extended to gates or circuits for larger number of
inputs, too.
Universality of NOR Gate

Figure 2.21 shows how all other logic gates can be obtained from NOR gates. To get a NOT gate we tie
inputs of NOR gate together (Fig. 2.21 a) so that there is only one input to the circuit. If input is 0, then both
the inputs to NOR gate are 0. Following NOR gate truth table (Table 2.1) we see output now is l. Similarly,
if input is 1, both the inputs to NOR gate are 1 that gives output 0. Therefore output of circuit, shown in Fig.
2.2 la is complement of its input and thus gives NOT operation.
A~A;~A.+B
B
(a) (b) (c)
Universality of NOR gate (a) NOT from NOR, (b) OR from NOR,
(c) AND from NOR
Figure 2.21 b shows how to get OR circuit using only NOR gates. The first NOR gate performs usual NOR
operation while second NOR gate performs as NOT gate and inverts the NOR logic to OR.
To understand how we get AND circuit using only NOR gates (Fig. 2.21c) let us refer to example 2.3. The
configuration is similar except the output there is generated from OR and here from NOR and of course the
NOT gates are replaced by NOR equivalent. Since NOR gate is NOT operation followed by OR we invert the
output of example 2.3, shown in Fig. 2.9b to get output of this circuit. Thus output of circuit in Fig. 2.2 lc is
high only when both the inputs are high and it functions like an AND gate.
The above equivalences can be proved simply, by applying Boolean theorems and we'll discuss those
theorems in next chapter. Since, we can perform all the Boolean operations using only NOR gates it is termed
as universal logic gate.
Eye of the Beholder

Which brings us to a principle. Truth tables, logic circuits, and Boolean equations are different ways of
looking at the same thing. Whatever we learn from one viewpoint applies to the other two. If we prove that
truth tables are identical, this immediately tells us the co1Tesponding logic circuits are interchangeable, and
their Boolean equations are equivalent. When analyzing, we generally start with a logic circuit, construct
Digital Logic
its truth table, and summarize with the Boolean equation. When designing, we often startwith a truth table,
generate a Boolean equation, and arrive at a logic circuit.
A 7402 is a quad 2-input NOR gate. This TTL IC has four 2-input NOR gates in a 14-pin DIP
as shown in Appendix 3. What is the Boolean equation for the output of Fig. 2.22a?
Solution The AND gates produce AB and CD. These are ORed to get AB+ CD. The final inversion gives
Y=AB+CD
The circuit of Fig. 2.22a is known as anAND-OR-INVERT network because it starts withANDing, follows with
ORing, and ends with INVERTing.
The AND-OR-INVERT network is available as a separate TTL gate. For instance, the 7451 is a dual 2-input
2-wide AND-OR-INVERT gate, meaning iwo networks like Fig. 2.22a in a single 14-pin TTL package. Appendix
3 shows the pinout diagram. Figure 2.22b shows how we can use half of a7451 to produce the same output as the
circuit of Fig. 2.22a.
7408 7451
A A
B B
y y
C C
D D
(a) (b)
AND-OR-INVERT network
Prove that Fig. 2.23c is logically equivalent to Fig. 2.23a.
Solution De Morgan's first theorem says we can replace the final NOR gate ofFig. 2.23a by a bubbled AND gate to
get the equivalent circuit of Fig. 2.23b. If you invert a signal twice, you get the original signal back again. Put another
way, double inversion has no effect on the logic state; double invert a low and you still have a low; double-invert a
high and.you still have a high. Therefore, each double inversion in Fig. 2.23b (a pair of bubbles on the same signal
line) cancels out, leaving the simplified circuit of Fig. 2.23c. Therefore, Fig. 2:23a and Fig. 2.23c are equivalent or
interchangeable.
Why would anyone want to replace Fig, 2.23a by 2.23c? Suppose your shelves are full of AND gates and OR
gates .. Ifyou have just run out of NOR gates and you are trying to build a NOR-NOR network like Fig. 2.23a, you
can connect the OR-AND circuit of Fig. 2.23c because it produces the same output as the original circuit. In general,
this idea applies to any circuit that you can rean-ange with De Morgan's theorem. You can build whichever equivalent
circuit is convenient.
A A
B B
y y y
C
D
(a) (b) (c)
Equivalence among logic circuits: Example 2.9

What is the truth table for the NOR-NOR circuit of Fig. 2.23a?
Convert Table 2.2 into a timing diagram.
Solution ... In tabl~ 2.2, IDflltD change;, statesfon~ach entry, input G'changes states every otl.ler entry, inpufB every
trutb
fourth entry, andjn.putA every eighth. eµtry. figure 2.24 shows how to draw the table in thef~llll ~f a tinli:11g
diagram. First, notice jhalthe transitions on i~put D are l, 2, 3, and. so on. Notic~. that input D. changes. state5 each
tr.lt:tsition, inp~tC eye137.?thertransition, input B . every fourth transition, and.illpµtA~very . eighthtransition.. ·Toagree
wit~ Jhe tl1.Ith tllbJf,.Qutput Yis low up to transition5, high between 5 and. 8; low between 8 and 9, and so forth.
D
0
l
0
1
0
1
0
1
0
1
0
1
0
1
0
Digital Logic
NANO Gates
Originally, the logic circuit of Fig. 2.25a was called NOT-AND gate because the output is
Y=AB
Read this as "Y equals NOT A AND B" or "Yequals the complement of A AND B." Because the circuit is
an AND gate followed by an inverter, the only way to get a low output is for both inputs to be high, as shown
in the truth table of Table 2.3.
;D-{>-y ;u-y ~=B-y

(a) (b) (c)
1
3
2
6
5
7
9
8
IO
12
14
13
(e)
NANO logic gate
NANO-Gate Symbol
The logic circuit of Fig. 2.25a has become so popular that the
abbreviated symbol of Fig. 2.25b is used for it. The bubble on NANO Gate
the output reminds us of the inversion after the ANDing. Also, y
the words NOT-AND are contracted to NAND. Whenever you
see this symbol, remember that the output is NOT the AND of 0 1
1 l
the inputs. With a NAND gate, all inputs must be high to get a
0 1
low output. If any input is low, the output is high.
0
Figure 2.25c shows the new IEEE rectangular symbol for the
NAND gate. The small triangle on the output is equivalent to the bubble used on the standard symbol. The
indicator"&" inside the box means "the output is high only when all inputs are high."
The 7400 is a quad 2-input NAND gate in a 14-pin DIP as illustrated in Fig. 2.25d. The new rectangular
symbol for the 7402 is shown in Fig. 2.25e.
Bubbled OR Gate
Figure 2.26a shows inverters on the input lines of an OR gate. The circuit is often drawn in the abbreviated
form shown in Fig. 2.26b, where the bubbles represent inversion. We will refer to the abbreviated drawing of
Fig. 2.2b as a bubbled OR gate. We have already analyzed this circuit in Example 2.3 and obtained its truth
table in Fig. 2.9b. We see that output Y and inputs A

A, Bare identical for bubbled OR gate and NAND
y
gate. Therefore, these two circuits are equivalent
and thus interchangeable. Given any logic circuit B
with NOR gates, we can replace it by bubbled AND (a)
gates and converse is also true.
De Morgan's Second Theorem

~=D-r
(b)
(a) OR gate with inverted
Y=AB
inputs, (b) Equivalent symbol
Y=X +B
The first equation describes a NAND gate, and the second equation a bubbled OR gate. Since the outputs
are equal for the same inputs, we can equate the right-hand members to get
AB= A +B (2.2)
This identity is known as De Morgans second theorem. It says the complement of a product
equals the sum of the complements. This can also be proved by comparing the truth tables shown
in Fig. 2.3(b) and NAND gate truth table of Table 2.2. A similar exercise that compares truth tables
of three input NAND gate and three input bubbled OR gate show they are identical and we can write,
(A.B.C)' =A'+ B' + C'. Note that this equivalence can be extended to gates or circuits with any number of
inputs.
Universality of NANO Gate

Figure 2.27 shows how all other logic gates can be obtained from NAND gates and why it is called a universal
logic gate. Figure 2.27a shows how we tie inputs ofNAND gate together (as we had done in case of NOR
gate) to get a NOT gate that has only one input. If input is 0, then both the inputs to NAND gate are. 0.
Following NAND gate trnth table (Table 2.3) we see output now isl. Similarly, if input is 1, both the inputs
to NAND gate are 1 that gives output 0. Therefore output of circuit, shown in Fig. 2.27a is complement of its
input and thus gives NOT operation.
Figure 2.27b shows how we get AND circuit using only NAND gates. The second NAND gate performs
as a NOT gate and inverts the NAND logic offirst NAND gate to AND logic.
A·~A;~A.B
B
(a) (b) (c)
Universality of NAND gate: (a) NOT from NAND, (b) AND from NAND,
(c)OR from NAND
Digital Logic
==c=>- =D- ¢=}
(a)
=D- =r>- ¢=}
(b)
=D- ¢=}
=[)- =CJ- =r=>- ¢=}
{c) (d)
Useful logic equivalences
To obtain OR logic using NAND gate we compare Fig. 2.27c circuit with Fig. 2.15a. The later gives NOR
logic and has AND gate at output. The present circuit has NAND gate at output and thus inverts the output
of previous circuit, from NOR to OR.
TTL NANO Gates

The NAND gate is the backbone of the 7400 TTL series because most devices in this family are derived from
it. Because of its central role in TTL technology, the NAND gate has become the least expensive and most
widely used TTL gate. Furthermore, the NAND gate is available in more configurations than other gates, as
shown in Table 2.4. Notice that the NAND gate is available as a 2-, 3-, 4-, or 8-input gate. The other gates
have fewer configurations, with the OR gate available only in 2-input fonn.
Standard TTL Gates
Type Quad 2-lnput Triple 3-lnput Dual 4-lnput Single 8-lnput

NAND 7400 7410 7420 7430
NOR 7402 7427 7425
AND 7408 74ll 7421
OR 7432
Prove that Fig. 2.29c is logically equivalent to Fig. 2.29a.
A
B
y
C
D
(a)
Equivalence of logic gates: Example 2.12
Solution Ile.Mor~an's second theorem says we can replace the final NAND gate of Fig. 2.29a by a bubbled OR
gate to getthe equivalent circuit ofFig. 2.29b. Each double inversion in Fig. 2.29b cancels out, leaving the simplified
circuit of Fig. 2.29c .. Therefore, Figs. 2.29a and 2.29c are equivalent
Incidentally, most people find Fig. 2.29b easy to analyze because they learn to ignore the double inversions and
see only the simplified AND-OR circuit of Fig. 2.29c. For this reason, if you build a NAND-NAND Network like
Fig. 2.29a, you can draw it like Fig. 2.29b. Anyone who sees Fig. 2.29b on a schematic diagram will know it is two
input NAND gates driving an output NAND gate. Furthermore, when troubleshooting the circuit, they can ignore the
bubbles and visualize the easy-to-analyze AND-OR circuit of Fig. 2.29c.
What is the truth table for the NAND-NAND circuit of Fig. 2.29a?
Solution Let us analyze the equivalent circuit of Fig. 2.29c because it is simpler to work with. Table 2.5 lists every
possibility starting with all inputs low and progressing to all inputs high. By analyzing each input possibility, we can
determine the resulting output Fo.r fostance, when all inputs llt'e 1owin Fig. 2,29c, ho.th AND gates have low outputs,
so the OR gate produces a low output. This is the first entry of Table 2.5. Proceeding like this, we can arrive at the
output for the remaining possibilities ofTable2.5,
Show a timing diagram for the NAND-NAND circuit of Fig. 2.29a.
Solution All you have to do is convert the low-high states of Table 2.5 into low-high waveforms like
D
First, notice that. the. traJJ.sitions .on. input a.re. numbered l, 2, 3, and S() on. Input D chan~es states each .transition,
input C every other transition, input 8 ~very fourth transition, and input A every eighth transiti~n. To agree with the
truth table, output Yis low up to transition 3,.highbetween 3 and 4, lowl)etween 4 and 7, and so forth.
NANO-NANO Circuit
A 8 C D r.
0 0 0 0 0
0 0 0 I 0
0 0 l 0 0
0 0 1 I 1
0 I 0 0 0 A
0 I 0 1 0
0 1 l 0 0
0 I 1 I l
I 0 0 0 0
1 0 0 I 0
1 0 l 0 0
l 0 1 1 1
l 0 0 l
1 0 I I
1 1 0 1
l l 1 Timing diagram
l 0. Write the Boolean expression for a 2 input NANJJ gate.

11. 'Write De}forgan's second theorem. . < .•·
12. Wha~ symbol is used inside the IEijErectangular box to define a. NANI) gate?
Digital Logic
2.3 AND-OR-INVERT GATES
Figure 2.31a shows an AND-OR circuit. Figure 2.31b shows the De Morgan equivalent circuit, a NAND-
NAND network. In either case, the Boolean equation is
Y=AB+CD
A A A
B B B
y y y
C C C
D D D
(a) (b) (c)
(a) AND-OR circuit, (b) NANO-NANO circuit, (c) AND-OR-INVERT circuit
Since NAND gates are the preferred TTL gates, we would build the circuit of Fig. 2.31 b. As you know,
NAND-NAND circuits like this are important because with them you can build any desired logic circuit.
TTL Devices
AND-OR circuits are not easily derived from the basic NAND-gate design. But it is easy to get an AND-
OR-INVERT circuit as in Fig. 2.3 lc. A variety of circuits like this are available as TTL chips. Because of the
inversion, the output has the equation shown below.
Y= AB+CD (2.3)
Table 2.6 lists the AND-OR-INVERT gates available
AND-OR-INVERT Gates
in the 7400 series. In this table, 2-wide means two AND
gates across, 4-wide means four AND gates across, and Device Description
so on. For instance, the 7454 is a 2-input 4-wide AND- 7451 Dual 2-input 2-wide
OR-INVERT gate as in Fig. 2.32a; each AND gate has 7454 2-input 4-wide
two inputs (2-input), and there are four AND gates (4- 7459 Dual 2-3-input 2-wide
wide). Figure 2.32b shows the 7464; it is a 2-2-3-4-input 7464 2-2-3-4-input 4-wide
4-wide AND-OR-INVERT gate.
Connecting the output of a 2-input 2-wide AND-OR-INVERT gate to an inverter will give us the same
output as an AND-OR circuit.
(a) (b)
Examples of AND-OR circuits

Expandable AND-OR-INVERT Gates

The widest AND-OR-INVERT gate available in the 7400 series is 4-wide. What do we do when we need a
6- or 8-wide circuit? One solution is to use an expandable AND-OR-INVERT gate.
Figure 2.33 shows the logic symbol for an expandable AND-OR-INVERT gate. There are two additional
inputs, labeled bubble and arrow. Table 2.7 lists the expandable AND-OR-INVERT gates in the 7400 series.
A
B
y Expandable AND-OR-IN-
C VERT Gates
D
Device Description
Bubble----~ 7450 Dual 2-input 2-wide
Arrow - - - - - ~ 7453 2-input 4-wide
7455 4-input 2-wide
Expandable AND-OR-INVERT gate
Expanders
What do we connect to the arrow and bubble inputs of an expandable gate? We connect the output of an ex-
pander as in Fig. 2.34a. Connect bubble to bubble and arrow to arrow.
Visualize the outputs of Fig. 2.34a connected to the arrow and bubble inputs of Fig. 2.33. Figure 2.34b
shows the logic circuit. This means that the expander outputs are being ORed with the signals of the AND-
OR-INVERT gate. In other words, Fig. 2.34b is equivalent to the AND-OR-INVERT circuit ofFig. 2.34c.
y
~Bubble
=L.__;- Arrow
(a) (b)
(c) (d)
(a) Expander, (b) Expander driving expandable AND-OR-INVERT gate, (c) AND-
OR-INVERT circuit, (d) Expandable AND-OR-INVERT with two expanders
Digital Logic
We can connect more expanders. Figure 2.34d shows two expanders driving the expandable gate. Now we
have a 2-2-4-4-input 4-wide AND-OR-INVERT circuit.
The 7460 is a dual 4-input expander. The 7450, a dual expandable AND-OR-INVERT gate, is designed
for use with up to four 7460 expanders. This means that we can add two more expanders in Fig. 2-34d to get
a 2-2-4-4-4-4-input 6-wide AND-OR-INVERT circuit.
13. When we speak ofan AND-OR-INVERT gate, what is the meaning of2--wide?
14. What is the purpose of using an expander with an AND-OR..JNVERT gate?
2.4 POSITIVE AND NEGATIVE LOGIC
Up to now, we have used a binary O for low voltage and a binary 1 for high voltage. This is called positive
logic. People are comfortable with positive logic because it feels right. But there is another code known as
negative logic where binary O stands for high voltage and binary 1 for low voltage. Even though it seems
unnatural, negative logic has many uses. The following discussion introduces some of the terminology and
concepts for both types of logic.
Positive and Negative Gates

An OR gate in a positive logic system becomes an AND gate in a negative logic system. Why? Look at the
gate of Fig. 2.35. We have been calling it an OR gate. This is correct, provided we are using positive logic.
Table 2.8 shows the tn1th for the gate of Fig. 2.35, no matter what you call it. That is, if either input is high
in Fig. 2.35, the output is high.
Positive OR
A
Low Low
Negative AND Low High
High Low
Meaning ofsymbol depends on whether
High High
you use positive or negative logic
In a positive logic system, binary O stands for low and binary 1 for high. So, we can convert Table 2.8
to Table 2.9. Note that Y is a 1 if either A or B is 1. This sounds like an OR gate. And it is, because we are
using positive logic. To avoid ambiguity, we can call Fig. 2.35 a positive OR gate because it performs the OR
function with positive logic. (Some data sheets describe gates as positive OR gate, positive AND gate, etc.)
In a negative logic system, binary 1 stands for low and binary O for high. With this code, we can convert
Table 2.8 to Table 2.10. Now, watch what happens. The output Y is a 1 only when both A and B are 1. This
sounds like an AND gate! And it is, because we are now using negative logic. In other words, gates are
defined by the way they process the binary Os and 1s. If you use binary 1 for low voltage and binary O for
high voltage, then you liave to refer to Fig. 2.35 as a negative AND gate.
As you see, the gate of Fig. 2.35 always produces a high output if either input is high. But what you call
it depends on whether you see positive or negative logic. Use whichever name applies. With positive logic,
call it a positive OR gate. With negative logic, call it a negative AND gate.
0
0 0
In a similar way, we can show the truth table of other gates with positive or negative logic. By analyzing
the inputs and outputs in terms of Os and ls, you find these equivalences between the positive and negative
logic:
Positive OR H negative AND
Positive AND H negative OR
Positive NOR H negative NAND
Positive NAND H negative NOR
Table 2.11 summarizes these gates and their definitions ill terms of voltage levels. These definitions are
always valid. If you get confused from time to time, refer to Table 2.11 to get back to the ultimate meaning
of the basic gates.
Voltage Definitions of Basic Gates
·•· ··.·· Gate ·. . . •

Definition
.•.
J:>ositivl'l O!Vn,egatjveAND Output is high if any input is high .
.E'ositive AND/negative OR Output is high when all inputs are high.
Positive NOR/negative NAND Output is low if any input is high.
P?sitiye NAND/negative-NOR Output is low when all inputs are high.
Assertion-level logic
Why do we even bother with negative logic? The reason is related to the concept of active-low signals. For
instance, the 74150 multiplexer has an active-low input strobe; this input turns on the chip only when it is low
(negative true). This is an active-low signal; it causes something to happen when it is low, rather than high.
As another example, the 74154 decoder has 16 output lines; the decoded output signal is low (negative true).
In other words, all output lines have a high voltage, except the decoded output line. Besides TTL devices,
microprocessor chips like the 8085 have a lot of active-low input and output signals.
Many designers draw their logic circuits with bubbles on all pins with active-low signals and omit bubbles
on all pins with active-high signals. This use of bubbles with active-low signals is called assertion-level
logic. It means that you draw chips with the kind of input that causes something to happen, or with the kind
of output that indicates something has happened. If a low input signal turns on a chip, you show a bubble on
that input. If a low output is a sign of chip action, you draw a bubble on that output. Once you get used to
assertion-level logic, you may prefer drawing logic circuits this way.
One final point. Sometimes you hear expressions such as "The inputs are asserted" or "What happens when
the inputs are asserted?" An input is asserted when it is active. This means it may be low or high, depending
on whether it is an active-low or active-high input. For instance, given a positive AND gate, all inputs must
be asserted (high) to get a high output. As another example, the STROBE input ofa TTL multiplexer must be
Digital Logic
asserted (low) to turn on the multiplexer. In short, you can equate the word assert with activate. You assert,
or activate, the inputs of a gate or device to get something to happen.
Here are some ideas that you should try to remember:

1. Positive true always represents a high voltage, and negative true always represents a low
voltage.
2. If possible, draw basic gates with bubbles on active-low signal lines.
3. When a signal is active-low, use an overbar as a reminder that the signal voltage is negative true
when the underlying statement is true.
(a) The number stored in a register may be zero (all bits low). Show how to detect this condition.
(b) What change in (a) will detect presence of the word 10110101 in the 8-bit register?
Solution
a
{a) Figure 236 shows design using assertion-level logic. The bits go to a bubbled AND gate (the Satlle as
positive
NOR gate). When all the bits are low, output ZERO is high. Because ofthe inverter, the final output ZERQis
a~tive-lo~,Therefore, wheil th~ SUfil is zero, ZERO isnegativ7 true.
Some of the bubbles .at the. inp~tofthebub.bled AND gate need to be removed.These are
code word where '1' is J>rese11t, specifically S7 , S5 , S4 , S2 and S0 •
Register
Assertion-level logic diagr.im ,showing the detectio., of zero and mir:ms

accumulator contents
What isne~ative l?gic?

What is meant assertion-level logic?
2~5 INTRODUCTION TO HOL
In this section, we introduce an interesting development in the field of hardware design. This is textual
description of a digital circuit. Though we have already described hardware, can there be a language which
is more crisp and more importantly, machine-readable? The advantage of course, is to be able to (i) describe
a large complex design requiring hundreds of logic gates in a convenient manner, in a smaller space, (ii) use
software test-bench to detect functional error, if any, and correct it (called simulation) and finally, (iii) get
hardware implementation details (called synthesis). Hardware Description Language, more popular with its
acronym HDL is an answer for that.
Currently, there are two widely used HDLs-Verilog and VHDL (Very high speed integrated circuit
Hardware Description Language). Verilog is considered simpler of the two and is more popular. However,
both share lot of common features and it is not too difficult to switch from one to the other. In this book, we'll
deal with Verilog and shall discuss it over a span of number of chapters by introducing features relevant to
that chapter. We expect by the time you finish Chapter 11, you'll have reasonable knowledge about HDL to
deal with any digital logic design problem. We discuss target hardware devices on which HDL code can be
directly exported in Section 13.6 of Chapter 13.
Verilog HDl
Verilog as a hardware descriptionlanguage has a small history. Introduced in 1980, primarily as a simulation
and verification tool by Gateway Design Automation, it was later acquired by Cadence Data Systems. Put to
public domain in 1990, it gained popularity and is now controlled by a group of companies and universities,
called Open Verilog International. The reader with an exposure to any programming language like C will find
it relatively easier to learn Verilog or any HDL.
Describing Input/Output In any digital circuit, we find there are a set of inputs and a set of outputs. Often
termed as ports, the relationship between these input and outputs are explained within the digital circuit.
To design any circuit that has say, three inputs a, b, c and two outputs say, x, y as shown in Fig. 2.37 the
corresponding Verilog code can be written as shown next.
module testckt(x,y,a,b,c); //module name with port list
input a,b,c; //defines input ports

a
output x,y; //defines output ports
X
b testckt //module body begins next describing logic relation

y
C
//module body ends

endmodule
Input/output definition in Verilog HDL for logic circuit described within

black-box testckt
Note that, module and endmodule written in bold are keywords for Verilog. A module describes a design
entity with a name or identifier selected by user (here, testckt) followed by input output port list. This entity if
used by another then arguments (i.e. ports) are to be passed in the same order as it appears here. The symbol
'//' is used to put comments and improve readability for a human but not used by the machine, i.e. compiler.
The module body describes the logic within the black box which acts on the inputs a, b, c and generates
outputx,y. Observe, where semicolon';' is used and where not to end a statement, e.g. endmodule in above
code does not end with semicolon.
Digital Logic
Writing Module Body There are three different models of writing module body in Verilog HDL. Each
one has its own advantage and suited for certain kind of design. We start with structural model by example of
two-input OR gate described in Fig. 2.4a.
module or_gate {A, B, Y);

input A, B; / / defines two input port
output Y; / / defines one output port
o:r (Y,A,B); te declaration with predefined keyword
logic OR, is optional user defi.ned
encbnodule
Verilog supports predefined gate level primitives such as and, or, not, nand, nor, xor, xnor etc. The
syntax followed above can be extended to other gates and for 4 input OR gate itis as given next,
or (output, input 1, input 2, input 3, input 4)
For NOT gate, not (output, input)
Note that, Verilog can take up to 12 inputs for logic gates. Comments when extends to next line is written
within /* ..... */. Identifiers in Verilog are case sensitive, begin with a letter or underscore and can be of any
length.
Let us now look at description of a logic circuit shown in Fig. 2.17 a that has 4 inputs and 1 output. The
inputs are fed to two 2-input AND gate. AND gate outputs are fed to a 2-input OR gate to generate final
output. The verilog code for this is given below. Note that, we define two intermediate variables and_opl
and and_op2 representing two AND gate outputs through keyword wire. Wire represents a physical wire in
a circuit.
module fig2_24a(A,B,C,D,Y);
input A,B,C,D;
output Y;
wire and_opl, and_op2;·
and gl(arid_opl,A,
and g2(arid_op2,C,D); // g2 represents lower A.ND
or g3(Y,and_opl,and_op2); // g3 represents the OR gate
encbnodule
One can see that structural model tries to replicate graphi- testckt
cal layout design of a logic circuit. It does not matter if or
statement in above example is written before and statements. X
This is as if one draws or collllects the OR gate first on a de-
sign board and then the AND gates.
y
Consider, the black box testckt of Fig.
2.38 has following logic circuit in it.
Give Verilog structural code for the Logic circuit for
same. Example 2.16
Solution The code from the above discussion can be written as follows.
/* internal connecr:1.ons, outputs of upper

*/
gate
Preparation of Test Bench We shall discuss data flow model and behavioral model ofVerilog VHDL in
subsequent chapters. But, before we wind up this chapter let us see how to prepare a test bench in Verilog to
simulate a digital circuit. For those of you with no programming background, this may appear little difficult.
We could have postponed this discussion to a later chapter, but this gives you a feel of how simulation works
or how a circuit you design can be tested. More clarity is assured as you go through discussions of subsequent
chapters.
We take up the example of simulating a simple OR gate (Fig. 2.4a) for which Verilog code is already
described. The test bench, creates an input in the form of a timing waveform and passes this to OR gate module
through a function or procedural can (passing arguments in proper order). To generate timing waveform we
use time delay available in Verilog in the form of #n where n denotes a number in decimal that gives delay
in nanosecond. Input values to a variable can be provided through syntax m'tn where m represents number of
digits, t represents type of number and n represents value to be provided.
The test bench used here generates all possible combinations of two inputs AB as 00,01,10 and 11 but at
an interval of20 ns. Note that, we have provided a 20 ns gate delay with or statement by #(20). All practical
logic circuit comes with finite gate delay, i.e. output changes according to input after certain time. To change
the gate delay to 10 ns we should write #(10) in or statement. The keyword reg is used to hold value of a
data object in a procedural assignment. The keyword initial ensures sequential execution of codes following
it, but once. We'll learn another keyword always in later chapter, which too is used for sequential execution
but for infinite time.
a name
of 20 ns
AB=Ol
Digital Logic
endmodul.e
module·or_gate
input A,B;
output
ox,- # (20) gl (x,A,
output
E!ndmodule
Execution of above Verilog code generates following timing diagram. One can see that input AB, given
by testor.A and testor.B (testor is module name of the test bench) is taking value 00,01,10,11 as expected and
retain them for 20 ns. Output of OR gate, testor.x changes according to input but after a delay of20 ns. For
first 20 ns, OR gate output is unknown as it needs 20ns (gate delay) to respond to first appearance of input
logic at A,B. Note that Verilog, in general offers four logic values in simulation 0, 1, unknown (or x) and high
impedance (or z). Unknown value is exhibited when input is ambiguous and high impedance is shown when
a wire by mistake is left unconnected or the circuit is following tri-state logic (Chapter 14, Section 6).
!Ons
i I! ! l
ilOns
l l I
, 11201 ns1 !
1'30ns
I I I
140ns
i I f I !
j50ns!
l I i
i60ns
! l f I
!70ns!
! ! I
testor.x /
~ocAI /
testor.B I I \ I
Verilog simulation of 2 input OR gate with 20ns gate delay
Write the statements between begin and end of a test bench for circuit described in
Example 2.16 with 50 ns holding time of each input combination.
Solution . Sincethe circuit hast~e~)nputs 11eed 23 = 8 differe11t con1binati0Ils .ofinputs.iThus ~e
statements would look like as follows:
Delay .of ns
'bl; bl; ABC is assigned 011
II Delay of 50 ns
;b=l' bO; bO; ABC is assigned 100
IF50 II Delay of 50 ns
a=l' bl; b=l' bO; 'bl; ABC is assigned 101
l50 II Delay of 50 ns
1
bO; II ABC is assigned 110
of ns
II ABC is .assigned 111
terminates after 400 ns
end
The following timing diagram is generated by simulation of Verilog code for

2-input, 1-output device where A and B are input and x is output. Can you (i) estimate the
gate delay and (ii) identify the logic?
testand.x
testand.A
testand.B
-
i 0ns I
1
I I
11qns I
12on~
I
I i39n~ I
[40ns
I
\
'
1sqn~
' '
i6?n~
I
I
I I
170ns
l I I I !
Verilog simulation for Example 2.18
Solution
(i) The unknown value of the output is approximately half of l Ons time scale. Hence, gate delay is 5ns. ·
(ii). Output goes HIGH when both the inputs go high after a delay of 5 ns. Hence, the logic underlying is AND.
PROBLEM SOLVING WITH MULTIPLE METHODS
Realize Y = AB + C using only one type of gate.

Solution The functioilto berealized involves AND from NOR gate
AND, NOT and OR operations. We can realize r ------------ - I
I :A.B
this expression using universal logic gate.
,n Method-4, we realize it using NOR

OR from NOR gate
r--------------. j
:AB+C
g~te. We realize in~ividual logfo operations I
AA:eANI>,NOTandORasdepictedfoFig.
2.2LThe solutionis given in Fig. 2.41.
ID Method-'.!, . werealize it using NANO
I
f
.
'.' ·. -·· - - - · --·----I
:c
gate. We reali;ze individual logic 9perations NOT.frQlllNOR gate
like AND,NOTandOR as depicted in Fig;
Realization of Y = AB + C
2.27. The solution is given in Fig. 2.42.
using only NOR gate
Digital Logic
Thus, two NOR operations

X ==.X'Jrequiretwo.NOilgat~s,. ~ndfour inyersigns A,B,Clj!lll<lL((l:A<fJi.)'/·t<I.X'.!r.t,equtJI¢Jo1,i,:•·~q.qR/
gat~totaling six N"ORgates•fQr rtal~tion.
byMethod~l.
'fhu§, re need two N ~ gates-one for ·BY

(A and another
thatthe final logic circuitofMethod-2is similar to what is obtam~:d
Almost alldigitaldrcuits are designed for two-state operation, which means the signal voltages are
either at a low level or a high level. Because they duplicate mental processes, digital circuits are often
called logicdrcuits. A gate is a digital circuit with 1 or more inputs, but only l output The output is high
only for certain combinations of the input signals.
An inverter is one type of logic circuit, it produces an output that is the complement of the input. An
ORgate has 2 or more input signals; it produces ahigh output if any input is high. An ANDgate has 2 or
more input signals; it produces a high output only when all inputs are high. Truth tables often use binary
Ofor the low state and binary 1 for the high state. The number of entries in a truth table equals 2", where
n is the number of input signals.
is
The overbar the algebraic symbol for the NOT operation, the plus sign is the gymbol for the OR
operation, and the. times sign is the symbol for the AND operatjon, Since the Boolean operator$ a!'e
codes for the OR gate, AND gate, and inverter, we can use Boolean algebra to analyze digital circuits.
An ANO-OR circuit always produces a sum-of-products equation, while the O~-AND circuit resultsin
a pfoduct~of-sums equation.
The NOR gate is equivalent to an OR gate followed by an inverter. De Morgan's first theorem tells .U$
that a NOR gate isequivalentto a bubbled AND gate. Because of De Morgan's first theorem, a NOR-NOR
circuitis equivalent to an OR-AND circuit.
The NAND gate represents an AND gate followed by an inverter. De Morgan's second theorem says
the NAND gate is equivalent toa bubbled OR gate. Furthermore, a NAND-NAND circuit is equivalent
to an AND-OR circuit. The NAND gate is the backbone of the 7400 TTL series because most devices in
this family are derived from the NAND-gate design. The NAND gate is a universal gate since anylogic
circuit can be built with NAND gates only.
With positive logic, binary l represents high voltage and binary O represents low voltage. Also,
positive. true stands for high voltage and positive false for low voltage. With negative logic, binary 1
stands. for low voltage and binaryO for high voltage. In this system, negative true is equivalent to low
voltage and negative false to high voltage.
With assertion-levellogi<::,we .draw gates and other devices with bubbled pins for active'-low signals.
Also, signal voltages are labeled with abbreviations of statements that describe circuit behavior. An
overbads used on a label whenever the signal is active-low.
Figure 2.43 shows three sets of equivalentgates. Changing from one to the other is accomplished by
adding or<deleting bubbles, and changing AND to OR or OR to ANO; The NORgate and NAND gate
equivalents illustrate De Morgan's first and second theorems.
A-[>-A A
Inverter
!:£>EEC w l~C=A+B+C !D-y ;~y

NOR gate ;=c)-r !=Et-y
De Morgan's First Theorem
t~wi~=ABC ;=[),-r !=GJ-v

NANDgate
De Morg-dll's Second Theorem ;jJ--r !=Et-y
Digital Logic
Figure 2.44 shows the additional logic symbols for five basic gates along with the corresponding IEEE
rectangular symbols.
• active-low Active-low refers to the concept in • logic circuit A digital circuit, a switching
which a signal must be low to cause something circuit, or any kind of two-state circuit that
to happen or to indicate that something has duplicates mental processes.
happened. • negative true A signal is negative true when
• AND gate A gate with 2 or more inputs. The the voltage is low.
output is high only when all inputs are high. • OR gate A gate with two or more inputs. The
• assert To activate. If an input line has a bubble output is high when any input is high.
on it, you assert the input by making it low. • positive true A signal is positive true when the
If there is no bubble, you assert the input by voltage is high.
making it high. • product-of-sums equation A Boolean
• De Morgan -s first theorem In words, the equation that is the logical product of logical
complement of a logical sum equals the sums. This type of equation applies to an OR-
logical product of the complements. In terms AND circuit.
of circuits, a NOR gate equals a bubbled AND • sum-of-products equation A Boolean
gate. equation that is the logical sum of logical
• De Morgan~ second theorem In words, the products. This type of equation applies to an
complement of a logical product equals the AND-OR circuit.
logical sum of the complements. In terms • timing diagram A picture that shows the
of circuits, a NAND gate is equivalent to a input-output wavefonns of a logic circuit.
bubbled OR gate. • truth table A table that shows all of the input-
11
gate A digital circuit with one or more input output possibilities of a logic circuit.
voltages but only one output voltage. • two-state operation The use of only two
• inverter A gate with only one input and a points on the load line of a device, resulting in
complemented output. all voltages being either low or high.
PROBLEMS
2.1 What is the output in Fig. 2.45a if the input is 7404

low? The output if the input is high?
2.2 The input is low in Fig. 2.45b. Is the output
~
(a)
low or high? Is the circuit equivalent to an
inverter? If you cascade an odd number of
6
inverters, what kind of gate is the overall
circuit equivalent to?
(b)
2.3 Construct the truth table for Fig. 2.46a. After
you are finished, discuss the relation between
the circuit of Fig. 2.46a and a 3-input OR 2. 7 Construct the truth table for Fig. 2.48a. Then
gate. discuss the relation between the circuit of Fig.
2.4 Construct the truth table for Fig. 2.46b. 2.48a and a 3-input AND gate.
2.5 Construct the truth table for Fig. 2.46c. 7408
7432 A
2 3~
4 l
6
B 5 Y
A~6 C
B ~ c-2.Lr-Y (a)
(a)
A
y
A y (b)
I 7411 7404
(b)
7432
;~
C
13 y
A (c)
B y
(c)
2.8 Construct the truth table of Fig. 2.48b.
2.9 Construct the truth table for Fig. 2.48c.
2.6 The circuit of Fig. 2.46b has trouble. Figure 2.10 Assume the circuit of Fig. 2.48b has trouble.
2.47 shows its timing diagram. Which of the If Fig. 2.49 is the timing diagram, which of
following is the trouble: the following is the trouble:
a. Input inverter acts like OR gate. a. Input inverter is shorted.
b. Pin 6 is shorted to ground. b. OR gate is used instead of AND gate
c. AND gate is used instead of OR gate. c. Pin 6 is shorted to ground.
d. Output inverter is faulty. d. Pin 8 is shorted to + 5 V.
Pin I Pin I
Pin2 Pin4
Pin 5 +5V
Pin 5
Pin6 +5 V
Pin 6
0
Pin 8
+5V
Pin 8
Digital Logic
2.11 What is the Boolean equation for the output of 2.19 The circuit of Fig. 2.50c has trouble. If output
Fig. 2.46a? Y is stuck in the high state, which of the
For Fig. 2.46b? For Fig. 2.46c? following is the trouble:
2.12 Draw the logic circuit whose Boolean equation a. Either input pin of the AND gate is
is shorted to ground.
Y=A+B+C b. Any input of either OR gate is shorted to
2.13 Use the 7404 and the 7432 with pin numbers. ground.
What is the Boolean equation for the output of c. Any input of either OR gate is shorted to
Fig. 2.46a? a high voltage.
2.14 For Fig. 2.46b? For Fig. 2.46c? d. AND gate is defective.
Draw the logic circuit described by 2.20 Construct the truth table for the 4-input NAND
Y= (ABC)D gate of Fig. 2.51a.
2.15 Use a 7404, 7408, and 7411 with pin nwn- 2.21 The inputs are A 0, A 1, A 2 , ••• , A 7 in Fig. 2.51b.
bers. What is the Boolean equation for the input of
Draw the logic circuit given by this Boolean the NAND gate?
equation: 2.22 Draw an equivalent NAND-NAND circuit
for Fig. 2.51c. Use the 7420 and include pin
Y=ABC+ABC+ABC+ABC
numbers.
Use the following devices with pin numbers:
7404, 7411, and 7432.
A 2 7420
vl _
B 6
C 4 y
D 5
2.16 Construct the truth table for the 3-input NOR
(a) (b)
gate of Fig. 2.50a.
2.17 Construct the truth table for the 4-input NOR
gate of Fig. 2.50b.
2.18 Show an equivalent NOR-NOR circuit for
Fig. 2.50c. Use the 7402 and the 7427 with
pin numbers.
~~y
J 7427 Av!
B
C
2
4
7425
6
y
c~ D 5
(a) (b)
(c)
y 2.23 Suppose the final output of Fig. 2.51c is stuck

A-......r-----. in the high state. Which of the following is the
B
C - ------1-__.- trouble?
(c) a. Any input to the OR gate is shorted to a
high voltage.
b. Any AND-gate input is shorted to
ground.
c. Any AND-gate input is shorted to a high

voltage.
d. One of the AND gates is defective be-
8
cause its output is always low. y
ll
2.24 What is the output in Fig. 2.3 lc for these

inputs?
a. ABCD=OOOO b. ABCD=OlOl
c. ABCD = 1100 d. ABCD = 1111
2.25 Is the output Y of Fig. 2.52 low or high for
these conditions?
a. Both switches open, A is low.
b. Both switches closed, A is high. 2.28 In Fig. 2.54, is each of the following an active-
c. Left switch open, right switch closed, A low or an active-high?
is low. a. Pin 1 b. Pin 2
d. Left switch closed, right switch open, A c. Pin 3 d. Pin 5
is high. e. Pin 6
2.26 If all inputs are low in Fig. 2.34b, what is
2.29 An 8085 microprocessor uses the following
the output? If all inputs are high, what is the
labels with assertion-level logic. Is each signal
output?
active-low or active-high?
a. HOLD b. RESET IN
lOkQ c. RD d. WR
e. ALE f. INTR
y g. INTA
2.30 When switch B of Fig. 2.54 is closed, is pin 6
high or low? For this condition, is B CLOSED
A
negative true or negative false?
2.27 What is the value of Yin Fig. 2.53 for each of Jk.Q JkQ
these? ,A CLOSED I
a. ABCD = 0000 b. ABCD=OlOl 2
c. ABCD = 1000 d. ABCD = 1111 8 CLOSED 7400 7404

Switch.41
Digital Logic
LABORATORY
AIM: ~~.~ii()ftliis experiment is to study
basic NAND gate and implement a bounce-
free switch using basic gates.
Theory: The NAND gateimplements the
logic
Y=(A.B.C ... )'

where A, B, C, ... are inputs and Y is output.
The mechanical switches used for electri~
cal connection go through several make-break Apparatus: +5 Volt de power supply, multi-
situations before resting in a particular posi- meter, bread board, and oscilloscope
tion. For digital circuits, this could amount to
Work element: IC 7400 is a quad 2-input
a series of HIGH-LOW which is particularly
NAND gate. Study its pin configuration and
detrimental to sequential logic ciffuit.Jhe
verify the NAND truth table. Study the de-
following circuit presents a NAND based de-
bounce switch circuit and find out the principle
bounce switch.
behind its working. Use two NAND gates of
'I. 7400 IC 7400 and wire it as shown in the diagram.
Awire may be used as a switch, the other side
of\vhich is connected to a de power supply
or Ground. Observe voltage level at the oscil-
loscope,· a.t various points ofthe circuit when
switching is done at the input side. Discuss
the result.Design and implement a NOR (IC
7402) gate based debounce switch.
l. positive 13. There are two AND gates at the input

2. OR 14. It is used to increase the number of input
3. AND AND gates.
4. Y=A 15. Converse of positive fogic. Here binary 0
5. Y=A+B stands for high voltage and binary 1 stands
6. Y=A ·B=AB for low voltage.
7. Y=A+B 16. It means drawing logic symbols to indicate
8. A+B=A·B the action of each signal. If the si!:,>nal
9. ~ causes something to happen when low, it
10. Y=A·B is drawn with a bubble; this is an active-
low ·signal. Ifa signal causes something to
A·B=A+B happen when high, it is drawn without a
12. &
bubble; this is an active-high signal.
Combinational Logic
Circuits
+ Demonstrate the ability to use basic Boolean laws.

+ Use the sum-of-products method to design a logic circuit based on a design truth
table.
+ Be able to make Karnaugh maps and Entered variable maps and use them to simplify
Boolean expressions.
+ Use the product-of-sums method to design a logic circuit based on a design truth
table.
+ Use Quine-McClusky tabular method for logic simplification
+ Analyze hazards in logic circuit and provide solution for them.
This chapter discusses Boolean algebra and several simplification techniques. After learning the laws and
theorems of Boolean algebra, you can rearrange Boolean equations to arrive at simpler logic circuits. An
alternative method of simplification is based on the Kamaugh map. In this approach, geometric rather than
algebraic techniques are used to simplify logic circuits. Quine-McClusky tabular method provides a more
systematic reduction technique, which is preferred when a large number of variables are in consideration.
There are two fundamental approaches in logic design: the sum-of-products method and the product-
of-sums method. Either method produces a logic circuit corresponding to a given truth table. The sum-of-
products solution results in an AND-OR or NAND-NAND network, while the product-of-sums solution
results in an OR-AND or NOR-NOR network. Either can be used, although a designer usually selects the
simpler circuit because it costs less and is more reliable. A practical logic circuit can show hazard due to finite
propagation delay involved in each logic gate. This gives glitches or shows multiple transitions at the output.
This chapter discusses different types of hazards and ways to prevent them.
Combinational Logic Circuits
3.1 BOOLEAN LAWS ANO THEOREMS
You should know enough Boolean algebra to make obvious simplifications. What follows is a discussion of
the basic laws and theorems of Boolean algebra. Some of them will look familiar from ordinary algebra but
others will be distinctly new.
Basic laws
The commutative laws are
A+B=B+A (3.1)
AB =BA (3.2)
These two equations indicate that the order of a logical operation is unimportant because the same answer
is arrived at either way. As far as logic circuits are concerned. Figure 3.la shows how to visualize Eq. (,.1).
All it amounts to is realizing that the inputs to an OR gate can be transposed without changing the output.
Likewise, Fig. 3.lb is a graphical equivalent for Eq. (3.2).
The associative laws are
A + (B + C) = (A + B) + C (3.3)
A(BC) = (AB)C (3.4)
;=[)-r !=f:>-r
(a)
~=[)-y !=[)-r
(b)
~=e>-=D-y ;~y
(c)
B~Y
C
A=C>;=[)- y
B
C
(d)
A y
C
(e)
Commutative, associative, and distributive laws

These laws show that the order of combining variables has no effect on the final answer. In terms oflogic
circuits, Fig. 3.lc illustrates Eq. (3.3), while Fig. 3.ld represents Eq. (3.4).
The distributive law is
A(B + C) = AB + AC (3.5)
This law is easy to remember because it is identical to ordinary algebra. Figure 3 .1 e shows the corresponding
logic equivalence. The distributive law gives you a hint about the value of Boolean algebra. If you can
rearrange a Boolean expression, the corresponding logic circuit may be simpler.
The first five laws present no difficulties because they are identical to ordinary algebra. You can use these
laws to simplify complicated Boolean expressions and arrive at simpler logic circuits. But before you begin,
you have to learn other Boolean laws and theorems.
OR Operations
The next four Boolean relations are about OR operations. Here is the first:
A+O=A (3.6)
This says that a variable ORed with Oequals the variable. If you think about it, makes perfect sense. When
A is 0,
O+O =O
And when A is 1,
1+0 = 1
In either case, Eq. (3.6) is true.
Another Boolean relation is
A+A =A (3.7)
Again, you can see right through this by substituting the two possible values of A. First when A = 0, Eq.
(3.7) gives
O+O =O
which is true. Next, A = I results in
1+ 1 = 1
which is also true because 1 ORed with 1 produces 1. Therefore, any variable ORed with itself equals the
variable.
Another Boolean rule worth knowing is
A+ I= 1 (3.8)
Why is this valid? When A= 0, Eq. (3.8) gives
0+1 =1
which is true. Also. A = 1 gives
1+ 1 =1
This is correct because the plus sign implies OR addition, not ordinary addition. In summary,
Eq. (3.8) says this, if one input to an OR gate is high, the output is high no matter what the other input.
Finally, we have
A+ A= I (3.9)
You should see this in a flash. If A is 0, A is 1 and the equation is true. Conversely, if A is 1, A is O and
the equation still agrees. In short, a variable ORed with its complement always equals I.
AND Operations
Here are three AND relations
A· 1 =A (3.10)
A ·A =A (3.11)
A ·O =O (3.12)
When A is 0, all the foregoing are true. Likewise, when A is 1, each is true. Therefore, the three equations
are valid and can be used to simplify Boolean equations.
One more AND formula is
A· A =O (3.13)
This one is easy to understand because you get either
0·l =0
or
I· 0 =0
for the two possible values of A. In words, Eq. (3.13) indicates that a variable ANDed with its complement
always equals zero.
Double Inversion and De Morgan's Theorems

The double-inversion nde is
A =A (3.14)
which shows that the double complement of a variable equals the variable. Finally, there are the De Morgan
theorems discussed in Chapter 2:
A+B =AB (3.15)
AB= A +B (3.16)
You already know how important these are. The first says a NOR gate and a bubbled AND gate are
equivalent. The second says a NAND gate and a bubbled OR gate are equivalent.
Duality Theorem
The duality theorem is one of those elegant theorems proved in advanced mathematics. We will state the
theorem without proof. Here is what the duality theorem says. Starting with a Boolean relation, you can
derive another Boolean relation by
1. Changing each OR sign to an AND sign
2. Changing each AND sign to an OR sign
3. Complementing any O or 1 appearing in the expression
For instance, Eq. (3.6) says that

A+O=A
The dual relation is
A· 1 =A
This dual property is obtained by changing the OR sign to an AND sign, and by complementing the Oto
get a 1.
The duality theorem is useful because it sometimes produces a new Boolean relation. For example, Eq.
(3 .5) states that
A(B+C) =AB+AC
By changing each OR and AND operation, we get the dual relation
A + BC = (A + B)(A + C) (3.17)
This is new, not previously discussed. (If you want to prove it, construct the truth table for each side of the
equation. The truth tables will be identical, which means the Boolean relation is true.)
Covering and Combination

The covering rule, where one term covers the condition of the other term so that the other term becomes
redundant, can be represented in dual form as
A +AB =A (3.18)
and A(A +B) =A (3.19)
The above can be easily proved from basic laws because,
A + AB = A · I +AB= A(I + B) = A · I = A
and A (A + B) = A · A +AB= A + AB = A
The combining rules are,
AB+AB =A (3.20)
and in its dual form (A + B)(A + B) = A (3.21)
Eq. (3.20) can easily be proved as B + B =1
Expanding left hand side ofEq. (3.21)
A·A+A·B+A·B+B·B =A+A(B+B)+O
= A + A · 1 = A + A = A = right hand side
Consensus Theorem
The consensus theorem finds a redundant term which is a consensus of two other terms. The idea is that if
the consensus term is true, then any of the other two terms is true and thus it becomes redundant. This can be
expressed in dual form as
AB+ AC+ BC =AB+ AC (3.22)
(A + B)( A + C) (B + C) = (A + B)( A + C) (3.23)
In the first expression, BC is the consensus term and thus redundant. This is because if BC= 1, then both
B = 1 and C = 1 and any of the other two terms AB or AC must be one as either A = 1 or A = 1. Similarly,
in the second expression, (B + C) is the consensus term and if this term is O then both B = 0 and C = 0. This
makes one of the other two sum terms Oas either A= 0 or A= 0.
For future reference, here are some Boolean relations and their duals:
A+B=B+A AB=BA
A+ (B + C) =(A+ B) + C A(BC) = (AB)C
A(B + C) =AB+ AC A +BC= (A+ B)(A + C)
A+O=A A·l=A
A+l =1 A-0=0
A+A=A A·A=A
A+A =1 A· A =0
A=A A=A
A+ B= AB AB= A+B
A+AB=A A(A +B) =A
A+AB=A+B A(A +B)=AB
AB+AB =A (A+ B) (A+ B) = A
AB+ AC+ BC= AB+ AC (A+ B) (A + C) (B + C) =(A+ B) (A + C)
Prove that, A(A' + C) (A'B + C) (A'BC + C') = 0
Solution
LHS =(AA'+AC)(A'B+C)(A'BC+C') : distributive law
=AC(A'B + C) (A'BC+ C') : since, XX' =0
=(AC· A'B +AC· C) (A'BC+ C') : distributive law
=AC(A'BC+ C') : since, ){){' = 0
=AC A'BC+AC· C' : distributive law
=O=RHS : since, .-IT' = 0
Simplify, Y= (A+ B) (A'(B' + C'))' + A'(B + C)
Solution
Y =(A+ B) ((A+ (B' + C')') +A'(B + C) : De Morgan's theorem
. = (A+ JJ).(A +BC)+ A'(B + C) : De Morgan's theorem
=(AA +ABC+ AB+ BBC)+ A'(B + C)
=(A +AB +ABC+BC)+A'(B + C)
=A(l + B +BC)+ BC+ A'(B + C)
+ BC +A 1(B + C)
(A+ A'(B + C)) +BC
=A +B + C+BC
=A+ B + C(l + B)
=A+B+C
A logic clip is a device that you can attach to a 14- or 16-pin DIP. This troubleshooting
tool contains 16 light-emitting diodes (LEDs) that monitor the state of the pins. When a pin
voltage is high, the corresponding LED lights up. If the pin voltage is low, the LED is dark.
Suppose you have built the circuitofFig. 3.2a, but it doesn't work correctly. When you connect
a logic clip to the 7408, you get the readings ofFig. 3.2b (a black circle means an LED is off,
and a white one means it's on). When you connect the clip to the 7432, you get the indications of
Fig. 3.2c. Which of the gates is faulty?
e1 140 fill 140

A 02 13 0 92 130
e3 120 lll3 120
B
y
04 11 0 • =Off
0 =On
94 110
A 05 100 05 100
B 06 90 06 90
97 80 e7 80
(a) (b) (c)
Solution When you use a logic clip, all you have to do is look at the inputs and output to isolate a faulty gate. For
instance, Fig. 3.2b applies to a 7408 (quad 2-input AND gate). The First AND gate (pins l to 3) is all right because
PinJ-,-low
Pin2-high
Pin3-low
A 2-input AND gate is supposed to have a low output if any input is low.
The second AND gate (pins 4 to 6) is defective, Why? Because
Pfa4-high
Pin5-high
Pin6--low
Something is wrong with this AND gate because it produces a low output even. though both inputs are high.
If you check Fig. 3.2c (the 7432), all OR gates are normal. For instance, the first OR gate (pins! to3) is all right
because it produces a low output when the 2 inputs are low. The second OR gate (pins 4 to 6) is working. correctly
since it produces a high output when I input is high.
L All the rules for Boolean algebra are exactly the same as for ordinary algebra. (Tor F)
2. Expand using the distributive law: Y = A(B + C).
3. Simplify: Y= AQ+ AQ.
3.2 SUM-Of-PRODUCTS METHOD
Figure 3 .3 shows the four possible ways to AND two input signals that are in complemented and uncomplemented
form. These outputs are calledfimdamental products. Table 3.1 lists each fundamental product next to the
input conditions producing a high output. For
instance, AB is high when A and B are low; AB Fundamental Products for Two
is high when A is low and Bis high; and so on. The Inputs
fundamental products are also called minterms.
A B Fundamental Product
Products A' B', A'B, AB', AB are represented by
m0, mi, m2 , and m3 respectively. The suffix i ofmi 0 0 AB
comes from decimal equivalent of binary values 0 AB
(Table 3.1) that makes corresponding product 0 AB
term high. AB
i =[]-AB ~ =[]-As ~ =[]-As ~ =[]-AB
00 ~ ~ ~
ANDing two variables and their complements
The idea of fundamental products applies to three or more input variables. For example, assume three
input variables: A, B, C and their complements. There are eight ways to AND three input variables and their
complements resulting in fundamental products of
ABC, ABC, ABC, ABC, ABC, AB c, ABC, ABC
C
j~
(a)
Examples of ANDing three variables and their complements
The above three variable minterms can alterna-

Fundamental Products for
tively be represented by mo, m1, 1112, 1113, 1114, 1115,
Three Inputs
1116, and 111 7 respectively. Note that, for n variable
problem there can be 211 number of minterms. B Fundamental Products
Figure 3.4a shows the first fundamental product,
Fig. 3.4b the second, and Fig. 3.4c the third. (For 0 ABC
practice, draw the gates for the remaining funda- 0 0 1 ABC
mental products.) for twice variable case. 0 0 ABC
Table 3.2 summarizes the fundamental products 0 1 ABC
by listing each one next to the input condition that 1 0 0 ABC
results in a high output. For instance, when A = 1, 1 0 ABC
B = 0 and C = 0, the fundamental product results 1 0 ABC
in an output of I 1 ABC
Y= ABC= 1 · 0 · 0 = 1
Sum-of-Products Equation
Here is how to get the sum-of-products solution, given a truth table like Table 3.3. What you have to do is
locate each output 1 in the truth table and write down the fundamental product. For instance, the first output
1 appears for an input of A = 0, B = 1, and C = 1. The corresponding fundamental product is ABC. The next
output 1 appears for A = 1, B = 0, and C = 1. The corresponding fi.mdamental product is ABC. Continuing
like this, you can identify all the fundamental products, as shown in Table 3.4. To get the sum-of-products
equation, all you have to do is OR the fundamental products of Table 3.4:
- - -
Y =ABC+ ABC+ ABC+ ABC (3.24)
Alternate representation of Table 3.3,
Y = F(A, B, C) = I: m (3, 5, 6, 7)
where 'I:' symbolizes summation or logical OR operation that is performed on corresponding mintem1s and
Y = F (A, B, C) means Y is a function of three Boolean variables A, B and C. This kind of representation of a
truth table is also known as canonical sum.form.
Design Truth Table Fundamental Products for

y Table 3.3
A B C
A B C y
0 0 0 0
0 0 1 0 0 0 0 0
0 1 0 0 0 0 1 0
0 1 1 1 0 1 0 0
1 0 0 0 0 l l 1-, ABC
1 0 l 1 l 0 0 0
I 1 0 1 l 0 I I-, ABC
I 1 1 1 1 l 0 1-, ABC
1 I I 1 -,ABC
logic Circuit A ABC

B
After you have a sum-of-products equation, you can derive the C
co1Tesponding logic circuit by drawing an AND-OR network,
or what amounts to the same thing, a NAND-NAND network. A ABC
In Eq. (3.24) each product is the output of a 3-input AND B
gate. Furthermore, the logical sum Yis the output of a4-input C
y
OR gate. Therefore, we can draw the logic circuit as shown
A
in Fig. 3.5. This AND-OR circuit is one solution to the design ABC
B
problem that we started with. In other words, the AND-OR c
circuit ofFig. 3.5 has the truth table given by Table 3.3.
We cannot build the circuit of Fig. 3.5 because a 4-in- A
ABC
put OR gate is not available as a TTL chip (a synonym for B
C
integrated circuit). But a 4-input NAND gate is. Figure 3.6
shows the logic circuit as a NAND-NAND circuit with TTL
AND-OR solution
pin numbers. Also notice how the inputs come from a bus, a
group of wires carrying logic signals. In Fig. 3.6, the bus has six wires with logic signals A, B, C, and their
complements. Microcomputers are bus-organized, meaning that the input and output signals of the logic
circuits are connected to buses.
Suppose a three-valuable trnth table has a high output for these input conditions: 000, 010,
100, and 110. What is the
AABBCC
sum-of-products circuit?
Solution Here are the fundamental products:

ooo: ABC
010: ABC
100: Alic
110 :ABC
When you OR these products, you get y
Y=ABC +ABC +ABC +ABC

The circuit of Fig. 3.6 will work if we reconnect .the
input lines to the bus as follows:
A :pins. I and 3 2 12
----- o--~
B : .pins 2 and 10 13
7410
C : pinsB, 5,11, and 13
A : pins 9 and!
B :pins4and2
Combinational logic circuit
Simplify the Boolean equation in Example 3.4 and describe the logic circuit.
Solution The Boolean equation is

y =ABC+ ABC+ ABC+ ABC
Since C is common to each term, factor as follows:
Y=(AB +AB+AB + AB)C
Again, factor to get
f;::[A(B +B)+A(B+B)]C
Now, simplify the foregoing as follows:
r= [A (I)+ A(l)Jc = (A + A)c
or
Y=c
This final equation means that you don't even need a logic circuit; All you need is a wire connecting input· C to output
Y.
The lesson is clear. The AND-OR (NAND-NAND) circuit you get with the sum-of-products method isnotnecessarily
as simple as possible. With algebra, you often can factor and reduce the .sum-ofcproducts equation to arrive at a
simpler Boolean equation, which means a simpler logic circuit. A simpler logic circuit is prefon-ed because. it usually
costs less to build.and is more reliable.
4. How many fondamental products are there for two variables? How many for three
variables?
5. The AND-OR or the NAND-NAND circuit obtained with the sum-of-products method is
always the simplest possible circuit. (T or F)
3.3 TRUTH TABLE TO KARNAUGH MAP
A Karnaugh map is a visual display of the fundamental

products needed for a sum-of-products solution. For instance,
here is how to convert Table 3.5 into its Karnaugh map. Begin A B y
by drawing Fig. 3.7a. Note the variables and complements: 0 0 0
the vertical column has A followed by A, and the horizontal 0 l 0
row has B followed by B. The first output 1 appears for A = 1 1 0 1
and B = 0. The fundamental product for this input condition is 1 1
AB . Enter this fundamental product on the Karnaugh map as
shown in Fig. 3.7b. This 1 represents the product AB because the 1 is in row A and column Ji.
Similarly, Table 3.5 has an output 1 appearing for inputs of A= 1 and B = 1. The fundamental product is
AB, which can be entered on the Karnaugh map as shown in Fig. 3.7c. The final step in drawing the Karnaugh
map is to enter Os in the remaining spaces (see Fig. 3.7d).
In terms of decimal equivalence each position of Karnaugh map can be drawn as shown in
Fig. 3.7b. Note that, Table 3.5 can be written using minterms as Y= L m(2, 3) and Fig. 3.7e represents that.
B B B B B B
(a)
A~
A I2
(b)
3
(c)
:~ (d)
A~
A I1
(e)
1
Constructing a Karnaugh map
Three-Variable Maps
Here is how to draw a Karnaugh map for Table 3.6 or for y
A .... B C
logic equation, Y = F(A, B, C) = Lm(2,6,7). First, draw
0 0 0 0
the blank map of Fig. 3.8a. The vertical column is labeled
0 0 l 0
AB, AB, AB, and AB. With this order, only one variable 0 1 0 1
changes from complemented to uncomplemented form (or 0 I 1 0
vice versa) as you move downward. In terms of decimal 1 0 0 0
equivalence of each position the Karnaugh map is as l 0 I 0
shown in Fig. 3.8b. Note how mintenns in the equation 1 1 0 1
gets mapped into corresponding positions in the map. l l 1 I
Next, look for output ls in Table 3.6. Output ls appear for ABC inputs of 010, 110 and 111. The fundamental
products for these input conditions are ABC, ABC, and ABC Enter 1s for these products on the Kamaugh
map (Fig. 3.8b).
The final step is to enter Os in the remaining spaces (Fig. 3.8c).
c C c C c C c C
AB AB 0 AB AB 0 0
AB AB 2 3 AB AB 0
AB AB 6 7 AB AB
AB AB 4 5 AB AB 0 0
(a) (b) (c) (d)
Three-variable Karnaugh map
Four-Variable Maps
Many digital computers and systems process 4-bit
numbers. For instance, some digital chips will work y
A B C D
with nibbles like 0000, 0001, 0010, and so on. For this
reason, logic circuits are often designed to handle four 0 0 0 0 0
input variables (or their complements). This is why 0 0 0 l
you must know how to draw a four-variable Kamaugh 0 0 1 0 0
0 0 I l 0
map.
0 I 0 0 0
Here is an example. Suppose you have a truth 0 0 1 0
table like Table 3.7. Start by drawing a blank map 0 I 0 J
like Fig. 3.9a. Notice the order. The vertical column 0 1 1 1
is AB, AB, AB, and AB. The horizontal row is I 0 0 0 0
CD, CD, CD, and CD. In terms of decimal equi- 0 0 1 0
valence of each position the Kamaugh map is as shown 0 1 0 0
in Fig. 3.9b. In Table 3.7, you have output ls appearing 0 I. 1
for ABCD inputs of 0001, OllO, 0111, and 1110. The 0 0
0
fundamental products for these input conditions are
ABCD,ABCD,ABCD, and ABCD. After entering
ls on the Karnaugh map, you have Fig. 3.9c. The final
step of filling in Os results in the complete map of Fig. 3.9d.
6. WhatisaKarµaugh map?
7. How many entries are there on a four-variable Kamaugh map?
Entered Variable Map

As the name suggests, in entered variable map one of the input variable is placed inside Kamaugh map. This
is done separately noting how it is related with output. This reduces the Karnaugh map size by one degree,
ci5 CD G7J CD c:15 CD CD CD c:15 CD CD CD cl5 CD CD CD

AB AB 0 3 2 AB 0 3 2 AB 0 0 0
AB AB 4 5 7 6 AB 4 5 7 6 AB 0 0 1
AB AB 12 13 15 14 AB 12 13 15 14 AB 0 0 0
AB AB 8 9 11 10 AB 8 9 11 10 AB 0 0 0 0
(a) (b) (c) (d)
Constructing a four-variable Karnaugh map
i.e. a three variable problem that requires 2 3 = 8 locations in Karnaugh map will require i 3 -ll = 4 locations
in entered variable map. This technique is particularly useful for mapping problems with more than four input
variables.
We illustrate the technique by taking a three variable example, truth table of which is shown in Table 3.6.
Let's choose C as map entered variable and see how output Y varies with C for different combinations of
other two variables A and B. Fig. 3.1 Oa shows the relation drawn from Table 3.6. For AB= 00 we find Y = 0
and is not dependent on C. For AB= 01 we find Y is complement of C thus we can write Y = C'. Similarly,
for AB= 10, Y = 0 and for AB= 11, Y= 1. The corresponding entered variable map is shown in Fig. 3.10b. If
we choose A as map entered variable we have table shown in Fig. 3 .1 Oc showing relation with Y for various
combinations of BC; the corresponding entered variable map is shown in Fig. 3.10d.
A B Y B B B C Y c C
0 0 0 7i~l' 0 0 0 B~
o c A IO 1 0 0 Bl I A
0 0 0
l A
(a) (b) (c) (d)
Entered variable map of truth table shown in Table 3.6
3.4 PAIRS, QUADS, AND OCTETS
Look at Fig. 3.lla. The map contains a pair of cl5 CD CD CD cl5 CD CD CD

ls that are horizontally adjacent (next to each
other). The first l represents the product AB CD;
the second l stands for the product ABC I5.
As we move from the first 1 to the second 1,
only one variable goes from uncomplemented
AB
AB
AB
0
0
0
0
0
0
0
0
0
0 ~1:I
AB 0
0
0
0
0
0
C[J)
0
0
to complemented form (D to D); the other

AB 0 0 0 0 AB o 0 0 0
variables don't change form (A, Band C remain (a) (b)

uncomplemented). Whenever this happens, you
can eliminate the variable that changes form. Horizontally adjacent 1 s
Combinational Circuits
Proof
The sum-of-products equation corresponding to Fig. 3.1 la is
Y=ABCD + ABCD
which factors into
y = ABC(D + D)
Since D is ORed with its complement, the equation simplifies to
Y=ABC
In general, a pair of horizontally adjacent Is like those of Fig. 3.11 a means the sum-of-products equation
will have a variable and a complement that drop out as shown above.
For easy identification, we will encircle two adjacent Is as shown in Fig. 3 .11 b. Two adjacent 1s such as
these are called a pair. In this way, we can tell at a glance that one variable and its complement will drop out of
the c01Tesponding Boolean equation. In other words, an encircled pair of ls like those of Fig. 3.1 lb no longer
stand for the ORing of two separate products, ABCD and ABCD. Rather, the encircled pair is visualized as
representing a single reduced product ABC.
Here is another example. Figure 3.12a shows a pair of 1s that are vertically adjacent. These ls correspond
to ABC D and AB CD. Notice that only one variable changes from uncomplemented to complemented form
(B to B). Therefore, B and B can be factored and eliminated algebraically, leaving a reduced product of
ACD.
CD CD CD CD CD CD CD CD cB CD CD c75 CD CD CD CD
~
AB 0 0 0 0 AB 0 0 0 AB 0 0 0 0 AB () 0 0 0
AB 0 0 0 0 AB 0 0 0 AB 0 0 0 0 AB 0 <:CJ) 0
AB 0 AB 0 AB 0
A~~ 0 0 0
0 0 0 () 0 0 0 0
AB 0 0 0 ~. AB 0 0 0 0 AB cc=J) 0 0 AB I 0 0 0
(a) (b) (c) (d)
Examples of pairs
More .Examples
Whenever you see a pair of horizontally or vertically adjacent 1s, you can eliminate the variable that appears
in both complemented and uncomplemented form. The remaining variables (or their complements) will be
the only ones appearing in the single-product tenn corresponding to the pair of ls. For instance, a glance
at Fig. 3.12b indicates that B goes from complemented to uncomplemented form when we move from the
upper to the lower I; t~ other variables remain the same. Therefore, the encircled pair of ls in !::ig. 3.12b,
represents the product A CD. Likewise, given the pair of 1sin Fig. 3.12c, the only change is from D to D. So
the encircled pair of ls stands for the product ABC,
If more than one pair exists on a Kamaugh map, you can OR the simplified products to get the Boolean
equation. For instance, the lower pair of Fig. 3.12d represents the simplified product ACD; the upper pair
stands for ABD. The corresponding Boolean equation for this map is
Y= ACD + ABD
The Quad
A quad is a group of four ls that are horizontally or vertically adjacent. The ls may be end-to-end, as shown
in Fig. 3.13a, or in the form of a square, as in Fig. 3.13b. When you see a quad, always encircle it because it
leads to a simpler product. In fact, a quad eliminates two variables and their complements.
cl5 CD CD CD c:15 CD CD CD cl5 CD CD CD

AB 0 0 0 0 AB 0 0 0 0 AB 0 0 0 0
AB 0 0 0 0 AB 0 0 0 0 AB 0 0 0 0
AB
AB 0
~
0
(a)
0 0
AB 0
Ali 0
0
0
(b)
0 1
AB
AB 0
CC}) CC})
0
(c)
0 0
Examples of quads
Here is why a quad eliminates two variables and their complements. Visualize the four 1s of
Fig. 3.13a as two pairs (see Fig. 3.13c). The first pair represents ABC; the second pair stands for ABC. The
Boolean equation for these two pairs is
Y=ABC +ABC
This factors into
Y=AB(C + C)
which reduces to
Y=AB
So, the quad of Fig. 3. l 3a represents a product whose two variables and their complements have dropped
out.
A similar proof applies to any quad. You can visualize it as two pairs whose Boolean equation leads to a
single product involving only two variables or their complements. There's no need to go through the algebra
each time. Merely step through the different ls in the quad and determine which two variables go from
complemented to uncomplemented form (or vice versa); these are the variables that drop out.
For instance, look at the quad of Fig. 3.13b. Pick any 1 as a starting point. When you move horizontally,
D is the variable that changes form. When you move vertically, B changes form. Therefore, the remaining
variables (A and C) are the only ones appearing in the simplified product. In other words, the simplified
equation for the quad of Fig. 3.13b is
Y=AC
The Octet
Besides pairs and quads, there is one more group to adjacent 1s to look for: the octet. This is a group of eight 1s
like those of Fig. 3.14a on the next page. An octet like this eliminates three variables and their complements.
Here's why. Visualize the octet as two quads (see Fig. 3.14b). The equation for these two quads is
Y=AC +AC
CD CD CD c75 CD CD CD c75
AB 0 0 0 0 AB 0 0 0 0
A~GD A~o D
AB
AB
0 0
I .· · 1
(a)
0
I
0
1
AB
AB
0
I
0
(b)
0 0
Example of octet
After factoring,
Y=A(C +C)
But this reduces to
Y=A
So the octet of Fig. 3.14a means three variables and their complements drop out of the corresponding
product.
A similar proof applies to any octet. From now on don't bother with the algebra. Merely step through the
ls of the octet and detennine which three variables change fom1. These are the variables that drop out.
8. On a Kamaugh map, tvvo adjacent ls are called a __.

9. On a Kamaugh map, an octet contains how many ls?
3.5 KARNA UGH SIMPUFICATIONS

As you know, a pair eliminates one variable and its complement, a quad eliminates two variables and their
complements, and an octet eliminates three variables and their complements. Because of this, after you draw
a Kamaugh map, encircle the octets first, the
quads second, and the pairs last. In this way, the CD CD CD CD CD CD CD CD
greatest simplification results. AB o AB o
An Example
Suppose you have translated a truth table into
the Karnaugh map shown in Fig. 3.15a. First,
look for octets. There are none. Next, look for
AB
AB
AB
o
(a)
0
0 0
AB l 1
(b)
A~ol
AB
0
O o 0
0
quads. When you find them, encircle them. Fi-

nally, look for and encircle pairs. If you do this Encircling octets, quads and pairs
correctly, you arrive at Fig. 3.l 5b.
The pair represents the simplified product ABD, the lower quad stands for AC, and the quad on the right
represents CD. By ORing these simplified products, we get the Boolean equation corresponding to the entire
Kamaugh map:
Y=ABD+AC+CD (3.25)
Overlapping Groups
You are allowed to use the same 1 more than once. ci5 CD CD CD cl5 CD CD CD
Figure 3.16a illustrates this idea. The I representing
the fundamental product ABC D is part of the pair AB o o o o AB 0 0 0 0
and part of the octet. The simplified equation for the 0 0 AB 0 0 0
overlapping groups is AB 1
Y=A + BCD (3.26) AB
It is valid to encircle the ls as shown in Fig.
3. l 6b, but then the isolated 1 results in a more com- (a) (b)
plicated equation:
Y=A+ ABCD Overlapping groups
So, always overlap groups if possible. That is,

use the 1s more than once to get the largest groups you can.
Rolling the Map

Another thing to know about is rolling. Look at cl5 CD CD CD cl5 CD CD CD
Fig. 3.17a on the next page. The pairs result in
this equation: AB 0 0 0 0 AB 0 0 0 0
Y=BCD +BCD
Visualize picking up the Kamaugh map and
(3.27) AB
AB (J 0
0
0
0 (J AB
AB J
0
0
0
0 G
rolling it so that the left side touches the right side. AB 0 0 0 0 AB 0 0 0 0
If you are visualizing correctly, you will realize
the two pairs actually form a quad. To indicate (a) (b)
this, draw half circles around each pair, as shown
in Fig. 3: 17b. From this viewpoint, the quad of Rolling the Karnaugh map
Fig. 3.17b has the equation
Y=BD (3.28)
Why is rolling valid? Because Eq. (3.27) can be algebraically simplified to Eq. (3.28). The proof starts
with Eq. (3.27):
Y=BCD +BCD
This factors into
Y=BD(C+C)
which reduces to
Y=BD
But this final equation is the one that represents a rolled quad like Fig. 3.17b. Therefore, ls on the edges
of a Kamaugh map can be grouped with ls on opposite edges.
More Examples
If possible, roll and overlap to get the largest
groups you can find. For instance, Fig. 3.18a
ci5 CD CD CD ci5 CD CD CD
shows an inefficient way to encircle groups. The AB 0 0 AB 0 0
a
octet and pair have a Boolean equation of
~
AB 0 AB l 0
Y=C +BCD
You can do better by rolling and overlapping
AB 0 AB J I 0
as shown in Fig. 3.18b; the Boolean equation AB 0 0 AB 0 0

now is (a) (b)
Y= C + BD
Here is another example. Figure 3.19a shows · Rolling and overlapping
an inefficient grouping of ls; the corresponding
equation is
y = C + A CD+ AB CD
ci5 CD CD CD ci5 CD CD CD ci5 CD CD CD
AB
AB
AB
0
0
a
0
AB
AB
AB
0
0
~ 0
AB
AB
AB
0
0
f 0
AB 0 CD AB 0 C[ AB 0 C[
(a) (b) (c)
Different ways of encircling groups
Ifwe roll and overlap as shown in Fig. 3.19b, the equation is simpler:
Y=C +AD +ABD
It is possible to group the 1s as shown in Fig. 3.19c. The equation now becomes
Y=C+AD+BD (3.29)
Compare this with the preceding equation. As you can see, the equations are comparable in simplicity.
Either grouping (Fig. 3.19b or c) is valid; therefore, you can use whichever you like.
Eliminating Redundant Groups

After you have finished encircling groups, eliminate any redundant group. This is a group whose ls are
already used by other groups. Here is an example. Given Fig. 3.20a, encircle the quad to get Fig. 3.20b. Next,
group the remaining 1s into pairs by overlapping (Fig. 3 .20c). In Fig. 3 .20c, all the 1s of the quad are used by
the pairs. Because of this, the quad is redundant and can be eliminated to get Fig. 3.20d. As you see, all the
ls are covered by the pairs. Figure 3.20d contains one less product than Fig. 3.20c; therefore, Fig. 3.20d is
the most efficient way to group the ls.
cl5 CD CD CD CJ5 CD CD CD cl5 CD CD CD cl5 CD CD CD
AB 0 0 0 AB 0 0 0 AB 0 0 1 0 AB o o r\ o
\y
AB
AB
AB
0
0 0
0
0
AB
AB
AB
0
0
0 l
0
0
0
AB
AB
AB
0
0
AB CC})
~;: ~~
0
(a) (b) (c) (d)
Eliminating an unnecessary group
Conclusion
Here is a summary of the Karnaugh-map method for simplifying Boolean equations:
1. Enter a 1 on the Kamaugh map for each fundamental product that produces a I output in the truth
table. Enter Os elsewhere.
2. Encircle the octets, quads, and pairs. Remember to roll and overlap to get the largest groups possible.
3. If any isolated ls remain, encircle each.
4. Eliminate any redundant group.
5. Write the Boolean equation by ORing the products corresponding to the encircled groups.
Simplification of Entered Variable Map

This is similar to Kamaugh map method. Refer to entered variable maps shown in Fig. 3.10. The groupings
for these are as shown in Fig. 3.21a and Fig. 3.21b. Note that in Fig. 3.21a C' is grouped with 1 to get a larger
group as I can be written as 1 = 1 + C'. Similarly A is grouped with 1 in Fig. 3.21b.
~1:~ :r;
Next, the product term representing each group B B C C
is obtained by including map entered variable in the
group as an additional ANDed term. Thus, group 1 of
Fig. 3.21a gives B.(C') = BC' and group 2 givesAB.(1)
= AB resulting Y =BC'+ AB.
In Fig. 3.21 b, group 1 gives product term B.(A) = AB (a) (b) (c)
and group 2 gives BC'.(l) = BC' so that Y= BC'+ AB.
The final expression is same for both as they represent Simplification of entered
the same truth table (Table 3.6). variable map
Note that, entered variable map shown Fig. 3.21c
for a different truth table (Take it as an exercise to prepare that truth table) has only two product terms and
doesn't need a separate coverage of 1. This is because one can write 1 = C + C' and C is included in one group
while C' in other. The output of this map can be written as Y =AC+ BC'.
What is the simplified Boolean equation for the following logic equation expressed by
minterms?
Y=F(A,B,C,D)=I:.m(7,9, 10, 11, 12, 13, 14, 15)
Solution We know, each minterm makes corresponding location in I(arnaugh map 1 and thus Fig. 3.22a represents
the given equation. There are 110 octets, but there is a quad as shown in Fig. 3.22b. By overlapping, we can find two
more quads (see Fig. 3.22c). We can encircle the remaining l by making it part of an overlapped pair (Fig. 3.22d).
Finally, there are no redundant groups.
The horizontal quad of Fig. 3.22d corresponds to a simplified product AB. The square quad on the right corresponds
to AC, while the one on the left stands for AD. The pair represents BCD. By ORing these products, we get the
simplified Boolean equation:
Y=AB+AC+AD+BCD (3.30)
CD CD CD CD CD CD CD CD CDCD CD CD CD CDCD CD
AB 0 0 0 0 AB 0 0 0 0 AB 0 0 0 0 AB 0 0 0 0
AB 0 0 0 AB 0 0 1 0 AB 0 0 0 AB 0 0 0
AB
AB 0
l 1
1
l
l
1 AB
AB 0
~
1 1 1
A~~
ABO 1 1 1
AB
AB
1
0 l
(a) (b) (c) (d)
Using the Karnaugh map
10. Write the sum-of-product terms for the entries in Fig. 3.18. Use Boolean algebra to simplify
the expression.
3.6 DON'T-CARE CONDITIONS Truth Table with Don't-

Care Conditions
In some digital systems, certain input conditions
A B C D y
never occur during normal operation; therefore, the
corresponding output never appears. Since the output 0 0 0 0 0
never appears, it is indicated by an X in the truth table. 0 0 0 0
For instance, Table 3.8 on the next page shows a truth 0 0 l 0 0
table where the output is low for all input entries from 0 0 1 1 0
0000 to 1000, high for input entry 1001, and an X 0 1 0 0 0
0 1 0 0
for l O10 through 1111. The X is called a don 't-care
0 l 1 0 0
condition. Whenever you see anX in a truth table, you
0 1 1 l 0
can let it equal either O or 1, whichever produces a 1 0 0 0 0
simpler logic circuit. 1 0 0 1
Figure 3.23a shows the Karnaugh map of Table 1 0 1 0 X
3.8 with don't-cares for all inputs from 1010 to 1111. 1 0 1 1 X
These don't-cares are like wild cards in poker because 1 1 0 0 X
you can let them stand for whatever you like. Figure 1 0 1 X
3.23b shows the most efficient way to encircle the l. 1 l 0 X
1 X
Notice two crucial ideas. First, the 1 is included in a
quad, the largest group you can find if you visualize all X's as ls. Second, after the 1 has been encircled,
all X's outside the quad are visualized as Os. In this way, the Xs are used to the best possible advantage. As
already mentioned, you are free to do this because don't-cares coITespond to input conditions that never ap-
pear.
The quad of Fig. 3.23b results in a Boolean equation of
Y=AD
The logic circuit for this is an AND gate with inputs of A and D, as shown in Fig. 3.23c. You can check
this logic circuit by examining Table 3.8. The possible inputs are from 0000 to 1001; in this range a high A
and a high D produce a high Y only for input condition 100 I.
ci5 CD CD CD ci5 CD CD CD
AB AB
tttt=o-y
0 0 0 0 0 0 0 0
A BCD
AB 0 0 0 0 AB 0 0 0 0
AB
0
X X X X AB X X
AB 0 X X AB 0 X X
(a) (b) (c)
Don't-care conditions
Remember these ideas about don't-care conditions:

I. Given the truth table, draw a Kamaugh map with Os, Is, and don't-cares.
2. Encircle the actual ls on the Kamaugh map in the largest groups you can find by treating the don't-
cares as ls.
3. After the actual ls have been included in groups, disregard the remaining don't cares by visualizing
them as Os.
Suppose Table 3.8 has high output for an input of 0000, low output, for 0001 to 1001, and
don't cares for l O10 to 1111. What is the simplest logic circuit with this truth table?
Solution The truth table has a I output only CDCD CD CD

fortheinput condition 0000. The corresponding
fundamental product is ABCD. Figure 3.24a AB CD 0 0 0 ABc D
shows the Karnaugh map with a 1 for the AB 0 0 0 0
fundamental product, Os for inputs 0001 to
1001, andXs for inputs 1010 to UlL In this AB X X X X ~ y
case, the don't-cares are ofno help. The best AB 0 0 X X
we can do is to encircle the isolated 1, while
treating the don't-cares as Os. So, the Boolean (a) (b)
equation is
Y=ABCD Decoding 0000
Figure 3.24b shows the logic circuit. The 4-
inputAND gate produces a high output only for the input condition. A = 0, B = 0. C = 0, and D = 0.
Give the simplest logic circuit for following logic equation where d represents don't-care
condition for following locations.
F(A, B, C, D) = I,m(7) + d(lO, 11, 12, 13, 14, 15)
Solution Figure 3.25a is the Karnaugh map. CD CDCD CD

The most efficient encircling is to group the ls
AB 0 0 0 0
Ht=o-y
into a pair using the don't-care as shown. Since ABCD
this is the largest group possible, all remaining
don 'i cares are treated as Os. The equation for the
pair is
Y=BCD
and Fig. 3.25b is the logic circuit. This 3.input
AB
AB
AB
0
X
0
0
X
0
a
X
0
X
(a) (b)
AND gate produces a high output only for anin-
put of A = 0, B = 1, C = 1, and D I because
the input possibilities range only from 0000 to Decoding 0111
1001.
11. What is meant by a don't-care condition on a Karnaugh map? How is it indicated?

12. How can using don't-cares aid circuit simplification?
3.7 PRODUCT-Of-SUMS METHOD

With the sum-of-products method the design starts with a truth table that summarizes the desired input-output
conditions. The next step is to convert the truth table into an equivalent sum-of-products equation. The final
step is to draw the AND-OR network or its NAND-NAND equivalent.
The product-of-sums method is similar. Given a truth table, you identify the fundamental sums needed
for a logic design. Then by ANDing these sums, you get the product-of-sums equation corresponding to the
truth table. But there are some differences between the two approaches. With the sum-of-products method,
the fundamental product produces an output l for the corresponding input condition. But with the product-
of-sums method, the fundamental sum produces an output O for the corresponding input condition. The best
way to understand this distinction is with an example.
Converting a Truth Table to an Equation

Suppose you are given a truth table like Table 3.9 and you want to get the product-of-sums equation. What
you have to do is locate each output O in the truth table and write down its fundamental sum. In Table 3.9, the
first output O appears for A= 0, B = 0, and C = 0. The fundamental sum for these inputs is A+ B + C. Why?
Because this produces an output zero for the corresponding input condition:
Y=A+B+C=O+O+O=O
A B C y Max:term
0 0 0 0"""7A+B+C Mo
0 0 1 1 M1
0 I 0 I M2
0 1 l 0"""7A+B+C M3
I 0 0 I M4
1 0 1 I Ms
l I 0 0"""7A+B+C M6
l 1 I 1 M1
The second output Oappears for the input condition of A= 0, B = I, and C = 1. The fundamental sum for
this is A + B + C. Notice that B and Care complemented because this is the only way to get a logical sum
of O for the given input conditions:
Y=A+B+C=O+I+I=O+O+O=O
Similarly, the third output O occurs for A = l, B = I, and C = O; therefore, its fundamental sum is
A +B +C:
Y=A+B+C=T+T+O=O+O+O=O
Table 3.9 shows all the fundamental sums needed to implement the truth table. Notice that each variable is
complemented when the corresponding input variable is a l; the variable is uncomplemented when the corre-
sponding input variable is 0. To get the product-of-sums equation, all you have to do is AND the fundamental
sums:
Y =(A+ B + C)(A + B + C)(A + B + C) (3.31)
This is the product-of-sums equation for Table 3.9.
As each product term was called minterm in SOP representation in POS each sum term is called maxterm
and is designated by Mi as shown in Table 3.9. Equation 3.31 in terms ofmaxtenn can be represented as
Y = F(A, B, C) = IlM(O, 3, 6)
where 'Il' symbolizes product, i.e. AND operation. This kind ofrepresentation of a truth table is also known
as canonical productform.
logic Circuit
After you have a product-of-sums equation, you can get the logic circuit by drawing an OR-AND network,
or if you prefer, a NOR-NOR network. In Eq. (3.31) each sum represents the output of a 3-input OR gate.
Furthem10re, the logical product Y is the output of a 3-input AND gate. Therefore, you can draw the logic
circuit as shown in Fig. 3.26.
A 3-input OR gate is not available as a TTL chip. So, the circuit of Fig. 3.26 is not practical. With De
Morgan's first theorem, however, you can replace the OR-AND circuit of Fig. 3.26 by the NOR-NOR circuit
ofFig. 3.27.
A A B JJ C C
7427
2
A--r--..... 13
B
c-_,_---- 3
4
A-_.--..... 5
Jj y
c-_,_---- 9
10
1 _ __,---....
Jj 11
c-_,_-
Product-of-sums circuit
Conversion between SOP and POS

We have seen that SOP representation is obtained by considering ones in a truth table while POS comes
considering zeros. In SOP, each one at output gives one AND tem1 which is finally ORed. In POS, each zero
gives one OR term which is finally ANDed. Thus SOP and POS occupy complementary locations in a tmth
table and one representation can be obtained from the other by
(i) identifying complementary locations,
(ii) changing mintenn to maxtenn or reverse, and finally
(iii) changing summation by product or reverse.
Thus Table 3.9 can be represented as

Y = F(A, B, C) = ITM(O, 3, 6) = Lm(l, 2, 4, 5, 7)
Similarly Table 3.4 can be represented as
Y = F(A, B, C) = Lm(3, 5, 6, 7) = TIM(O, 1, 2, 4)
This is also known as conversion between canonical forms.
Suppose a truth table has a low output for the first three input conditions: 000, 001, and 010.
If all other outputs are high, what is the product-of-sums circuit?
Solution Theproduct-of~sums equation is

Y =(A+B+C)(A +B+ C)(A+ii +C)
circuit of Fig. 3.2Twill work if we reconnect the input lines as follows:
A: pins I, 3, andi
B: pins 2 and4
C: pins Band 11
s :pin10
: pin 5
Principles and Applications
13. A product-of-sums expression leads to what kind oflogic circuit?

14. Explain how to convert the complementary NAND-NAND circuit into its dual NOR-NOR
circuit
3.8 PRODUCT-Of-SUMS SIMPLIFICATION
After you write a product-of-sums equation, you can simplify it with Boolean algebra. Alternatively, you
may prefer simplification based on the Kamaugh map. There are several ways of using the Kamaugh map.
One can use a similar technique as followed in SOP representation but by forming largest group of zeros and
then replacing each group by a sum term. The variable going in the formation of sum term is inverted if it
remains constant with a value 1 in the group and it is not inverted if that value is 0. Finally, all the sum terms
are ANDed to get simplest POS fonn. We illustrate this in Examples 3.11 and 3.12. In this section we also
present an interesting alternative to above technique.
Sum-of-Products Circuit
Suppose the design starts with a truth table like Table 3.10. The first thing to do is to draw the Kamaugh map
in the usual way to get Fig. 3.28a. The encircled groups allow us to write a sum-of-products equation:
Y= AB +AB+AC
Figure 3.28b shows the corresponding NAND-NAND circuit.
Complementary Circuit
To get a product-of-sums circuit, begin by comple-
menting each O and 1 on the Kamaugh map of Fig.
3.28a. This results in the complemented map shown y
A B C D
in Fig. 3.28c. The encircled ls allow us to write the
following sum-of-products equation: 0 0 0 0 l
0 0 0 1 I
y =AB+ABC 0 0 l 0 1
Why is this Y instead of Y? Because complement- 0 0 l 1 l
ing the Kamaugh map is the same as complementing 0 1 0 0 0
the output of the truth table, which means the sum-of- 0 l 0 1 0
products equation for Fig. 3 .28c is for Y instead of Y. 0 1 I 0 0
0 1 1 I 0
Figure 3.28d shows the corresponding NAND- 1 0 0 0 0
NAND circuit for Y. This circuit does not produce l 0 0 1 0
the desired output; it produces the complement of the 1 0 1 0 1
desired output. I 0 1 1 1
l l 0 0 1
finding the NOR-NOR Circuit 1 1 0 1 l
1 l l 0 1
What we want to do next is to get the product-of-sums 1 l l l l
solution, the NOR-NOR circuit that produces the
Cl5 CD CD CD A
B
AB cCIT))
A y
AB 0 0 0 0
B
~~
ABO O I I
A
C
(a) (b)
Cl5 CD CD CD
A
AB 0 0 0 0 B
y
AB cCIT)) A
AB 0 0 0 0 B
AB CC]) 0 0
c
(c) (d)
Deriving the sum-of-products circuit
original truth table ofTable 3.10. De Morgan's first theorem tells us NAND gates can be replaced by bubbled
OR gates; therefore, we can replace Fig. 3.28d by Fig. 3.29a. A bus with each variable and its complement
is usually available in a digital system. So, instead of connecting A and B to a bubbled OR gate, as shown
in Fig. 3.29a, we can connect A and B to an OR gate, as shown in Fig. 3.29b. In a similar way, instead of
connecting A, B, and C to a bubbled OR gate, we have connected A, B, and C to an OR gate. In short,
Fig. 3.29b is equivalent to Fig. 3.29a.
The next step toward a NOR-NOR circuit is to convert Fig. 3.29b into Fig. 3.29c, which is done by sliding
the bubbles to the left from the output gate to the input gates. This changes the input OR gates to NOR gates.
The final step is to use a NOR gate on the output to produce Yinstead off, as shown in the NOR-NOR
circuit ofFig. 3.29d.
A A
B B
y y
A A
B B
c C
(a) (b)
A A
B B
y y
A A
B B
C C
(c) (d)
Deriving the product-of-sums circuit

From now on, you don't have to go through every step in changing a complementary NAND-NAND
circuit to an equivalent NOR-NOR circuit. Instead, you can apply the duality theorem as described in the
following.
Duality
An earlier section introduced the duality theorem of Boolean algebra. Now we are ready to apply this theo-
rem to logic circuits. Given a logic circuit, we can find its dual circuit as follows: Change each AND gate to
an OR gate, change each OR gate to an AND gate, and complement all input-output signals. An equivalent
statement of duality is this: Change each NAND gate to a NOR gate, change each NOR gate to a NAND gate,
and complement all input-output signals.
Compare the NOR-NOR circuit of Fig. 3.29d with the NAND-NAND circuit of Fig. 3.28d. NOR gates
have replaced NAND gates. Furthermore, all input and output signals have been complemented. This is an
application of the duality theorem. From now on, you can change a complementary NAND-NAND circuit
(Fig. 3.28d) into its dual NOR-NOR circuit (Fig. 3.29d) by changing all NAND gates to NOR gates and
complementing all signals.
Here is a summary of the key ideas in the preceding discussion:

1. Convert the truth table into a Karnaugh map. After grouping the ls, write the sum-of-products
equation and draw the NAND-NAND circuit. This is the sum-of-products solution for Y.
2. Complement the Karnaugh map. Group the 1s, write the sum-of-products equation, and draw the
NAND-NAND circuit for Y. This is the complementary NAND-NAND circuit.
3. Convert the complementary NAND-NAND circuit to a dual NOR-NOR circuit by changing all
NAND gates to NOR gates and complementing all signals. What remains is the product-of-sums
solution for Y.
4. Compare the NAND-NAND circuit (Step 1) with the NOR-NOR circuit (Step 3). You can use
whichever circuit you prefer, usually the one with fewer gates.
Show the sum-of-products and product-of-sums circuits for the Karnaugh map of Fig. 3.30a.
Solution The Boolean equatio11for Fig. J.30a ott the next page is
Y=A+BCD
f'igure 3.301:iis the sum-of-prod1.1cts circuit.
After colllplementing and simplifying the Kamaugh map, we get Fig. 3.30c. The Bool~ equation for this is
=AB+AC+AD
Figure 3 .30d is the sum-of-products ciffuit fo:rthe shown earlier, we can convert the dual circriitinto a NOR-
NOR equivalent circuit to get Fig. 3.30e:
The two desigtt choices are Fig. 3,30b and 3.30e, Fignre 3.30b is simpler.
AB 0 0 0
0
1
1 1
(a) (b) (c)
(d)
Give simplest POS form ofKarnaugh map shown in Fig. 3.30a by grouping zeros.
Solution Refer to grouping of zeros as shown in Fig. 3.31a. Three groups cover alHhe zeros that give three sum
terms. The first group has A' and C' constant witb-
CJ5 CD CD CD CJ5 CD CD CD
in tbe group that gives sum term (A+ C). Group 2
has A' and D constant giving sum term (A + JY). AB 0 1(2?
Group 3 has A' and B' constant generating (A + B)
as sum term .
AB 0
The final solution is thus product oftbese three AB l 1 1 1 AB X X l

sum terms and expressed as A1i 1 1 l 1 AB '-'"'_x_, X ~
Y =(A+ B) (A +C)(A+D')
(a) (b)
Note that, the above relation can be realized by
OR-AND circuit or NOR-NOR (Fig. 330e) cir-. Simplification by grouping zeros
cuit.
Give simplest POS form ofKarnaugh map shown in Fig. 3.31b by grouping zeros.
Solution In a Karnaugh map if don't care conditions exist, we may consider them as zeros if that gives larger group
size. This in turn reduces number ofliterals in tbe sum term. · Refer to grouping of zeros in Fig. 33lb; We require
minimum two groups that includes all the zeros and are also largest in sizes. In group 1, only C' is constant tbat gives
only one literal in. sum term as C. Group 2 has B' .and D' constant giving sum term CB+ D). The final solution is thus
produ<:t of tbese two sum terms and expressed as
= C(B+D)
3.9 SIMP[IFICATION BY QUINE-McCLUSKY METHOD
Reduction oflogic equation by Kamaugh map method though very simple and intuitively appealing is some-
what subjective. It depends on the user's ability to identify patterns that gives largest size. Also the method
becomes difficult to adapt for simplification of 5 or more variables. Quine-McClusky method is a systematic
approach for logic simplification that does not have these limitations and also can easily be implemented in
a digital computer.
Determination of Prime Implicants

Quine-McClusky method involves preparation of two tables; one determines prime implicants and the other
selects essential prime implicants to get minimal expression. Prime implicants are expressions with least
number of literals that represents all the terms given in a truth table. Prime implicants are examined to get
essential prime implicants for a particular expression that avoids any type of duplication. We illustrate the
method with a 4-variable simplification problem for truth table appearing in Table 3.10. Figure 3.32 shows
prime implicant determination table for the problem.
In Stage 1 of the process, we find out all the tenns that gives output 1 from truth table (Table 3.10) and put
them in different groups depending on how many l input variable combinations (ABCD) have. For example,
first group has no l in input combination, second group has only one 1, third two 1s, fourth three ls and fifth
four Is. We also write decimal equivalent of each combination to their right for convenience.
In Stage 2, we first try to combine first and second group of Stage I, on a member to member basis.
The rule is to see if only one binary digit is differing between two members and we mark that position by
Stage 1 Stage 2 Stage 3

ABCD ABCD ABCD
0000 (0)-v 000- (0,1)-V 00-- (0,1,2,3)
00-0 (0,2)-V 00-- (0,2,1,3)
0001 (1 )-V
0010 (2)..J 00- 1 (1,3)..J - 0 1- (2,10,3,11)
001- (2,3)-V
1- 1- (10,11,14,15)
-010 (2,10)-V
0011 (3)-V 1 - 1- (10,14,11,15)
101 0 (10)-V -0 11 (3,11)-V 1 1- - (12,13,14,15)
1100 (12)-V 10 1- (10,11)-V 1 1- - (12,14,13,15)
1- 10 (10,14)-V
110- (12, 13)-V
10 1 1 (11)-V 11- 0 (12,14)-V
1 10 1 (13)-V
1 1 10 (14)-V 1- 1 1 (11,15)-V
1I-1 (13,15)-V
1111 (15)-V 1 1 1- (14,15)-V
Determination of prime implicants

'-'. This means con-esponding variable is not required to represent those members. Thus (0) of first group
combines with (1) of second group to form (0,1) in Stage 2 and can be represented by A'B'C' (0 0 0 -). The
logic of this representation comes from the fact that mintermA'B'C'D' (0) andA'B'C'D (1) can be combined
as A'B'C'(D' + D) = A'B'C'. We proceed in the same manner to find rest of the combinations in successive
groups of Stage 1 and table them in Fig. 3.32. Note that, we need not look beyond successive groups to find
such combinations as groups that are not adjacent, differ by more than one binary digit. Also note that each
combination of Stage 2 can be represented by three literals. All the members of particular stage, which finds
itself in at least one combination of next stage are tick (V) marked. This is followed for Stage 1 terms as well
as tem1s of other stages.
In Stage 3, we combine members of different groups of Stage 2 in a similar way. Now it will have two'-'
elements in each combination. This means each combination requires two literals to represent it. For example
(0,1,2,3) is represented by A'B' (0 0- ). There are three other groups in Stage 3; (2,10,3,11) represented by
B'C, (10,14,11,15) by AC and (12,13,14,15) by AB. Note that, (0,2,1,3), (10,11,14,15) and (12,14,13,15) get
represented by A'B, AC and AB respectively and do not give any new tem1.
There is no Stage 4 for this problem as no two members of Stage 3 has only one digit changing among
them. This completes the process of detennination of prime implicants. The rule is all the tenns that are not
ticked at any stage is treated as prime implicants for that problem. Here, we get four of them from Stage 3,
namely A'B', B'C, AC, AB and none from previous stage as all the tenns there are ticked (V).
Selection of Prime Implicants

Once we are able to detennine prime implicants that covers all the tem1s of a truth table we try to select es-
sential prime implicants and remove redundancy or duplication among them. For this, we prepare a table as
shown in Table 3.11 that along the row lists all the prime implicants and along columns lists all mintenns.
The cross-point of a row and column is ticked if the tenn is covered by con-esponding prime implicant. For
example, terms O and 1 are covered by A'B' only while 2 and 3 are covered by both A'B' and B' C and the cor-
responding cross-points are ticked. This way we complete the table for rest of the tenns.
0 1 2 3 10 11 12 13 14 15
A'B' (0,1,2,3) '1 '1 '1 '1 I
B'C(2,3,l0,11) '1 '1 V '1
AC'(Ip,11,14'.15) '1 '1 '1 '1
AlJ (12,13,14,15) '1 '1 '1 '1
Selection of essential prime implicants from this table is done in the following way. We find minimum
number of prime implicants that covers all the minterms. We find A'B' and AB cover terms that are not cov-
ered by others and they are essential prime implicants. B' C and AC among themselves cover 10, 11 which are
not covered by others. So, one of them has to be included in the list of essential prime implicants making it
three. And the simplified representation of truth table given in Table 3.10 is one of the following
Y =A'B' + B'C+ AB or Y=A'B' + AC+ AB
Simplification of the same truth table by Kamaugh map method is shown in Fig. 3.28a and we see the
results are the same.
Now, how do you compare the complexity of this approach with Karnaugh map groupings? Yes, this
method is more tedious and monotonous compared to Karnaugh map method and people don't prefer it
for simplification problems with smaller number of variables. However, as we have mentioned before, for
simplification problems with large number of variables Quine-McClusky method can offer solution and
Karnaugh map does not.
Give simplified logic equation of Table 3.6 by Quine-McClusky method.
Solution Tables that determine prime implicants and selects essential prime in1plicants are shown in Figs. 3.33aand
3.33b .respectively. We find both the prime inlplicants are essential prime inlplicai1ts, The simplified logic .equation
thus is expressed as
Y=AB+BC'
Note that.we got the same expression by simplification entered. variable map shown iti Figs. 3.22a and 3.22b.
Stage2
ABC ABC
010 (2)'4 -1 0 (2,6)
l I6 (6)'4 1 1- (6,7)
(7)'4
Simplification by Quine-McClusky method for Example 3.14
15. \\That is a prime implicant? . ·.. .

16. \\lhat~re the advantages of Quine-McClusky metl3:od?
3.1 o HAZARDS AND HAZARD COVERS

In past few sections we have discussed in detail various simplification techniques that give minimal expres-
sion for a logic equation which in turn requires minimum hardware for realization of that. It may sound off-
beat, but due to some practical problems, in certain cases we may prefer to include more terms than given
by simplification techniques. The discussion so far considered gates generating outputs instantaneously. But
practical circuits always offer finite propagation delay though very small, in nanosecond order. This gives rise
to several hazards and hazard covers are additional terms in an equation that prevents occurring of them. In
this section, we discuss this problem and its solution.
Static-1 Hazard
This type of hazard occurs when Y =A+ A' type of situation appears for a logic circuit for certain combination
of other inputs and A makes a transition 1 ~ 0. An A + A' condition should always generate 1 at the output,
i.e. static-I. But the NOT gate output (Fig. 3.34a) takes finite time to become 1 following 1 ~ 0 transition of
A. Thus for the OR gate there are two zeros appearing at its input for that small duration, resulting a Oat its
output (Fig. 3.34b). The width of this zero is in nanosecond order and is called a glitch. For combinational
circuits it may go unnoticed but in sequential circuit, more particularly in asynchronous sequential circuit
(discussed in Chapter 11) it may cause major malfunctioning.
r 1 = NOT gate delay
A~y
A
A
y ~
_; r L r2 = OR gate delay
(a) (b)
Static-1 hazard
To discuss how we cover static- I hazard let's look at one example. Refer to Karnaugh map
shown in Fig. 3.35a, which is minimally represented by Y = BC' + AC. The corresponding circuit
is shown in Fig. 3.35b. Consider, for this circuit input B = 1 and A = 1 and then C makes transition
1~ 0. The output shows glitch as discussed above. Consider another grouping for the same map in Fig.
3.35c. This includes one additional term AB and now output Y =BC+ AC+ AB. The corresponding circuit
diagram is shown in Fig. 3.35d. This circuit though require more hardware than minimal representation, is
hazard free. The additional term AB ensures Y = 1 for A = I, B = I through the third input of final OR gate and
a 1 ~ 0 transition at C does not affect output. Note that, there is no other hazard possibility and inclusion of
hazard cover does not alter the truth table in anyway.
A -,----r----...._
c C C C
A C --t--r-----1L.__./
AB 0 0 AB o o
00
AB 0
AB%0
AB B AB 1 1
AB 0 C AB O 1
(a) Y=BC+AC (b) Circuit with static-I hazard (c) Y= BC+ AC+ AB (d) Hazard free circuit
Static-1 hazard and its cover

Again, a NAND gate with A and A' connected at its input for certain input combination will give static- I
hazard when A makes a transition O -+ 1 and requires hazard cover.
Static-0 Hazard
This type of hazard occurs when Y = A.A' kind of situation occurs in a logic circuit for certain combination
of other inputs and A makes a transition O -+ 1. An A.A' condition should always generate Oat the output,
i.e. static-0. But the NOT gate output (Fig. 3.36a) takes finite time to become O following a O-+ 1 transition
of A. Thus for final AND gate there are two ones appearing at its input for a small duration resulting a 1 at its
output (Fig. 3.36b). This Y= 1 occurs for a very small duration (few nanosecond) but may cause malfunction-
ing of sequential circuit.
A_J I
r 1 = NOT gate delay
A : I r2 = OR gate delay
A--c;:[)-y -i r1 ._!:-:::
_ _ __
_: r2 ~
A y---+--J I__.,.,
~
rJ , -
(a) (b)
Static-0 hazard
Again, we take an example to discuss how we can prevent static-0 hazard. We use the same
truth table as shown in Fig. 3.35a but form group of Os such that a POS form results. Figure 3.37a
shows the minimal cover in POS form that gives Y = (B + C)(A + C') and corresponding circuit in
Fig. 3.37b. But if B = 0, A= 0 and C makes a transition 0-+ 1 there will be static-0 hazard occurring at output.
To prevent this we add one additional group, i.e. one more sum term (A+ B) as shown in Fig. 3.37c and the
corresponding circuit is shown in Fig. 3.37d. The additional term (A + B) ensures Y = 0 for A = 0, B = 0
through the third input of final AND gate and a O -+ 1 transition at C does not affect output. Again note that
for this circuit there is no other hazard possibility and inclusion of hazard cover does not alter the truth table
in anyway.
c C c C
\9)
~
AB AB \9)
AB 1 AB 1
AB 1 AB 1
AB (o\ AB (o\
(a) Y= (B+C) (b) Circuit with static-0 hazard (c) Y= (B+C) (A+C) (d) Hazard free circuit
(A+C) (A+B)
Static-1 hazard and its cover
Also note, a NOR gate with A and A' connected at its input for certain input combination will give static-0
hazard when A makes a transition 1-+ 0 and requires hazard cover.
Dynamic Hazard
Dynamic hazard occurs when circuit output makes multiple transitions before it settles to a final value
while the logic equation asks for only one transition. An output transition designed as 1 ~ 0 may give
1 ~ 0 ~ 1 ~ 0 when such hazard occurs and a O ~ I can behave like O ~ 1 ~ 0 ~ I. The output of logic
equation in dynamic hazard degenerates into Y = A + A'.A or Y = (A + A').A kind of relations for certain
combinations of the other input variables. As shown by these equations, these occur in multilevel circuits
having implicit static-I and/or static-0 hazards. Providing covers to each one of them dynamic hazard can be
prevented.
Check if the circuit shown in Fig. 3 .38a exhibit dynamic hazard. Show how output varies
with time if dynamic hazard occurs. Consider all the gates have equal propagation delay of r
nanosecond. Also mention how the hazard can be prevented.
Solution Thelogiccircuit can bewritten inth{: form ofequation .. . (A.C +KC').C'. Cleady for A= 1, B = I we
=
geff (C+C').C which shows potential dynamic hazard with an iinplicit static- I hazard. Figure 3.38b shows how
a transition l -c* 0 at input CforAB = 1lrcauses dynamic hazard at the output.
The hazard can b~ preve~ted by using an aclditional two inpufAND gate fed by input A and B and replacing two in-
put ORgate by ailiree input OR gate. The additional (third)input of OR gate will be fed by output of the new AND
gate.
A ""High, ll= High

C f·
··• · ··.· .. · · r= Each gate delay
I l '
I !
I l
l I
I I
I
I
I
I
I
'
J'
y
Y---~-~-~, '
I I
r 2,: 3r
(b)
Example of dynamic hazard
What·isstatic.:.ffhazard?
Whafis dynamic hazard?
3.11 HDl IMPLEMENTATION MODELS
We continue our discussion of Verilog HDL description for a digital logic circuit from Chapter 2, Section
2.5. We have seen how structural gate level modeling easily maps a digital circuit and replicates graphical
symbolic representation. We have also seen how a simple test bench can be prepared to test a designed circuit.
There, we generated all possible combinations of input variables and passed it to a circuit to be tested by
providing realistic gate delays. We'll follow similar test bench but more ways to describe a digital circuit in
this and subsequent chapters.
Dataflow Modeling
Gate level modeling, though very convenient to get started with an HDL, consumes more space in describing
a circuit and is unsuitable for large, complex design. Verilog provides a keyword assign and a set of opera-
tors (partial list given in Table 3.11, some operations will be explained in later chapters) to describe a circuit
through its behavior or function. Here, we do not explicitly need to define any gate structure using and, or
etc. and it is not necessary to use intermediate variables through wire showing gate level interconnections.
Verilog compiler handles this while compiling such a model. All assign statements are concurrent, i.e. order
in which they appear do not matter and also continuous, i.e. any change in a variable in the right hand side
will immediately effect left hand side output.
A Partial List of Verilog Operator
Relational Operation Symbol

Less than < Bit..wise NOT
Less than or equal to <= Bit'.'wise AND &
Greater than > Bit-wise OR I
Equalto /\
Not equal to !=
Logical Operation(for expressions) Symbol A,rl~hllleticOperation Symbol
l3i~,tY. aqditi~n +
Logical NOT I3in;:uy suhtrac~on
LogicalAND && Binary ,ultiplicatiort *
Logical OR II Bit1ary divisi<>n
Now, we look at data flow model of two circuits shown in Fig. 2.17a and Fig. 2.38. We compare these
codes with gate level model code presented in Section 2.5 and note the advantage. We see that data .flow
model resembles a logic equation and thus gives a more crisp representation.
Behavioral Modeling
In a behavioral model, statements are executed sequentially following algorithmic description. It is ideally
suited to describe a sequential logic circuit. However, it is also possible to describe combinatorial circuits
with this but may not be a preferred model in most of the occasions. It always uses always keyword followed
by a sensitivity list. The procedural statements following always is executed only if any variable within
sensitivity list changes its value. Procedure assignment or output variables within always must be of register
type, defined by reg which unlike wire is not continuously updated but only after a new value is assigned to
it. Note that, wire variables can only be read and not assigned to in any procedural block, also it cannot store
any value and must be continuously driven by output or assign statement.
Now, let us try to write behavioral code for circuit given in Fig. 2.17a. We note that, Y = AB + CD, i.e.
Y = 1 if AB = 11 or if CD = 11, otherwise Y = 0. We use if.. . else if.. . else construct to describe this circuit.
Here, the conditional expression after if, if true executes one set of instructions else executes a different set
following else or none at all.
You can compare how logic circuit described in Fig. 2.17a is realized in Verilog HDL following three
different models two of which are described in this chapter and one in previous chapter. One might find
data fl.ow model more convenient to use for combinatorial circuits. We'll learn more about it in subsequent
chapters.
Realize the truth table shown in Kamaugh Map of Fig. 3.19 using data flow model.
Note that, - operator has higher precedence over & and I; while & and I are at same level. To avoid confu-
sion and improve readability it is always advised to use parentheses( ... ) that has second highest precedence
below bit select [ ... ].
The test bench for all the examples described in this chapter can be prepared in a mam1er similar to what
is described in Chapter 2. A simpler HDL representation to prepare a test bench will be discussed in Chapter
6.
PROBLEM SOLVING WITH MUtTIPLE METHODS

Get a minimized expression for Y=F(A, B, C) =ABC+ A BC+ ABC+ ABC
Solution We·can so!vethis usingBooleanAlgebra, KarnaughMap, Entered Variable Map and QMAlgorithm.
In Method-1 •We take help of Boolean Algebra for minimization, We see that A BC can be combined
. withall three terms using distributive law (Eq. 3.5)
Since, in Boolean algebraX =; X+ X + X( extending Eq. 3.7} we can write
Y= ABC +(ABC+ ABC+ ABC)+ ABC+ABC
From associative law (Eq. 3.3}
Y=(ABC + ABC)+(ABC+ ABC)+(ABC+ABC)
From distributive law(Eq. 3:5)
Y= AB(C + C)+ AC(B +B)+ BC(A +A)
From Eq. 3.9, since X+ X = 1
Y =AB · 1+ AC· I + BC· l
= AB BC (since,X· l =XfromEq. 3.10)
In Method-2, we use Kamaugh Map for minimization. Fig. 3.39 shows the solution by this meth-
od.
y AB AC
A B C
0 0 0 1
0 0 I 1
0 l 0 0
0 l 1
1 0 0 0
1 0 1 l
1 l 0 0
1 1 1
Y=AB + AC+ BC
Solution.· using· Karnaugh Map
Note how one term is·common in three groups ·formed and the similarity withMetho4- l soJutio,:i•.·
In Method-3, .we use Entered Variable Map for minimization. figure 3 .40 shows the so!utHm t>V
method.
Since 1 + C, we need a separate group for AB = 00 as C is not explained by other two groups.
We use C embedded in 1 to make other two groups bigger and reduce the number of literals, and thus
minimize the expression.
- - - - - - - - ~ IA\
, Combinational Logic Circuits
y
1
1 l
0 0
l l
0 0
J l BC
0 0 Y=AB+AC+BC
l 0
Solution using Entered Variable Map
In Method-4, we use QMalgorithmfor minimization. Fig. 3.41 shows prime implicants and essen-
tial prime implicants. The final solution is arrived at by combining essential prime implicants.
Stage 1 Stage 2
0 3 5
ABC ABC
A'B' '1
000 (0) '1 00- (0, 1)
001 (l) 0-1 (1, 3)

A'C
" "'
011 (3)
"' -01 (1, 5) B'C
"'
All are essential
IOI (5)
Y=A'B' + A'C+ B'C
Prime implicants only from stage 2.
Theyare:
00-(A'B'), 0-1 (A'C) and-01 (B'C)
Solution using QM Algorithm
Ev~ry Boolean equation has a dual form obtained by changing OR to AND, AND ~oOR, 0 to l,and 1 to
O.J,Vith Boolean algebra you maybe able to simplify a Boolean equation, which implies a simplified logic
circuit.
Given a truth table, you can identify the fundamental products that produce output ls. By ORing these
products, you get a sum-of-products equation for the truth table. A sum-of-products equation always
results in an AND-OR circuit or its equivalent NAND-NAND circuit
The Karnaugh method of simplifica.tion starts by converting a truth table intoaKarnaughmap.Ne}iit.
You encircle all the octets, quads, and pain,. Tl:µ§ allo'W's you t9 W¥~e ;:1 simplified Boolean .equati9u an<:l to
dra'; a simplified logic circuit. When a truth table contains don't-cares, you can treat the clon't:fares as ?s
or ls, whichever produces the greatest simplification. . .·. .· ....· . ···.. / . >
One way to get a product-of-sums circuit is to complement the Karnaugh map and write the simpli-
fied Boolean equation for Y . Next, you draw the NAND-NAND circuit for Y . Finally, you change the
NAND-NAND circuit into a NOR-NOR circuit by changing all NAND gates to NOR gates and comple-
menting all signals.
Entered variable map maps a. truth table intolower dimension space cgmpare(,l to Karnaugh map
though the simpHfication procedure is simUar. Quine-McQuskymethocl provide~ astee--py-step approach
for logic simplification and js. a preferred tool ~at involyes .large ~urnl:,er ofya:o.ables. Pr~c:tical digital
circuit requi~~s finite propagation. delay to tr~fer. infomiation from input t~ output. This 9ften leads to
hazards in the form of unwanted glitches. Hazards are. prevented by using additional gates serving al:l
hazard
" chip An integrated circuit. A piece of DIP. The LEDs in this troubleshooting tool
semiconductor material with a micro- indicate the logic states of the pins.
miniature circuit on its surface. 11
Karnaugh map A drawing that shows all the
• consensus theorem A theorem that simplifies fundamental products. and the corresponding
a Boolean equation removing a redundant output values of a truth table.
consensus theorem. • octet Eight adjacent ls in a 2 x 4 shape on a
" don't-care condition An input-output Kamaugh map.
condition that never occurs during normal • overlapping groups Using the same I more
operation. Since the condition never occurs, than once when looping the ls of a Kamaugh
you can use an X on the Kamaugh map. This map.
X can be a O or a 1, whichever you prefer. • pair Two horizontally or vertically adjacent 1s
" dual circuit Given a logic circuit, you can find on a Karnaugh map.
it dual as follows. Change each AND (NAND) " product-of-sums equation The logical product
gate to an OR (NOR) gate, change each OR of those fundamental sums that produce output
(NOR) gate to an AND (NAND) gate, and ls in the truth table. The corresponding logic
complement all input-output signals. circuit is an OR-AND circuit, or the equivalent
• Entered variable map an alternative to NOR-NOR circuit.
Karnaugh map where a variable is placed as • quad Four horizontal, vertical, or rectangular
output. ls on a Karnaugh map.
" Hazard unwanted glitches due to finite • redundant group A group of 1son a Kamaugh
propagation delay of logic circuit. map that are all part of other groups. You can
" Hazard cover additional gates in logic circuit eliminate any redundant group.
preventing hazard. " sum-of-products equation The logical sum
• Quine-McClusky method a tabular method of those fundamental products that produce
for logic simplification. output ls in the truth table. The corresponding
" logic clip A device attached to a 14- or 16-pin logic circuit is an AND-OR circuit, or the
equivalent NAND-NAND circuit.
Next, simplify the equation with Boolean

algebra and draw the simplified logic circuit.
3.1 Draw the logic circuit for 3.2 Draw the logic circuit for
Y=ABC+ABC y = (A + B + C) (A + B + C)
Use Boolean algebra to simplify the equation. c. Pin 9 is grounded.

Then draw the corresponding logic circuit. d. Pin 8 is shorted to +5 V.
3.3 In Fig. 3.42a, the output NAND gate acts like
a 2-input gate because pins 10 and 11 are tied
together. Suppose a logic clip is connected to
the 7410. Which of the three gates is defective 3.6 What is the sum-of-products circuit for the
if the logic clip displays the data of Fig. truth table of Table 3.11?
3.42b? 3.7 Simplify the sum-of-products equation in
Prob. 3.6 as much as possible and draw the
corresponding logic circuit.
A 3.8 A digital system has a 4-bit input from 0000
B
C
9 to 1111. Design a logic circuit that produces a
high output whenever the equivalent decimal
3 input is greater than 13.
A
B 3.9 We need a circuit with 2 inputs and 1 output.
c The output is to be high only when 1 input
(a) is high. If both inputs are high, the output is
to be low. Draw a sum-of-products circuit for
01 140
this.
02 139
83 120
@ =Off
04 119
0 =On
85 100
3 .10 Draw the Karnaugh map for Table 3.11.
86 90
e1 80
3 .11 Draw the Karnaugh map for Table 3 .13.
(b)
Pin 1
81 140
e2 139 Pin2
03 120
e =Off
04 110 Pin 13
0 =On
05 100
e6 90
07 80 Pin 12
(c) Pin3
Pin4
3.4 If a logic clip displays the states ofFig. 3.42c
for the circuit ofFig. 3.42a, which of the gates Pin5
is faulty?
+5V
3.5 The circuit of Fig. 3.42a has trouble. If Fig. Pin 6
3.43 is the timing diagram, which of the
+5V
following is the trouble: Pin 8
a. Upper NAND gate is defective.
b. Pin 6 is shorted to +5 V.
3.12 Show Kamaugh map for equation Y = F(A, B,

C) = I:m(l, 2, 3, 6, 7)
3 .13 Show Kamaugh map for equation Y = F(A, B, 3.19 Suppose the last six entries of Table 3.11 are
C, D) = I:m(l, 2, 3, 6, 8, 9, 10, 12, 13, 14) changed to don't-cares. Using the Karnaugh
map, show the simplified logic circuit.
3.20 Assume the first six entries of Table 3.13 are
3 .14 Draw the Kamaugh map for Table 3 .11. Then changed to don't-cares. What is the simplified
encircle all the octets, quads, and pairs you logic circuit?
3.21 Suppose the inputs 1010 through 1111 only ap-
can find.
3.15 Repeat Prob. 3.14 for Table 3.14. pear when there is trouble in a digital system.
Design a logic circuit that detects the presence
of any nibble input from 1010 to 1111.
3.16 What is the simplified Boolean equation for

the Kamaugh map of Table 3.13? The logic
circuit? 3.22 Draw the unsimplified product-of-sums circuit
3.17 Given Table 3.14, use Kamaugh simplification for Table 3.11.
and draw the simplified logic circuit. 3.23 Repeat Prob. 3.20 for Table 3.13.
3 .18 Table 3 .15 on the next page shows a special 3.24 Draw a NOR-NOR circuit for this Boolean
code known as the Gray code. For each binary expression:
input ABCD, there is a corresponding Gray- y =(A+ B + C)(A + B + C)(.f\ + B + C)
code output. What is the simplified sum-of- 3.25 Give SOP form of Y = F(A, B, C, D) IT M(O,
products equation for Y3? For Y2? For Y1? For 3, 4, 5, 6, 7, 11, 15)
Yo? Draw a logic circuit that converts a 4-bit 3.26 Draw Karnaugh map of Y = F(A, B, C, D) = IT
binary input to a Gray-code output. M(O, 1, 3, 8, 9, 10, 14, 15)
A B C D y A B C D y
0 0 0 0 0 0 0 0 0 0
0 0 0 I l 0 0 0 1 1
0 0 1 0 0 0 0 1 0 1
0 0 l l 0 0 0 I 1 l
0 1 0 0 0 0 1 0 0
0 1 0 1 1 0 I 0
0 l l 0 0 0 l 0 0
0 1 l 1 0 0 l 1
I 0 0 0 0 l 0 0 1
l 0 0 l 0 1 0 0 I l
l 0 l 0 1 I 0 I 0 I
1 0 l l 1 l 0 l 1 0
1 1 0 0 1 1 0 0 0
1 1 0 l 1 0 1 l
I l 1 0 0 0 0
I 1 1 1 0 I 0
Gray Code
A B C D Y3 Y2 Y1 Yo
0 0 0 0 0 0 0 0
0 0 0 0 0 0 l
0 0 0 0 0 l I
0 0 I l 0 0 1 0
0 0 0 0 1 0
0 0 l 0 1 1
0 1 0 0 0 1
0 l 1 I 0 0 0
1 0 0 0 1 0 0
1 0 0 1 l 0 l
1 0 0 I l
I 0 I 1 1 0
l 0 0 0 J 0
1 0 0 l
l l 0 I 0 0
1 1 0 0 0
3.30 You are given the following Boolean

equation
3.27 What is the simplified NOR-NOR circuit for Y=ABCD+ABCD +ABCD
Table 3.11? Show the simplified NAND-NAND circuit
3.28 Draw the simplified NOR-NOR circuit for for this. Also, show the simplified NOR-NOR
Table 3.13. circuit.
3.29 Figure 3.44 shows all the input waveforms for 3.31 Table 3.16 is the trnth table offidl adder,
the timing diagram of Fig. 3 .30e. Draw the a logic circuit with hvo outputs called the
waveform for the output Y. CARRY and the SUM. What is the simplified
NAND-NAND circuit for the CARRY output?
For the SUM output?
A 3.32 Repeat Prob. 3.27 using NOR-NOR circuits
8
B Full-Adder Truth Table
4 8 12
A B C Cany Sum
C
0 0 0 0 0
2 4 6 8 10 12 14
0 0 1 0 l
75 0 1 0 0 1
I 3 5 7 9 11 13 15 0 I l 0
y 1 0 0 0 1
1 0 I 0
I 0 0
1 1
3.33 Simplify to give POS form by grouping C c

zeros in Kamaugh map for equation given in AB
problem 3.27.
3.34 Simplify to give POS fonn by grouping AB o o
zeros in Kamaugh map for equation given in AB I 0
problem 3.28.
AB o
3.38 Verify with timing diagram if the following
circuit shows dynamic hazard.
3.35 Get simplified expression of Y = F(A, B, C, D)
= Z: m(l, 2, 8, 9, 10, 12, 13, 14) using Quine- A---~"-
B-,----1_ -__,,,
McClusky method.
3.36 Get simplified expression of Y = F(A, B, C, D, C'-"'-_.,.-...__
y
E)=Z:m(O, 1,2,3,4,5, 12, 13, 14,26,27,28,
29, 30) using Quine-McClusky method.
3.37 For the following Kamaugh map give SOP
and POS form that do not show static-0 or
static- I hazard.
AIM: The aim of this experiment is to verify Apparatus: 5 VDC Power supply,,Multi-
De Morgan's theorems meter,. and Bread Board
Theory: De Morgan's two theorems ate Work· element: Verify the truth table of IC
(A + B)' = A' · B' 7404;7408, 7432, 7402 and
7400.Intercon"
nect them, in such a manner so that right _hand
and (A· B)'=A' + B'
sides of the equations_ are implemented. Find
NAND gate and NOR gate can be used to its truth table. Compare it with truth table of
generate the left hand side of the two equations NORandNANDgates.
while NOT gate, AND gate and OR gate can be
used to generate the right hand side.
L False product..of~sUlns expression leads· directly

2. Y=AB+AC to an OR-AND circuit.
Y=Q ChangeallNAND gates.to.NOR.gates, and
Four, eight complement all signals (see Example 3,10).
5. False 15. Prime implicants are expressions with least
6. A Kamaugh map is a visual display· of the nUlllberofliterals that represents all the terms
fundamental products needed for a sum-of. given in a truth table.
products solution. 16. Systemati~, . step-by-step . approach that
Sixteen can .be itnplemented in adigital computer
8. Pair and providing solution for any number of
9. Eight variables.
Ht·· Xi== A.BCTi{+}BCD l7. A logiC high pulse of very short duration
when output should be at logic low,
Simplify as Y= BD
lL A don't-care condition is an input condition 18. Dynamic hazard occurs when circuit outpt1t
that never occurs during normal operations, makes before it settles
anditis indicated withanX: while asks for
12. An X can be used to create pairs, quads,
Data-Processing Circuits
+ Determine the output of a multiplexer or demultiplexer based on input conditions.

+ Find, based on input conditions, the output of an encoder or decoder.
+ Draw the symbol and write the truth table for an exclusive-OR gate.
+ Explain the purpose of parity checking.
+ Show how a magnitude comparator works.
+ Describe a ROM, PROM, EPROM, PAL, and PLA.
This chapter is about logic circuits that process binary data. We begin with a discussion of multiplexers,
which are circuits that can select one of many inputs. Then you will see how multiplexers are used as a design
alternative to the sum-of-products solution. This will be followed by an examination of a variety of circuits,
such as demultiplexers, decoders, encoders, exclusive-OR gates, parity checkers, magnitude comparator, and
read-only memories. The chapter ends with a discussion of programmable logic arrays and relevant HDL
concepts.
4~1 MUl.TIPLEXERS
Multiplex means many into one. A multiplexer is a circuit with many inputs but only one output. By applying
control signals, we can steer any input to the output. Thus it is also called a data selector and control inputs
are termed select inputs. Figure 4.la illustrates the general idea. The circuit has n input signals, m control
signals and 1 output signal. Note that, m control signals can select at the most 2111 input signals thus n ~ 2111 •
The circuit diagram of a 4-to- l multiplexer is shown in Fig. 4.1 c and its truth table in Fig. 4.1 b. Depending
on control inputs A, Bone of the four inputs Do to D 3 is steered to output Y.
Let us write the logic equation of this circuit. Clearly, it will give a SOP representation, each AND gate
generating a product term, which finally are summed by OR gate. Thus,
Y=A'B'.Do+A'B.D1 +AB'.D2+AB.D3
IfA = 0, B = 0, Y= O'O'.Do + O'.O.D1 + O.O'.D2 + O.O.D3
or, Y = 1.1.Do + l.O.D1 + O.l .D2 + O.O.D3
or, Y=D 0
In other words, for AB = 00, the first AND gate to which D0 is connected remains active and equal to Do
and all other AND gate are inactive with output held at logic 0. Thus, multiplexer output Y is same as D 0 . If
D 0 =0, Y=OandifD0 = 1, Y= 1.
Similarly, for AB= 01, second AND gate will be active and all other AND gates remain inactive. Thus,
output Y = D 1• Following same procedure we can complete the truth table of Fig. 4.1 b.
Control input
1 2----m
A
1
2
' 11-to-l Output
Data ''
Multiplexer
input :
n'
(a) y
A B y
0 0 Do
0 1 D1
1 0 D2
1 1 D3
(b) (c)
(a) Multiplexer block diagram, (b) 4-to-1 multiplexer truth table,

(c) Its logic circuit
Now, if we want 5-to- l multiplexer how many select lines are required? There is no 5th combination
possible with two select lines and hence we need a third select input. Note that, with three we
can select up to 23 = 8 data inputs. Commercial multiplexers ICs come in integer power of 2, e.g.
2-to-1, 4-to-1, 8-to- l, 16-to- l multiplexers. With this background, let us look at a 16-to- l multiplexer circuit,
which may look complex but follows same logic as that of a 4-to- l multiplexer.
16-to-1 Multiplexer
Figure shows a 16-to-l multiplexer. The input bits are labeled Do to D 15 . Only one of these is transmitted to
the output. Which one depends on the value of ABCD, the control input. For instance, when
ABCD=OOOO
the upper AND gate is enabled while all other AND gates are disabled. Therefore, data bit Do is transmitted
to the output, giving
Y=Do
If Do is low, Y is low; if Do is high, Y is high. The point is that Y depends only on the value of Do.
lfthe control nibble (group of 4-bits) is changed to
ABCD= 1111
all gates are disabled except the bottom AND gate. In this case, D 15 is the only bit transmitted to the output,
and
Y=D1s
As you can see, the control nibble determines which of the input data bits is transmitted to the output.
Thus we can write output as
Y=A' B'C'D'.Do + A B C D.D1 + A B CD'.D2 + ... + ABCD'.D14 + ABCD.D1s
1 1 1 1 1
At this point can we answer, how would an 8 to 1 multiplexer circuit look like? First of all we need three
select lines for 8 data inputs. And there will be 8 AND gates each one having four inputs; three from select
lines and one from data input. The final output is generated from an OR gate which takes input from 8 AND
gates. The equation for this can be written as
Y=A'B'C'.Do + A B C.D1 + A'BC'.D2 + A'BC.D3 + AB'C'.D4 + AB'C.Ds + ABC'.D6 + ABC.D7
1 1
Thus, for ABC= 000, multiplexer output Y = D 0 ; other AND gates and corresponding data inputs D 1 to D 7
remain inactive. Similarly, for ABC= 001, multiplexer output Y = D 1, for ABC= 010, multiplexer output Y =
D 2 and finally, for ABC= 111, multiplexer output Y = D7.
The 74150
Try to visualize the 16-input OR gate of Fig. 4.2 changed to a NOR gate. What effect does this have on the
operation of the circuit? Almost none. All that happens is we get the complement of the selected data bit
rather than the data bit itself. For instance, when ABCD = 0111, the output is
Y= D7
This is the Boolean equation for a typical transistor-transistor logic (TTL) multiplexer because it has an
inverter on the output that produces the complement of the selected data bit.
The 74150 is a 16-to-l TTL multiplexer with the pin diagram shown in Fig. 4.3. Pins 1 to 8 and 16 to 23 are
for the input data bits D 0 to D 15 . Pins 11, 13, 14, and 15 are for the control bits ABCD. Pin 10 is the output;
and it equals the complement of the selected data bit. Pin 9 is for the STROBE, an input signal that disables or
enables the multiplexer. As shown in Table 4.1, a low strobe enables the multiplexer, so that output Yequals
the complement of the input data bit:
Y= D,,
where n is the decimal equivalent of ABCD. On the other hand, a high strobe disables the multiplexer and
forces the output into the high state. With a high strobe, the value of ABCD doesn't matter.
A B C D
,D ~· Pl ~
.----i /
1st AN D gate output: A 'B'C' D~D 0
/
2nd AND gate output: A'B'C' D.D 1
I
......____J ) 3rd AND gate output: A 'B'C D~D 2

I
/ 4th AND gate output: A'B'C D.D 3
\
5th AND gate output: A'BC' D~D4
1----l
I
)
6th AND gate output: A'BC' D.D 5
I
I
......____J I 7th AN D gate output: A 'BC D'.D6

~
-
I
8th AN D gate output: A 'BC D.D7

I
y
I
......____J 9th AND gate output: AB'C' D~D8
J
~
- 10th AND gate output: AB'C' D.D 9

I
I
......____J ) llthAND gate output: AB'C D'.D 10

I
/
12th AND gate output: AB'C D.D 11
\ 13th AND gate output: ABC' D~D 12

.----i J
\
J 14th AND gate output: ABC'D.D 13
I
\
----1 /
15th AND gate output: ABC D'.D 14
/ 16th AND gate output: ABC D.D 15
Sixteen-to-one multiplexer
74150 Truth Table

D7
Strobe A B C D y
D6
-
L L L L L Do
Ds
L L L L H Di
D4 L L L H L
-
D2
D, L L L H H -
DJ
-'
L L H L L
-
D4
D2 L L H L H
-
74150 Ds
D1 L L H H L
-
D6
L L H H H ~
Do
L H L L L Dg
STROBE
L H L L H
-
D.)
y L H L H L Dio
L H L H H
-
A D11
L H H L L Di2
GND L H L H
H Di3
L H H H L -
D14
Pinout diagram of 74150 L H H H H
-
Dis
H X X X X H
Multiplexer logic
Digital design usually begins with a truth table. The problem is to come up with a logic circuit that has the
same truth table. In Chapter 3, you saw two standard methods for implementing a truth table: the sum-of-
products and the product-of-sums solutions. The third method is the multiplexer solution. For example, to use
a 74150 to implement Table 4.2. Complement each Youtput to get the corresponding data input:
Do= 1 = 0
D1 = 0 = I
D2 = 1 =0
and so forth, up to
D,s =I= 0
Next, wire the data inputs of74150 as shown in Fig. 4.4, so that they equal the foregoing values. In other
words, Do is grounded, D 1 is connected to +5 V, D2 is grounded, and so forth. In each of these cases, the data
input is the complement of the desired Youtput of Table 4.2.
Figure 4.4 is the multiplexer design solution. It has the same truth table given in Table 4.2. If in doubt,
analyze it as follows for each input condition. When ABCD = 0000, D 0 is the selected input in Fig. 4.4.
Since Do is low, Y is high. When ABCD = 0001, D 1 is selected. Since D 1 is high, Y is low. If you check the
remaining input possibilities, you will see that the circuit has the truth table given in Table 4.2.
Bubbles on Signal lines

Data sheets often show inversion bubbles on some of the signal lines. For instance, notice the bubble on pin
10, the output of Fig. 4.4. This bubble is a reminder that the output is the complement of the selected data
bit.
A B C D
A B C D y 11 13 14 15
+5V
0 0 0 8
0 I Do
0 0 0 1 0 7
D1
0 0 l 0 I 6
Dz
0 0 1 1 1 5 24
D3 +Vee
0 0 0 I 4
D4
0 0 1 I 3
0 1 I 0 0 D5
2
0 1 I l 0 D6
10 y
1 0 0 0 l D1
23 74150
I 0 0 1 1 Ds
22
1 0 1 0 I D9
l I 21
I 0 1 D10
1 1 0 0 1 20 9
Dll STROBE
l 1 0 1 1 19
D12
1 1 0 0 18 12
D13 GND
1 1 1 17
D14 -
16
D15
-
Using a 74150 for multiplexer
logic
Also notice the bubble on the STROBE input (pin 9). As discussed earlier, the multiplexer is active
(enabled) when the STROBE is low and inactive (disabled) when it is high. Because of this, the STROBE is
called an active-low signal; it causes something to happen when it is low rather than when it is high. Most
schematic diagrams use bubbles to indicate active-low signals. From now on, whenever you see a bubble on
an input pin, remember that it means the signal is activealow.
Universal logic Circuit

Multiplexer sometimes is called universal logic circuit because a 2n-to-l multiplexer can be used as a design
solution for any n variable truth table. This we have seen for realization of a 4 variable truth table by 16-to-l
multiplexer in Fig. 4.5. Here, we show how this truth table can be realized using an 8-to-l multiplexer. Let's
consider A,B and C variables to be fed as select inputs. The fourth variable D then has to be present as data
input. The method is shown in Fig. 4.5a. The first three rows map the truth table in a different way, similar
to the procedure we adopted in entered variable map (Section 3.3). We write all the combinations of3 select
inputs in first row along different columns. Now corresponding to each value of 4th variable D, truth table
ABC 000 001 010 011 100 101 110 111

D=O 1 1 1 0 1 1 1 0
D= 1 0 I 1 0 I 1 1 1
y D' 1 1 0 1 1 1 D
8-to-l MUX D 0 =D' D1= 1 D2 = 1 D 3 =0 D4 = 1 D 5 = I D6 = 1 D 7 =D
data input
(a)
D +5v
A B C
0
1
2
3 y
4
5
6
7
(b)
A four variable truth table realization using 8-to-1 multiplexer
output Y is ·written in 2nd and 3rd row. The 4th row writes Y as a function of D. In fifth row we assign data
· input values for 8-to- l multiplexer simply copying Y values obtained in previous row. This is because for
each select variable combination a multiplexer transfers a particular input to its output. In 8-to- l multiplexer,
ABC= 000 selects Do, ABC= 001 selects D 1 and so on. The corresponding circuit is shown in Fig. 4.5b.
Note that, we can choose any of the four variables (A,B,C,D) of truth table to feed as input to 8-to-l
multiplexer but then mapping in first three rows of Fig. 4.5a will change. The rest of the procedure will
remain same. We show an alternative to this technique for a new problem in Example 4.2.
Nibble Multiplexers
Sometimes we want to select one of two input nibbles. In this case, we can use a nibble multiplexer like the
one shown in Fig. 4.6. The input nibble on the left is A3A 2A1Ao and the one on the right is B 3B2B 1B 0 . The
control signal labeled SELECT determines which input nibble is transmitted to the output. When SELECT is
low, the four NAND gates on the left are activated; therefore,
Y3 Y2Y1 Yo= A3A2A1Ao
When SELECT is high, the four NAND gates on the right are active, and
Y3 Y2Y1 Yo =B3B2B1Bo
Figure 4.7a on the next page shows the pinout diagram of a 74157, a nibble multiplexer with a SELECT
input as previously described. When SELECT is low, the left nibble is steered to the output. When SELECT ,
Nibble multiplexer
is high, the right nibble is steered to the output. The 74157 also includes a strobe input. As before, the strobe
must be low for the multiplexer to work properly. When the strobe is high, the multiplexer is inoperative.
SELECT
A3 STROBE
B3 2 5 11 14 3 5 10 13
Y3 SELECT
74157 74157
A2 15
STROBE
B2 4 7 9 12
Y2
GND
(a) (b)
Pinout diagram of 74157
Figure 4.7b shows how to draw a 74157 on a schematic diagram. The bubble on pin 15 tells us that
STROBE is an active-low input.
Show how 4-to-l multiplexer can be obtained using only 2-to-l multiplexer.
Logic equation for 2-to-+Multiplexer:

Logic equation for 4-to-1 Multiplexer: Y = A'B' Do+ A'BD 1 + AB' D2 + AB.D3
This can be rewritten as, Y=A'(B'.Do + B.Di) +A(B'D2 + B.D3)
Compare this with equation of2~to-1 multiplexer. We need two 2-to-1 multiplexer to realize two bracketed terms
where B serves as select input The output of these two multiplexers can be sent to a third multiplexer as data inputs
where A serves as selectinput and we get the 4-to~ l multiplexer. Figure 4.8a shows circuit diat,rrarn for this.
(a) Realize Y=A'B + B'C' + ABC using an 8-to-l multiplexer. (b) Can it be realized with a 4-to-l multiplexer?
Solution
(a) First we express Y as a function of mintenns of three variables. Thus
Y A'B + B'C' + ABC
Y =A'B(C' + C)+B'C'(A' + A)+ ABC[As,X+X'= I]
Y = A'B'C' + A'BC' + A'BC + AB'C' + ABC
Comparing this with equation of 8 to 1 multiplexer, we find by substituting Do = D 2 = D3 D4 = D1 = I and
Di = Ds = D6 = 0 we get given logic relation.
(b) Let variables A and B be used .as selector in 4 to 1 multiplexer .and C fed as input The 4-to-1 multiplexer
generates 4 minterms for different combinations of AB. We rewrite given logic equation in such a way that all
tliese terms/are present inJhe equation.
Y =A'B+B'C' +ABC
Y =A'B+ B'C'(A' +A)+ ABC [As,X +X' = I]
Y =A'B'.C' + A'B.I +AB'.C' + AB.C
Compare above with equation of a4-to-l multiplexer. We see Do= C', D 1 = I, D2 C' andD3 = Cgenerate the
given logic function.
Design a 32-to- l multiplexer using two 16-to-l multiplexers and one 2-to-l multiplexer.
Solution The circuit diagram is shown in Fig. 4.8b. A 32-to-l nmltiplexerrequires log232 =.5 select lines say,
ABCDE. The Iower4 select lines BCDEchose 16-to-l multiplexeroutputs. The 2-to-1 multiplexer chooses one of the
output of two 16-to-l multiplexers depending on what appears in the 5th selectliue, A.
B BCDE
0
A
y y
(a) (b)
Realization of higher order multiplexers using lower orders

1. A circuit with many inputs but only one output is called a _ _ .

2. What is the significance of the bubble on pin lO of the multiplexer in Fig. 4.5?
4.2 DEMUlTIPU:XERS
Demultiplex means one into many. A demultiplexer is a logic circuit with one input and many outputs. By
applying control signals, we can steer the input signal to one of the output lines. Figure 4.9a illustrates the
general idea. The circuit has 1 input signal, m control or select signals and n output signals where n :::; 2111 •
Figure 4.9b shows the circuit diagram of a 1-to-2 demultiplexer. Note the similarity of multiplexer and
demultiplexer circuits in generating different combinations of control variables through a bank of AND gates.
Figure 4.9c lists some of the commercially available demultiplexer ICs. Note that a demultiplexer IC can also
behave like a decoder. More about this will be discussed in next section.
Control input
1 2 m
---{ A DEMUX Decoder
D IC No. Type Type
1
2
74154 1-to-16 4-to-16
Input Output
74138 1-to-8 3-to-8
n 74155 l-to-4 2-to-4
(a) (b) (c)
(a) Demultiplexer block diagram, (b) Logic circuit of 1-to-2 demultiplexer,

(c) few commercially available ICs
1-to-16 Demultiplexer
Figure 4.10 shows a l-to-16 demultiplexer. The input bit is labeled D. This data bit (D) is transmitted to the
data bit of the output lines. But which one? Again, this depends on the value of ABCD, the control input.
When ABCD = 0000, the upper AND gate is enabled while all other AND gates are disabled. Therefore, data
bit Dis transmitted only to the Yo output, giving Yo= D. If Dis low, Yo is low. If D is high, Yo is high. As you
can see, the value of Y0 depends on the value of D. All other outputs are in the low state. If the control nibble
is changed to ABCD = 1111, all gates are disabled except the bottom AND gate. Then, D is transmitted only
to the Y1s output, and Y1s = D.
The 74154
The 74154 is a l-to-16demultiplexer with the pin diagram ofFig. 4.11. Pin 18 is for the input DATAD, and
pins 20 to 23 are for the control bits ABCD. Pins l to 11 and 13 to 17 are for the output bits Yo to Y15 • Pin 19
is for the STROBE, again an active-low input. Finally, pin 24 is for Vcc and pin 12 for ground.
A B C D
V V V' V
DATAD
I
I
I
..
..
.
1-to- t 6 demultiplexer
Table 4.3 shows the truth table of a 74154. First, notice the STROBE input. It must be low to activate the
74154. When the STROBE is low, the control inputABCD determines which output lines are low when the
DATA input is low. When the DATA input is high, all output lines are high. And, when the STROBE is high,
all output lines are high.
Strobe Data A B C D
L L L L
L L L H
L L L H L
L L L H H
L H L L
L H L H
L H H L
L H H H
H L L L
H L L H
H L H L
H L H H
H H L L
H H L H
H H H L
H H H H
X X X X
X X X X
H H X X X X
ABC D
20 21 22 23
1
Yo
2
Y1
3
Y2
4
Y3
5
Y4
6
Ys
7 y6
74154 18
DATA 8
Y7
74154 9
19 Ys
STROBE 10
Y9
11
Y10
13 yll
14
Y12
15 y
16 13
-Y14
17 y
15
Pinout diagram of 74154 Logic diagram of 74154
Figure 4.12 shows how to draw a 74154 on a schematic diagram. There is one input DATA bit (pin 18)
under the control of nibble ABCD. The DATA bit is automatically steered to the output line whose subscript is
the decimal equivalent of ABCD. Again, the bubble on the STROBE pin indicates an active-low input. Notice
that DATA is inverted at the input (the bubble on pin 18) and again on any output (the bubble on each output
pin). With this double inversion, DATA passes through the 74154 unchanged.
In Fig. 4.13a, what does the Y12 output equal for each of the following conditions:
a. R is high, Tis high, ABCD = 0110.
b. R is low, Tis high, ABCD = llOO.
c. R is high, Tis high, ABCD = 1100.
Solution
Since1(and Tare bothhigh,the STROBE is low and the 7 4154:is active. Because ABCD "" 0110, the input data
is steered to .theY6 output lint: (pill)). ;rile .Y\2 oµtputxemaills in the high. state (seeTable4.3);
b. Here, the .STROBE is high andthe}4154 is inactive. 'fhe Xr2 9utputis bigµ.
c. \VithJ? and Tbothhigh, tµe STROBEislow and the74154is actixe. Since ABC[)=
steered to the Y12 output (pin· 14).
Show how two l-to-16 demultiplexers can be connected to get a l-to-32 demultiplexer.
Solution Figure 4J 3b shows fhe circuit diagram. Al,-to-32 demultiplexer has 5 select vllriableRA.lfCpE. four.of
the~J~C:DE) ar~fed to nvo l-to-16 de!13Ul~ple':{er. :b11d thr fifth (A) i~ us~dt0, ~:eft~n~ of ~esJ nvo multirl.e:>1:li!r
thr?ughstrobe inpptifA ~ 0,th~top 7I4154is hos~naridBCDE directs datato.one.<>fth~ 15 outpt1~tth~tIC. If
A = i,the bottorn: IC is chosen and depending on7
valueofBCDEdata is directed to one ofthe15outputs this IC.
@ Digital Principles and Applications
A B CD
20 21 22 23 A BCDE
1
Yo
2
3
Yi ! Yo
Y2
_fl___fl_ 4 DATA Y1
Y3
t1 tz t3 t4 18 5 74154
Y4
DATA 6
Y5 STROBE 15 Y1s
7 y6
8
Y7
R 19 74154 9 Ys BCDE
T STROBE 10
11
Y9
Yw
!0 Y16
13 yil
14 DATA I Y17
Y12 D
15 74154
Y13
16 STROBE
Y14 15 Y31
17
Y15
(a) (b)
:Alogicdtcuiftth one inp~t and many outputs is called a __..

Forthe74154 demultiplexer, what must the logic levels ABCD be in order to steer the DATA
inputsignalto outputline Y10?
5. IfAJJ<;P = LHLH, DATA= and STROBE = H, what wHI the logic level be at Ys on a
74154?
4.3 l-OF-16 DECODER
A decoder is similar to a demultiplexer, with one exception-there is no data input. The only inputs are the
control bits ABCD, which are shown in Fig. 4.14. This logic circuit is called a l-of-16 decoder because only
1 of the 16 output lines is high. For instance, when ABCD is 0001, only the Y1 AND gate has all, inputs high;
therefore, only the Y1 output is high. If ABCD changes to O100 only the Y4 AND gate has all inputs high; as
a result, only the Y4 output goes high.
If you check the other ABCD possibilities (0000 to 1111 ), you will find that the subscript of the high output
always equals the decimal equivalent of ABCD. For this reason, the circuit is sometimes called a binary-to~
decimal decoder. Because it has 4 input lines and 16 output lines, the circuit is also known as a 4-line to
16-line decoder.
Normally, you would not build a decoder with separate inverters and AND gates as shown in
Fig. 4.14. Instead, you would use an IC such as the 74154. The 74154 is called a decoder-demultiplexer,
because it can be used either as a decoder or as a demultiplexer.
A B C D
v·v·ru.ru
u-
n-
u-
u-
u-
u- -
-
u-
n-
u-
u-
1-of-16 decoder
You saw how to use a 74154 as a demultiplexer in Sec. 4.2.To use this same IC as a decoder, all you have
to do is ground the DATA and STROBE inputs as shown in Fig. 4.15. Then, the selected output line is in the
low state (see Table 4.3). This is why bubbles are shown on the output lines. They remind us that the output
line is low when it is active or selected. For instance, if the binary input is
ABCD=Olll
then the Y7 output is low, while all other-outputs are high.
ABC D
20 21 22 23
l
Yo
2
Y1
3
Y2
4
Y3
5
Y4
6
Ys
7 y6
18
DATA 8
Y7
74154 9
19 Yg
STROBE 10
Y9
II
- 13
Yw
Y11
14
Y12
15
Y13
16
Y14
17
Y15
Using 7 4154 as decoder
Figure 4.16 illustrates chip expansion. We have expanded two 74154s to get a 1-of-32
decoder. Here is the way.the circuit works. BitX drives the first 74154, and the complement of
X drives the second 74154. When Xis low, the first 74154 is active and the second is inactive.
74154 74154
Yo Yo
2 2
Y1 Yi
}'. 3 y: 3
19 19
STROBE/ 4 STROBE/ 4
18 3 18 3
X DATA 5 DATA 5
Y4 Y4
6 6
20 Ys 20 Y5
A A y6
7 A y6
7
21 8 21
B B B 8
22 Y7 22 Y7
C
23
C Yg 9 2t3
C Yg 9
D D Y9
10 D 10
Y9
11 11
Y10 Yw
13 13
Yu Yu
14 14
Y12 f12
15 15
Y13 Y13
16 16
Y14 Y14
17 17
Y15 Y15
Chip expansion
The ABCD input drives both decoders but only the first is active; therefore, only one output
line on the first decoder is in the low state.
On the other hand, when Xis high, the first 74154 is disabled and the second one is enabled.
This means the ABCD input is decoded into a low output from the second decoder. In effect,
the circuit ofFig. 4.16 acts like a l-of-32 decoder.
In Fig. 4.16, all output lines are high, except the decoded output line. The bubble on each
output line tells anyone looking at the schematic diagram that the active output line is in the
low state rather than the high state. Similarly, the bubbles on the STROBE and DATA inputs
of each 74154 indicate active-low inputs.
Show how using a 3-to-8 decoder and multi-input OR gates following Boolean expressions
can be realized simultaneously.
Fi (A, B, C) = l:m(O, 4, 6); F2(A, B, C) = l:m(O, 5); F2(A, B, C) = l:m(l, 2, 3, 7)
Solution Since .• attlltl.iecocli;:r (}ll;tpll;tWtlget a}\ ttltl Illinterrns.we.use. thelll.as .i,howniµ Fig, 4l,17 .to.getthtl req~red
Boolean. functions.
BCD-TO-DECIMAL DECODERS
BCD is an abbreviation for binary-coded decimal. The BCD code expresses each digit in a decimal number
by its nibble equivalent. For instance, decimal number 429 is changed to its BCD form as follows:
4 2 9
t t t
0100 0010 1001
To anyone using the BCD code, 0100 0010 1001 is equivalent to 429.
As another example, here is how to convert the decimal number 8963 to its BCD form:
8 9 6 3
t t t t
1000 1001 0110 0011
Again, we have changed each decimal digit to its binary equivalent.
Some early computers processed BCD numbers. This means that the decimal numbers were changed into
BCD numbers, which the computer then added, subtracted, etc. The final answer was converted from BCD
back to decimal numbers.
Here is an example of how to convert from the BCD form back to the decimal number:
0101 0111 1000
t t t
5 7 8
As you can see, 578 is the decimal equivalent of010I 0111 1000.
One final point should be considered. Notice that BCD digits are from 0000 to 1001. All combinations
above this (1010 to 1111) cannot exist in the BCD code because the highest decimal digit being coded is 9.
BCD-to-Decimal Decoder
The circuit of Fig. 4.18 is called a l-of-10 decoder because only 1 of the 10 output lines is high. For instance,
when ABCD is 0011, only the Y3 AND gate has all high inputs; therefore, only the Y3 output is high, IfABCD
changes to 1000, only the Y8 AND gate has all high inputs; as a result, only the Y8 output goes high.
If you check the other ABCD possibilities (0000 to 1001 ), you will find that the subscript of the high
output always equals the decimal equivalent of the input BCD digit. For this reason, the circuit is also called
a BCD-to-decimal converter.
The 7445
Typically, you would not build a decoder with separate inverters and AND gates, as shown in Fig. 4.18.
Instead, you would use a TTL IC like the 7445 ofFig. 4.19. Pin 16 connects to the supply voltage Vcc and pin
8 is grounded. Pins 12 to 15 are for the BCD input (ABCD), while pins I to 7 and 9 to 11 are for the outputs.
This IC is functionally equivalent to the one in Fig. 4.18, except that the active output line is in the low state.
All other output lines are in the high state, as shown in Table 4.4. Notice that an invalid BCD input (1010 to
1111) forces all output lines into the high state.
The decoded outputs of a 7445 can be connected to light-emitting diodes (LEDs), as shown
in Fig. 4.20. If each resistance is I kQ and each LED has a forward voltage drop of2 V, how
much current is there through a LED when it is conducting? (See Chapter 13 for a discussion
of LEDs.)
A B C D
11\7 1\7 '1\7 1\7
n-
u-
u-
n- 7445
n-
u- Pinout diagram of
1-of-10 decoder 7445
7445 Truth Table
Inputs
No. A B C D Yo
0 L L L L L
l L L L H H
2 L L H L H
L L H H H
4 L H L L H H
L H L H H H
L H H L H H
L H H H H H
8 H L L L H H
9 H L L H H H
H L H L H H
H L H H H H
H H L L H H
H H L H H H
H H H L H E
H H H H H H
.,,..,,. .,,..,,.
7445
Yo 2 3 4 5 6 7 8 9
16
Vee Y1
3
Y2
4
12 Y3
A 5
13 Y4
B 6
14 Ys
C 7
15 y6
D 9
Y7
10
Ys
8 11
GND Y9
-
Circuit for Example 4.7
The LEDs of Fig. 4.20 are numbered O through 9. Which of the LEDs is lit for each of the
following conditions:
a. ABCD=OIOI.
b. ABCD = 1001.
c. ABCD = 1100.
A LED emits radiation when forward-biased. Why? Because free electrons recombine with holes near the
junction. As the free electrons fall from a higher energy level to a lower one, they give up energy in the form
of heat and light. By using elements like gallium, arsenic, and phosphorus, a manufacturer can produce LEDs
that emit red, green, yellow, blue, orange and infrared (invisible) light. LEDs that produce visible radiation
are useful in test instruments, pocket calculators, etc.
Seven-Segment Indicator
Figure 4.21 a shows a seven-segment indicator, i.e. seven It L
LEDs labeled a through g. By forward-biasing different LI _I
LEDs, we can display the digits O through 9 (see Fig. i-
I
4.21b). For instance, to display a 0, we need to light up I i I
segments a, b, c, d, e, and/ To light up a 5, we need
segments a, c, d,f, and g. I I t
I
Seven-segment indicators may be the common-anode
type where all anodes are connected together (Fig.
4.22a) or the common-cathode type where all cathodes LI
are connected together (Fig. 4.22b). With the common- I
anode type of Fig. 4.22a, you have to connect a current- (a) (b)
limiting resistor between each LED and ground. The
size of this resistor determines how much current flows Seven-segment indicator
through the LED. The typical LED current is between I
and 50 mA. The common-cathode type of Fig. 4.22b uses a current-limiting resistor between each LED and
+Vee·
a b c d e f g
a b c d e f g
(a) (b)
(a) Common-anode type, (b) Common-cathode type
The 7446
A seven-segment decoder-driver is an IC decoder that can be used to drive a seven-segment indicator. There
are two types of decoder-drivers, corresponding to the common-anode and common-cathode indicators. Each
decoder-driver has 4 input pins (the BCD input) and 7 output pins (the a through g segments).
Figure 4.23a shows a 7446 driving a common-anode indicator. Logic circuits inside the 7446 convert the
BCD input to the required output. For instance, if the BCD input is 0111, the internal logic (not shown) of the
7446 will force LEDs a, b, and c to conduct. As a result, digit 7 will appear on the seven-segmentindicator.
Notice the current-limiting resistors between the seven-segment indicator and the 7446 of
Fig. 4.23a. You have to connect these external resistors to limit the current in each segment to a safe value
between I and 50 mA, depending on how bright you want the display to be.
BCD input
'TBCD'
7448
Decoder/driver
13 12 11 10 9 15 14
7446 Decoder/driver
-~-
i I ~--~---~--~--- I--l-
i
7-Segment
indicator
~
BCD input
(a) (b)
(a) 7446 decoder-driver, (b) 7448 decoder-driver
The 7448
Figure 4.23b is the alternative decoding approach. Here, a 7448 drives a common-cathode indicator. Again,
internal logic converts the BCD input to the required output. For example, when a BCD input of OI 00 is used,
the internal logic forces LEDs b, c,f, and g to conduct. The seven-segment indicator then displays a 4. Unlike
the 7446 that requires external current-limiting resistors, the 7448 has its o,vn current-limiting resistors on
the chip. A switch symbol is used to illustrate operation of the 7446 and 7448 in Fig. 4.23. Switching in the
actual IC is of course accomplished using bipolar junction transistors (BJTs).
Sketc~ tile ~~gmentsina seven-s~gment indic~tor.

Each segment of a seven-segment indicator is.what type ·of d~vice?
4;6··· ENCODERS
An encoder converts an active input signal into a coded output signal. Figure 4.24 illustrates the general idea.
There are n input lines, only one of which is active. Internal logic within the encoder converts this active input
to a coded binary output with m bits.
Decimal-to-BCD Encoder
Figure 4.25 shows a common type of encoder-the decimal-to-BCD
n inpots { : Eocod~
encoder. The switches are push-button switches like those of a pock-
et calculator. When button 3 is pressed, the C and D OR gates have
high inputs; therefore, the output is
L.-y---1
ABCD=OOil m outputs
If button 5 is pressed, the output becomes
ABCD=OlOI Encoder
When switch 9 is pressed, +5V
l
ABCD= 1001
:
The 74147 :
Figure 4.26a is the pinout diagram for a 74147, a 4 __J_
decimal-to-BCD encoder. The decimal input, X 1 to X9, :
5 __J_
connect to pins 1 to 5, and 10 to 13. The BCD output 6 __J_
comes from pins 14, 6, 7, and 9. Pin 16 is for the supply 7 __J_
voltage, and pin 8 is grounded. The label NC on pin 15 :
8 __J_
means no connection (the pin is not used). 9
...
y
__J_
- T
Figure 4.26b shows how to draw a 74147 on a l I ~-
schematic diagram. As usual, the bubbles indicate
active-low inputs and outputs. Table 4.5 is the truth table
ofa 74147. Notice the following. When allXinputs are
high, all outputs are high. When X 9 is low, the ABCD
yA B
I
B B
output is LHHL (equivalent to 9 if you complement the
Decimal-to-BCD encoder
bits). When X8 is the only low input, ABCD is LHHH
11 16
X4
X1 Vee
12 8
X2 GND
X5
13
X3
x6 14
X4 A
X7 2 6
7445 Xs 74147 B
Xs 3 7
X6 C
B 4 X 9
7 D
C 5
Xs
GND le
X9
(a) (b)
(a) Pinout diagram of 74147, (b) logic diagram

Outputs
X1 X2 X3 X4 A B C D
H H H H H H H H H H H H H
X X X X X X X X L L H H L
X X X X X X X L H L H H H
X X X X X X L H H H L L L
X X X X X L H H H H L L H
X X X x L H H H H H L H L
X X X L H H H H H H L H H
X X L H H H H H H H H L L
X L H H H H H H H H H L H
L H H H H H H H H H H H L
( equivalent to 8 if the bits are complemented). When X7 is the only low input, ABCD becomes HLLL
(equivalent to 7 if the bits are complemented). Continue like this through the rest of the truth table and you
can see that an active-low decimal input is being converted to a complemented BCD output.
Incidentally, the 74147 is called a priority encoder because it gives priority to the highest-order input. You
can see this by looking at Table 4.5. If all inputs X 1 through X9 are low, the highest of these, X 9, is encoded
to get an output of LHHL. In other words, X 9 has priority over all others. When X9 is high, X8 is next in line
of priority and gets encoded if it is low. Working your way through Table 4.5, you can see that the highest
active-low from X 9 to X 0 has priority and will control the encoding.
What is the ABCD output of Fig. 4.27 when button 6 is pressed?
Solution When all switches are open, the X1 to X9 inputs are pulled up to the high state ( + 5 V). A glance at Table
4.5 .indicates thatthe ABCD output is HHHH at this time.
When switch 6 is pressed, the X6 input is grounded. Therefore, all X inputs are high, except for X6. Table 45
indicates that the ABCD output is HLLH, which is equivalent to 6 when the output bits are complemented.
+5V
All resistors are l kQ 16

J_L_ 11 X I Vee
2_L_ 12 74147
13
Xz 14
A
l X3 6
B
2 X4
X5 7
3 C
4
x6
9
X 7 D
5
Xs
10 X
9
GND
- 8
-
Design a priority encoder the truth table of which is shown in Fig. 4.28a. The order of priority
for three inputs is X1 > X2 > X3. However, if the encoder is not enabled by Sor all the inputs
are inactive the output AB= 00.
Solution Figure 4.28b and .Fig, '4.28cshow the Karnaugh map for output A and B respectively. Note that, we have
used a differentnotation.forinput variables Ill these maps. Compare this with notations presented in previous chapters.
You will find a variab.le with pri:rne is presented by O and if it is not primed is represented by 1. Then taking groups
of Is we get the design equations as shown in the figure. The logic circuits for output A and B can be directly drawn
from tllese equations.
Intput Output S. l'i SX1

xx 00 01 11 rn XzX3 00 01 11
s XI Xz X3 A B 2 3
00 0 0 0 0 00 0 0
·0
0 X X X 0 0
I 1 X X 0 I 01 0 0 01 0 0
1 0 1 X 1 0 11 0 0 0 1 11 0 0 l 0
1 0 0 I 1 1
10 0 0 0 I 10 0 0 0
1 0 0 0 0 0
A SXiX3 + s.1\Xz B = SX1 + SXzX3
(a) (b) (c)
Design of a priority encoder
12. What is an encoder?

I3. What type of encoder is the TTL 74147?
4.7 EXCLUSIVE-OR GATES
The exclusive-OR gate has a high output only when an odd

A
number of inputs is high. Figure 4.29 shows how to build
an exclusive-OR gate. The upper AND gate forms the
product AB, while the lower one produces AB. There-
y
fore, the output of the OR gate is
Y=AB+AB
Here is what happens for different inputs. When A and B
B are low, both AND gates have low outputs; therefore,
the final output Y is low. If A is low and B is high, the
Exclusive-OR gate
upper AND gate has a high output, so the OR gate has high
output. Likewise, a high A and a low B result in a final output that is high. If both inputs are high, both AND
gates have low outputs and the final output is low.
Table 4.6 shows the truth table for a 2-input exclusive-OR gate. The output is high when A or Bis high, but
not when both are high. This is why the circuit is known as an exclusive-OR gate. In other words, the output
is a 1 only when the inputs are different.
Exclusive-OR Truth Table
A B y
0 0 0 ;==j[)-r
0 I
1 0 l Logic symbol for
1 1 0 exclusive-OR gate
Figure 4.30 shows the symbol for a 2-input exclusive-OR gate. Whenever you see this symbol, remember
the action-the output is high if either input is high, but not when both are high. Stated another way, the
inputs must be different to get a high output.
Four Inputs
Figure 4.3 la shows a pair of exclusive-OR gates A
driving an exclusive-OR gate. If all inputs (A to D) B
are low, the input gates have low outputs, so the fi- y
nal gate has a low output. If A to C are low and D C
is high, the upper gate has a low output, the lower D
gate has a high output, and the output gate has a (a)
high output.
Ifwe continue analyzing the circuit operation for
the remaining input possibilities, we can work out
Table 4. 7. Here is an important prope1ty of this truth
table. Each ABCD input with an odd number of ls
produces an output I. For instance, the first ABCD
!~y (b)
entry to produce an output 1 is 000 l; it has an odd Four-input exclusive OR gate
'-",::·· ·.. . _.,

able 4.7 · 4-lnput Exclusive-OR Gate
Comment A B C D y
Even 0 0 0 0 0
Odd 0 0 0 l I
Odd 0 0 0 1
Even 0 0 1 l 0
Odd 0 0 0 1
Even 0 0 0
Even 0 0 0
Odd 0 1 l l
Odd 0 0 0 l
Even 0 0 l 0
Even 0 I 0 0
Odd 0 1 1 I
Even 0 0 0
Odd 0 1
Odd 1 0 I
Even l 0
number of 1s. The next ABCD entry to produce an output 1 is 001 O; again, an odd number of Is. An output
1 also occurs for these ABCD inputs: 0100, 0111, 1000, 1011,1101, and 1110, each having an odd number
of ls.
Figure 4.3 la illustrates the logic for a 4-input exclusive-OR gate. In this book, we will use the abbreviated
symbol given in Fig. 4.31 b to represent a 4-input exclusive-OR gate. When you see this symbol, remember
the action-the gate produces an output 1 when the ABCD input has an odd number of ls.
Any Number of Inputs

Using 2-input exclusive-OR gates as building blocks, you can produce exclusive-OR gates with any number
of inputs. For example, Fig. 4.32a shows a pair of exclusive-OR gates. There are 3 inputs and l output. If you
analyze this circuit, you will find it produces an output 1 only when the 3-bit input has an odd number of ls.
Figure 4.32b shows an abbreviated symbol for a 3-input exclusive-OR gate.
(a) (b)
(c) (d)
Exclusive-OR gate with several inputs
As another example, Fig. 4.32c shows a circuit with 6 inputs and 1 output. Analysis of the circuit shows
that it produces an output 1 only when the 6-bit input has an odd number of 1s. Figure 4.32d shows an
abbreviated symbol for a 6-input exclusive-OR gate.
In general, you can build an exclusive-OR gate with any number of inputs. Such a gate always produces
an output I only when the n-bit input has an odd number of Is.
14. When is the output of an exclusive-OR gate high?

15. Draw the logic symbol for an exclusive-OR gate.
4~8 PARITY GENERATORS AND CHECKERS
Even parity means an n-bit input has an even number of ls. For instance, 110011 has even parity because
it contains four ls. Odd parity means an n-bit input has an odd number of ls. For example, 110001 has odd
parity because it contains three ls.
Here are two more examples:

1111 0000 1111 0011 even parity
1111 0000 1111 0111 odd parity
The first binary number has even parity because it contains ten ls; the second binary number has odd
parity because it contains eleven 1s. Incidentally, longer binary numbers are much easier to read if they are
split into nibbles, or groups of four, as done here.
Parity Checker 10101 100100 01100

Exclusive-OR gates are ideal for checking the parity of a
binary number because they produce an output 1 when the
input has an odd number of 1s. Therefore, an even-parity in-
put to an exclusive-OR gate produces a low output, while an
odd-parity input produces a high output.
For instance, Fig. 4.33 shows a 16-input exclusive-OR
gate. A 16-bit number drives the input. The exclusive-OR
gate produces an output 1 because the input has odd parity
(an odd number of ls). If the 16-bit input changes to another
Exclusive-OR gate
value, the output becomes O for even-parity numbers and 1
with 16 inputs
for odd-parity numbers.
Parity Generation
In a computer, a binary number may represent an instruction that tells the computer to add, subtract, and so
on; or the binary number may represent data to be processed like a number, letter, etc. In either case, you
sometimes will see an extra bit added to the original binary number to produce a new binary number with
even or odd parity.
For instance, Fig. 4.34 shows this 8-bit binary number:
X1X6XsX4 X3X2X1 Xo 8-bit number
Suppose this number equals OI 00 0001. Then, the mun-
ber has even parity, which means the exclusive-OR gate
produces an output of 0. Because of the inverter,
Xs= 1
and the final 9-bit output is 1 01000001. Notice that this has
odd parity.
I 1
~
Suppose we change the 8-bit input to O110 0001. Now, it
has odd parity. In this case, the exclusive-OR gate produces
an output 1. But the inve1ter produces a 0, so that the final
9-bit output is O O110 0001. Again, the final output has odd
parity. X. Instruct10n or data btts
The circuit given in Fig. 4.34 is called an odd-parity gen- 9-bit number with odd parity
erator because it always produces a 9-bit output number
witn odd parity. If the 8-bit input has even parity, a 1 comes Odd-parity generation
out of the inverter to produce a final output with odd parity. On the other hand, if the 8-bit input has odd
parity, a O comes out of the inverter, and the final 9-bit output again has odd parity. (To get an even-parity
generator, delete the inverter.)
Application
What is the practical application of parity generation and checking? Because of transients, noise, and other
disturbances, 1-bit errors sometimes occur when binary data is transmitted over telephon,' lines or other
communication paths. One way to check for errors is to use an odd-parity generator at the iansmitting end
and an odd-parity checker at the receiving end. If no 1-bit errors occur in transmission, the received data will
have odd parity. But if one of the transmitted bits is changed by noise or any other disturbance, the received
data will have even parity.
For instance, suppose we want to send 0100 0011. With an odd-parity generator like Fig. 4.34, the data
to be transmitted will be O O100 0011. This data can be sent over telephone lines to some destination. If no
errors occur in transmission, the odd-parity checker at the receiving end will produce a high output, meaning
the received numqer has odd parity. On the other hand, if a 1-bit error does creep into the transmitted data,
the odd-parity checker will have a low output, indicating the received data is invalid.
One final point should be made. Errors are rare to begin with. When they do occur, they are usually 1-bit
e1rnrs. This is why the method described here catches almost all of the errors that occur in transmitted data.
The 74180
Figure 4.35 shows the pinout diagram for a 74180, which is a TTL parity generator-checker. The input data
bits are X 7 to X0 ; these bits may have even or odd parity. The even input (pin 3) and the odd input (pin 4)
control the operation of the chip as shown in Table 4.8. The symbol I stands for summation. In the left input
column of Table 4.8, I of H's (highs) refers to the parity of the input dataX7 toX0 . Depending on how you
set up the values of the even and odd inputs, the I even and I odd outputs may be low or high.
For instance, suppose even input is high and odd input is low. When the input data has even parity (the
first entry of Table 4.8), the I even output is high and the I odd output is low. When the input data has odd
parity, the I even output is low and the 1: odd output is high.
74180 Truth Table
EVEN INPUT Inputs Outputs
ODD INPUT 74180 I ofH's at Even Odd I even Iodd
I: EVEN OUTPUT
H
I:ODDOUTPUT L
L H
GND
H L
L L
Pinput diagram of 74180 H H
lfyou change the control inputs, you change the operation. Assume that the even input is low and the odd
input is high. When the input data has even parity, the 2: even output is low and the 2: odd output is high.
When the input data has odd parity, the I even output is high and the I odd output is low.
The 74180 can be used to detect even or odd parity. It can also be set up to generate even or odd parity.
+5V 1 2 8 9 10lu li2113

t1 3
ODD INPUT
p EVEN INPUT 74180
:[ODD OUTPUT
16
Using a 74180 to generate odd parity
xa!!'p.e .1-:12 Show how to connect a 74180 to geJ1erate a 9-bit output with odd parity.
Solution Figure 4.36 shows one solution. The ODD INPUT (pin 4) is connected to +5 V, and the EVEN INPUT
(pin 3) is grounded. Suppose the input data X7 ... Xo has even parity. Then, the third entry of Table 4.8 tells us the .:E
ODD OUTPUT (pin 6) is high. Therefore, the 9-bit number Xs ... Xo coming out of the circuit has odd parity.
On the other hand, supposeX7 ••• Xo has odd parity. Then the fourth entry of Table 4.8 says that the L odd output
is low. Again, the 9-bit number Xg ... Xi> coming out at the bottom of Fig. 4.36 has odd parity.
The following conclusion may be drawn. Whether the input data has even or odd parity, the 9-bit number being
generated in Fig. 4.36 always has odd parity.
16. What does it mean to say that an n-bit binary number has even parity?
17. Exclusive-OR gates are useful as parity generators. (Tor F)
4.9 MAGNITUDE COMPARATOR
Magnitude comparator compares magnitude two n-bit binary numbers, say X and Yand activates one of these
three outputs X = Y, X > Y and ,:r < Y. Figure 4.37a presents block diagram of such a comparator. Fig. 4.37b
presents truth table when two I-bit numbers are compare<l and its circuit diagram is shown in Fig. 4.3 7c. The
logic equations for the outputs can be written as follows, where G, L, E stand for greater than, less than and
equal to respectively.
(X> Y): G =XY' (X < Y): L =X'Y (X= Y): E =X'Y' + XY = (XY' + X'Y)' = (G + L)'
}-1
n~2
Xo (X> Y) Input Output

n-bit X y X>Y X=Y X<Y
(X= Y) X
comparator
0 0 0 0 1
y•-1
11-2
(X< Y) 0 1 0 1 0 X=Y
1 0 1 0 0
1 1 0 0 1 y
Yo
(a) (b) (c)
(a) Block diagram of Magnitude comparator, (b) Truth table, (c) Circuit
for 1-bit comparator
Now, how can we design a 2-bit comparator? We can fom1 a 4-variable (X: X 1X 0 and Y: Y1Yo) truth table
and get logic equations through any simplification technique. But this procedure will become very complex
ifwe try to design a comparator for 3-bit numbers or more. Here, we discuss a simple but generic procedure
for 2-bit comparator design, which can easily be extended to make any n-bit magnitude comparator. We shall
use the truth table of I -bit comparator that generates greater than, less than and equal terms.
Let's first define bit-wise greater than terms ( G): Gi = Xi Y{, Go= XoYo'
Then, bit-wise less than term (L): Li =Xi'Yi, L0 =Xo'Yo
Therefore, bit-wise equality tenn (£): E1 = (Gi + Li)', Eo =(Go+ Lo)'
From above definitions we can easily write 2-bit comparator outputs as follows.
(X= Y) = Ei.Eo
The logic followed in arriving at these equations is this; X = Y when both the bits are equal.
X> Y ifMSB of Xis higher ( Gi = 1) than that of Y. If MSB is equal, given by E 1 = 1, then LSB of X and Y is
checked and if found higher ( G0 = I) the condition X > Y is fulfilled. Similar logic gives us the X < Y term.
Thus for any two n-bit numbers X: X 11 _ 1 X,,_z .. .Xo and Y: Y11 _i Yn-2· . .Yo
We can write, (X= Y) =En-i En-2···Eo
(X> Y) = Gn-1 + En-I Gn-2 + ... +En-I En-2··· Ei Go
(X < Y) = Ln-1 + En-ILn-2 + ... + En-i En-2··· E1Lo
where E;, G; and L; represent for ith bit X; = Y; , X; > Y; and X; < Y; terms respectively.
The block diagram ofIC 7485, which compares two 4-bit numbers is shown in Fig. 4.38a. This is a 16 pin
IC and all the pin numbers are mentioned in this functional diagram. Note that the circuit has three additional
inputs in the form of (X = lJin, (X> lJin and (X < lJin· What is the use of them? They are used when we need
to connect more than one IC 7485 to compare numbers having more than 4-bits. But these inputs are oflower
priority. They can decide the output only when 4-bit numbers fed to this IC are equal. For example, if X =
0100 and Y= 0011, (X> Y) 0 ut will be high and other outputs will be low irrespective of the value appearing at
(X= lJin, (X> lJin and(X< lJin· When IC 7485 is not used in cascade we keep (X= Y)i11 = 1, (X> lJin =O and
(X< lJin=O.
X y
..--------, ..--------,
X3X2X1Xo Y3 Yz Y1 Yo X3X2X1Xo Y3 Y2Y1 Yo
! ! !1
15131210 1 1411 9 15131210 l 1411 9
!
15131210
l! !
1 1411 9
+5v
4 ~X> Y) 4 4
IC 7485 3 X-Bm IC 7485 3 IC 7485 3
72 (X~ ;~ 72 72
5 6 5 6 5 6
Vcc(16)
//
GND(8)
(X> Y)out (X= Y)out (X < Y)out (X> Y)out (X = Y)out (X < Y)out
(a) (b)
(a) functional diagram of IC 7485, (b) 8-bit comparator from two 4-bit
comparators
Show how two IC 7485 can be used to compare magnitude of two 8-bit numbers.
Solution Refer to Fig. 4.38h for iolution. The numbersto compare are x. . ..;Xo mtd Y: Y1.
Y6: .. Yo. We nfed
two IC 7485s each one comparing 4 bits. The most significant bits (suffix 7,6,5,4) are given higher;priority and tbe
final output is tllken from that IC 7485 which compares them.
18. How many outputs a magnitude comparator generates?

19. How many IC 7485s ate needed to compare two 12-bit numbers?
4. to READ-ONl Y MEMORY
A read-only mem01y (which is abbreviated ROM and rhymes with Mom) is an IC that can store thousands of
binary numbers representing computer instructions and other fixed data. A good example of fixed data is the
unchanging information in a mathematical table. Since the numerical data do not change, they can be stored
in a ROM, included in a computer system, and used as a "look-up" table when needed. Some of the smaller
RO Ms are also used to implement truth tables. In other words, we can use a ROM instead of sum-of-products
circuit to generate any Boolean function.
Diode ROM
Diode ROM Nibble
Suppose we want to build a circuit that stores the binary num- 0111
bers shown in Table 4.9. To keep track of where the numbers 1000
1011
are stored, we will assign addresses. For instance, we want to
llOO
store 0111 at address 0, 1000 at address 1, 1011 at address 2, and
0110
so forth. Figure 4.39 shows one way to store the nibbles given 1001
in Table 4.9. When the switch is in position O (address 0), the 6 0011
upper row of diodes are conducting current (they act as closed 7 1110
switches). (See Chapter 14 for a discussion of diodes.) The output of the ROM is thus
Y3 Y2 Y1 Yo = 0111
When the switch is moved to position I, the second row is activated and
Y3 Y2 Y1 Yo = I 000
As you move the switch to the remaining positions or addresses, you get a Y3 ••• Yo output that matches
the nibbles given in Table 4.9.
2
3
+5V
4
5
6
7
Diode ROM
On-Chip Decoding
Rather than switch-select the addresses as shown in Fig. 4.39, a manufacturer uses on-chip decoding. Figure
4.40 illustrates the idea. The 3-input pins (A, B, and C) supply the binary address of the stored number. Then,
a l-of-8 decoder produces a high output to one of the diode rows. For instance, if
ABC= 100
the l-of-8 decoder applies a high voltage to the ABC line, and the ROM output is
Y3Y2Y1 Yo= 0110
If you change the binary address to

ABC= 110
the ROM output changes to
Y3 Y2 Y1 Yo= 0011
With on-chip decoding, n inputs can select 2 11 memory locations (stored numbers). For instance, we need
3 address lines to access 8 memory locations, 4 address lines for 16 memory locations, 8 address lines for
256 memory locations, and so on.
Commercially Available ROMs

A binary number is sometimes called a word. In a computer, binary numbers or words represent instructions,
alphabet letters, decimal numbers, etc. The circuit given in Fig. 4.40 is a 32-bit ROM organized as 8 words
A B C
Alic
On-chip decoding
_ _ _ _ _ _ _ _ _ _ _ _ _ _o_a__ta_-P_ro_ce_ss_in_g_C_in_cu_it_s _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~
with 4 bits at each address (an 8 x 4 ROM). The ROM given in Fig. 4.40 is for instructional purposes only
because you would not build this circuit with discrete components. Instead, you would select a commercially
available ROM. For instance, here are some TTL ROMs:
7488: 256 bits organized as 32 x 8
74187: 1024 bits organized as 256 x 4
74S370: 2048 bits organized as 512 x 4
As you can see, the 7488 can store 32 words of8 bits each, the 74187 can store 256 words of 4 bits each,
and the 74S370 can store 512 words of 4 bits each. If you want to store bytes (words with 8 bits), then you
can parallel the 4-bit ROMs. For example, two parallel 74187s can store 256 words of8 bits each.
One way to change the stored numbers of a ROM is by adding or removing diodes. With discrete circuits,
you would have to solder or unsolder diodes to change the stored nibbles. With integrated circuits, however,
you can send a list of the data to be stored to an IC manufacturer, who then produces a mask (a photographic
template of the circuit). This mask is used in the mass production of your ROMs. As a rule, ROMs are used
only for large production runs (thousands or more) because of manufacturing costs.
Generating Boolean Functions

Because the AND gates of Fig. 4.40 produce all the fundamental products and the diodes OR some of these
products, the ROM is generating four Boolean functions as follows:
Y3 = ABC+ABC +ABC+ABC+ABC (4.1)
Y2 =ABC+ ABC+ ABC+ ABC (4.2)
Y1 =ABC+ ABC+ ABC+ ABC+ ABC (4.3)
Y0 =ABC+ ABC+ ABC+ ABC (4.4)
This means that you can use a ROM instead of a logic circuit to implement a truth table.
For instance, suppose you start with a truth table like the one in Table 4.10. There are four outputs: Y3, Y2 ,
Y1, and Y0. A sum-of-products solution would lead to four AND-OR circuits, one for Eq. (4.1), a second for
Eq. (4.2), and so on. The ROM solution is different. With a ROM you have to store the binary numbers of
Table 4.9 (same as Table 4.10) at the indicated addresses. When this is done, the ROM given in Fig. 4.40 is
equivalent to a sum-of-products circuit. In other words, you can use the ROM instead of an AND-OR circuit
to generate the desired truth table.
Truth Table
A B C Y3 Y2 Y1 Yo
0 0 0 0 l I 1
0 0 l I 0 0 0
0 1 0 1 0 1 1
0 1 1 1 l 0 0
1 0 0 0 1 1 0
I 0 1 1 0 0 1
l l 0 0 0 1 l
I I 1 I 1 1 0
Programmable ROMs
A programmable ROM (PROM) allows the user instead of the manufacturer to store the data. An instrument
called aPROMprogrammer stores the words by "burning in." Here is an example ofhow a PROM programmer
works. Originally, all diodes are connected at the cross points. For instance, in Fig. 4.40 there would be a
total of32 diodes (8 rows and 4 columns). Each of these diodes has afi1sible link (a small fuse). The PROM
programmer sends destructively high currents through all diodes to be removed. In this way, only the desired
diodes remain connected after programming a PROM. Programming like this is permanent because the data
cannot be erased after it has been burned in.
Here are some commercially available PROMs:
74Sl88: 256 bits organized as 32 x 8
74S287: ·1024 bits organized as 256 x 4
74S472: 4096bits organized as 512 x 8
PRO Ms such as these are useful for small production runs. For instance, if you are building only a few
hundred units (or maybe even just one), you would choose a PROM rather than a ROM.
Since PROMs are useful in many applications, manufacturers produce these chips in high volume.
Furthermore, the PROM is a universal logic solution. Why? Because the AND gates generate all the
fundamental products; the user can then OR these products as needed to generate any Boolean output. One
disadvantage of PRO Ms is the limit on number of input variables; typically, PRO Ms have 8 inputs or less.
Simplified Drawing of a PROM

It is cumbersome to draw large PROMs as illustrated in Fig. 4.41, because of the large number of diodes.
An alternative, streamlined drawing procedure for PROMs like the one in Fig. 4.40 is shown in Fig. 4.41. In
this simplified drawing, the solid black
A B C
bullets indicate connections to the AND-
gate inputs. Each bullet represents a fixed Programmable OR array
connection that cannot be changed. Fur-
thermore, each AND gate has 3 inputs,
indicated by the bullet on .its input line.
Similarly, each OR gate has 8 inputs,
as indicated by the x 's on its input line,
but each x is a fusible link that can. be ·
removed.
Notice that the input side of Fig. 4.41
is a fixed AND array, meaning the inputs
to the AND gates are not programmable
in a PROM. On the other hand, the out-
put side of the circuit is programmable
because each connection at the input of
Fixed AND array
each OR gate is a fusible link. A fixed
AND array and a programmable OR ar- Y3 Y2 Y1 Yo
ray are characteristic of all PRO Ms. To
begin with, every AND-gate output is Streamlined drawing of PROM
connected to every OR-gate input. Since
the AND gates produce all eight possible combinations Programmable OR array
of the input variables A, Band C, it is possible to produce
1----11---1--,iE---1-ABC
any Boolean function at the OR-gate outputs.
1-----1e----,...__,..._...,._]BC
Programming a PROM 1----11---+---l'---+-ABC
Generating a Boolean function at the output of a PROM l----11---+---1'---t-ABC
is accomplished by fusing (melting) fusible links at the
input to the OR gates in Fig. 4.41. For example, suppose 1-----;,1E---l!E---ll---+-ABC
we want to generate the function Yo = ABC. Simply fuse 1---.;i1E---llt'---ll---+-ABC

(melt) 7 of the AND-gate outputs connected to the Yo
1-----1e---_,._---1f---+-ABC
OR-gate input and leave the single AND-gate output
ABC connected. A portion of Fig. 4.41 is shown in Fig. 1----11----;tE---1'---J!:-- ABC
4.43 with the proper fusible link remaining for Y0 .
As a second example, suppose we want to generate the
function Y1 = AB . We must include all terms containing
AB, since
ABC +ABC= AB(C + C)=AB Boolean function from
PROM
The two top fusible links must be included, while the
remaining six are broken, as shown in Fig. 4.42. Continuing in this fashion, you can see that Y2 = A and Y3
=AB.
Erasable PROMs
The erasable PROM (EPRO.M) uses metal-oxide-semiconductor field-effect transistors (MOSFETs ). Data is
stored with an EPROM programmer. Later, data can be erased with ultraviolet light. The light passes through
a quartz window in the IC package. When it strikes the chip, the ultraviolet light releases all stored charges.
The effect is to wipe out the stored contents. In other words, the EPROM is ultraviolet-light-erasable and
electrically reprogrammable.
Here are some commercially available EPROMs:
2716: 16,384 bits organized as 2048 x 8
2732: 32,768 bits organized as 4096 x 8
The EPROM is useful in project development. With an EPROM, the designer can modify the contents
until the stored data is perfect. When the design is finalized, the data can be burned into PROMs (small
production runs) or sent to an IC manufacturer who produces ROMs (large production runs).
20. What is a ROM?

21. What does it mean to say that a particular ROMjs
22. What is a PROM?
• 4.11 PROGRAMMABLE ARRAY LOGIC I

Programmable array logic (PAL) is a programmable array of logic gates on a single chip. PALs are another
design solution, similar to a sum-of-products solution, product-of-sums solution, and multiplexer logic.
Programming a PAL
A PAL is different from a PROM because it has a programmable AND array and a fixed OR array. For
instance. Fig. 4.43 shows a PAL with 4 inputs and 4 outputs. The x's on the input side are fusible links, while
the solid black bullets on the output side are fixed connections. With a PROM programmer, we can burn in
the desired fundamental products, which are then ORed by the fixed output connections.
A B C D
Fixed OR array
Programmable AND array
Y3 Y2 Y1 Yo
ce::~ti;:f}I) Structure of PAL
Here is an example of how to program a PAL. Suppose we want to generate the following Boolean
functions:
Y3 = ABC D + A.BCD + ABCD + ABCD (4.5)

Y2 = ABCD +A.BCD+ ABCD (4.6)
Y, = ABC +ABC+ABC+ABC (4.7)
Yo =ABCD (4.8)
Start with Eq. (4.5). The first desired product is A.BCD. On the top input line of Fig. 4.44 we have
to remove the first x, the fourth x, the fifth x, and the eighth x. Then the top AND gate has an output of
ABCD.
By removing xs on the next three input lines, we can make the top four AND gates produce the fundamental
products ofEq. (4.5). The fixed OR connections on the output side imply that the first OR gate produces an
output of
1:3 = ABCD + ABCD + ABCD + ABCD
A B C D
ti R-7 \7 v Fixed OR array
i,
Example of programming a PAL

Similarly, we can remove xs as needed to generate Y2, Y1, and Y0 . Figure 4.44 shows how the PAL looks
after the necessary xs have been removed. If you examine this circuit, you will see that it produces the Y
outputs given by Eqs. (4.5) to (4.8).
Commerdaily Available PAls

The PAL given in Fig. 4.43 is hypothetical. Commercially available PALs typically have more inputs. For
instance, here is a sample of some TTL PALs available from National Semiconductor Corporation:
10H8; 10 input and 8 output AND-OR
16H2: 6 input and 2 output AND-OR
14L4: 14 input and 4 output AND-OR-INVERT
For these chip numbers, H stands for active-high output and Lfor active-low output. The 10H8 and the
16H2 produce active-high outputs because they are AND-OR PALs. The 14L4, on the other hand, produces
an active-low output because it is an AND-OR-INVERT circuit (one that has inverters at the final outputs).
Unlike PROMs, PALs are not a universal logic solution. Why? Because only some of the fundamental
products can be generated and ORed at the final outputs. Nevertheless, PALs have enough flexibility to
produce all kinds of complicated logic functions. Furthermore, PALs have the advantage of 16 inputs
compared to the typical limit of 8 inputs forPROMs.
23. What is a PAL?

24. A PAL has an AND array and an OR array. Which one is fixed and which is programmable?
4.12 PROGRAMMABLE LOGIC ARRAYS
Programmable logic arrays (PLAs), along with ROMs and PALs, are included in the more general
classification ofICs called programmable logic devices (PLDs). Figure 4.45 illustrates the basic operation of
these three PLDs. In each case, the input signals are presented to an array of AND gates, while the outputs
are taken from an array of OR gates.
The input AND-gate array used in a PROM is fixed and cannot be altered, while the output OR-gate array
isji,sible-linked, and can thus be programmed. The PAL is just the opposite: The output OR-gate array is
fixed, while the input AND-gate array is fusible-linked and thus programmable. The PLA is much more
versatile than the PROM or the PAL, since both its AND-gate array and its OR-gate array are fusible-linked
and programmable. It is also more complicated to utilize since the number of fusible links are doubled.
A PLA having 3 input variables (ABC) and 3 output variables (XYZ) is illustrated in Fig. 4.46. Eight AND
gates are required to decode the 8 possible input states. In this case, there are three OR gates that can be used
to generate logic functions at the output. Note that there could be additional OR gates at the output if desired.
Programming the PLA is a two-step process that combines procedures use~ with the PROM and the PAL.
As an example, suppose it is desired to use a PLA to recognize each of the 10 decimal digits represented
in binary form and to correctly drive a 7-segment display. The 7-segment indicator was presented in Sec.
4.5. To begin with, the PLA must have 4 inputs, as shown in Fig. 4.47a. Four bits (ABCD) are required to
represent the 10 decimal numbers (see Table 1.1 ). There must be 7 outputs (abcdefg), 1 output to drive each
Input
Fixed ,___ _ _ _ _ Fusible A B C

AND OR Output
Array Array Programmable OR array
,---------"---
PROM
Input
Fusible ,___ _ _ __ Fixed

AND OR Output
Array Array
PAL
Input
Fusible 1--------1 Fusible

AND OR Output
Array Array Programmable AND array
PLA X Y Z
of the 7 segments of the indicator. Let's assume that our PLA is capable of driving the 7-segment indicator
directly. (This is not always a valid assumption, and a buffer amplifier may be needed to supply the proper
current for the indicator.)
To begin with, all fusible links are good. The circuit in Fig. 4.47b shows the remaining links after
programming. The input AND-gate array is programmed (fusible links are removed) such that each AND
gate decodes one of the decimal numbers. Then, with the use of Fig. 4.47c, links are removed from the output
OR-gate array such that the proper segments of the indicator are illuminated. For instance, when ABCD =
LHLH, segments afgcd are illuminated to display the decimal number 5. You should take the time to examine
the other nine digits to confirm proper operation.
One final point. Many PLDs are programmable only at the factory. They must be ordered from the
manufacturer with specific programming instructions. There are, however, PLDs that can be programmed
by the user. These are said to be field-programmable, and the letter F is often used to indicate this fact. For
instance, the Texas Instruments TIFPLA840 is a field-programmable PLA with 14 input variables, 32 AND
gates, and 6 OR gates; it is described as a 14 x 32 x 6 FPLA.
Wbatis aPLA'l
How does a PLA differ from a PAL?
27. In Fig. 4.47, ABCD =LLHH. What segments are activated?
a
A
b
a
.rjf
C
B p
L d
e/ f
C A e
l g
D
g d
(a) (c)
A B C D
v· ~i ~·R7 0
I
2
3
4
5
6
7
8
a b c d e f g
(b)
7-segment decoder using PLA
4.13 TROUBLESHOOTING WITH A LOGIC PROBE
Chapter 3 introduced the logic clip, a device that connects to a 14 or 16-pin TC. The logic clip contains 16
LEDs that monitor the state of the pins. When a pin voltage is high, the corresponding LED lights up. When
the pin voltage is low, the LED is dark.
Figure 4.48 shows a logic probe, which is another troubleshooting tool you will find helpful in diagnosing
faulty circuits. When you touch the probe tip to the output node as shown, the device lights up for a high state
and goes dark for a low state. For instance, if either A or B, or both. arc low, then Yis high and the probe lights
up. On the other hand, if A and B are both high, Y is low and the probe is dark.
Among other things, the probe is useful for locating short

circuits that occur in manufacturing. For example, during the
stuffing and soldering of printed-circuit boards, an undesirable
splash of solder may connect two adjacent traces (conducting
lines). Known as a solder bridge, this kind of trouble can short- Bright or dark
circuit a node to the ground or to the supply voltage. The node
is then stuck in a low or high state. The probe helps you to find
short-circuited nodes because it stays in one state, no matter
how the inputs are changing.
Using a logic probe
4.14 HDl IMPLEMENTATION OF DATA

PROCESSING CIRCUITS
We start with hardware design of multiplexers using Verilog code. The data flow model provides a different
use of keyword assign in the fom1 of
assign X= S ? A : B;
This statement does following assignment. If, S = 1, X = A and if S = 0, X = B. One can use this statement
or the logic equation to realize a 2 to 1 multiplexer shown in Fig. 4.2(a) in one of the following ways.
module mux2tol(A,D0,D1,Y); module mux2tol(A,DO,Dl,Y);

input A,DO,Dl; /* Circuit shown input A,DO,Dl; /* Circuit shown in
in Fig. 4.3(a) */ Fig. 4.3(a)*/
output Y; output Y;
assign Y=(-A&D0) I (A&Dl); assign Y= A? Dl DO; /*Conditional
endmodule assignment*/
endmodule
The behavioral model can be used to describe the 2 to 1 multiplexers in following two different ways, one
using if ... else statement and the other using case statement. The case evaluates an expression or a variable
that can have multiple values each one corresponding to one statement inthe following block. Depending on
value of the expression, one of those statements get executed. The behavioral model of2 to 1 multiplexer in
both is given below:
module mux2tol(A,DO,Dl,Y); module mux2tol(A,D0,Dl,Y);

input A,DO,Dl; /* Circuit shown input A,DO,Dl; /* Circuit shown
in Fig. 4.3(a)*/ in Fig. 4.3(a) */
output Y; output Y;
reg Y; reg Y;
always@ (A or DO or Dl) always@ (A or DO or Dl)
if {A==l) Y=Dl; case (A)
else Y=DO; 0 : Y=DO;
endmodule 1 : Y=Dl;
endcase
endmodule
Design a 4 to 1 multiplexer, shown in Fig. 4.l(c) using conditional assign and case
statements.
The codes are given next. We have used nested condition for assign statement. If AP 1, coµdition
(B ? . D2) is evaluated. Then if B = 1, Y =. D3. And this is whatis given in l(c). Similarly, the other
combinations of A and B are evaluated and Y is assigned a. value from D2 to DO. For case statement we C<)llcatenp,ted
A and B by using operator . } and generated four possible combim.itions, For a particular value of AB, stateme11t
corresponding to one ofthemgets executed.
module mux4to1 ,D3,Y); module mux4tol(A,

inputA,B,DO,Dl,D2, input A,B,DO,Dl,D2,
output Y; / t:: output
in . 4. 1 (cJ * I
assign Y = A ? { B ? D3
D1 : DO);
endmodule
BUS Representation in HDl

We introduce concept of BUS or vector representation in HDL description through design of a 1 to 4
demultiplexer that can also serve as a 2 to 4 decoder. The data input of former is treated as enable input of
later. We consider S as a select input defined by two binary digits S[l] and S[O]. Output Y is 4 bit long, one of
which goes high for a particular combination of select inputs if data( enable) input is high. The Verilog code
for this demultiplexer/decoder is given below:
module demuxlto4(S,D,Y);
input (1:0J S;
input
output f3 : 0] Y;
reg [3:0] Y;
always @ (S or D)
({ S}} //Concatenation of D and S to 3 bits,
: Y= 4'b0001; tion, to
, S=OO,
3'b101 Y= 4 Y=OOlO
3'b110 : Y=4' Y=OlOO
3'b111 : Y= 4' Y=lOOO
default: Y= 4'b0000; combinations D=O, then Y=OOOO
end.case
endmodule
A verilog HDL code for a digital circuit is given as follows. Can you describe the function it
performs? Can it be related to any logic circuit discussed in this chapter?
moduJ.e
i.ri.put
il'lpUt
output
reg :OJ Y;
always @ .{A<or B or C)
if. {A<B}
else if (A>B) Y=3'b010;
else Y=C;
end.module
SoltJ:iOn The drcuit described by the HDLcompares two 4-bit numbefSA andB and generates a 3 bitoutput Y. It
has alsoa3 bit inputC. If A isless than B, output Y = 001 and does not depend onC Similarly, if A is greater than B,
Y = plOirrespective ofC. Butifthese two conditions are not me~ i.e. . = B then Y = C.
Ifw~ considerthree bits ofYrepresent (starting from MSB) A= B, A> Band A < B respectivelythen, this circuit
represents a 4-bit magnitude qJmparator where. C represents comparator output of previous stage. that is (}f Jower
significance, If numbers of this stage are equal then the value at C that represents equal, greater less than
<:or1d1t1011 of previotis stage nu1nbers is reflected by Y. This is similar. to IC 7485 discussed in Section
PROBLEM SOLVING WITH MUlTIPlE METHODS

Show how data processing circuits can be used to compare two 2-bit numbers, A 1Ao and B 1B0 to
generate two outputs, A> Band A= B.
Solution We can use multiplexers, decoder or simply a 4-bit comparator. The truth table of the above problem
is shown in fig. 4.49.
ln.Method-1, · • we use two 16 to 1 multiplexers to realize > B and A B as shownin Fig. 4.50.
The numbers A 1A0 and B 1Bo ~re used a:, ;a;ele<:tion inputs as shown. For every selection of input, the
00 00 0 1
00 01 0 0
00 10 0 0
00 1I 0 0
OI 00 l 0
Ol 01 0 1
01 10 0 0
01 1l 0 0
10 00 1
10 01 l
10 10 0
rn I1 0
Truth table Solution using 16 ·tq. l multiplexers

corresponding data input goes to the output. The input assignment comes straight from the truth· table
in Fig. 4.49 for the two cases.
In Method-2, we use two 8 to 1 multiplexers to realize A> Band A= Bas shown in Fig. 4.51.The
numbers A1A0 and B1 are used as selection inputs while Bo is part of the data input. We form pair of
combinations of the truth table for constant A 1A0B 1 and B 0 variable. This helps to find out how output
varies with Bo.
In Method-3, we use one 4 to 16 decoder and two multi-input OR gates to realize A > B andA= B
as shown in Fig.4.52. We sum selected minterms, as required from the truth table, from. the set of all
the minterms generated by the decoder.
A1AoB1 Bo A>B A=B 0000 t------~.,.....--

0 0001 ,___ _ _ _ _ _ __
0
0 0 0
0 0 0
0
1
0 (0)
0 6(Bo) B'
00
00101--------'-l---
OOll 1------'----'-l---
0 A>B OIOO t----e----..,.-+---
0 0 1
0 0 1
0
l
g(0) g(O) 0
Ai
0101
0110
1----1--------
1----1--------
1
B'0 Ao
0 1 0
0 1 0
0
l 6(Bo) ?(Bo) B1
0111 - - - - - - - -
10001----i...~---H.;...._-
1001 1 - - - - r i . - - - - H - -
A1AoB1 Bo
0 1 1 0
0 1 1 1 8(0) 0 (0)
0
1010 J - - - + H - - - - - H + - -
1011 1----+t+------
ll 00 1-----ttt..-------;-r1--
1 0 0
1 0 0
0
1
l (I)
l 8(0)
B'
00 1101 --------t--H--
1110 1---+H-H.----H'+--
Bo ll 11 1----H+I-H----H-~
1 0 l 0 0
0 (0) 0l (B')
0, 0 A=B
10 1 1 0
B'
10
1 I 0 0 1 (1) 0 (0)
1 l 0 1 1 0. Bo
?(Bo) A1A0 B1. A>B A=B
Solution using 8 to 1 multiplexers Solution using 4 to 16

decoder
Though we are not presenting them as a

separate method, the AND bank (inside de-
coder) and OR bank combination concept 15 13 12 JO 1 14 11 9
4 0
presented here can be used to obtain solu-
tion from programmable logic devices such IC 7485 3
as PLA, PAL, etc.
2 0
In Method:..4, we follow a straightfor- ,_.;...__~5_ _~6;;.._______-'---'
ward approach to use a 4-bit comparator{IC
7485 : Fig. 4.38a}for the purpose as shown A=B
in Fig. 4.53. We keep the higher two bits 'O' Solution using 4-bit comparator
and 'A = B input' high so that it essentially
becomes a 2-'bit comparator generating all three outputs A > B, A = B and A < B of which only first
.two are useful here.
Amultiplexer is a circuit with many inputs but only one output. The 16-to-1 multiplexer has 16 input
bits, 4 control bits, and 1 output bit. The 4 control bits select and steer 1 of the 16 inputs to the output. The
multiplexer is a universal logic circuit because it can generate any truth table.
A demultiplexer has one input and many outputs. By applying control signals, we can steer the input
signal fo ·one of the output lines. A decoder is similar to a demultiplexer, except that there is no data input.
The control bits are the only input. They are decoded by activating one of the output lines.
BCD is an abbreviation for binary-coded decimal. The BCD code expresses each digit in a decimal
number by its nibble equivalent. A BCD-to-decimal decoder converts a BCD input to its equivalentdecimal
value. A seven-segment decoder converts a BCD input to an output suitable for driving a seven-segment
indicator.
An encoder converts an input signal into a coded output signal. An example is the decimal-to-BCD
encoder. An exclusive-OR gate has a high output only when a~ odd number of inputs are high. Exclusive:-
OR gates are useful in parity generators-checkers.
Magrutude comparators are useful in comparing two binary numbers. It generates three outputs that
give if one number is greater, equal or less than the other number. Cascading magnitude comparators we
can compare two numbers of any size.
A ROM is a read-only memory. Smaller ROMs are used to implement truth tables. ROMs are expensive
because they require a mask for programming. PROMs are user-programmable and ideal for small
production runs. EPROMs are not only user-programmable, but they are also erasable and reprogrammable
during the design and development cycle. PALs are chips that.are programmable arrays of logic. Unlike
the PROM with its fixed AND array and programmable OR array, a PAL has programmable AND array
and a fixed OR array. The PAL has the advantage ofhaving up to 16 inputs in commercially available
devices. In the PLA both the AND array and the OR array are programmable. The PLA is a much more
versatile programmable logic device (PLD) IC than the PROM or the PAL.
• active low The low state is the one that causes " even parity A binary number with an even
something to happen rather than the high number of 1s.
state. • exclusive-OR gate A gate that produces a high
• BCD A binary-coded decimal. output only when an odd number of inputs is
• data selector A synonym for multiplexer. high.
• decoder A circuit that is similar to a • LED A light-emitting diode.
demultiplexer, except there is no data input. • logic probe A troubleshooting device that
The control input bits produce one active indicates the state of a signal line.
output line. " Magnitude comparator compares two binary
• demultiplexer A circuit with one input and numbers and signals if one is greater, equal or
many outputs. less than other.
• EPROM An erasable programmable read- • multiplexer A circuit with many inputs but
only memory. With this device, the user can only one output.
erase the stored contents with ultraviolet light • odd parity A binary number with an odd
and electrically store new data. EPROMs are number of 1s.
useful during project development where • PAL A programmable array logic (sometimes
programs and data are being perfected. written PLA, which stands for programmable
logic array). In either case, it is a chip with links at the diode cross points. Once the data
a programmable AND array and a fixed OR is stored, the programming is permanent.
aITay. PROMs are useful for small production runs.
11 parity generation An extra bit that is generated
" ROM A read-only memory. An IC that. can
and attached to a binary number, so that the store many binary numbers at locations called
new number has either even or odd parity. addresses. ROMs are expensive to manufacture
" PLA A programmable logic array. and are used only for large production runs
" PLD A programmable logic device. where the cost of the mask can be recovered
" PROM A programmable read-only memory. A by sales.
type of chip that allows the user to program it • strobe An input that disables or enables a
with a PROM programmer that bums fusible circuit.
4.4 Show how to connect a 74150 to implement

this Boolean equation:
4.1 In Fig. 4.2, if ABCD = 1001, what does Y
equal? y = ABCD + ABCD + ABCD
4.2 In Fig. 4.4, if ABCD = llOO, what does Y 4.5 Draw a circuit with four 74150s that has a
equal? truth table like the one in Table 4.11.
4.3 We want to implement Table 3.12 of the 4.6 Table 4.12 shows the Gray code. Show how
preceding chapter using multiplexer logic. four 74150s may be connected to convert
Show a circuit, similar to the one in Fig. 4.4, from binary to Gray code. Show how the
that can do the job. same can be realized by four 74151 ICs (8-to-
l multiplexer).
A B C Y1 Yo A Yo
0 0 0 0 0 0 J 0 0 0 0 0 0 0
0 0 0 I I 0 I 0 0 0 0 1 0 1
0 0 1 0 0 0 0 0 0 0 l 0 0 0 1
0 0 I 0 1 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 I 0
0 0 I 0 0 0 0 ,Q 0 1 0 1
0 1 I 0 1 0 0 0 0 1 0 0 I 1
0 I 1 1 1 0 0 0 0 l l 1 0 1 0
I 0 0 0 0 I 0 l l 0 0 0 1 0
l 0 0 l 0 0 0 I J 0 0 I I l
1 0 1 0 0 0 0 0 l 0 1 0 I 1 l
1 0 l 0 0 0 0 1 0 1 l 1 1 0
J 0 0 0 0 0 0 1 0 0 l 0 l 0
1 1 0 1 0 1 0 1 l l 0 1 I 0 1 I
1 I I 0 l 0 1 0 I I 1 0 0 0 1
1 I 1 0 0 1 0 1 1 1 0 0 0
F 1(A,B) = L m(0,3) and

F2(A,B) =Lm(l,2)
4.7 In Fig. 4.12, if ABCD = 0101, which is the 4.13 Design a circuit that realizes following three
active output line when the strobe is high? functions using a decoder and three OR
When it is low? gates.
4.8 Input signals R and T are low in Fig. 4.13. F1(A,B,C) = L m(l,3,7),
Which is the active output line when ABCD = F2(A,B,C) = L m(2,3,5) and
0011? To have the Y9 output line active, what F3(A,B,C) = L m(O, 1,5,7)
input signals do you need?
4.9 Suppose a logic probe shows that pin 19,
given in Fig. 4.13, is always high. Which of
the following may possibly cause trouble: 4.14 Convert the following decimal numbers into
a. Pin 20 is grounded. their BCD equivalents:
b.Pin 18 has a sine wave instead of a. 32 b. 634
pulses. C. 4898
c. The R input is grounded. 4.15 Convert the following BCD numbers into their
d. The T input is connected to +5 V. decimal equivalents:
a. 0110 0111
b. 1000 0001 0011
C. 0111 0010 0101 1001
4.10 Are the output signals of Fig. 4.15 active low
or active high? For the IC to decode the ABCD 4.16 In Fig. 4.18, what is the high output line when
input, does the strobe have to be low or high? ABCD=Ol01?
4.11 In Fig. 4.16, supposeX= 1 andABCD = 0110. 4.17 In Fig. 4.20, which is the low output when
Which is the active chip and which is the ABCD = 0111?
active output line? 4.18 Figure 4.54 shows a group of chips numbered
4.12 Design a circuit that realizes following two 0 through 9. Each chip has an active-low
functions using a decoder and two OR gates. STROBE input. Which chip is active for each
of these conditions:
ChipO Chip 1 Chip2 ··········· Chip9

I 111 II
STROBE STROBE 111111 STROBE
+5V
Yo I 11111
16 111111
Vee Y1
Yz 111111
12 Y3 111 I I
A 1111
13 Y4
B 111
14 Ys
C y6 11
15
D I
Y7
Yg
8
GND Y9
-
a. ABCD = 0000.
b. ABCD = 0010.
c. ABCD = 1001. 4.22 In Fig. 4.25, what is the output when button 7
4.19 The ABCD input of Fig. 4.54 initially equals is pressed? When button 3 is pressed?
1111. For this condition, all output waveforms 4.23 In Fig. 4.27, if button 8 is pressed, which
start high in the timing diagram of Fig. 4.55. is the input pin that goes into the low state?
Another circuit not shown is supposed to What does the ABCD output equal?
produce the following input values of ABCD:
0000, 0001, 0010, 0011, 0100, 0101, 0110,
0111, 1000, and 1001.
4.24 In Fig. 4.32d, what does Y equal for each of
Yo
the following inputs:
Y, --U LJ a. 000110 b. 011001
Y2 C. 011111 d. 111100
4.25 In Fig. 4.33, what does Y equal for the
Y3
following inputs:
Y4 a. 1111 0000 0000
1111
Ys b. 0101 1010 1100 0111
y6 C. 1110 1011 1101 0001
d. 0001 0101 0011 0110
Y7
4.26 In Fig. 4.56, the 8-bit register is a logic circuit
Yg
that stores byte A 1 ... A 0 . What does byte Y1
Y9 ... Yo equal for each of these conditions:
a. A1 ... Ao= 1000 0111 and INVERT= 0.
b. A1 ... Ao= 0011 1100 and INVERT= I.
The timing diagram tells us that something c. A 7 ... Ao= 1111 0000 and INVERT= 0.
is wrong with the logic circuit of Fig. 4.54. d. A 7 ... Ao= 1110 0001 and INVERT= 1.
Which of the following is a possible trouble:
a. Pin 16 is not connected to the supply 8-bit register
voltage. b. Pin 8 is open.
c. Pin 12 is short-circuited to the ground.
d.Pin 15 is short-circuited to +5 V.
4.20 ln Fig. 4.21, which of the segments have to be

active to display the following digits:
a. 2 b. 6 4.27 In Fig. 4.57 on the next page, each register
C. 8 is a logic circuit that stores a 6-bit number.
4.21 In Fig. 4.23a, Vcc = +5 V, all resistors are 1 The left register stores A 5 ••• Ao and the right
k.Q, and each LED has a voltage drop of 2 register stores B 5 ..• B 0 . What value does the
V. Approximately how much cun-ent is there output signal labeled EQUAL have for each of
through an active segment? these:
4.30 In Fig. 4.58, assuming the circuit is working

A register B register all right, what will the logic probe indicate for
A5 A4 A 3 A 2 A 1 A0 B5 B4 B3 B2 B 1 B0
each of the following:
TFFr~~~o a. Input data has even parity.
b. Input data has odd parity.
c. Pins 3 and 4 are grounded.
4.31 Write the (X > Y) equation for a 4-bit
comparator.
4.32 Show how magnitude of two IO-bit numbers
EQUAL
can be compared using IC 7485.
4.33 Suppose a ROM has 8 input address lines.
How many memory locations does it have?
4.34 Two 74S370s are connected in parallel. To
a. A 7 ••• Ao is less than B1 ... Bo. address all memory locations, how many bits
b. A1 ... Ao equals B1 ... Bo. must the binary address have?
c. A1 ... Ao is greater than B1 ... B+ 4.35 In Fig. 4.40, ifABC= 011, what does Y3Y2Y1 Yo
equal?
4.36 Draw a ROM circuit similar to the one in Fig.
4.40 that produces these outputs:
4.28 In Fig. 4.58, what does X8 equal for each of
the following X 7 ••• Xo inputs: Y3 =ABC
a. 0000 1111 b. 1111 0001 Y2 ABC+ABC
C. 1010 1110 d. 1011 1100
Yi= ABC+ ABC+ ABC
4.29 In Fig. 4.58, what changes can you make to
get a 9-bit output with even parity? Yo =ABC+ ABC+ ABC+ ABC
+5 V 1 2 8 9 10 11 12 13
14
: ODDINPUT
EVEN INPUT 74180
7
~ODD OUTPUT
4.37 Draw a PROM circuit similar to the one in Fig. 4.40 Write. the Boolean expression for the output
4.41 that generates the Y3 to Yo output given in Y3 in Fig. 4.42.
Table 4.11. 4.41 The input to the PLA in Fig. 4.47 is ABCD
4.38 What is the Boolean equation for Y3 in Fig. = 0011. What segments of the indicator are
4.59 on the previous page? For Y2? For Yi? illuminated and what decimal number is
For Yo? displayed? What if ABCD = 1001? What
4.39 Draw a 4-input and 4-output PAL circuit that about 1111?
has the truth table of Table 4.11. 4.42 Will there be any ambiguity ifsegmentgofthe
7-segment indicator in Fig. 4.47 is defective
(burned out)? What numbers are displayed?
A B C D
RiRiKl ~ Fixed OR array

AIM:. The· aim of this. experiment is to dis- Work element: Verify the truth table of
play one of two BCD numbers in a 7-..segment multiplexerIC 74157. Note that STROBE is an
display, input .and find its use. The common select line
applies to all four 2-to- l multiplexers. Verify
Theory: .·. . . . BCffm.~bt!rs ca!lbe se- the truth table ofIC7446 for BCD inputs. Select
lected by activating select line of a multiplexer.
The multiplexer output then is one of the two ~

BCD numbers. These outputs can be connect- BCD input
ed tO four inputs of a ?-segment decoder/driv-
resistance values to be connected in the range
er. The outputs of this driver can be connected
220 to 1000 ohm. This is to ensure that entire
to a ?-segment display to display.the decimal
power supply voltage does not drop across the
equivalent of the BCD number selected.
LED of display. Interconnect properly all the
Apparatus: 5 V DC Power supply, Multime- different units and verify.
ter, and Bread Board
L Multiplexer 9. LED stands for light-emitting diode.

2. It means that active low. IO. See Fig. 4.21.
3. Demultiplexer 11. Each segment is an LED.
4. ASCD= HLHL 12. An encoder converts an active input
It will be high since STROBE is high. signal into a coded output signal, for
6. The outputs are active low. instance, decimal to binary.
Y10 is low; all other outputs are high. 13. The TTL 74147 is a decimal-to-binary
8. BCD stands for binary-coded decimal. encoder.
14. The output for an exclusive-OR gate is 22. PROM stands for programmable read-
high only when an odd number of inputs only memory.
are high. 23. PAL stands for programmable array
15. See Fig. 4.30. logic.
16. There are an even number of ls (highs). 24. The AND array is programmable; the
17. True. OR array is fixed.
18. Three:X= Y,X> YandX< Y. 25. PLA stands for programmable logic
19. Three. array.
20. ROM stands for read-only memory. 26. In a PLA, both the AND array and the
21. A 512 x 8 ROM is arranged as 512 OR array are programmable.
eight-bit words. 27. Decimal 3; segments abcdg
Number Systems and Codes
+ Convert decimal numbers to binary and convert binary numbers to decimal

+ Convert binary and decimal numbers to octal and convert octal numbers to binary
and decimal
+ Convert binary and decimal numbers to hexadecimal and convert hexadecimal
numbers to binary and decimal
+ Describe the ASCII code, excess-3 code, and Gray code
+ Understand Error Detection and Correction Code
5.1 BINARY NUMBER SYSTEM

The bina,y number system is a system that uses only the digits O and I as codes. All other digits (2 to 9) are
thrown away. To represent decimal numbers and letters of the alphabet with the binary code, you have to
use different strings of binary digits for each number or letter. The idea is similar to the Morse code, where
strings of dots and dashes are used to code all numbers and letters. What follows is a discussion of decimal
and binary counting.
Decimal Odometer
To understand how to count with binary numbers, it helps to review how an odometer (miles indicator of a
car) counts with decimal numbers. When a car is new, its odometer starts with
00000
After 1 km the reading becomes
00001
Successive kms produce 00002, 00003, and so on, up to

00009
A familiar thing happens at the end of the tenth km. When the units wheel turns from 9 back to 0, a tab on
this wheel forces the tens wheel to advance by 1. This is why the numbers change to
00010
Reset-and-Carry
The units wheel has reset to Oand sent a carry to the tens wheel. Let's call this familiar action reset and cany
The other wheels of an odometer also reset and carry. For instance, after 999 kms the odometer shows
00999
What does the next km do? The units wheel resets and caiTies, the tens wheel resets and carries, the
hundreds wheel resets and carries, and the thousands wheel advances by 1, to get
01000
Binary Odometer
Visualize a binary odometer as a device whose wheels have only two digits, 0 and 1. When each wheel turns,
it displays 0, then 1, then back to 0, and the cycle repeats. A four-digit binary odometer starts with
0000 (zero)
After 1 mile, it indicates
0001 (one)
The next mile forces the units wheel to reset and carry, so the numbers change to
0010 (two)
The third mile results in 4-Digit Binary Numbers
OOll (three)
Binary Decimal
After 4 miles, the units wheel resets and carries, the
0
second wheel resets and carries, and the third wheel ad-
1
vances by 1: 2
0100 (four) 3
4
Table 5.1 shows all the binary numbers from OOOOto
5
l ll 1, equivalent to decimal O to 15. Study this table care- OHO 6
fully and practice counting from 0000 to 1111 until you 0111 7
can do it easily. Why? Because all kinds oflogic circuits 1000 8
are based on counting from 0000 to 1111. 1001 9
The word bit is the abbreviation for binary digit. Table 1010 10
5.1 is a list of 4-bit number from 0000 to 1111. When a nm 11
binary number has 4 bits, it is sometimes called a nib- HOO 12
ble. Table 5.1 shows 16 nibbles (0000 to llll). A binary 1101 13
1110 14
number with 8 bits is known as a byte; this has become
llll 15
the basic unit of data used in computers. You will learn
NumberSystems and Codes
more about bits, nibbles, .and bytes in later chapters. For now memorise these definitions:
bit =X
nibble = XXXX
byte = XXXXXXXX
where the X may be a O oral.
1. What is the binary number~or dycimal 13?

2. Whatis the decimal.equivalent ofbim1ry 1001?
3. How many binary digits (bits)are required to represent decimal 15?
5.2 BINARY-TO-DECIMAL CONVERSION
Table 5.1 lists the binary numbers from 0000 to 111 L But how do you convert larger binary numbers into
their decimal values? For instance, what does binary 101001 represent in decimal numbers? This section
shows how to convert a binary number quickly and easily into its decimal equivalent.
Positional Notation and Weights

We can express any decimal integer (a whole number) in units, tens, hundreds, thousands, and so on. For
instance, decimal number 2945 may be written as
2945 = 2000 + 900 + 40 + 5
In powers of 10, this becomes
2945 = 2(10 3) + 9(10 2) + 4(10 1) + 5(10°)
The decimal number system is an example of positional notation, each digit position has a weight or
value. With decimal numbers, the weights are units, tens, hundreds, thousands, and so on. The sum of all the
digits multiplied by their weights gives the total amount being represented. In the foregoing example, the 2
is multiplied by a weight of 1000, the 9 by a weight of 100, the 4 by a weight of 10, and the 5 by a weight of
1; the total is
2000 + 900 + 40 + 5 = 2945
Binary Weights
In a similar way, we can rewrite any binary number in terms of weights. For instance, binary number 111
becomes
111=100+10+1 (5.1)
In decimal numbers, this may be rewritten as
7=4+2+1 (5.2)
Writing a binary number as shown in Eq. ( 5 .1) is the same as splitting its decimal equivalent into units, 2s,
and 4s as indicated by Eq. (5.2). In other words, each digit position in a binary number has a weight. The least
significant digit (the one on the right) has a weight of 1. The Binary System
second position from the right has a weight of 2; the next, 4;
and then 8, 16, 32, and so forth. These weights are in ascending Bit Position Weight
powers of 2; therefore, we can write the foregoing equation as 1 • (Right most) 1
2 1
7= 1(2 )+ 1(2 )+ 1(2°) 2
3 4
Whenever you look at a binary number, you can find its deci- 8
mal equivalent as follows: 16
1. When there is a 1 in a digit position, add the weight of 32
that position. 64
128
2. When there is a Oin a digit position, disregard the weight
of that position. For example, binary number 101 has a decimal equivalent of
4+0+1=5
As another example, binary number 1101 is equivalent to
8+4+0+1=13
Still another example is 1100 l, which is equivalent to
16 + 8 + 0 + 0 + 1 = 25
Streamlined Method
We can streamline binary-to~decimal conversion by the following procedure:
1. Write the binary number.
2. Directly under the binary number write 1, 2, 4, 8, 16 ... , working from right to left.
3. If a zero appears in a digit position, cross out the decimal weight for that position.
4. Add the remaining weights to obtain the decimal equivalent.
As an example of this approach, let us convert binary 101 to its decimal equivalent:
STEP 1 101
STEP 2 42 1
STEP 3 42 1
STEP4 4 + 1= 5
As another example, notice how quickly 10101 is converted to its decimal equivalent:
1 0 1 0 1
16 g 4 2 1 -+ 21
Fractions
So far, we have discussed binary integers (whole numbers). How are binary fractions converted into
corresponding decimal equivalents? For instance, what is the decimal equivalent of0.101? In this case, the
weights of digit positions to the right of the binary point are given by 1
t, t, t,
~ , and so on. In powers of 2,
the weights are
_ _ _ _ _ _ _ _ _ _ _ _ _ _N_u_m_b_er_S_y_st_em_s_a_n_d_C_od_e_s _ _ _ _ _ _ _ _ _ _ _ _ _ ~
or in decimal form:
Powers of 2
0.5 0.25 0.125 0.0625 etc.
Abbreviation
Here is an example. Binary fraction 0.101 has a
decimal equivalent of 1
2
0.1 0 1
4
0.5 + O+ 0.125 = 0625 8
Another example, the decimal equivalent of 16
32
0.1101 is
64
0.1 1 0 1 128
256
0.5 + 0.25 + 0 + 0.0625 = 0.8125
512
1,024
Mixed Numbers 2,048
For mixed numbers (numbers with an integer 4,096
and a fractional part), handle each part accord- 8,192
16,384
ing to the rules just developed. The weights for a
32,768
mixed number are
65,536 64K
etc. 23 22 2 1 20 · T 1
T 2
T 3
etc. 131,072 128K
i 262,144 256K
524,288 5I2K
Binary point
1,048,576 l,024K=lM
For future reference, Table 5.3 lists powers of 2,097,152 2,048K=2M
2 and their decimal equivalents and the numbers 4,194,304 4,096K::4M
ofK and M. The abbreviation K stands for 1024.
Therefore, lK means 1024. 2K stands for 2048, 4K represents 4096, and so on. The abbreviation M stands
for 1,048,576, which is equivalent to 1024K (1024 x 1024 = 1,048,576). A memory chip that stores 4096 bits
is called a "4K memory." A digital device might have a memory capacity of 4,194,304 bytes. This would be
referred to as a "4-megabyte (Mb) memory."
Convert binary 110.001 to a decimal number.
0
% 0.125 .'"'"7 6.125
What is the decimal value of binary l O11.11?
A computer has a 2 Mb memory. What is the decimal equivalent of 2 Mb?

Solution
This means that the computer can store 2,097,152 bytes iri its· memory.
4. What is the decimal equivalent of 1()010?

5. What is the binary equivalentof35'?
6. A binary number has 9 bits. What is the binary weight of the most significantbit'?
5.3 DECIMAL-TO-BINARY CONVERSION

One way to convert a decimal number into its binaiy equivalent is to reverse the process described in the
preceding section. For instance, suppose that you want to convert decimal 9 into the corresponding binary
number. All you need to do is express 9 as a sum of powers of 2, and then write 1s and Os in the appropriate
digit positions:
9=8+0+0+1
-:-7 1001
As another example:
25 = 16 + 8 + 0 + 0 + 1
-:-7. 11001
Double Dabble
A popular way to convert decimal numbers to binary numbers is the double~dabble method. In the double-
dabble method you progressively divide the decimal number by 2, writing down the remainder after each
division. The remainders, taken in reverse order, form the binary number. The best way to understand the
method is to go through an example step by step. Here is how to convert decimal 13 to its binary equivalent
Step 1 Divide 13 by 2, writing your work like this:
6
2 )13 I -:-7 (first remainder)
The quotient is 6 with a remainder of 1.

Step 2 Divide 6 by 2 to get
3
0 -:-7 (second remainder)
2)6
l -:-7 (first remainder)
2)13
This division gives 3 with a remainder of 0.
Step 3 Again you divide by 2:

I
2 f3 0 ~ (second remainder)
2 )6 I~ (first remainder)
2 )13 1 ~ (first remainder)
r
Here you get a quotient of I with a remainder of I.
Step 4 One more division gives
0
I (fourth ,emainde,)
2)1
1
2)3
0 Read down
2)6
I
2)13
In this final division 2 does not divide into 1; thus, the quotient is Owith a remainder of 1.
Whenever you arrive at a quotient of O with a remainder of 1, the conversion is finished. The remainders
when read downward give the binary equivalent. In this example, binary 1101 is equivalent to decimal 13.
There is no need to keep writing down 2 before each division because you are always dividing by 2. Here
is an efficient way to show the conversion of decimal 13 to its binary equivalent:
~1
0
1
3 Read down
6
2)13
Fractions
As far as fractions are concerned, you multiply by 2 and record a carry in the integer position. The carries read
downward are the binary fraction. As an example, 0.85 converts to binary as follows:
0.85 x 2 = 1.7 = 0.7 with a carry of I
0.7 x 2 = 1.4 = 0.4 with a carry of 1
0.4 x 2 = 0.8 = 0.8 with a carry ofO Read down
0.8 x 2 = 1.6 = 0.6 with a carry of 1
0.6 x 2 = 1.2 = 0.2 with a carry of 1
0.2 x 2 = 0.4 = 0.4 with a carry of 0
Reading the carries downward gives binary fraction 0.110110. In this case, we stopped the conversion
process after getting six binary digits. Because of this, the answer is an approximation. If more accuracy is
needed, continue multiplying by 2 until you have as many digits as necessary for your application.
Useful Equivalents
Table 5.4 shows some decimal-binary equivalences. This will be useful in the future. The table has an
important property that you should be aware of. Whenever a binary number has all 1s (consists of only 1s),
you can find its decimal equivalent with this formula:
Decimal = 211 - 1
where n is the number of bits. For instance, 1111 has 4 bits; therefore, its decimal equivalent is
Decimal = 24 - 1 = 16 -'- I = 15
Decimal-Binary Equivalences
Decimal Binary
l
3 11
7 111
15 1111
31 I 1111
63 11 1111
127 111 lll I
255 Ill! 1111
511 1 llll 1111
1,023 111111 llll
2,047 111 llll Ill!
4,095 ll 11 11 ll 1111
8,191 l llll llll 1111
16,383 ll llll 11111111
32,767 Ill 1111 1111 llll
65,535 1111 1111 llll 1111
As another example, 1111 1111 has 8 bits, so

Decimal= 28 - 1 =256-1 = 255
BCD-8421 and BCD-2421 Code

Binary Coded Decimal (BCD) refers to rep- BCD-8421 and BCD-2421 Code
resentation ofdigits 0-9 in decimal system
by 4-bit unsigned binary numbers. The usual Decimal BCD-8421 BCD-2421
method is to follow 8421 encoding which 0 0000 0000
employs conventional route of weight place- 1 0001 0001
ments like 8 representing the weight of the 4th. 2 0010 0010
place (as 24- 1 = 8), 4, i.e. 23- 1 of the 3rd place, 3 0011 0011'
2, i.e. 22- 1 of the 2nd place and 1, i.e. 2 1- 1 4 0100 0100
of the 1st place. The 2421 code is similar to 5 0101 1011
8421 code except for the fact that the weight 6 0110 HOO
assigned to 4th place is 2 and not 8. The deci- 7 Olll 1101
mal numbers 0-9 in these two codes then can 8 1000 1110
9 1001 llll
be represented as shown in Table 5.5.
As an example, decimal number 29 in BCD-8421 is written as 00101001 (0010 representing 2 and 1001
representing 9) while in BCD-2421, it is written as 00101111 (0010 representing 2 and 1111 representing
9).
Convert decimal 23.6 to a binary number.
Split decimal 23.6 into an integer of 23 ·and a fraction of 0.6, arid apply double dabble to each
0 1
1 0
2 Read down
5 1
11 I
2)23
and
0,6 x 2 = 1.2 = 0.2 with a carry ofl
0.2 x 2 = 0.4 = 0.4with a carry ofO
0.4 x 2 = 0.8 = 0.8 with a carry ofO Read down
0.8 x 2 = L6 = 0.6 with a carry ofl
0.6 x 2 = 0.2 0.2 vvith a carry of 1
The binary number is 10111.1001 L This 10-bit numberis an approximation of decimal 21.6 because we terminated
the conversion of the fractional part after 5 bits.
A digital computer processes binary numbers that are 32 bits long. If a 32-bit number has all
1s, what is its decimal equivalent?
Solution
Decimal a:231 - =(28)(28)(28)(28)-· I
=(256)(256)(256)(256)-l 4,294,967,295
7. Whatis double dabble?

A binafy nmnber is composed of twelve Ts. What is its decimal equivalent?
9. What is the binary number for decimal 255?
5.4 OCTAL NUMBERS
The base of a number system equals the number of digits it uses. The decimal number system has a base of
10 because it uses the digits O to 9. The binary number system has a base of 2 because it uses only the digits
0 and I. The octal number system has a base of 8. Although we can use any eight digits, it is customary to
use the first eight decimal digits:
0, 1,2,3,4,5,6, 7
(There is no 8 or 9 in the octal number code.) These digits, 0 through 7, have exactly the same physical
meaning as decimal symbols; that is, 2 stands for••, 5 symbolizes ..... , and so on.
Octal Odometer
The easiest way to learn how to count in octal numbers is to use an octal odometer. This hypothetical device
is similar to the odometer of a car, except that each display wheel contains only eight digits, numbered O to
7. When a wheel turns from 7 back to 0, it sends a carry to the next-higher wheel.
Initially, an octal odometer shows
0000 (zero)
The next 7 kms produces readings of
0001 (one)
0002 (two)
0003 (three)
0004 (four)
0005 (five)
0006 (six)
0007 (seven)
At this point, the least-significant wheel has run out of digits. Therefore, the next km forces a reset and
carry to obtain
0010 (eight)
The next 7 kms produces these readings: 0011, 0012, 0013, 0014, 0015, 0016, and 0017. Once again, the
least-significant wheel has run out of digits. So the next km results in a reset and carry:
0020 (sixteen)
Subsequent kms produce readings of 0021, 0022, 0023, 0024, 0025, 0026, 0027, 0030, 0031, and so on.
You should have the idea by now. Each km advances the least-significant wheel by one. When this wheel
runs out of octal digits, it resets and carries. And so on for the other wheels. For instance, if the odometer
reading is 6377, the next octal number is 6400.
Octal-to-Decimal Conversion
How do we convert octal numbers to decimal numbers? In the octal number system each digit position
corresponds to a power of 8 as follows:
g3 g2 gI gO. g-1 g-2 g-3
i
Octal point
Therefore, to convert from octal to decimal, multiply each octal digit by its weight and add the resulting
products. Note that s0 = I.
For instance, octal 23 converts to decimal like this:
2(8 1) + 3(8°) = 16 + 3 = 19
Here is another example. Octal 257 converts to

2(8 1)+5(8 1)+7(8°)= 128+40+7= 175
Decimal-to-Octal Conversion
How do you convert in the opposite direction, that is, from decimal to octal? Octal dabble, a method similar
to double dabble, is used with octal numbers. Instead of dividing by 2 (the base of binary numbers), you
divide by 8 (the base of octal numbers) writing down the remainders after each division. The remainders in
reverse order form the octal number. As an example, convert decimal 175 as follows:
0
8)2 2 ~ (third remainder)
8 }"TI 5 ~ (second remainder)
8 )175 7 ~ (first remainder)
You can condense these steps by writing
0
2 2~ ·1 Read down
21
8 )175
Thus decimal 175 is equal to octal 257.
Fractions
With decimal fractions, multiply instead of divide, writing the carry into the integer position. An example of
this is to convert decimal 0.23 into an octal fraction.
0.23 x 8 = 1.84 = 0.84 with a carry of 11
0.84 x 8 = 6.72 = 0.72 with a carry of6 Read down
0.72 x 8 = 5.76 = 0.76 with a carry of5
etc.
The carries read downward give the octal fraction 0.165. We terminated after three places; for more
accuracy, we would continue multiplying to obtain more octal digits.
Octal-to-Binary Conversion
Because 8 (the base of octal numbers) is the third power of 2 (the base of binary numbers), you can convert
from octal to binary as follows: change each octal digit to its binary equivalent. For instance, change octal 23
to its binary equivalent as follows:
2 3
t t
010 Oll
Here, each octal digit converts to its binary equivalent (2 becomes O10, and 3 becomes O11 ). The binary
equivalent of octal 23 is O10 011, or O10011. Often, a space is left between groups of 3 bits; this makes it
easier to read the binary number.
As another example, octal 3574 converts to binary as follows:

3 5 7 4
J, J, J, J,
011 101 111 100
Hence binary O11101111100 is equivalent to octal 3574. Notice how much easier the binary number is to
read ifwe leave a space between groups of3 bits: 011 101 111 100.
Mixed octal numbers are no problem. Convert each octal digit to its equivalent binary value. Octal 34.562
becomes
3 4 5 6 2
J, J, J, J, J,
011 100 101 110 010
Binary-to-Octal Conversion
Conversion from binary to octal is a reversal of the foregoing procedures. Simply remember to group the bits
in threes, starting at the binary point; then convert each group of three to its octal equivalent (Os are added at
each end, if necessary). For instance, binary number 1011.01101 converts as follows:
1011.01101 ~ 001 011. 011 010
J, J, J, J,
1 3 3 2
Start at the binary point and, working both ways, separate the bits into groups of three. When necessary,
as in this case, add Os to complete the outside groups. Then convert each group of three into its binary
equivalent. Therefore:
1011.01101 = 13.32
The simplicity of converting octal to binary and vice versa has many advantages in digital work. For one
thing, getting information into and out of a digital system requires less circuitry because it is easier to read
and print out octal numbers than binary numbers. Another advantage is that large decimal numbers are more
easily converted to binary if first converted to octal and then to binary, as shown in Example 5.6.
What is the binary equivalent of decimal 363?
Solution One approach is double dabble. Another approach is octal dabble, followed by octal-to~binary conversion.
Here is how the second method works:
Next, convert octal 553 to its binary equivalent:

:J
5 3
J, J,
101 101
The double-dabble approach would produce the same answer, hut it is tedious because you h,aye to divide by 2
times before the conversion terminates.
10. What are the digits used in the octal number system?
What is the oc~l,numberfor .binary. l ll? What is the decimal number. for binary 111?
5.5 HEXADECIMAL NUMBERS

Hexadecimal numbers are used extensively in
Hexadecimal Digits
microprocessor work. To begin with, they are much
shorter than binary numbers. This makes them easy to Decimal Binwy Hexadecimal
write and remember. Furthermore, you can mentally
0 0000 0
convert them to binary whenever necessary. l 0001 l
The hexadecimal number system has a base of 16. 2 0010 2
Although any 16 digits may be used, everyone uses 0 3 0011 3
to 9 and A to F as shown in Table 5.6. In other words, 4 0100 4
after reaching 9 in the hexadecimal system, you continue 5 0101 5
counting as follows: 6 0110 6
7 0111 7
A,B,C,D,E,F 8 1000 8
9 1001 9
Hexadecimal Odometer 10 1010 A
11 1011 B
The easiest way to learn how to count in hexadecimal
12 1100 C
numbers is to use a hexadecimal odometer. This 13 1101 D
hypothetical device is similar to the odometer of a car, 14 1110 E
except that each display wheel has 16 digits, numbered 0 15 1111 F
to F. When a wheel turns from F back to 0, it sends a carry
to the next higher wheel.
Initially, a hexadecimal odometer shows
0000 (zero)
The next 9 kms produces readings of The next 6 kms gives

0001 (one) OOOA (ten)
0002 (two) OOOB (eleven)
0003 (three) oooc (twelve)
0004 (four) OOOD (thirteen)
0005 (five) OOOE (fourteen)
0006 (six) OOOF (fifteen)
0007 (seven)
0008 (eight)
0009 (nine)
At this point, the least-significant wheel has run out of digits. Therefore, the next km forces a reset and
carry to obtain
0010 (sixteen)
The next 15 kms produces these readings: 0011, 0012, 0013, 0014, 0015, 0016, 0017, 0018, 0019, 001A,
OOIB, OOlC, 001D, OOlE, and OOlF. Once again, the least significant wheel has run out of digits. So, the next
km results in a reset and carry:
0020 (thirty-two)
Subsequentkmsproducereadingsof0021,0022,0023,0024,0025,0026,0027,0028,0029,002A,002B,
002C, 002D, 002E, and 002F.
You should have the idea by now. Each km advances the least-significant wheel by one. When this wheel
runs out of hexadecimal digits, it resets and carries, and so on for the other wheels. For instance, here are
three more examples:
Number Next number
835C 835D
A47F A480
BFFF cooo
Hexadecimal-to-Binary Conversion
To convert a hexadecimal number to a binary number, convert each hexadecimal digit to its 4-bit equivalent
using the code given in Table 5.5. For instance, here's how 9AF converts to binary:
9 A F
J, J, J,
1001 1010 1111
As another example, C5E2 converts like this:
C 5 E 2
J, J, J, J,
1100 0101 1110 0010
Binary-to-Hexadecimal Conversion
To convert in the opposite direction, from binary to hexadecimal, again use the code from Table 5.5. Here are
two examples. Binary 1000 llOO converts as follows:
1000 llOO
J, J,
8 C
Binary 1110 1000 1101 0110 converts like this:
1110 1000 1101 0110
J, J, J, J,
E 8 D 6
In both these conversions, we start with a binary number and wind up with the equivalent hexadecimal
number.
Hexadecimal-to-Decimal Conversion
How do we convert hexadecimal numbers to decimal numbers? In the hexadecimal number system each
digit position corresponds to a power of 16. The weights of the digit positions in a hexadecimal number are
as follows
16 3 16 2 16 1 16° . 16- 1 16-2 16-3
i
Hexadecimal point
Therefore, to convert from hexadecimal to decimal, multiply each hexadecimal digit by its weight and add
the resulting products. Note that 16° = 1.
Here's an example. Hexadecimal F8E6.39 converts to decimal as follows:
F8E6 = F(16 3) + 8(162) + E(16 1) + 6(16°) + 3(16- 1) + 9(16-2 )
= 15(163) + 8(162 ) + 14(16 1) + 6(16°) + 3(16- 1) + 9(16-2 )
= 61,440 + 2048 + 224 + 6 + 0.1875 + 0.0352
= 63,718.2227
Decimal-to-Hexadecimal Conversion
One way to convert from decimal to hexadecimal is the hex dabble. The idea is to divide successively by 16,
writing down the remainders. Here's a sample of how it's done. To convert decimal 2479 to hexadecimal, the
first division is
154 15 ~F
16)2479
In this first division, we get a quotient of 154 with a remainder of 15 (equivalent to F). The next step is
9 lO~A
154 15 ~F
16)2479
l
Here we obtain a quotient of9 with a remainder of 10 (same as A). The final step is
0
9~9
9 lO~A Read down
154 15~F
16)2479
Therefore, hexadecimal 9AF is equivalent to decimal 2479.

Notice how similar hex dabble is to double dabble. Notice also that remainders greater than 9 have to be
changed to hexadecimal digits (10 becomes A, 15 becomes F, etc.).
Using Appendix 1 *
A typical microcomputer can store up to 65,535 bytes. The decimal addresses of these bytes are from O to
65,535. The equivalent binary addresses are from
0000 0000 0000 0000

1111 1111 1111 1111
The first 8 bits are called the upper byte, and the second 8 bits are the lower byte.
If you have to do many conversions between binary, hexadecimal, and decimal, learn to use Appendix 1. It
has four headings: binwy, hexadecimal, upper byte, and lower byte. For any decimal number between O and
255, you would use the binary, hexadecimal, and lower byte columns. Here is the recommended way to use
Appendix 1. Suppose you want to convert binary 0001 1000 to its decimal equivalent. First, mentally convert
to hexadecimal:
0001 1000 ~ 18 (mental conversion)
Next, look up hexadecimal 18 in Appendix 1 and read the corresponding decimal value from the lower-
byte column:
18 ~ 24 (look up in Appendix 1)
For another example, binary 1111 0000 converts like this:
1111 0000 ~ FO ~ 240
The reason for mentally converting from binary to hexadecimal is that you can more easily locate a
hexadecimal number in Appendix 1 than a binary number. Once you have the hexadecimal equivalent, you
can read the lower-byte column to find the decimal equivalent.
When the decimal number is greater than 255, you have to use both the upper byte and the lower byte in
Appendix 1. For instance, suppose you want to convert this binary number to its decimal equivalent:
1110 1001 0 ll l 0100
First, convert the upper byte to its decimal equivalent as follows:
1110 1001 ~ E9 ~ 59,648 (upper byte)
Second, convert the lower byte to its decimal equivalent:
0111 0100 ~ 74 ~ 116 (lower byte)
Finally, add the upper and lower bytes to obtain the total decimal value:
59,648 + 116 = 59,764
Therefore, binary 1110 1001 0111 0100 is equivalent to decimal 59,764.
Once you get used to working with Appendix 1, you will find it to be a quick and easy way to
convert between the number systems. Because it covers the decimal numbers from Oto 65,535, Appendix 1
is extremely useful for microprocessors where the typical memory addresses are over the same decimal
range.
* A number of hand calculators will convert binary, octal, decimal and hexadecimal numbers.
A computer memory can store thousands of binary instructions and data. A typical
microprocessor has 65,536 addresses, each storing a byte. Suppose that the first 16 addresses
contain these bytes:
OOll llOO
1100 llOl
0101 Olll
0010 1000
1111 0001
0010 1010
1101 0100
0100 0000
Olll 0111
llOO 0011
1000 0100
0010 1000
0010 0001
OOll 1010
OOll lllO
0001 1111
Convert these bytes to their hexadecimal equivalents.
Solution Here are the stoted bytes and their hexadecimal equivalents:
00101000
llUOOOl
00101010
HOfOlOO
01000000
that it contains 3C. Either way, we obtain the .same information. But notice how much easier it
think 3C than it is to say, write, and thinkOO H 1100. In otherwords, hexadecimal numbers are tm1ch,easiiehFornec1nle
to work with.
Convert the hexadecimal numbers of the preceding example to their decimal equivalents.
Solution The first address contains 3C, which converts like this:
3(16 1)+C{l6°)=48+ 12=60
Even easier, look up the decimal equivalent of 3C in Appendix 1, and you get 60. Either by powers of 16 or with
reforence to Appendix 1, we can convert the other memory contents to get the following:
Memory contents Hexadecimal equivalents Decimal equivalents
0011 llOO 3C 60
1100 1101 CD 205
01010111 57 87
00101000 28 40
ll lJ 0001 Fl 241
00101010 2A 42
1101 0100 D4 212
01000000 40 64
om om 77
1100 0011 C3
10000100 84
00101000 28
00100001 21
0011 1010 3A
oonn10 3E
0001 llll 1F
Convert decimal 65,535 to its hexadecimal and binary equivalents.
Solution Use hex dabble as follows:

0
15 15~F Read down
255 1.5. . ~.F ··1··
15~F
4095 .15~F
16)65,535
is
Therefore, decimal 65,535 equivalent to hexadecimal FF'FE
Next, convert from hexadecimal to binary as follows:
F F F
i i
llll Illl 1111
This means that hexadecimal FFFF is equivalent to binary 1111 1111 · 1111 1111.
Show how to use Appendix l to convert decimal 56,000 to its hexadecimal and binary
equivalents.
Solution Th([! first thing to dois tolocate the largest decimal number equal to 56.000 or less in Appendix 1. The
number is 55,808, which converts like this:
55,80K-,i. DA (upper byte)
Next, you need to subtract this upper byte from the originalnumber:
56,000 55,808 = 192 (difference)
This difference is always less than 256 and represents the lower byte, which Appendix 1 converts as follows:
192 -,i. co
Now, combine the upper and lower byte to obtain
DACO
which you can mentally convert to binary:
DACO -,i. 1101 1010 llOO 0000
Convert Table 5.4 into a new table with three column headings: "Decimal," "Binary," and
"Hexadecimal."
Solution This is easy. Convert each group of bits to its hexadecimal equivalent as shown in Table 5.7.
Decimal-Binary-Hexadecimal Equivalences
Decimal Binary, hexadecimal

1 1 l
3 11 3
7 111 7
15 1 lll F
31 11 lll IF
63 111111 3F
127 1111111 7F
255 11111111 FF
511 111111 lll lFF
1,023 lll 1111 ll l 3FF
2,047 lllllllllll 7FF
4,095 111111111111 FFF
8,191 lll 11111 lll ll IFFF
16,383 ll ll 1111111111 3FFF
32,767 111111111111 l ll 7FFF
65,535 111111111 ll lll ll FFFF
What are the symbols used in hexadecimalnumbers?

Whatis the binary equivalent of hexadecimal 3C?
What is the decimal equivalent ofhexadecimal 3C?
To get information into and out of a computer, we need to use some kind of alphanumeric code (one for let-
ters, numbers, and other symbols). At one time, manufacturers used their own alphanumeric codes, which
led to all kinds of confusion. Eventually, industry settled on an input-output code known as the American
Standard Code for Information Interchange (ASCII, pronounced ask' -ee). This code allows manufacturers to
standardize computer hardware such as keyboards, printers, and video displays.
Using the Code

The ASCII code is a 7-bit code whose format is
X6X5X4X3X2X1Xo
where each Xis a O or a 1. Use Table 5 .8 to find the ASCII code for the uppercase and lowercase letters of the
alphabet and some of the most commonly used symbols. For example, the table shows that the capital letter
A has an X05X 4 of 100 and anX3X2X1Xo ofOOOl. The ASCII code for A is, therefore,
1000001
For easier reading, we can leave a space as follows:
100 0001 (A)
The letter a is coded as
110 0001 (a)
More examples are
110 0010 (b)
ASCII Code
X6X5X4
010 JOO 101 110 ill
SP @ p p
A Q a q
B R b r
# C C
$ D d
% E e
& F f
G g
( H h
) I
* J j
+ K k
L l
M m
N n
0 0
1100011 (c)
110 0100 (d)
and so on.
Also, study the punctuation and mathematical symbols. Some examples are
010 0100 ($)
010 1011 (+)
011 1101 (=)
In Table 5.7, SP stands for space (blank). Hitting the space bar of an ASCII keyboard sends this into a
microcomputer:
010 0000 (space)
Parity Bit
The ASCII code is used for sending digital data over telephone lines. As mentioned in the preceding chapter,
1-bit errors may occur in transmitted data. To catch these errors, a parity bit is usually transmitted along with
the original bits. Then a parity checker at the receiving end can test for even or odd parity, whichever parity
has been prearranged between the sender and the receiver. Since ASCII code uses 7 bits, the addition of a
parity bit to the transmitted data produces an 8-bit number in this format:
X1X6X5X4 X3X2X1Xo
i
Parity bit
This is an ideal length because most digital equipment is set up to handle bytes of data.
EBCDIC as Alphanumeric Code

There exists few others but relatively less used alphanumeric codes. The EBCDIC is an abbreviation of
Extended Binary Coded Decimal Interchange Code. It is an eight-bit code and primarily used in IBM make
devices. Here, the binary codes ofletters and numerals come as an extension of BCD code. The bit assignments
of EBCDIC are different from the ASCII but the character symbols are the same.
With an ASCII keyboard, each keystroke produces the ASCII equivalent of the designated
character. Suppose that you type PRINT X. What is the output of an ASCII keyboard?
A computer sends a message to another computer using an odd-parity bit. Here is the
message in ASCII code, plus the parity bit:
1100 1000
0100 0101
0100 1100
0100 1100
0100 1111
What do these numbers mean?
Solution First, notice that each 8-bit number has odd parity, an indication that no I-bit.errors occurred during
transmission. Next, use Table 5.7 to translate the ASCII.characters. If you do this correctly, you get a message of
HELLO.
15. \\'hat is the ASCII code?

16. What symbol is represented by the ASCII code 100 0000?
17. \\'hat ASCIIcode is used for
the percent sign, %?
5.7 THE EXCESS-3 CODE
The excess-3 code is an important 4-bit code sometimes used with binary-coded decimal (BCD) numbers. To
convert any decimal number into its excess-3 fonn, add 3 to each decimal digit, and then convert the sum to
a BCD number.
For example, here is how to convert 12 to an Take another example; convert 29 to an excess-3
excess-3 number. First, add 3 to each decimal digit: number:
1 2 9
+3 +3 +3 +3
- -
4 5 5 12
Second, convert the sum to BCD fom1: j, j,
4 5 0101 llOO
j, j,
After adding 9 and 3, do not carry the 1 into the
0100 0101
next column; instead, leave the result intact as 12,
So, 0100 0101 in the excess-3 code stands for and then convert as shown. Therefore, 0101 1100 in
decimal 12. the excess-3 code stands for decimal 29.
Table 5.9 shows the excess-3 code: In each case,
the excess-3 code number is 3 greater than the BCD
equivalent. Such coding helps in BCD arithmetic as
9's complement of any excess-3 coded number can
be obtained simply by complementing each bit. Take 0000 0011
for example decimal number 2. Its 9's complement is 0001 0100
0010 0101
9- 2 = 7. Excess-3 code of2 is 0101. Complementing
OOll OHQ
each bit we get 1010 and its decimal equivalent is 7. 0100 0111
To convert BCD to excess-3 we need an adder and for 0101 1000
the reverse we need a subtractor. These circuits are 0110 1001
discussed in the next chapter. Incidentally, if you need 0111 1010
an integrated circuit (IC) that converts from excess 1000 1011
3 to decimal, look at the data sheet of a 7443. This 1001 1100
transistor-transistor logic (TTL) chip has four input
lines for the excess-3 input and IO output lines for the decoded decimal output.
5.S
The advantage of such coding will be understood from this example. Let an object move along a track and
move from one zone to another. Let the presence of the object in one zone is sensed by sensors ABC. If
consecutive zones are binary coded then zone-0 is represented by ABC= 000, zone- I by ABC= 001, zone-
2 by ABC= 010 and so on, as shown in Fig. 5.la. Now consider, the object moves from zone-1 to zone-2.
Both BC has to change to sense that movement. Suppose, sensor B (may be an electro-mechanical switch)
reacts slightly late than sensor C. Then, initially ABC= 000 is sensed as if the object has moved in the other
direction from zone-1 to zone-0. This problem can be more prominent if the object moves from zone-3 (ABC
= 011) to zone-4 (ABC= 100) when all three sensors has to change its value. Note that, if zones are gray
coded (Fig. 5.lb) such problem does not appear as between two consecutive zones only one sensor changes
its value.
Zone No. 0 1
0 - 2 3 4 5 6 7
Sensor ABC 000 001 010 011 100 101 110 111
(Binary coded)
(a)
o-
Zone No. 0 1 I 2 3 4 5
111
6
101
7
100
Sensor ABC 000 001 011 010 110
( Gray coded)
(b)
Object moving along a track with sensors: (a) Binary coded, (b) Gray coded
The disadvantage with gray code is that it is not good for arithmetic operation. However, comparing truth
tables of binary coded numbers and gray coded numbers (Table 5.18) we can design binary to gray converter
as shown in Fig. 5.2a and gray to binary converter as shown in Fig. 5.2b. Let's see how these circuits work
by taking one example each.
(MSB)B 3 G3 G3 B3
G2
Bz
B2
Bi
Bi GI
(LSB)B 0 Go
(a) (b)
(a) Binary to Gray converter, (b) Gray to Binary converter
Consider, a binary number B3B2 B i Bo= IO ll. Following the relation shown in Fig. 5.2a we get, G3 = B3 =
1, G2 = B3 ffi B 2 = 1 ffi O= 1, G1 = B 2 ffi B 1 = 0 ffi 1 = 1 and Go = B 1 ffi Bo= 1 ffi 1 = 0, i.e. G3 G2 G1 Go = 1110
and we can verify the same from truth table.
Similarly, for a gray coded number say, G3 G2G 1 Go

= 0111 from Fig. 5.2b we get, B3 = G3 = 0, B2 = G3
EB G2 = 0 EB 1 = 1, Bi= B2 EB G1 = 1 EB l = 0 andBo
= B 1 EB G0 = 0 EB 1 = 1, i.e. B 3 B2B 1B0 = 0101. Again 0000
this conversion can be verified from Table 5.10 that 0001
shows the Gray code, along with the corresponding OOil
binary numbers. Each Gray-code number differs from 0010
any adjacent number by a single bit. For instance, in OllO
going from decimal 7 to 8, the Gray-code numbers 5 Olll
change from 0100 to 1100; these numbers differ only 6 0101 0110
in the most significant bit. As another example, deci- 7 0100 OUJ
mal numbers 13 and 14 are represented by Gray-code 8 1100 1000
numbers 1011 and 1001; these numbers differ in only 9 1101 1001
10 1111 1010
one digit position (the second position from the right).
11 lllO 1011
So, it is with the entire Gray code; every number dif- 12 1010 1100
fers by only 1 bit from the preceding number. 13 1011 1101
Besides the excess-3 and Gray codes, there are oth- 14 1001 lllO
er binary-type codes. Appendix 5 lists some of these 15 1000 nn
codes for future reference. Incidentally, the BCD code
is sometimes referred to as the 8421 code because the
weights of the digit positions from left to right are 8, 4, 2, and 1. As shown in Appendix 5, there are many
other weighted codes such as the 7421, 6311, 5421, and so on.
5.9 TROUBLESHOOTING WUHA lOGIC PULSER

Figure 5.3 shows a typical logic pulser, a trouble-
shooting tool that generates a brief voltage pulse
when its push-button switch is pressed. Because of
its design, the logic pulser (on the left) senses the Push-button switch
original state of the node and produces a voltage
pulse of the opposite polarity. When this happens,
the logic probe (on the right) blinks, indicating a
temporary change of output state.
Thevenin Circuit Using a logic pulser and a

Figure 5.4a shows the Thevenin equivalent circuit logic probe
for a typical logic pulser. The Thevenin voltage is
a pulse with an amplitude of 5 V; the polarity automatically adjusts to the original state of the test node. As
shown, the Thevenin resistance or output impedance is only 2Q. This Thevenin resistance is representative;
the exact value depends on the particular logic pulser being used. Typically, a TTL gate has an output resis-
tance between 12Q (low state) and 70Q (high state). When a logic pulser drives the output ofa NAND gate,
the equivalent circuit appears as shown in Fig. 5.4b. Because of the low output impedance (2Q) of the logic
pulser, most of the voltage pulse appears across the load (12 to 70Q). Therefore, the output is briefly driven
into the opposite voltage state.
2Q 2Q
r
+5~_f1__
or
+5~--u--
(a) (b)
+5V
Short to
2Q Test
2Q supply Test
+5~_f1__ node node
or rt to
und
+5~--u--
(c)
= =
(d)
(a) Thevenin equivalent of logic pulser, (b) Logic pulser driving NAND-gate
output, (c) Node stuck in high state
Testing Any Node

You can use a logic pulser to drive any node in a circuit, whether input or output. Almost always, the load
impedance of the node being driven is larger than the output impedance of the logic pulser. For this reason,
the logic pulser can usually change the state of any node in a logic circuit. Also, the pulse width is kept very
short (fractions of a microsecond) to avoid damaging the circuit being tested. (Note: Power dissipation is
what damages ICs. A brief voltage pulse produces only a small power dissipation.)
Stuck Nodes
When is a logic pulser unable to change the state of a node? When the test node is shorted to ground or to
the supply voltage. For instance, Fig. 5.4c shows the test node shorted to ground. In this case, all the voltage
pulse is dropped across the internal impedance of the logic pulser; therefore the test node is stuck at OV, the
low state.
On the other hand, the test node may be shorted to the supply voltage as shown in Fig. 5.4d. Most power
supplies are regulated and have impedances in fractions of 1Q. For this reason, most of the voltage pulse
is again dropped across the output impedance of the logic pulser, which means that the test node is stuck at
+5V.
Finding Stuck Nodes

If a circuit is faulty, you can use a logic pulser and logic probe to locate stuck nodes. Here's how. Touch both
the logic pulser and the logic probe to a node as shown in Fig. 5.3. If the node is stuck in either state, the logic
pulser will be unable to change the state. So, if the logic probe does not blink, you have a stuck node. Then,
you can look for solder bridges on any trace connected to the stuck node, or possibly replace the IC having
the stuck node.
5.10 ERROR DETECTION AND CORRECTION
Error Detection and Correction (EDAC) techniques are used to ensure that data is correct and has not been
corrupted, either by hardware failures or by noise occurring during transmission or a data read operation from
memory. There are many different error correction codes in existence. The reason for different codes being
used in different applications has to do with the historical development of data storage, the types of data
errors occurring, and the overhead associated with each of the error-detection techniques. We discuss some
of the popular techniques here with details of Hamming code.
Parity Code
We have discussed parity generation and checking in detail in Section 4.8. When a word is written into
memory, each parity bit is generated from the data bits of the byte it is associated with. This is done by a tree
of exclusive-OR gates. When the word is read back from the memory, the same parity computation is done on
the data bits read from the memory, and the result is compared to the parity bits that were read. Any computed
parity bit that does not match the stored parity bit indicates that there was at least one error in that byte (or in
the parity bit itself). However, parity can only detect an odd number of errors. If even number of errors occur,
the computed parity will match the read parity, so the error will go undetected. Since memory errors are rare
if the system is operating correctly, the vast majority of errors will be single-bit errors, and will be detected.
Unfortunately, while parity allows for the detection of single-bit errors, it does not provide a means of
determining which bit is in error, which would be necessary to correct the error. Thus the data needs to be
read again if an error is detected. Error Correction Code (ECC) is an extension of the parity concept.
Checksum Code
This is a kind of error detection code used for checking a large block of data. The checksum bits are generated
by summing all the codes of a message and are stored with data. Usually the block of data summed is of
length 512 or 1024 and the checksum results are stored in 32 bits that allow overflow. When data is read, the
summing operation is again done and checksum bits generated are matched with the stored one, If they are
unequal, then an error is detected. Obviously, it can fool the detection system if error occurring at one place
is compensated by the other.
Cycle Redundancy Code (CRC)

CRC code is a more robust error checking algorithm than the previous two. The code is generated in the
following manner. Take a binary message and convert it to a polynomial, then divide it by another predefined
polynomial called the key. The remainder from this division is the CRC. This is stored with the message.
Upon reading the data, memory controller does the same operation, i.e. divides the message by the same key
and compares with CRC stored. If they differ, then the data has been wrongly read or stored. Not all keys are
equally good. The longer the key, the better is the error checking. On the other hand, the calculations with
long keys can get quite complex. Two of the polynomials commonly used are:
CRC-16 =x 16 + x15 + x2+ 1
CRC-32 = X32 + X26 + X23 + X22 + X16 + X12 + XJ 1 + X10 + Xg + X7 + X5 + X4 + X2 + x + 1
Usually, series of exclusive-OR gates are used to generate CRC code. We shall see in the next chapter that
t~e sum term arising out of addition is essentially an exclusive-OR operation.
Hamming Code
Introduced in 1950 by R W Hamming, this scheme allows one bit in the word to be corrected, but is unable to
correct events where more than one bit in the word is in error. These multi-bit errors can only be detected, not
corrected, and therefore will cause a system to malfunction. Hamming code uses parity bits discussed before
but in a different way. For n number of data bits, if number of parity bits required here ism, then
2m;:::m+n+ 1
In the memory word, (i) all bit positions that are of the form i are used as parity bits (like 1, 2, 4, 8, 16,
32 ... ) and (ii) the remaining positions are used as data bits (like 3, 5, 6, 7, 9, 10, 11, 12, 13, 14, 17, 18 ... )
Thus code will be in the form of
Pl P2 D3 P4D5 D6D7 P8 D9 DlO Dll ...
where Pl, P2, P4, P8 ... are parity bits and D3, D5, D6, D7 ... are data bits.
We discuss Hamming code generation with an example. Consider the 7-bit data to be coded is O110101.
This requires 4 parity bits in position 1, 2, 4 and 8 so that Hamming coded data becomes 11-bit long. To
calculate the value of PI, we check parity of zeroth binary locations of data bits. This is shown in 3rd row of
Fig. 5.5 for this example. Zeroth locations are the places where address ends with a 1. These are D3, D5, D9
and D 11 for 7-bit data. Since we have total odd number of 1s in these 4 positions P 1 = I. This is calculated as
done in case of parity generation (refer to Section 4.8) by series of exclusive-OR gates through the equation
Pl= D3 EB D5 EB D9 EB Dll
Similarly for P2, we check locations where we have 1 in address of the 1st bit, i.e. D3, D6, D7, D 10 and
D 11. Since there are even number of 1s, P2 = 1. Proceeding in similar manner and examining parity of 2nd
and 3rd position, we get P4 = 0 and P8 = 0.
0001 0010 OOll 0100 0101 0110 01 ll 1000 1001 1010 1011
Pl P2 D3 P4 D5 D6 D7 PS D9 DlO Dll
Data word (without parity) 0 1 .. 1 0 1 0 1
Pl 1 0 1 0 l 1
P2 0 0 1 0 0 I
P4 0 l 1 0
PS 0 l 0 l
Data with parity 1 0 0 0 1 l 0 0 1 0 1
Calculation of Parity Bits
Next we discuss how error in a Hamming coded data is detected and if it is in single bit, how it is corrected.
We continue with the previous example and consider that the data is incorrectly read in position D 11 so that
11-bit coded data is 10001100100. Figure 5.6 describes the detection mechanism. First of all, we check the
parity of zeroth position and find it to be even. Since Pl = 1, the parity check fails and this is equivalent to
generating a parity bit at the output (last column) following the equation
Parity Pl check bit= D3 EB D5 EB D9 EB Dll EB Pl
This is similar to parity checker in Section 4.8. Note that, in addition to data bits, we have also included the
corresponding parity bit to the input of exclusive-OR gate tree. Proceeding similarly for other positions, we
find that except for P4 all other parity checks fail. Note that, even a single failure detects an error. However,
to correct the error, we use the output of last column 1011 (in the order PS P4 P2 Pl) and find its decimal
equivalent which is 11. So the data of location 11, which is D 11 needs to be corrected.
Pl P2 D3 P4 D5 D6 D7 PS D9 Dl0 Dll Parity Parity

check bit
Received data word I 0 0 0 I 1 0 0 I 0 0
Pl I 0 1 0 I 0 Fail 1
P2 0 0 1 0 0 0 Fail 1
P4 0 1 I 0 Pass 0
PS 0 1 0 0 Fail 1
Error detection and correction
Note that, this method detects error in more than one position unlike.the first method but overhead is more.
In simple parity method, we add I additional bit for 7-bit data whreas it is 4 in this method. Also note, by
further increasing this overhead, error in more than one position can also be corrected. However, more than
one-bit error is unlikely for memory read. With overhead for one-bit correction, ifthere occurs error in more
than one-bit positions, then the data needs to be read once again from the memory.
18. Can parity code detect even number of errors?

19. What is the full form ofCRC?
20. What is the advantage of Hamming code'?
21. Whatis error detection-correction overhead?
PROBLEM SOLVING WITH MUti8PlEMETH00S

Add two gray coded numbers O100 and O111 and express the result in gray code.
Solution Since gray coded numbers are not suitable for arithmetic operations, we h.ave to co;nvert the numbers
to some Other form, perform the addition and then convert the resu!rto gray £Ode. \Ve first show how it Can be done
through lookup tables. It would require storage oflargeJook:µp tables,ifthenumbers.are large in value. Next, we
show the converter-based approach which only needs the implementation ofconversion equations.
In Method-1, ·.· we take help of first two columns of Table 5.9 ~~dconvert these two numb.~rs t? ~eci-
mal, add the decimal numbers. and then again use the table to; get corresponding gray coded number:
This is shown in Fig. 5.7a. ·
In Method-2, we take help oflast two c.olU1U11s of Table 5,,9 ~d convert th!;lse two numbers.to 1:>inary.,
perform binary addition and. then again use the table. to get corresponding gray coded number. This is
shown in Fig. 5.7b.
·'" Method-3,.. we take help. of gray to. binary. conversion.relati?n sho;vn inFig. 5.2ba11d pot1yert
these two numbers to binary, perform binary addition and then use binary to gray conversion relation'
shown in Fig. 5.2a to get corresponding gray coded number. This is shown in Fig. 5.7c.
UsingTable.5.9
Gray Binary
0100 0111 Binary Gray
Olll +0101 1100 1010
1100
(b) Addition using Method-2
From Fig. 5.2b
Gra)'to Biliary Conversion: B3 =63 B2=B3$G2 B1 @G1 Bo=B1 $Go Binary
GfG2G1Go"" 0100: lJ3=0 B2=0$= l B1 =l $ 0 =1 Bo= l $0= I 0111
ForG]G2G1Go =0110: B3=0 B2=0$ l= B1 = 1 @1 =O Bo= 0 EB 1 = I +0101
1100
.From .Fig, 5.2a
Binarytl) Gray C?t1V(:rsio11: (73=B3 =B3@B2 G1=B2E!3B1 Go.= Bi@ Bo Gray
ForB3 l12 B! lfo = 1100: B3 = 1 .B2= 1 $=0 B1 = 1 $0= 1 Bo= 0@ 0 = 0 1010
(c}Addition using.Methodc3
of
To c?hverffrom ~in~ to decimal nµInbers, add the "'.eight each bi.t position (1, 2, 4, s, ... )when .there is
a.1 in that po~ition. With fractions, the binary weights are J,{J, _,.,and so on. To convert from decimal
tobin.iry, ~ do~ble da~ble for integers and the multiply-bY:.2method for fractions.
Th! b~se.of ~ n~ber systein equats the number of digits it uses, The decimal number systeIU has base
oUO,while the binary number system has a base of 2. The octal number system has a base of8. Auseful
a
model for counting is the octalodometer•When a display wheel turns from 7back to 0, it sends a carry to
the next-higher wheel.
Hexadecimal numbers have a base of 16. The model for counting is. the hexadecimalodometer, whose
wheels reset and carry beyond F. He)lt~~eciIUaln~bers are ~asytoconvert mentallyinto thefrb'
equivalents. For this reason, people prefetusinghexadecimalnunibers because they aremuchsharter
the corresponding binary numbers.
The ASCII code is an alphanumeric code widely used for transferring data into cu,~,v~u
~ 7-bi.t 5ode i~ used to. represe11t alphabet letters, numpers, and other symbols. The excess-3
the Gray code are two other codes that are used.
A logic pulser can temporarily change the state of a node under test.If the original state is low, the logic
pulser drives the node briefly into the high state. If the state is high, the logic pulser drives the node briefly
into the low state. The output impedance of a logic pulser is so low that it can drive almo$t. any normal
node in a logic circuit When a node is shorted to ground or to the supply voltage, thelogic pulseds unable
to change the voltage level; this is a confirmation of the shorted condition.
Parity code, Checksmn code, and CRC code have been discussed for error detectioncodeand Banµning
code for error detection and correction. These techniques are used to ensure that datais correct and has
not been corrupted, either by hardware failures or by noise occurring during transmission or a data read
operation from memory.
• base The number of digits or basic symbols in " hexadecimal Refers to number system with a
a number system. The decimal system has a base of 16. The hexadecimal system has digits
base of 10 because it uses 10 digits. Binary has 0 through 9, followed by A through F.
a base of 2, octal a base of 8, and hexadecimal • logic pulser A troubleshooting device that
a base of 16. generates brief voltage pulses. The typical
• binary Refers to a number system with a base logic pulser has a push-button switch that
of 2, that is, containing two digits. produces a single pulse for each closure. More
• bit An abbreviated fom1 of binary digit. advanced logic pulsers can generate a pulse
Instead of saying that 10110 has five binary train with a specified number of pulses.
digits, we can say that it has 5 bits. • nibble An binary number with 4 bits.
• byte A binary number with 8 bits. " octal Refers to a number system with a base
• checksum code A error detection code of 8, that is, one that uses 8 digits. Normally,
generating sum of a block of data. these are 0, 1, 2, 3, 4, 5, 6, and 7.
• CRC code Cyclic Redundancy Code is a " parity code An error detection code using one
polynomial key based error detection code. additional parity bit.
• digit A basic symbol used in a number system. • weight Refers to the decimal value of each
The decimal system has 10 digits, 0 through digit position of a number. For decimal
9. numbers, the weights are 1, 10, 100, 1000,
• error detection and correction A method . .. , working from the decimal point to the left.
of detection of e1Tor in a group of bits and For binary numbers the weights are 1, 2, 4, 8,
correction of the same. ... to the left of the binary point. With octal
• hamming code A parity bit based error numbers, the weights become l, 8, 64, ... to
detection and correction code. the left of the octal point.
5.1 What is the binary number that follows 5.3 How many nibbles are there in each of these:
01101111? a. 1001
5.2 How many bits are there in 2 bytes? b. 11110000
C. 110011110000
d. 1111000011001001
5.18 What are the hexadecimal numbers that follow
each of these:
5.4 Give the decimal equivalents for each of the a. ABCD b. 7F3F
following binary numbers: c. BEEF
a. 110101 b. 11001.011 5.19 Convert the following hexadecimal numbers
5.5 Convert the following binary numbers to their to binary numbers:
decimal equivalents: a. E5 b. B4D
a. 1011 1100 b. 11111111 C. 7AF4
5.6 What is the decimal equivalent of 1000 1100 5.20 Convert these binary numbers into hexadecimal
1011 0011? numbers:
5. 7 A computer has 128K of memory. How many a. 1000 1100 b. 0011 0111
bytes does this represent? c. 1111 0101 0110
5.21 Convert hexadecimal 2F59 to its decimal
equivalent.
5.8 Conve11 the following decimal numbers to 5.22 What is the hexadecimal equivalent of decimal
binary numbers: 24, 65, and 106. 62359?
5.9 What binary number does decimal 268 stand 5.23 Give the value of Y3Y2Y1Yo in Fig. 5.8 for each
for? of these:
5.10 Convert decimal 108.364 to a binary number. a. All switches are open
5.11 Calculate the binary equivalent for 5280. b. Switch 4 is closed
c. Switch A is closed
d. Switch F is closed
5.12 Convert the following octal numbers to 5.24 A computer has the following hexadecimal
decimal equivalents: contents stored at the addresses shown:
a. 65 b. 216 Address Hexadecimal contents
C. 4073 2000 D5
5.13 What is the decimal equivalent of octal 2001 AA
325.736? 2002 96
5.14 Convert these decimal numbers to octal 2003 DE
numbers: 2004 AA
a. 4096 b. 65535 2005 EB
5.15 What is the octal equivalent of decimal What are the binary contents at each address?
324.987?
5 .16 Convert the following octal numbers to binary
numbers: 34,567, 4673.
5.25 Give the ASCII code for each of these:
5 .17 Convert the following binary numbers to octal
a. 7 b. W
numbers:
C. f d. y
a. 10101111
5.26 Suppose that you type LIST with an ASCII
b. 1101.0110111
keyboard. What is the binary output as you
C. 1010011.101101
strike each letter.
+5V
·~
•,-1\/1/\
0
2-
1
-
•>-W. 3
~ 4 ~
.~ ~
5
.~
,L.J\AA 6
VVv
'LA.., ..f'v
~"v
7 .
8 ·-
9
~\ A-
~./'v B
~
~A
C
~\ D-
~v
Ml E -
F_
I
A
'V V
All resistors I \I .~ I
are 101&
y7430 y7430 y7430 97430
5.27 In Example 5.15, a computer sends the word 5.29 Here is an excess-3 number:
HELLO to another computer. The characters 0110 1001 1100 0111
are coded in ASCII with an odd-parity bit.
Here is how the word is stored in the memory What is the decimal equivalent?
of the receiving computer:
Address Alphanumeric Hexadecimal
5.30 What is the Gray code for decimal 8?
contents
5.31 Convert Gray number 1110 to its BCD
2000 H cs equivalent.
2001 E 45
2002 L 4C
2003 L 4C
2004 0 4F 5.32 Figure 5.9 shows the decimal-to-BCD encoder
The transmitting computer then sends the word discussed in Sec. 4.6. Answer the following
GOODBYE. Show how this word is stored in questions:
the receiving computer. Use a starting address a. If all switches are open and the logic
of 2000 and include a parity bit. pulser is inactive, what voltage level
does the logic probe indicate?
b. If switch 6 is closed and the logic pulser
is inactive, what does the logic probe
5.28 Express decimal 5280 in excess-3 code.
indicate?
_ _ _ _ _ _ _ _ _ _ _ _ _ _N_u_m_b_er_S_y_st_em_s_a_n_d_C_o_de_s_ _ _ _ _ _ _ _ _ _ _ _ _ ~
c. If all switches are open and the logic c. I1s ... / 12 = 1000 and logic pulser active
pulser is activated, what does the logic d. I1s ... 112 = 1111 and logic pulser active
probe do? 5.35 The logic pulser and logic probe shown in Fig.
5.33 The push-button switch of the logic pulser 5.10 are used to check the pins of the 7404
shown in Fig. 5.9 is pressed. Suppose that the for stuck states. Suppose pin 8 is stuck in the
logic probe is initially dark and remains dark. high state. Indicate which of the following are
Indicate which of the following are possible possible sources of trouble:
sources of trouble: a. No supply voltage anywhere in circuit
a. 74147 defective b. Pin I ofIC2 shorted to ground
b. Pin 9 shorted to ground c. Pin 2 ofIC4 shorted to the supply volt-
c. Pin 9 shorted to +5 V age
d. Pin 10 shorted to ground d. Pin 3 ofIC5 shorted to ground
5.34 The instruction register shown in Fig. 5.10 e. Pin 4 ofIC8 shorted to the supply volt-
on the next page is a logic circuit that stores age
a 16-bit number, /1 5 ... Io. The first 4 bits,
/is ... I12, are decoded by a 4 to 16-line
decoder. Determine whether the logic probe 5 .36 Find Hamming code of data 11001.
indicates low, high, or blink for each of these 5.37 Find Hamming code of data 1000111.
conditions: 5.38 If an error occurs in the 3rd data bit, how will
a. I1s ... /12 = 0000 and logic pulser inac- it be corrected for data of problem 5.37?
tive 5.39 How many parity bits are needed to Hamming
b. /is ... / 12 = 1000 and logic pulser inac- code (a) 16-bit data and (b) 24-bit data.
tive
+SV
All resistors are 1 kQ 16
1-1-.. 11 xI Vee
2-1-.. 12 X 74147
3-1-.. 2 14
13 A
X3
4-1-.. 6
X4 B
5-1-.. 2
X5 7
6-1-.. 3 C
x6
7-1-.. 4 9
X1 D
8-1-.. 5 Xg
9-1-.. 10
X 9 GND
- 8
-
Instruction register
I15 114 113 I12 lo
·~ ·~ ·~ R7 7404
2 4 6 8
I
''
4
6
9 ICI
IO
12
13
8
I
'
3 6
4
9 IC2
10
12
13
8
I
2
3
4
6
9
- IC3
10
<. 8
o~c 12
13
41,,.,; 1
2
J'("_,,. 3 6
0
4
9 IC4 ._,~~~
10
12 8 vo~
13
1
6
3
4
9
l()
IC5
12
Li
8
l
2
3
4
6
9 IC6
JO
12
13
8
l
3
4
6
9 IC7
JO
12
13
8
l
2
3
4
6
9 IC8
JO
12
13
8
_ _ _ _ _ _ _ _ _ _ _ ___:_N:.:u::.:.m::.be::.r.:S!.:.ys:::te:.:m::_s~a'.:nd:_:C::::o~de::::s'..__ _ _ _ _ _ _ _ _ _ _ _ ~
AIM: The aim of this experiment is to gener- Work element: Verify. the truth table of
ate and IC 74180, the 8~bit parity gen~:ator/cll~cker.
Connect as shown to use it as parity
Theor ..
elusive-OR ofdata bits:Theeven parity .makes
by
. . . .....··. ... . . .· ·. obtained ex~ generator. Submit 5 different numbers and
check the parity?f the coded data, i.e. data
the.number ofls even after tfie:addition of the
plusp~~bit.Configure it in such a way that
parity code while odd .. ~a~tai~s}t as
itbecomes .a parity checker and then check the
odd, The parity~. the bit .·.. .·. < s;even or odd,
parity ofthese 5 numbers. IC 7486 is a quad 2-
is a}so checked by exclusive-OKof incoming
input exclusive-OR gate with pin configuration
data. Thus the .same circuit can he used both
similar to 7400 or 7408. Use this to generate
for parity generation and checking after
and compare the result with 74180.
priate configuration.
find how 7- and 9-bit long data can be
· Apparatus: coded.
tet, ·and Bread Board
13. 0011 1100

14. 60
15. ASCll stands for American Standard Code
for Infor:nation. faterchange, a code used. to
represent alphanumeric information.
16.@
0100101
18.No
19. Cycle RedundancyCode
20. It can detect as well as correct one.:.bit
error.
21. Additional bits to be included with data bits
for this purpose.
Arithmetic Circuits
+ Add and subtract unsigned binary numbers

+ Show how numbers are represented in unsigned binary form, sign-magnitude form,
and 2's complement (signed binary) form
+ Add and subtract signed binary (2's complement) numbers
+ Describe the half-adder, full-adder, and adder-subtractor
+ Design a fast adder circuit that user parallelism to speed up the responses
+ Describe how an Arithmetic Logic Unit can be operated
+ Explain the means by which multiplication and division are performed on typical
8-bit microprocessors
Circuits that can perform binary addition and subtraction are constructed by combining logic gates. These
circuits are used in the design of the arithmetic logic unit (ALU). The electronic circuits are capable of very
fast switching action, and thus an ALU can operate at high clock rates. For instance, the addition of two
numbers can be accomplished in a matter of nanoseconds! This chapter begins with binary addition and
subtraction, then presents two different methods for representing negative numbers. You will see how an
exclusive OR gate is used to construct a half-adder and a full-adder. You will see how to construct an 8-bit
adder-subtracter using a popular IC. A technique to design a fast adder is discussed in detail followed by
discussion on a multifunctional device called Arithmetic Logic Unit or ALU. Finally, an outline to perform
binary multiplication and division is also presented.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _A_n_·th_m_e_ti_c_C_irc_u_it_s _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ @)
6.1 BINARY ADDITION
Numbers represent physical quantities. Table 6.1 shows

The Decimal Digits
the decimal digits and the corresponding amount of
pebbles. Digit 2 stands for two pebbles (.. ), 5 for five Pebbles Symbol
pebbles (..... ), and so on. Addition represents the
None 0
combining of physical quantities. For instance:
•
2+3=5 •• 2
symbolizes the combining of two pebbles with three ••• 3
pebbles to obtain a total of five pebbles. Symbolically, •••• 4
this is expressed
••••• 5
•••••• 6
•• + ••• = ••••• ••••••• 7
•••••••• 8
Four Cases to Remember ••••••••• 9
Computer circuits don't process decimal numbers; they process binary numbers. Before you can understand
how a computer perfonns arithmetic, you have to learn how to add binary numbers. Binary addition is the
key to binary subtraction, multiplication, and division. So, let's begin with the four most basic cases of binary
addition:
O+O =O (6.1)
0+1 = 1 (6.2)
l+0 = 1 (6.3)
1+1 =10 (6.4)
Equation (6.1) is obvious; so are Eqs. (6.2) and (6.3) because they are identical to decimal addition. The
fourth case, however, may bother you. If so, you don't understand what Eq. (6.4) represents in the physi-
cal world. Equation (6.4) represents the combining of one pebble and one pebble to obtain a total of two
pebbles:
• +. = ••
Since binary 10 stands for ee, the binary equation
l+1 = 10
makes perfect sense. From now on, remember that numbers, whether binary, decimal, octal, or hexadecimal
are codes for physical amounts. If you're in doubt about the meaning of a numerical equation, convert the
numbers to pebbles to see if the two sides of the equation are equal.
Subscripts
The foregoing discussion brings up the idea of subscripts. Since we already have discussed four kinds of
numbers (decimal, binary, octal, and hexadecimal), we have four different ways to code physical quantities.
How do we know which code is being used? In other words, how can we tell when l O is a decimal, binary,
octal, or hexadecimal number?
Most of the time, it's clear from the discussion which kind of numbers are involved. For instance, if we
have been discussing nothing but binary numbers for page after page, you can count on the next 10 being
( ; ) _ _ _ _ _ _ _ _ _ _ _ _ _D_ig_ita_l_P_rin_c_ip_le_s_an_d_A_pp_l_ica_t_io_ns_ _ _ _ _ _ _ _ _ _ _ __
binary 10, which represents ee in the physical world. On the other hand, if a discussion uses more than one
type of number, it may be helpful to use subscripts for the base as follows:
2 ~ binary
8 ~ octal
10 ~ decimal
16 ~ hexadecimal
For instance, 11 2 represents binary 11,23 8 stands for octal 23, 45 10 for decimal 45, and F4 16 for hexadeci-
mal F4. With the subscripts in mind, the following equations should make perfect sense:
12 + 12 = 102
78 + 18 = 108
910 + 110 = 1010
F16+ 116 = 1016
larger Binary Numbers
Column-by-column addition applies to binary as well as decimal numbers. For example, suppose you have
this problem in binary addition:
11100
+ 11010
?
Start by adding the least-significant column to get
11100
+11010
0
Next, add the bits in the second column as follows:
11100
+ 11010
10
The third column gives
11100
+ 11010
110
The fourth column results in
Carry~ 1
11100
+ 11010
0110
Arithmetic Circuits
Notice the carry into the final column; this carry occurs because 1 + I = 10. As in decimal addition, you
write down the O and carry the I to the next-higher column.
Finally, the last column gives
Carry-"? 1
11100
+ 11010
110110
In the last column, 1 + 1 + 1 = 10 + 1 = 11.
8-Bit Arithmetic
That's all there is to binary addition. If you can remember the four basic rules, you can add column by column
to find the sum of two binary numbers, regardless of how long they may be. In first-generation microcomput-
ers (Apple II, TRS-80, etc.), addition is done on two 8-bit numbers such as
A7 A6 A5 A4 A3 A2 A1A0
+ B7 B6 B5 B4 B3 B2 B1B0
?
The most-significant bit (MSB) of each number is on the left, and the least-significant bit (LSB) is on the
right. For the first number, A 7 is the MSB and Ao is the LSB. For the second number, B 7 is the MSB and Bo
is the LSB. Try to remember the abbreviations MSB and LSB because they are used frequently in computer
discussions.
Add these S-bit numbers: 010 I O111 and 0011 0 l OI. Then, show the same numbers in hexa-
decimal notation.
Solution This is the problem:

0101 0111
+0011 0101
?
If you add the bits in each column as previously discussed, you will obtain
0101 0111
+0011 0101
1000 1100
Many people prefer hexadecimal notation because it's a faster code to work with. Expressed in hexadecimal numbers,
the foregoing addition is
57
+35
SC
used to signify hexadecimal numbers, so the foregoing addition may be written as
57H
+35H
SCH
Add these 16-bit numbers: 0000 1111 l Ol O ll 00 and 0011 1000 0111 1111. Show the
com:sponding hexadecimal and decimal numbers.
Solution Start at the right and add the bits, column by column:
Binary Hexadecimal Decimal
0000 Ill I 1010 1100 OFACH 4,012
-'-00ll 1000 Ol ll 1111 + 387FH + 14,463
0100 1000 0010 1011 482BH 18,475
(Note: Remember Appendix I: it takes most of the work out of conversions between number systems.)
Repeat Example 6.2, showing how a first-generation microcomputer does the addition.
Solution First-generation microcomputers like the Apple II have an 8-bit microprocessor (a digital IC that performs
binary arithmetic on 8-bit numbers). To add 16-bit numbers, a first-generation microcomputer adds the lower 8 bits in
one operation and then the upper 8 bits in another operation.
Here is how it works for numbers of the preceding example. The original problem is
Upper bytes Lower bytes
l l
0000 1111 1010 1100
+ 001 I 1000 Olll 1111
'!
The microcomputer starts by adding the lower bytes:
1010 1100
+0111 Jill
10010 101 l
Notice the carry into the final column. The microcomputer will store the lower byte (0010 1011). Then, it will.do
another addition of the upper bytes, plus the carry, as follows:
1 t- Carry
0000 111 I
+ 0011 1000
0100 1000
The microcomputer then stores the upper byte. To output the total answer, the microcomputer pulls the upper and
lower sums out of its memory to get
0100 1000 0010 1011
which is equivalent to 482BH or 18,475, the same as we found in the preceding example.
1. Write the four rules for binary addition.

2. What kind of number is 179FH?
3. \Vhat is the meaning of I l h? Of 111 10?
Arithmetic Circuits
6.2 BINARY SUBTRACTION

Let's begin with four basic cases of binary subtraction:
0-0 =O (6.5)
1-0 = 1 (6.6)
1-1 =O (6.7)
10-1=1 (6.8)
Equations (6.5) to (6.7) are easy to understand because they are identical to decimal subtraction. The
fourth case will disturb you if you have lost sight of what it really means. Back in the physical world, Eq.
(6.4) represents
Two pebbles minus one pebble equals one pebble.

··-· =.
For larger binary numbers, subtract column by column, the same as you do with decimal numbers. This
means that you sometimes have to borrow from the next-higher column. Here is an example:
1101
-1010
?
Subtract the L'SBs to get
1101
-1010
To subtract the bits of the second column, borrow from the next-higher column to obtain
Borrow -ct 1
1001
-1010
1
In the second column from the right, subtract as follows: 10 -1 = 1, to get
Borrow -ct 1
1001
-1010
11
Then subtract the remaining columns:
Borrow -ct I
1001
-1010
0011
After you get used to it, binary subtraction is no more difficult than decimal subtraction. In fact, it's easier
because there are only four basic cases to remember.
Show the binary subtraction of 12510 from 20010.
Solution First, use Appendix 1 to convert the numbers as follows:

200 ~ C8H ~ llOO 1000
125 ~ 7DH ~ 0111 1101
So, here is the problem:
1100 1000
-0111 1101
?
Column-by-column subtraction gives:
1100 1000
- 0111 1101
0100 1011
In hexadecimal notation, the foregoing appears as
C8H
-7DH
4BH
4. Write the four rules for binary subtraction.
6.3 UNSIGNED BINARY NUMBERS

In some applications, all data is either positive or negative. When this happens, you can forget about + and
- signs, and concentrate on the magnitude (absolute value) of numbers. For instance, the smallest 8-bit num-
ber is 0000 0000, and the largest is 1111 1111. Therefore, the total range of 8-bit numbers is
0000 0000 (OOH)
to
1111 1111 (FFH)
This is equivalent to a decimal Oto 255. As you can see, we are not including+ or - signs with these
decimal numbers.
With 16-bit numbers, the total range is
0000 0000 0000 0000 (OOOOH)
to
1111 1111 1111 1111 (FFFFH)
which represents the magnitude of all decimal numbers from Oto 65,535.
Data of the foregoing type is called unsigned binary because all of the bits in a binary number are used
to represent the magnitude of the corresponding decimal number. You can add and subtract unsigned binary
Arithmetic Circuits
numbers, provided certain conditions are satisfied. The following examples will tell you more about unsigned
binary numbers.
limits
First-generation microcomputers can process only 8 bits at a time. For this reason, there are certain restric-
tions you should be aware of. With 8-bit unsigned arithmetic, all magnitudes must be between O and 255.
Therefore, each number being added or subtracted must be between Oand 255. Also, the answer must fall in
the range ofO to 255. If any magnitudes are greater than 255, you should use 16-bit arithmetic, which means
operating on the lower 8 bits first, then on the upper 8 bits (see Example 6.3).
Overflow
In 8-bit arithmetic, addition of two unsigned numbers whose sum is greater than 255 causes an ove1ifow, a
carry into the ninth column. Most microprocessors have a logic circuit called a canyfiag; this circuit detects
a carry into the ninth column and warns you that the 8-bit answer is invalid (see Example 6.7).
Show how to add 1501 o and 851 o with unsigned 8-bit numbers.
Solution With Appendix 1, we obtain

150 -,, 96H -,, 1001 0110
85 -+ 55H -,, 0101 0101
Next, we can add these unsigned numbers to get
1001 0110 96H
+0101 0101 +55H
1110 1011 EBH
Again, Appendix l gives
1110 1011 -"'7 EBH -"'7 235
Show how to subtract 8510 from 15010 with unsigned 8-bit numbers.
Solution Use the same binary numbers as in the preceding example, but subtract to get
1001 0110 96H
-0101 0101 -55H
0100 0001 41H
Again, Appendix 1 gives
0100 000 l -"'7 41H -"'7 65
In the two preceding examples, everything was well behaved because both decimal answers
were between O and 255. Now, you will see how an overflow can occur to produce an invalid
8-bit answer.
Show the addition of 17510 and 11810 using unsigned 8-bit numbers.
Solution
175
+ 118
293
The answer is greater than 255. Here is what happens when we try to add 8-bit numbers:
Appendix I gives
175 -;. BFH -;. 1010 1111
118 ~ 76H ~ Olll 0110
An 8-bit microprocessor adds like this:
1010 1111 AFH
+0111 0110 + 76H
Overflow ~ 1 0010 0101 125H
With 8-hit arithmetic. only the lower 8 bits are used. Appendix J gives
0010 0101 ~ 25H -;. 37
As you see, the 8-bit answer is wrong. It is true that if you take the overflow into account, the answer is valid, but
then you no longer are using 8-bit arithmetic. The point is that somebody (the programmer) has to worry about the
possibility of an overflow and must take steps to correct the final answer when an overflow occurs. If you study as-
sembly-language programming, you will leammore about overflows and what to do about them.
In summary, 8-bit arithmetic circuits can process decimal numbers between Oand 255 only. If there is any chance
of an overflow during an addition, the programmer has to write instructions that look at the carry flag and use l 6~bit
arithmetic to obtain the final answer. This means operating on the lower 8 bits, and then the upper 8 bits and the over-
flow (as done in Example 6.3).
5. What is the carry flag in a microprocessor?

6. What is the largest decimal number that can be represented with an 8-bit unsigned binary
number?
6.4 SIGN-MAGNITUDE NUMBERS

What do we do when the data has positive and negative values? The answer is important because
it determines how complicated the arithmetic circuits must be. The negative decimal numbers are
-1, -2, -3, and so on. The magnitude of these numbers is 1, 2, 3, and so forth. One way to code these as bi-
nary numbers is to convert the magnitude to its binary equivalent and prefix the sign. With this approach, the
sequence-I, -2, and-3 becomes-001, -010, and-011. Since everything has to be coded as strings ofOs and
ls, the+ and- signs also have to be represented in binary fonn. For reasons given soon, 0 is used for the+
sign and 1 for the - sign. Therefore, -001, -010, and-011 are coded as 1001, 1010, and lOll.
The foregoing numbers contain a sign bit followed by magnitude bits. Numbers in this form are called
sign-magnitude numbers. For larger decimal numbers, you need more than 4 bits. But the idea is still the
same: the MSB always represents the sign, and the remaining bits always stand for the magnitude. Here are
________________A_rit_hm_et_ic_C_irc_u_it_s_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ( ; )
some examples of converting sign-magnitude numbers:

+7 ~ 0000 0111
-16 ~ 1001 0000
+25 ~ 0000 0000 0001 1001
-128 ~ 1000 0000 1000 0000
Range of Sign-Magnitude Numbers

As you know, the unsigned 8-bit numbers cover the decimal range ofO to 255. When you use sign-magnitude
numbers, you reduce the largest magnitude from 255 to 127 because you need to represent both positive and
negative quantities. For instance, the negative numbers are
1000 0001 (-1)
to
1111 1111 (-127)
The positive numbers are
0000 0001 (+ 1)
to
0111 1111 (+127)
The largest magnitude is 127, approximately half of what is for unsigned binary numbers. As long as your
input data is in the range of -127 to + 127, you can use 8-bit arithmetic. The programmer still must check
sums for an overflow because all 8-bit answers are between -127 and+ 127.
If the data has magnitudes greater than 127, then 16-bit arithmetic may work. With 16-bit numbers, the
negative numbers are from
1000 0000 0000 0001 (-1)
to
1111 1111 1111 1111 (-32, 767)
and the positive numbers are from
0000 0000 0000 0001 (+1)
to
0111 1111 1111 1111 (+32, 767)
Again, you can see that the largest magnitude is approximately half that of unsigned binary numbers. Un-
less you actually need + and - signs to represent your data, you are better off using unsigned binary.
The main advantage of sign-magnitude numbers is their simplicity. Negative numbers are identical to
positive numbers, except for the sign bit. Because of this, you can easily find the magnitude by deleting
the sign bit and converting the remaining bits to their decimal equivalents. Unfortunately, sign-magnitude
numbers have limited use because they require complicated arithmetic circuits. If you don't have to add or
subtract the data, sign-magnitude numbers are acceptable. For instance, sign-magnitude numbers are often
used in analog-to-digital (AID) conversions (explained in a latter chapter).
7. What is the decimal number range that can be represented with an 8-bit sign-magnitude
binary number?
8. In sign-magnitude form, what is the decimal. value of 1000 1101? Of 0000 1101?
6.5 2'S COMPLEMENT REPRESENTATION
There is a rather unusual number system that leads to the simplest logic circuits for performing arithmetic.
Known as 2~, complement representation, this system dominates microcomputer architecture and program-
mmg.
1 's Complement
The I's complement of a binaiy number is the number
that results when we complement each bit. Figure 6.1
shows how to produce the I's complement with log-
ic circuits. Since each bit drives an inverter, the 4-bit
output is the l's complement of the 4-bit input. For in-
stance, if the input is
X :02X1Xo = 1000
Inverters produce the 1 's
the l's complement is complement.
X:1X2X1Xo = 0111
The same principle applies to binary numbers of any length: complement each bit to obtain the l's comple-
ment. More examples of l's complements are
1010 ~ 0101
1110 1100 ~ 0001 0011
00 11 1111 0000 0 ll O ~ 1100 0000 1111 1001
2' s Complement
The 2's complement is the binary number that results when we add l to the l's complement. As a fonnula:
2's complement = l's complement + 1
For instance, to find the 2's complement of 1011, proceed like this:
1011 ~ 0100 (l's complement)
0100 + 1 = 0101 (2's complement)
Instead of adding 1, you can visualize the next reading on a binary odometer. So, after obtaining the l's
complement O100, ask yourself what comes next on a binary odometer. The answer is OIO 1.
Arithmetic Circuits
Here are more examples of the 2's complements:

Number ~ l's complement ~ 2' s complement
1110 1100 ~ 0001 0011 ~ 0001 0100
1000 0001 ~ 0111 1110 ~ 0111 1111
0011 0110 ~ 1100 1001 ~ 1100 1010
Back to the Odometer

The binary odometer is a marvelous way to understand 2's complement representation. By examining the
numbers of a binary odometer, we can see how the typical microcomputer represents positive and negative
numbers. With a binary odometer, all bits eventually reset to Os. Some readings before and after a complete
reset look like this:
1000 (-8)
1001 (-7)
1010 (-6)
1011 (-5)
1100 (-4)
1101 (-3)
1110 (-2)
1111 (-1)
0000 (0)
0001 (+1)
0010 (+2)
OOll (+3)
0100 (+4)
0101 (+5)
0110 (+6)
0111 (+7)
Binary 1101 is the reading 3 miles before reset, 1110 occurs 2 miles before reset, and 1111 indicates 1 mile
before reset. Then, 0001 is the reading 1 mile after reset, 0010 occurs 2 miles after reset, and OOH indicates
3 miles after reset.
Positive and Negative Numbers

"Before" and "after" are synonymous with "negative" and "positive." Figure 6.2 illustrates this idea with the
number line of basic algebra: 0 marks the origin, positive numbers are on the right, and negative numbers are
on the left. The odometer readings are the binary equivalents of decimal numbers: 1000 is the binary equiva-
lent of -8, 1001 stands for - 7, 1010 stands for -6, and so on.
The odometer readings in Fig. 6.2 demonstrate how positive and negative numbers are stored in a typical
microcomputer. Here are two important ideas to notice about these odometer readings. First, the MSB is the
sign bit: 0 represents a + sign, and 1 stands for a - sign. Second, the negative numbers in Fig. 6.2 are the 2's
complements of the positive numbers, as you can see in the following:
Magnitude Positive Negative

1 0001 1111
2 0010 1110
3 0011 1101
4 0100 1100
5 0101 lOll
6 0110 1010
7 Olll 1001
8 1000
Except for the last entry, the positive and negative numbers are 2's complements of each other.
1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
-8 -7 -6 -5 --4 -3 -2 -1 0 +l +2 +3 +4 +5 +6 +7
Representing decimal numbers as 2's complements
In other words, you can take the 2's complement of a positive binary number to find the corresponding
negative binary number. For instance:
3 ~ OOll
-3 f- 1101
After taking the 2's complement of 0011, we get 1101, which represents -3. The principle also works in
reverse:
-7 ~ 1001
+7 f- 0111
After taking the 2's complement of 1001, we obtain O111, which represents +7.
What does the foregoing mean? It means that taking the 2's complement is equivalent to negation, chang-
ing the sign of the number. Why is this important? Because it's easy to build a logic circuit that produces the
2's complement. Whenever this circuit takes the 2's complement, the output is the negative of the input. This
key idea leads to an incredibly simple arithmetic circuit that can add and subtract.
In summary, here are the things to remember about 2's complement representation:
I. Positive numbers always have a sign bit of 0, and negative numbers always have a sign bit
of 1.
2. Positive numbers are stored in sign-magnitude form.
3. Negative numbers are stored as 2's complements.
4. Taking the 2's complement is equivalent to a sign change.
Converting to and from 2's Complement Representation

We need a fast way to express numbers in 2's complement representation. Appendix 2 lists all
8-bit numbers in positive and negative form. You will come to love this Appendix if you have to work a Jot
with negative numbers. By reading either the positive or negative column, you can quickly convert from
decimal to the 2's complement representation, or vice versa.
Arithmetic Circuits
Here are some examples of using Appendix 2 to convert from decimal to 2's complement representation:
+23-+ 17H-+0001 0111
-48-+ DOH-+ 1101 0000
-93-+ A3H-+ 1010 0011
Of course, you can use Appendix 2 in reverse. Here are examples of converting from 2's complement
representation to decimal:
0111 0111 -+ 77H -+ + 119
1110 1000 -+ E8H -+ -24
1001 0100 -+ 94H -+ -108
A final point. Look at the last two entries in Appendix 2. As you see, + 127 is the largest positive number
in 2's complement representation, and-128 is the largest negative number. Similarly, in the 4-bit odometer
discussed earlier, + 7 was the largest positive number, and -8 was the largest negative number. The largest
negative number has a magnitude that is one greater than the largest positive number. This slight asymmetry
of 2's complement representation has no particular meaning, but it is something to keep in mind when we
discuss overflows.
A first-generation microcomputer stores 1 byte at each address or memory location, Show

how the following decimal numbers are stored with the use of2's complement representation:
+20, -35, +47, -67, -98, + 112, and-125. The first byte starts at address 2000.
Solution With Appendix 2, we have

Address Binary contents Hexadecimal Decimal contents
contents
2000 0001 0100 14H +20
2001 1101 1101 DDH -35
2002 0010 llll 2DH +47
2003 1011 1101 BDH -67
2004 1001 lllO 9EH -98
2005 0111 0000 70H +112
2006 1000 0011 83H -125
The computer actually stores binary 0001 0100 at address 2000. Instead of saying 0001 0100, however, we may
prefer to say that it stores 14H. To anyone who knows the hexadecimal code, 14H, means the same thing as 0001
0100, but 14H is much easier to say. To the person on the street who knows only the decimal code, we would say that
+20 is stored at address 2000.
As you see, understanding computer operation requires knowledge of the different codes being used. Get this into
your head, and you are on the way to understanding how computers work.
Express -19, 7 50 in 2's complement representation. Then show how this number is stored
starting at address 2000. Use hexadecimal notation. to compress the data.
Solution The number-19,750 is outside the range of Appendix 2,·so we have to fall back on Appendix L Start by
converting; the magnitude to binary· fo11ll, With Appendix 1, we have
19,750 ~ 4D26H ~ 0100 1101 0010 0110
Now, take the 2's complement to obtain the negative value:

IOll OOIO 1101 IOOI + l = 1011 0010 1101 I010
This means that
-19,750-+ IOll 0010 1101 1010
In hexadecimal notation, this is expressed
!011 0010 1101 1010-+ B2DAH
The memory of a first-generation microcomputer is organized in bytes. Each address or memory location contains
l byte. Therefore, a first-generation microcomputer has to break a 16-bit number like B2DA into 2 bytes: an upper
byte of B2 and a lower byte of DA The lower byte is stored at the lower address and the upper byte, at the next-higher
address like this:
Address Binary contents Hexadecimal contents
2000 1101 1010 DA
2001 1011 0010 B2
The same approach, lower byte first and upper byte second, is used with first-generation microcomputers such as
the Apple II and TRS-80.
9. What is the 1's complement representation of 1101 011 O?

10. What is the 2's complement representation of 1101 0110?
6.6 2'S. COMPLEMENT ARITHMETIC

Early computers used sign-magnitude numbers for positive and negative values. This led to complicated
arithmetic circuits. Then an engineer discovered that 2's complement representation could simplify arithme-
tic hardware. (This refers to the electronic, magnetic, and mechanical devices of a computer.) Since then, 2's
complement representation has become a universal code for processing positive and negative numbers.
Help from the Binary Odometer

Addition and subtraction can be visualized in terms of a binary odometer. When you add a positive number,
this is equivalent to advancing the odometer reading. When you add a negative number, this has the effect of
turning the odometer backward. Likewise, subtraction of a positive number reverses the odometer, but sub-
traction of a negative number advances it. As you read the following discussion of addition and subtraction,
keep the binary odometer in mind because it will help you to understand what's going on.
Addition
Let us take a look at how binary numbers are added. There are four possible cases: both numbers positive, a
positive number and a smaller negative number, a negative number and a smaller positive number, and both
numbers negative. Let us go through all four cases for a complete coverage of what happens when a computer
adds numbers.
Arithmetic Circuits
Case 1 Both positive. Suppose that the numbers are +83 and + 16. With Appendix 2, these numbers are
converted as follows:
+83-; 0101 0011
+ 16-; 0001 0000
Then, here is how the addition appears:
+83 0101 0011
+16 + 0001 0000
99 0110 OOll
Nothing unusual happens here. Column-by-column addition produces a binary answer of 0110 0011.
Mentally convert this to 63H. Now, look at Appendix 2 to get
63H-; 99
This agrees with the decimal sum.
Case 2 Positive and smaller negative. Suppose that the numbers are +125 and-68. With Appendix 2, we
obtain
+ 125 -; 0111 1101
-68-; 1011 1100
The computer will fetch these numbers from its memory and send them to an adding circuit. The numbers
are then added column by column, including the sign bits to get
125 0111 1101
+ (-68) + 1011 1100
57 1 OOll 1001 -; 0011 1001
With 8-bit arithmetic, you disregard the final carry into the ninth column. The reason is related to the bi-
nary odometer, which ignores final carries. In other words, when the eighth wheel resets, it does not generate
a carry because there is no ninth wheel to receive the carry. You can convert the binary answer to decimal as
follows:
0011 1001-; 39H (mental conversion)
39H-;+57 (look in Appendix 2)
Case 3 Positive and larger negative. Let's use +37 and -115. Appendix 2 gives these 2's complement
representations:
+37-; 0010 0101
-115-; 1000 1101
Then the addition looks like this:

+37 0010 0101
+ (-115) + 1000 1101
-78 1011 0010
Next, verify the binary answer as follows:

1011 0010 ~ B2H (mental conversion)
B2H ~-78 (look in Appendix 2)
Incidentally, mentally converting to hexadecimal before reference to the appendix is an optional. step.
Most people find it easier to locate B2H in Appendix 2 than 1011 00 I 0. It only saves a few seconds, but it
adds up when you have to do a lot of binary-to-decimal conversions.
Case 4 Both negative. Assume that the numbers are --43 and -78. In 2's complement representation, the
numbers are
-43 ~ 1101 0101
-78 ~ 1011 0010
The addition is
-43 1101 0101
+ (-78) + 1011 0010
-121 1 1000 0111 ~ 1000 0111
Again, we ignore the final carry because it's meaningless in 8-bit arithmetic. The remaining 8 bits convert
as follows:
1000 0111 ~ 83H
83H ~ -121
This agrees with the answer we obtained by direct decimal addition.
Conclusion
We have exhausted the possibilities. In every case, 2's complement addition works. In other words, as long
as positive and negative numbers are expressed in 2's complement representation, an adding circuit will au-
tomatically produce the correct answer. (This assumes the decimal sum is within the -128 to+ 127 range. If
not, you get an overflow, which we will discuss later.)
Subtraction
The format for subtraction is
Minuend
- Subtrahend
Difference
There are four cases: both numbers positive, a positive number and a smaller negative number, a negative
number and a smaller positive number, and both numbers negative.
The question now is how can we use an adding circuit to do subtraction. By trickery, of course. From
algebra, you already know that adding a negative number is equivalent to subtracting a positive number. If
we take the 2's complement of the subtrahend, addition of the complemented subtrahend gives the correct
answer. Remember that the 2's complement is equivalent to negation. One way to remove all doubt about this
critical idea is to analyze the four cases that can arise during a subtraction.
Arithmetic Circuits
Case 1 Both positive. Suppose that the numbers are +83 and+ 16. In 2's complement representation, these
numbers appear as
+83 ~ 0101 0011
+16 ~ 0001 0000
To subtract+ 16 from +83, the computer will send the + 16 to a 2's complementer circuit to produce
-16 ~ 1111 0000
Then it will add +83 and-16 as follows:
83 0101 0011
+ (-16) + 1111 0000
67 1 0100 0011 ~ 0100 0011
The binary answer converts like this:
0100 0011 ~ 43H
43H~+67
Case 2 Positive and smaller negative. Suppose that the minuend is +68 and the subtrahend is
-27. In 2's complement representation, these numbers appear as
+68 ~ 01'00 0100
-27 ~ 1110 0101
The computer sends -27 to a 2's complementer circuit to produce
+27 ~ 0001 1011
Then it adds +68 and +27 as follows:
+68 0100 0100
+27 + 0001 1011
95 0101 1111
The binary answer converts to decimal as follows:
0101 1111 ~ 5FH
5FH~+95
Case 3 Positive and larger negative. Let's use a minuend of+ 14 and a subtrahend of -108. Appendix 2
gives these 2's complement representations:
+14 ~ 0000 1110
-108 ~ 1001 0100
The computer produces the 2' s complement of -108:
+108 ~ 0110 1100
Then it adds the numbers like this:
14 0000 1110
+108 + 0110 1100
122 0111 1010
The binary answer converts to decimal like this:

0111 1010 ~ 7AH
7AH ~+122
Case 4 Both negative. Assume that the numbers are -43 and - 78. In 2' s complement representation, the
numbers are
-43 ~ 1101 0101
-78 ~ 1011 0010
First, take the 2's complement of - 78 to get
+78 ~ 0100 1110
Then add to obtain
-43 1101 0101
+78 + 0100 1110
35 1 0010 0011 ~ 0010 0011
Then
0010 0011 ~ 23H
23H ~+35
Overflow
We have covered all cases of addition and subtraction. As shown, 2's complement arithmetic works and is
the standard method used in microcomputers. In 8-bit arithmetic, the only thing that can go wrong is a sum
outside the range of -128 to + 127. When this happens, there is an overflow into the sign bit, causing a sign
change. With the typical microcomputer, the programmer has to write instructions that check for this change
in the sign bit.
Let's take a look at overflow problems. Assume that both input numbers are in the range of-128 to+ 127.
If a positive and a negative number are being added, an overflow is impossible because the answer is always
less than the larger of the two numbers being added. Trouble can arise only when the arithmetic circuit adds
two positive numbers or two negative numbers. Then, it is possible for the sum to be outside the range of
-128 to + 127. (Subtraction is included in the foregoing discussion because the arithmetic circuit adds the
complemented subtrahend.)
Case 1 Two positive numbers. Suppose that the numbers being added are + 100 and +50. The decimal
sum is + 150, so an overflow occurs into the MSB position. This overflow forces the sign bit of the answer to
change. Here is how it looks:
100 0110 0100
+50 + 0011 0010
150 1001 01 IO
The sign bit is negative, despite the fact that we added two positive numbers. Therefore, the overflow has
produced an incorrect answer.
Arithmetic Circuits
Case 2 Two negative numbers. Suppose that the numbers are -85 and -97. Then
-85 1010 1011
+ (-97) + 1001 1111
182 1 0100 1010 ~ 0100 1010
The 8-bit answer is 0100 1010. The sign bit is positive, but we know that the right answer should contain
a negative sign bit because we added two negative numbers.
What to Do with an Overflow

Overflows are a software problem, not a hardware problem. (Software means a program or list of instructions
telling the computer what to do.) The programmer must test for an overflow after each addition or subtrac-
tion. A change in the sign bit is easy to detect. All the programmer does is include instructions that compare
the sign bits of the two numbers being added. When these are the same, the sign bit of the answer is compared
to either of the preceding sign bits. If the sign bit is different, more instructions tell the computer to change
the processing to 16-bit arithmetic. You will learn more about overflows, 16-bit arithmetic, and related topics
if you study assembly-language programming.
How would an 8-bit microcomputer process this:
18,357
-12,618
?
Solution It would use double-precision arithmetic, synonymous with 16-bit arithmetic. This arithmetic is used with
16-bit numbers in this form:
X1sX1+¥13A'12 X!!XwX9X"s X7X(,Xs,\"4 X:,X2X1Xo
Numbers like these have an upper byte Xis ... Xs and a lower byteX7 ... Xo. To perform. 16-bit arithmetic, an 8-bit
microcomputer has to operate on each byte separately. The idea is similar to Example 6.3,where the lower bytes were
added and then the upper bytes.
Here is how it is done, WithAppendix 1, we have
18,357-+ 47B5H-+ 0100 0111 IOll 0101
12,618-+ 314AH-+ 0011 0001 0100 1010
The 2's complemeritof 12,618.is
--12,618-+ CEB6H-+ 1100 mo 10!1 OllO
The addition is carried out in two steps of 8-bit arithmetic. First, the lower bytes are added:
1011 0101
+ 1011 0110
l 0110 1011-+ XsX1X6X5X4 X3X2X1Xo
The computer will store X7 ... Xo. The carry Xg is used in the addition of the upper bytes.
Now, the computer adds the upper bytes plus the carry as follows:
1 <c- Xs
0100 0111
+ 1100 1110
1 0001 0110 -+ 0001 0110
To obtain the final answer, the two 8-bit answers are combined:
0001 0110 0110 1011
Notice that the MSB is 0, which means that the answer is positive. With Appendix 1, we can convert this answer
to decimal form:
0001 OllO OllO 1011 -;. 166BH -;.+5739
11. What is the standard method for doing binary arithmetic in nearly all microprocessors?
12. How is 2's complement representation used to perfonnsubtraction?
6.7 ARITHMETIC BUILDING BLOCKS
We are on the verge of seeing a logic circuit that performs 8-bit arithmetic on positive and negative numbers.
But first we need to cover three basic circuits that will be used as building blocks. These building blocks are
the half-adder, the full-adder, and the controller inverter. Once you understand how these work, it is only a
short step to see how it all comes together, that is, how a computer is able to add and subtract binary numbers
of any length.
Half-Adder
When we add two binary numbers, we start with the least-
CARRY=AB
significant column. This means that we have to add two
bits with the possibility of a carry. The circuit used for this
is called a half-adder. Figure 6.3 shows how to build a half- SUM=AB+AB
adder. The output of the exclusive-OR gate is called the
SUM, while the output of the AND gate is the CARRY. The
AND gate produces a high output only when both inputs
are high. The exclusive-OR gate produces a high output if
either input, but not both, is high. Table 6.2 shows the
truth table of a half-adder. Half-adder Truth Table
When you examine each entry in Table 6.2, you are A B CARRY SUM
struck by the fact that a half-adder performs binary
0 0 0 0
addition. 1
0 0
As you see, the half-adder mimics our brain pro- l 0 0 1
cesses in adding bits. The only difference is the half- l 0
adder is about a million times faster than we are.
Full-Adder
For the higher-order columns, we have to use afi1ll-adder, a logic circuit that can add 3 bits at a time. The
third bit is the carry from a lower column. This implies that we need a logic circuit with three inputs and two
outputs, similar to the full-adder shown in Fig. 6.4a. (Other designs are possible. This one is the simplest.)
Arithmetic Circuits
Table 6.3 shows the truth table of a full-adder. You can easily check this truth table for its validity. For
instance, CARRY is high in Fig. 6.4a when two or more of the ABC inputs are high; this agrees with the
CARRY column in Table 6.3. Also, when an odd number of high ABC inputs drives the exclusive-OR gate,
it produces a high output; this verifies the SUM column of the truth table.
(tJ !;,~{~&;IJ Full-Adder Truth Table

A B C CARRY SUM
0 0 0 0 0
0 0 1 0 I
0 l 0 0 I
0 1 1 1 0
1 0 0 0 l
1 0 l 1 0
1 1 0 l 0
1 1 l 1 1
A BC
AB
c 00
0 0
1 0
CARRY Carry=AB+ BC+ AC
AB
C 00 0 1 1 1 1 0
0 0 I 0 1
1 1 0 1 0
SUM SUM = A (±) B Et> C
(a) (b)
(a) Full-adder, (b) Karnaugh map of Table 6.3
When you examine each entry in Table 6.3, you can see that a full-adder performs binary addition on 3
bits.
From this truth table we get Karnaugh map as shown in Fig. 6.4b that gives following logic equations,
CARRY=AB+BC+AC and SUM=A EBB$ C.
A general representation of full-adder which adds i-th bit A; and B; of two numbers A and Band takes carry
from (i-l)th bit could be
C; = A;B; + B;C;-1 + A;CH or C; = A;B; + (A; +B;)C;-1 and S; =A;$ B; $ C;_ 1
where, C; and S; are carry and sum bits generated from the fall adder. The second representation of C; has an
interesting meaning. The first term gives, if both A; and Bi are 1 then C; = 1. The second term gives if any of
A; or B; is 1 and ifthere is carry from previous stage, i.e. C;_ 1 = 1 then also C; = 1. That this is the case, we can
verify from full adder truth table and this understanding is useful in design of fast adder in Section 6.9.
Controlled Inverter
Figure 6.5 shows a controlled inverter. When INVERT is low, it transmits the 8-bit input to the output; when
INVERT is high, it transmits the l's complement. For instance, if the input number is
A1--·Ao=OllO 1110
Controlled inverter
a low INVERT produces

Y1···Yo=OI10 1110
But a high INVERT results in
Y1 ... Yo= 1001 0001
The controlled inverter is important because it is a step in the right direction. During a subtraction, we first
need to take the 2's complement of the subtrahend. Then we can add the complemented subtrahend to obtain
the answer. With a controlled inverter, we can produce the l's complement. There is an easy way to get the
2 's complement, discussed in the next section. So, we now have all the building blocks: half-adder, full-adder,
and controlled inverter.
13. What are the it1pt1tsJndotltptitsof iihalf-ad~er? ....

14. What are tµ.e inputs and ol.l.tpµts of.a, fulkad,der?J <. . · .
...··.·. ·• · . ·• · · . . •• · . . ··•·· .......·
15. The SUM output of a full-adder is easily implemented using an exclusive-OR gate. (Tor F) ··
6.8 THE ADDER..SUBTRACTER .

We can connect full-adders as shown in Fig. 6.6 to add or subtract binary numbers. The circuit is laid out from
right to left, similar to the way we add binary numbers. Therefore, the least-significant column is on the right,
and the most-significant column is on the left. The boxes labeled FA are full-adders. (Some adding circuits
use a half-adder instead of a full-adder in the least-significant column.)
The CARRY OUT from each full-adder is the CARRY IN to the next-higher full-adder. The numbers be~
ing processed are A 7 ... Ao and B 7 ... Bo, and the answer is S7 ... S0. With 8-bit arithmetic, the final carry is
ignored for reasons given earlier. With 16-bit arithmetic, the final carry is the carry into the addition of the
upper bytes.
Arithmetic Circuits
Binary adder-subtracter
Addition
Here is how an addition appears:
A7At,A5Ai A3A2A1Ao
+ B1B6B5B4 /hlJ.iBiBo
S1S6S5S4 S3S2S1So
During an addition, the SUB signal is deliberately kept in the low state. Therefore, the binary number B7
... Bo passes through the controlled inverter with no change. The full-adders then produce the correct output
sum. They do this by adding the bits in each column, passing carries to the next higher column, and so on.
For instance, starting at the LSB, the full-adder adds Ao, Bo, and SUB. This produces a SUM of So and a
CARRY OUT to the next-higher full-adder; The next-higher full-adder then adds A 1, B 1, and the CARRY IN
to produce S1 and a CARRY OUT. A similar addition occurs for each of the remaining full-adders, and the
correct sum appears at the output lines.
For instance, suppose that the numbers being added are +125 and -67. Then, A 7 ... Ao = 0111 1101 and
B 7 ••• B 0 = 1011 1101. This is the problem:
0111 1101
+ 1011 1101
?
Since SUB = 0 during an addition, the CARRY IN to the least-significant column is 0:
0 ~ SUB
0111 1101
+ 1011 1101
?
The first full-adder performs this addition:
0 + 1+ 1=0 with a carry of l
The CARRY OUT of the first full-adder is the CARRY IN to the second full-adder:
1 ~ Carry
0111 1101
+ 1011 1101
0
In the second column

1+0+0=1 with a carry of 0
The carry goes to the third full-adder:

0 ~ Carry
0111 1101
+ lOll 1101
10
In a similar way, the remaining full-adders add their 3 input bits until we arrive at the last full-adder:
1 ~ Carry
Olll 1101
+ 1011 1101
0011 1010
When the CARRY IN to the MSB appears, the full-adder produces
1+ 0 + 1=0 with a carry of 1
The addition process ends with a final carry:
0111 1101
+ IOI1 1101
l 0011 1010
During 8-bit arithmetic, this last carry is ignored as previously discussed; therefore, the answer is
S7 ... So = 0011 IO 10
This answer is equivalent to decimal +58, which is the algebraic sum of the numbers we started with: +125
and-67.
Subtraction
Here is how a subtraction appears:
A1A6AsA4 A3A1A1Ao
+ B1B6BsB4 B3B2B1Bo
During a subtraction, the SUB signal is deliberately put into the high state. Therefore, the controlled
inverter produces the l's complement of B7 ••• B0. Furthermore, because SUB is the CARRY IN to the first
full-adder, the circuit processes the data like this:
1 ~ SUB
A3A2A1Ao
-- --
B3B2B1Bo
When A7 ... A 0 = 0, the circuit produces the 2's complement of B 7 •.. B0 because 1 is being added to the l's
complement B7 ... B0. When A 7 ... A 0 does not equal zero, the effect is equivalent to adding A 7 ... A0 and the
2's complement of B7 . .. Bo.
Arithmetic Circuits
Here is an example. Suppose that the numbers are +82 and +17. Then A 7 ... Ao= 0101 0010 and B 7 ...
Bo= 0001 000 I. The controlled inverter produces the l's complement ofB, which is 1110 1110. Since SUB
= 1 during a subtraction, the circuit performs the following addition:
1 f- SUB
0101 0010
+ 1110 1110
1 0100 0001
For 8-bit arithmetic, the final carry is ignored as previously discussed; therefore, the answer is
S7 · .. So= 0100 0001
Upper Lower
3 8 3 8
5 5
+5V +5V
13 14 13
7483 7483
12 12
- 15 2 6 9 - 15 2 6 9
S7 s6 Ss S4 S3 S2 S1 So
Fig.6:7 Two 7483s can add or subtract bytes
This answer is equivalent to decimal +65, which is the algebraic difference between the numbers we
started with: +82 and+ 17.
Show how to build an 8-bit adder-subtracter with TTL circuits.
Solution The 7483 is a TTL circuit witb four full-adders. This means that it can add nibbles. To add bytes, we need
to use two 7483s as shown in Fig. 6.7. The CARRY OUT (pin 14) of the lower 7483 is used as the CARRY IN (pin
13) to the upper 7483. This allows the two 7483s to add 8-bit numbers. Two 7486s form the controlled inverter needed
for subtraction.
The 74LS83, 74283, and 72LS283 are all TTL 4-bit adder ICs. They .are pin-for-pin compatible, except that tbe
'2.83 an<i 'LS283 have +Vee on pin 16 and GROUND on pin 8. The 74HC283 is.the CMOS version of the same 4-bit
adder.
The 74181, 74LS181, and 74LS381 are TTLALUs, and the 74HC381 is the CMOS equivalent. Each is capable of
adding two 4-bit binary numbers as well as performing numerous other logic operations.
~9 FAST ADDER.
Fast adder is also called parallel adder or carry look ahead adder because that is how it attains high speed
in addition operation. Before we go into that circuit, let's see what limits the speed of an adder. Consider, the
worst case scenario when two four bit numbers A: 1111 and B: 0001 are added. This generates a carry in the
first stage that propagates to the last stage as shown next.
Carry: 111
A: 1111
B: 0001
10000
Addition such as these (Fig. 6.6) is called serial addition or ripple carry addition. It also reveals from the
adder equation (given in Section 6.8) result of every stage depends on the availability of carry from previous
stage. The minimum delay required for carry generation in each stage is two gate delays, one coming from
AND gates (1st level) and second from OR gate (2nd level). For 32-bit serial addition there will be 32 stages
working in serial. In worst case, it will require 2 x 32 = 64 gate delays to generate the final carry. Though each
gate delay is of nanosecond order, serial addition definitely limits the speed of high speed computing. Parallel
adder increases the speed by generating the carry in advance (look ahead) and there is no need to wait for the
result from previous stage. This is achieved by following method.
Let us use the second equation for carry generation from previous section, i.e.
C; = A;B; + (A;+ B;)C;-1
This can be written as, C; = G; + PPi-!
where, G; = A;B; and P; =A;+ B;
G; stands for generation of carry and P; stands for propagation of carry in a particular stage depending on
input to that stage. As explained in previous section, ifA;B; = 1, then ith stage will generate a carry, no matter
previous stage generates it or not. And if A;+ B; = 1 then this stage will propagate a carry if available from
previous stage to next stage. Note that, all G; and P; are available after one gate delay once the numbers A
and B are placed.
Starting from LSB, designated by suffix Oifwe proceed iteratively we get,
Co =Go+ P0 .C_1 [C_1 will normally be Oifwe are not using it as subtractor or cascading it.]
C1 = G1 +Pi.Co= G1 + PJ-(Go+ Po.C_1) = G1 + Pi.Go+ P1Po.C_1 [Substituting Co]
Similarly,
C2 = G2+ P2.C1 = G2+ P2.(G1 + Pi.Go+ P1Po,C_1) [Substituting Ci]
= G2 + P2.G1 + P2P1.Go +P2P1Po.C_1
C3 = G3 + P3.C2 = G3 + PJCG2+ P2.G1 + P2P 1.Go + P2P 1P0 .C_1) [Substituting C2]
= G3 + P3G2 + P3P2.G1 + P3P2P1.Go + P3P2P1Po.C-1
etc.
The equations look pretty complicated. But do we gain in any way? Note that, these equations can be real-
ized in hardware using multi-input AND and OR gates and in two levels. Now, for each carry whether Co or
C3 we require only two gate delays once the G; and P; are available. We have already seen they are available
after 1 gate delay. Thus parallel adder (circuit diagram for 2-bit is shown in Fig. 6.8a) generates carry within
Arithmetic Circuits
1 + 2 = 3 gate delays. Note that, after the carry is available at any stage there are two more gate delays from
Ex-OR gate to generate the sum bit as we can write S; = G; EB P; EB C;_ 1.
Thus serial adder in worst case requires at least (2n + 2) gate delays for n-bit addition and parallel adder
requires only 3 + 2 = 5 gate delays for that. One can imagine the gain for higher values of n. However, there
is a caution. We cannot increase n indiscriminately for parallel adder as every logic gate has a capacity to
accept at most a certain number of inputs, termed/an-in. This is a characteristic of the logic family to which
the gate belongs. More about this is discussed in Chapter 14. The other disadvantage of parallel adder is in-
creased hardware complexity for large n. In Fig. 6.8b we present functional diagram and pin connections of
a popular fast adder, IC 74283.
A3 12
A2 14
A1 3
Ao 5 10 S3
13 S2
IC
B3 11 74283 1 S1
B2 15 4 So
Bi 2
Bo 6 9 cout
C;n-7
Vcc:(16)
GND(8)
C1 So
(a) (b)
(a) Logic circuit for 2-bit fast adder, (b) Functional diagram of IC 74283
Now, how do we add two 8-bit numbers using IC 74283? Obviously, we need two such devices and Cout
of LSB adder will be fed as C;n of MSB unit. This way each individual 4-bit addition is done parallely but
between two ICs carry propagates by rippling. To avoid carry ripple between two ICs and get truly parallel
addition the following approach can be useful. Let each individual 4-bit adder unit generate two additional
outputs Group Carry Generate (G3-0) and Group Carry Propagate (P3-0). They are defined as follows
G3-0 = G3 + P3G2 + P3P2.G1 + P3P2P1.Go
P3-0 = P3P2P1Po
~ _ _ _ _ _ _ _ _ _ _ _ _ _ _D_ig_it_al_P_n_·nc_ip_le_s_a_n_d_A_pp_li_ca_ti_·on_s_ _ _ _ _ _ _ _ _ _ _ __
so that
C3 = G3_0 + P3_0 C1 [From equation of C3 in previous discussion]
Now, let us see how this is useful in 8-bit parallel addition. For the 4-bit adder adding MSB taking C3 as
carry input, we can similarly write
[C3 is equivalent to c_ 1 input for this adder]
where
G7-4 = G7 + P1G6 + P1P6.Gs + P1 P6P5.G4
P7-4 = P1P ff> sP4
Thus C7 = G7-4 + P7-4(G3--0 + P3_0 C1) [substituting C3]
or C7 = G7-4 + P7-4G3_0 + P7~3--0 C1
What do we get from above equation? Group carry generation and propagation terms are available from
respective adder blocks (G3_0, P3_0 from LSB and G 7-4, P 7-4 from MSB) after 3 and 2 gate delays respec-
tively. This comes from the logic equations that define them with Gi, Pi available after 1 gate delay.
Once these group-carry terms are available, we can generate C7 from previous equation by designing a
small Look Ahead Carry (LAC) Generator circuit. This requires a bank of AND gates (here one 2 input and
one 3 input) followed by a multi-input OR gate (here, three input) totaling 2 gate delays. Thus final carry is
available in 3 + 2 = 5 gate delays and this indeed is what we were looking for in parallel addition. In next
section we discuss a versatile IC 74181 that while performing 4-bit addition generates this group carry gen-
eration and propagation terms. LAC generator circuits are also commercially available; IC 74182 can take up
to four pairs of group carry terms from four adder units and generate final carry for 16 bit addition.
Before we go to next section can you answer after how many gate delays the sum bits (S15 ..• S0 ) of 16 bit
fast adders will be available?
Show how final carry is generated for a parallel adder when two numbers added are A: 1111
and B: 000 l.
Solution First it calculates, G; and P; parallely.

Go = 1.1 = l, G1 = 1.0 = 0, G3 = 1.0=0.
and Po =l+l=l,P1=l+O=l,
Note that C1 =O.
Then substituting thesein equation of C3 we get final carry as
C3 = G3 + P3G2 + P3P2.G1+ P3 P2P1.Go + P3P2P1Po.C1
= 0 +LO+ 1.1.0 + Ll.1.1 + 1.1.Ll.O
=O+O+O+l+O
=1
16. What is the savings in time in a parallel adder?

17. What is the maximum number of inputs for an OR gate in a 4-bit parallel adder?
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _A_n_'th_m_e_tic_C_i~_c_ui_ts _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ @)
6.10 ARITHMETIC LOGIC UNIT
Arithmetic Logic Unit, popularly called ALU is multifunctional device that can perfonn both arithmetic
and logic function. ALU is an integral part of central processing unit or CPU of a computer. It comes in
various forms with wide range of functionality. Other than normal addition, subtraction it can also perform
increment, decrement operations. As logic unit it performs usual AND, OR, NOT, EX-OR and many other
complex logic functions. It also comes with PRESET and CLEAR options, invoking which all the function
outputs are made 1 and O respectively. Normally, a mode selector input (M) decides whether ALU perfonns
a logic operation or an arithmetic operation. In each mode different functions are chosen by appropriately
activating a set of selection inputs.
Input A lnputB
A3A2A1Ao B3 Bz B1 Bo
1l 11
1921232 18 20 22
S3 3
S2 4 8 M
IC 74181
S1 5 7
So 6 14 16 17 15 1311109
Vcc(24)
GND(12)
A= B Cout G3_0 P3_0 F3 F2 F1 Fo
(a)
M= I M=O
(Logic (Arithmetic Function)
S3 S2S1 So Function) Cin = I (For C;0 = 0, add 1 to F)
0 0 0 0 F=A' F=A
0 0 0 1 F=(A+B)' F=A+B
0 0 1 0 F=A'B F=A+B'
0 0 1 1 F=O F=minus 1
0 1 0 0 F=(AB)' F=Aplus(AB')
0 1 0 1 F=B' F =(A+ B) plus (AB')
0 1 1 0 F=A ©B F = A minus B minus I
0 1 1 1 F=AB' F=AB'rninus 1
1 0 0 0 F=A'+B F = A plus (AB)
1 0 0 1 F=(A ©B)' F=AplusB
1 0 I 0 F=B F= (A+ B') plus (AB)
1 0 1 1 F=AB F=ABminus 1
1 1 0 0 F=l F=AplusA
1 1 0 1 F=A+B' F = (A + B) plus A
1 1 1 0 F=A+B F=(A +B')plusA
1 1 1 1 F=A F=A minus 1
(b)
(a) Functional representation of ALU IC 74181, (b) Its truth table

In this section, we take up one very popular discrete ALU device from TTL family for discussion. IC
74181 is a 4-bit ALU that can generate 16 different kinds of outputs in each mode selected by four selection
inputs S3, S2, S 1 and So. The functional diagram of this IC with pin numbers and corresponding truth table is
shown in Fig. 6.9(a) and Fig. 6.9(b) respectively. Note that this truth table considers data inputs A and Bare
active high. A similar but different trnth table is obtained if data is considered as active low.
Well, the truth table is pretty exhaustive though one might wonder what could be the utility of functions like
(A+ B) plus AB'. But a careful observation shows one important function missing, that of a comparator. Is it truly
so? No, it can be obtained in an indirect way. The Cout is activated (active low) by addition as well as subtractio.n
because subtraction is carried out by 2 's complement addition. Note that, if the result of an arithmetic operation
is negative it will be available in 2 's complement form. The A= B output is activated when an the function outputs
are 1, i.e. F 3 ... F 0 = 1111. Output A= B, together with Cout can give functions like A> Band A <B. Note that
A = B is an open collector output; thus when more than 4-bits are to be compared this output of different ALU
devices are wire-ANDed, simply by knotting outputs together to get the final result. To know more about
open collector gates refer to Section 14.5 of Chapter 14.
The outputs Cout, G3_0 and P 3 _o are useful when addition and subtraction of more than 4-bits are performed
using more than one IC 74181 as discussed in previous sections.
Logic operations are done bit-wise by making M = l and choosing appropriate select inputs. Note that,
carry is inhibited for M = 1. Let us see how AND operation between two 4-bit numbers 1101 and O111 is to be
performed. Enter input A 3 .. Ao = 1101 and B 3 .. Bo = 0111. Make S3 .. S0 = 1011 and of course M = I to choose
logic function. The output is shown as F 3 . .F0 = 00 ll.
For arithmetic operations M = 0 to be chosen and we have to appropriately place Cin ( active low), if any.
For example, ifwe want to add decimal numbers 6 with 4 we have to place 0110 for 6 at A and 0100 for 4 at
B. Then with S3 .. S0 = 1001 (from truth table) and Cin = 1 (active low) the output generated is F 3 ..F 0 = 1010
which is decimal equivalent of 10.
(a) Show how A > B output can be generated in IC 74181 ALU. (b) Also show how A ;=:: B condition can be
checked.
Solution
(a) If A > B, then :function A minus B will be positive and the result will not be in 2's complement form and more
importantly will generate a carry. Refer to discussion and examples in Section 6.6 0112 's complement arithmetic.
The final result for such snbtraction is obtained by disregarding the carry. But here by checking output carry
whether active we can conclude if A> B.
Thus to check A> B put M= 0 (arithmetic operation), S3 ..So = 0110 (gives A minusB),Cjn O (Cj 11 = l gives A
minus B minus I) and check carry is generated, i.e. Cout = 0 (active), which givesA > B.
(b) A similar reasoning shows by making Cm= I in above and checking if Cout = 0 we can verify .A 2:'. B condition.
Show how bits of input A shifted to left by one unit appear at output Fin IC 74181.
Solution We know shifting to left by one unit is equivalent to multiplication by two. Again multiplication by two can
be achieved by adding the number with itselfonce. Thus make data input at A, M= 0 ( arithmetic operation), qn = 1
and S3 ..So = 1100 (gives A plus A) and we have A shifted by 1 unit to left at function output F.
Arithmetic Circuits
18. What is an ALU?

19. How do you CLEAR all outputs ofIC 74181?
6.11 BINARY MULTIPUCATION AND DIVISION
Typical 8-bit microprocessors like the 6502 and the 8085 use software multiplication and division. In other
words, multiplication is done with addition instructions and division with subtraction instructions. Therefore,
an adder-subtracter is all that is needed for addition, subtraction, multiplication, and division.
For example, multiplication is equivalent to repeated addition. Given a problem such as
8x4=?
the first number is called the multiplicand and the second number, the multiplier. Multiplying 8 by 4 is the
same as adding 8 four times:
8+8+8+8=?
One way to multiply 8 by 4 is to program a computer to add 8 until a total of four 8s have been added. This
approach is known as programmed multiplication by repeated addition.
There are other software solutions to multiplication and division that you will learn about if you study
assembly-language programming.
There are ICs available that will multiply two binary numbers. For instance, the 74284 and the 74285 will
produce an 8-bit binary number that is the product of two 4-bit binary numbers. These ICs are very fast, and
the total multiplication time is only about 40 nanoseconds (ns)!
20. Explain how one can do division of binary numbers.
6~12 ARITHMETIC CIRCUITS USING HO[
We first describe a full adder circuit and create a test bench to test it. Please refer to discussion of Section 6.7.
[f A and B are the binary digits to be added and C is the Carry input then output Sum and Carry (represented
by sm and er in following Verilog code) is expressed by equations
Sum: sm =AB+ BC+ CA and Carry: er= A EBB EB C
We have used a test bench that generates all possible combinations of A, B and C by arithmetic addition
and takes less space than test bench described in Chapter 2. The output sum (sm) and carry (er) for this is
shown in simulation waveform. One can see this verifies truth table of a full adder.
Cj) ______________ D_ig_ita_l_P_rin_c_ip_le_s_a_nd_A_p_p_lic_a_fio_n_s_ _ _ _ _ _ _ _ _ _ _ __
mociul.etestFUllAdder;
regA:,B,
wire sm, er;
fal(A,B,C,sm,cr); t with fal
simulation begins
{A,B,C
$finish;
end
endmodule
module fulladder(A,B, of fulladder t

input A,B,C;
output sm,cr;
assign sm (A&BJ I
assign
endmodu1e
[Ons f20ns I l40ns I
160,ns, j80ns 11oons il20ns jI4~ns
I
I
' I
' 1 i I
' ' ' ' ! I f C ' I I I
testFullAdder.sm I I \ I
testFullAdder.cr _}
_ \ {
testFulV\dder.A {
testFulJAdder.B I \ I
. -
testFullAdder. C ! \ I \ I \ I
Show Verilog design of 4-bit ripple cany adder.
Solution The code is given as follows.

the right depends on the compiler. Based
implements a4-bit ripple carry adder in different manner.
lll()dul.e. adder4bit (surr,,<:out,a,

input [3:0] a,b; Tr,;o 4 bit data to be
input cin;
output to
output
generated in flrst three fulladder

fulladder*/ modul.e adder4bit
faO(a[O],b OJ,cin,sum[O],cint[OJ); (sum,cout,a,b,cin);
instantiates fulladder input [3:01 a,b;
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _A_n_"fh_m_e_tic_C_ir_c_ui_ts _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~
input
fal(a[l],b[l],cint[O],sum[l],cint[l]); output [3:0] sum;
output cout;
,b[2],cint11],sum[2],cint[2]); assign {cout,sum} a+ b + cin;
endmodule
fa3(a[3],b[3],cint[2],sum[3J,cout);
endmoduie
module fulladder(A,B,C,sm,cr);
input A,B,C;
output sm,cr;
assign sm = (A&B) I (B&C) l (C&A);
ass;i.gncr =
endmodule
Show how a half-adder can be realized.
Solution The half-adder truth table and logic equations are reproduced from Section 6. 7 in Fig. 6.lOa.
A B C s
C=AB
0 0 0 0
0 l 0 1 S=AEfJB
l 0 0 1 =AB'+A'B
1 1 1 0
fa)
: double co111plement
S=A·B'+A'B
= {A·B' + A'B)" : double complement
= ((A·B')'-(A'B)')' : from Eq. 2.1
= ((A'+B)-(A+B')' · from Eq. 2.2 A-_,_,-----..
= (A'B'+AB)' : since XX= 0
B--,,._ _./
= (A'B')'{AB)' : from Eq. 2.1
=; (A+B}(AB)' ; from Eq. 2,2
= (AB)'A+(AB)'B
= ((AB)'!+(AB)'B)" · double complement
= (((AB)'A)',((AB)'B))')' :. from Eq,. 2.1 C
(d)
(a) Truth tablE?' and logic equation for half-adder, (b) Realization using
AND and exclusive-OR gate, (c) Derivation of AND and exclusive-OR
relation, (d) Realization using only NAND gates
In Method-1, the logic relations can directly be realized using AND and exclusive-ORgate as
shown in Fig. 6.1 Ob.
In Method-2, we show how itcan be realized using only one type of basic gates, say NANI)gate.
The derivation is shown in Fig. 6.1 Oc and the realization is shown in Fig. 6.1 Od.
It is left as an exercise to find how it can be realized using only NOR gates.
In Method-3, we show how it can be realized using two 4 to .1 multiplexers. We make use of th,e truth
table to assign data inputs to the multiplexers while A and B are used as select inputs. The realization
is shown in Fig. 6.1 la.
001----,.--,.-~-
0I ______.__._
0
0
0
l
0 0C 0
01
10
1
l
11
A
0
Ol
10
B
0
. S
0
(a)
l1
A B
oo·. cBO. . . . ···s
B I
(b)
B' 1
A
A B
101------<1!--!--
11 ,_____,____,,.........,__
(c)
s
Realization using (a) 4 to 1 multiplexers, (b) 2 to 1 multiplexers,

(c) Decoder, OR gate
In Method-4, we show how it can be realized using two 2 to l multiplexers. Let the only selected
input to the multiplexers be A.
We note from the equation, if A = 0, C = 0 and if A = l, C = B
if A = 0, C = B and if A = l, C = B'
The realization from these is shown in Fig. 6.1 lb where Bis used in the data input,
In Method-5, we show how it can berealized using a 2 to 4 decoder and OR gate. The decoder gen-
erates all the four minterms A'B', A'B, AB' and AB. Carry output is generated directly from AB. Sum
output is generated OR-ingA'B and AB'. The realization is shown in Fig. 6.llc.
Numbers represent physical quantities. As long as you know the number code being used; those strange-
looking answers in other number systems make perfect sense. Subscripts can be used as a reminder of the
base of the number system.
The unsigned 8-bit numbers are from 0000 0000 to 1111.1111, equivalent to deci:rrialOto 255. The un-
signed 16-bit numbers are from decimal Oto 65,535. Overflows occur when a sum exceeds the range ofthe
number system. With 8-bit arithmetic, an overflow occurs when the unsigned sum exceeds 255.
Sign-magnitude numbers use the MSB as a sign bit, with O for the + sign and 1 for the - sigri. The rest
of th~ bits are for the magnitud~ of th,e number, For this reason, 8~bit numbers cover the decimill range of
-127 to +127, while 16,bit numbers cover -32,767 to +32,767.
Arithmetic Circuits
The 2's complement representationis the most widespread code for positive and negative numbers.
Positive numbers are coded as sign-magnitude numbers, and negative numbers are coded as 2's comple-
ments. The key feature of this nuII1ber:5Y'S~et).li$.that taking the 2's complement of a number is equivalent
to changing its sign. This charasteFi§ticaUmvs uslo subtract numbers by adding the 2's cm:nplementoftht;?
subtrahend. The advantage is simpler arithmetic hardware.
The half-adder has two inputs and two outputs; it adds 2 bits at a time. The full-adder has three inputs
and two outputs; it adds 3 bits at a time. By connecting a controlled inverter and full-adders, we can build
an adder~subtracter. This circuit can perform addition, subtraction, multiplication, and division.
A fast adder brings parallelism in <1ddition process, more specifically by generating the carry using extra
hardware through a look. ahead logic. An Arithmetic Logic Unit is a versatile device, which can generate
many useful arithmetic and logic functions with appropriate selection of inputs. Cascading ofthese dee
vices is usually possible for working with larger sized numbers.
• arithmetic logic unit A device that can • microprocessor A digital IC that combines the
perform both arithmetic and logic function arithmetic and control sections of a computer.
based on select inputs. • MSB Most-significant bit
• full-adder A logic circuit with three inputs " parallel addition A method of binary addition
and two outputs. The circuit adds 3 bits at a where carry generation at a particular stage
time, giving a sum and a carry output. does not depend on availability of carry from
• half-adder A logic circuit with two inputs and previous stage.
two outputs. It adds 2 bits at a time, producing • overflow An unwanted carry that produces an
a sum and a carry output. answer outside the valid range of the numbers
• hardware The electronic, magnetic, and being represented.
mechanical devices used in a computer or • ripple carry Carry that ripples from one stage
digital system. to other in serial addition.
• LSB Least-significant bit. • serial addition A method of binary addition
• look ahead carry Carry that need not ripple where carry sequentially propagates from one
from one stage to other and is obtained through stage to next stage.
a look ahead logic after the binary numbers are • software A program or programs. The
placed in adder unit; useful in fast addition. instructions that tell a computer how to
• magnitude The absolute or unsigned value of process the data.
a number. " 2's complement The binary number that results
when 1 is added to the l's complement.
6.2 Work out each of these binary sums:

a. 0000 1111 + 0011 0111
6.1 Give the sum in each of the following: b. 0001 0100 + 0010 1001
a. 3s + 7s = ? b. 5s + 6s = ? C. 0001 1000 1111 0110 +
0000 1111 0000 1000
6.3 Show the binary addition of 75010 and 53810 a. FCH b. 34H
using 16-bit numbers. C. 9AH d. B4H
6A Subtract the following: 0100 1111 -0000 6.13 Show the 8-bit addition of these decimal
0101. numbers in 2's complement representation:
6.5 Show this subtraction in binary form: 47 10 a. +45, +56 b. +89, -34
-2310. C. +67,'-98
6.14 Show the 8-bit subtraction of these decimal
numbers in 2's complement representation:
6.6 Indicate which of the following produces an a. +54, +65 b. +68, -43
overflow with 8-bit unsigned arithmetic: C. +16, -38 d. -28, ~5
a. 4510 + 7810 b. 34s + 56s
C. CF16 + 6716
6.15 Suppose that FD34H is the input to a 16-bit

controlled inverter. What is the inverted output
6.7 Express each of the following in 8-bit sign- in hexadecimal notation? In binary?
magnitude form:
a. +23 b. +123
C. -56 d. -107 6.16 Expressed in hexadecimal notation, the two
6.8 Convert each of the following sign-magnitude input numbers in Fig. 6.6 are 7FH and 4DH.
numbers into decimal equivalents: What is the output when SUB is low?
a. 00110110 6.17 The input numbers in Fig. 6.6 are 0001 0010
b. 1010 1110 and 1011 1111. What is the output when SUB
C. 1111 1000 is high?
d. 1000 1100 0111 0101
6.18 Show how two IC 74283s can be connected

6.9 Express the l's complement of each of the to add two 8-bit numbers. Find the worst case
following in hexadecimal notation: delay.
a. 23H b. 45H 6.19 Show how a parallel adder generates sum and
carry bits while adding two numbers 1001 and
c. C9H d. FDH
1011. What is the final result?
6.10 What is the 2's complement of each of these:
a. 0000 1111
b. 0101 1010
C. 1011 1110 6.20 How A < B function is performed in IC
d. 1111 0000 1111 0000 74181?
6.11 Use Appendix 2 to convert each of the 6.21 Show how 7 can be subtracted from 13 using
following to 2's complement representation: IC 74181.
a. +78 b. -23
C. -90 d. ~121
6.12 Decode the following numbers into decimal 6.22 Describe a program that multiplies 9 x 7 using
values, using Appendix 2: repeated addition.
Arithmetic Circuits
AIM: The aim of this experiment is to per- Apparatus: .5 VDC Power supply, Multime-
form addition and subtraction ·of two 8-bit ter, and Bread Board
data.
Work element: Verify the truth table of IC
Theory: Two's complement arithmetic 7483. Connect two 7483 to perform 8-bit addi-
complements the number.to be subtracted and tion as shown. The exclusive-OR gate passes
adds one to it. Then this is added with the other the same data to adder when SUB = 0 and a
number to perform subtraction. The addition is fOmplement of the data when SUB = 1 where
straight forward. IC 7483 is a 4-bit full adder assertion of SUB stands for subtraction. Add
with canyin input at pin 13.The exclusive-OR and subtract :five pair of numbers and compare
gate is useful to :find complement of a binary with theoretical result.
number.
Upper Lower
3 8 3 8
5 5
+5V +SV
13 14 13
7483 7483
12 12
- 15 2 6 9
S1 s6 S5 S4
See Eqs. (6.l) through (6.4). 14. Inputs: A, B, and CARRY IN; outputs:
2. This is the hexadecimal number l79F. SUM and CARRY
3, Binaryl11; decimal Ul 15. T; see Fig. 6.4.
4. See Eqs, (6.5) through (6.8). 16. Parallel adder requires 5 gate delays and
5. It is used to indicate an overflow. serial adder (2n + 2) gate delays for n-bit
6. 255 addition.
7. -127to+l27 17. Five.
8. -13; +13 18. ALU is .short form of Arithmetic Logic
9. 0010 1001 {Jnit, a digital hard\Vare that cart perf611l'l
10. 0010 1010 both arithmetic and logic operations.
ll. 2'scomplement 19. Substitute M"" 1 and S3 ..S0 = OOlL
12. Take the complement of the subtrahend 20. Itrealized only by repeatedly substracting
andadd.itto the minuend. one numberfrom·the other.
13, Inputs: A and B; outputs: SUM and
CARRY
Clocks and Timing Circuits
+ State the purpose of a clock in a digital system and demonstrate an understanding of

basic terms and concepts related to clock waveforms
+ Discuss the operation of the Schmitt trigger and its applications
+ Recognize the astable and the monostable 555 timer circuits and compare the
behavior of the two circuits
+ Describe the retriggerable and nonretriggerable monostables
The heart of every digital system is the system clock. The system clock provides the heartbeat without which
the system would cease to function. In this chapter we consider the characteristics of a digital clock signal
as well as some typical clock circuits. Schmitt triggers are used to produce nearly ideal digital signals from
otherwise noisy or degraded signals. Propagation delay is the time required for a signal to pass from the
input of a circuit to its output. You will see how to utilize logic gate propagation delay time to construct a
pulse-forming circuit. A monostable is a basic digital timing circuit that is used in a wide variety of timing
applications. We consider a number of different commercially available monostable circuits and examine
some common applications.
7.1 CLOCK WAVEFORMS
Up to this point, we have been considering static digital logic levels, that is, voltage levels that do not change
with time. However, all digital computer systems operate by "stepping through" a series oflogical operations.
The system signals are therefore changing with time: they are dynamic. The concept of a system clock was in-
troduced in Chapter. 1. It is the clock signal that advances the system logic through its sequence of steps. The
square wave shown in Fig. 7. la is a typical clock waveform -J r-

Clock cycle time
used in a digital system. It should be noted that the clock need
not be the perfectly symmetrical wavefonn shown. It could
(a)
simply be a se1ies of positive (ornegative) pulses as shown in
Fig. 7.lb. This waveform could of course be considered an -J J- Clock cycle time
asymmetrical square wave with a duty cycle other than 50 _fL_JLJULJl_
percent. The main requirement is that the clock be perfectly (b)
periodic, and stable.
Notice that each signal in Fig. 7.1 defines a basic timing Ideal clock waveforms
interval during which logic operations must be performed.
This basic timing interval is defined as the clock cycle time, and it is equal to one period of the clock wave-
fonn. Thus all logic elements must complete their transitions in less than one clock cycle time.
Synchronous Operation
Nearly all of the circuits in a digital system (computer) change states in .STnchronism with the system clock.
A change of state will either occur as the clock transitions from low to high or as it transitions from high to
low. The low-to-high transition is frequently called the positive transition (PT), as shown in Fig. 7.2. The PT
is given emphasis by drawing a small arrow on the rising edge of the clock waveform. A circuit that changes
state at this time is said to be positive-edge-triggered. The high-to-low transition is called the negative
transition (NI), as shown in Fig. 7.2. The NT is emphasized by drawing a small arrow on thefalling edge of
the clock wavefom1. A circuit that changes state at iliis time is said to be negative-
edge-triggered. Virtually all circuits in a digital system are either positive-edge- __f-i_JL
triggered or negative-edge-triggered, and thus are synchronized with the system PT NT PT NT
clock. There are a few exceptions. For instance, the operation of a push button
(RESET) by a human operator might result in an instant change of state that is
not in synchronism with the clock. This is called an asynchronous operation.
What is the clock cycle time for a system that uses a 500-kHz clock? An 8-MHz clock?
Solution The clock cyqleis simply one period of the clock. For the 500-kHz clock,
l
Cycle time = x = 2 µs
500
For the 8-MHz clock,
Cycle time = I25 ns
Characteristics
The clock waveform drawn above the time line in Fig. 7.3a is a perfect, ideal clock. What exactly
are the characteristics that make up an ideal clock? First, the clock levels must be absolutely stable.
When the clock is high, the level must hold a steady value of +5 V, as shown between points a and b
on the time line. When the clock is low, the level must be an unchanging O V, as it is between points
b and c. In actual practice, the stability of the clock is much more important than the absolute
value of the voltage level. For instance, it might be perfectly acceptable to have a high level of
+4.8 V instead of+ 5.0 V, provided it is a steady, unchanging, +4.8 V.
+5 V ---· +5 v---·--
ov _ ov-
__,__ _.__.,___ ___,__ _ _ Time _ __,__ _,__..___ __.__ ___.,. Time
a b C a b C
(a) Ideal waveform (b) Oscilloscope trace
+5 V --:f.sv-·:::::.- -
I
I I
I I
0.5 V __ . : I
I. --
0 V --- I I 1 ,,,----
~ I-fr tr-I I-
- - ~ - - - - - - - - ~ - - - - Time
a b
(c) Expanded oscilloscope trace
Clock waveforms
The second characteristic deals with the time required for the clock levels to change from high to low
or vice versa. The transition of the clock from low to high at point a in Fig. 7.3a is shown by a vertical line
segment. This implies a time of zero; that is, the transition occurs instantaneously-it requires zero time.
The same is true of the transition time from high to low at point bin Fig. 7.3a. Thus an ideal clock has zero
transition time.
A nearly perfect clock waveform might appear on an oscilloscope trace as shown in Fig. 7.3b. At first glance
this would seem to be two horizontal traces composed of line segments. On closer examination, however,
it can be seen that the waveform is exactly like the ideal waveform in Fig. 7.3a if the vertical segments are
removed. The vertical segments might not appear on the oscilloscope trace because the transition times are so
small (nearly zero) and the oscilloscope is not capable of responding quickly enough. The vertical segments
can usually be made visible by either increasing the oscilloscope "intensity," or by reducing the "sweep
time."
Figure 7.3c shows a portion of the wavefonn in Fig. 7.3b expanded by reducing the "sweep time" such
that the transition times are visible. Clearly it requires some time for the waveform to transition from low to
high-this is defined as the rise time tr- Remember, the time required for transition from high to low is de-
fined as the fall time If It is customary to measure the rise and fall times from points on the wavefonn referred
to as the JO and 90 percent points. In this case, a 100 percent level change is 5.0 V, so 10 percent of this is 0.5
V and 90 percent is 4.5 V. Thus the rise time is that time required for the waveform to travel from 0.5 up to
4.5 V. Similarly, the fall time is that time required for the waveform to transition from 4.5 down to 0.5 V.
Finally, the third requirement that defines an ideal clock is its frequency stability. The frequency of the
clock should be steady and unchanging over a specified period of time. Short-term stability can be specified
by requiring that the clock frequency (or its period) not be allowed to vary by more than a given percentage
over a short period of time-say, a few hours. Clock signals with short-tenn stability can be derived from
straightforward electronic circuits as shown in the following sections.
Long-term stability deals with longer periods of time~perhaps days, months, or years. Clock signals
that have long-term stability are generally derived from rather special circuits placed in a heated enclosure
(usually called an "oven") in order to guarantee close control of temperature and hence frequency. Such
circuits can provide clock frequencies having stabilities better than a few parts in 109 per day.
Propagation Delay Time

Propagation delay tp is the time between a PT (or an NT) at the input of
a digital circuit and the resulting change at the output. For all practical
purposes, the time difference between fifty percent level of the input and
corresponding output wavefonns is used to calculate propagation delay.
The box in Fig. 7.4 on the next page represents any TTL logic gate in
the 74LSXX family. Notice that the waveform at the output is delayed
in time from the input waveform, tpLH is the delay time when the output
is transitioning from low to high. fpHL is the delay time when the output
vJ _ 1
1~-----'i~I___
I I
is transitioning from high to low. At temperatures below 75°C, tpHL is

only slightly larger than lpLH· For the 74LSXX devices, we will simply v, i
assume they are equal, and for simplicity let's define propagation delay
tplll --,...: : - - : : - tpl/l
as I I I 1
Propagation delay = tp "" tpLH"" tpHL

The Texas Instruments data book gives a typical value of Ip"" 9 ns for
74LSXX devices. For comparison, the high-speed CMOS has slightly longer delay times. For example, the
74HC04 inverter has tP = 24 ns, which is typical.
The total propogation delay through a 74HC04 inverter is known to be 24 ns. What is the
maximum clock frequency that can be used with this device?
Solution An alternative way of posing the question is: How fast can the inverter operate? Remember, the circuit
must complete. any change of state within one clock cycle time. So,
Clock cycle time ;:: tp
The maxiimun clock frequency is then
1 1
Frequency = t P = 24 x 10_9 = 4 L 7 MHz
Pulse-Forming Circuits
It is sometimes necessary to use a series of narrow pulses in place of the
rectangular clock waveform. Two such wavefo1ms are shown in Fig.
cL.tll_S1S1Sl_
7.5. The positive pulses occurring at the leading edge of the clock will
p ~
define the PTs, while the negative pulses occurring at the falling edge
will define the NTs. By taking advantage of the propagation delay time N ~
through a gate, it becomes a simple matter to change the rectangular
clock into a series of pulses. There are numerous circuits that will change
the clock into a pulse train, and here are two possibilities.
In Fig. 7 .6a, the clock (CLK) is applied to a NAND gate and an AND gate at the same time. The output of
the NAND gate (A) is delayed by Ip. The output of the AND gate (PT) is high only when both its inputs are
high. This is shown as the shaded region on the waveforms in Fig. 7.6b. The output (PT) is also delayed by
tP through the AND gate, and it appears as a positive pulse. Each output pulse (PT) is delayed by Ip from the
leading edge of CLK, and each pulse has a width equal to tP' Any digital circuit that incorporates the pulse-
forming block in Fig 7 .6a is said to be positive-edge-triggered, since it will change states in synchronism
PT CLK PT
(a)
CL§L_
A•I
I
I
I
tp~ -
PT tp
(b) (a)
~ (c)
~ (b)
with the PT of the clock. The box in Fig. 7.6c is a general symbol for a positive-edge-triggered circuit. The
small triangle inside the box is called a dynamic input indicator, which simply means the circuit is sensitive
to PTs.
In Fig. 7.7a, CLK is applied to a NAND gate and an OR gate simultaneously. The output of the NAND-
gate (A) is delayed by tr The output of the OR gate (NT) is low only when both its inputs are low. This is the
shaded region on the waveforms. The output (NT) is also delayed by tp through the OR gate, and it appears
as a negative pulse. Each output pulse has a width of tP and each is delayed by tp from the falling edge of
CLK. Any digital circuit that incorporates this pulse-forming circuit is said to be negative-edge-triggered
since it will change states in synchronism with the NT of the clock. The box in Fig. 7.7b is a general symbol
for a negative-edge-triggered circuit. The small triangle is the dynamic input indicator, and the bubble shows
that the input is active-low. The small triangle on the output indicates that NT is normally high, and is active
when low. This triangle has the exact same meaning as the bubble. In fact, the IEEE standard uses these
symbols interchangeably. You will see both symbols used in industry and on manufacturers' data sheets. Just
remember, they both mean the same thing-active low!
It should be obvious that an inverter at the output of the AND gate in Fig. 7.6a will produce a series of
negative pulses that synchronize with the leading edge ofCLK. Similarly, an inverter at the output of the OR
gate in Fig. 7. 7 a will produce a series of positive pulses in synchronization with the falling edge of CLK.
These circuits, or variations of them, are used extensively with edge-triggered flip-flops-the subject of the
next chapter. If you care to look ahead at the flip-flop symbols, you will see the dynamic indicator and the
bubbled dynamic indicator used extensively.
Clocks and Circuits
l. Explain the meaning of positive-edge-triggered and negative-edge-triggered.

2. What is a dynamic input indicator'?
3. What is the logic symbol for an input sensitive to NTs?
7.2 TTL CLOCK
A 7404 hexadecimal inverter can be used to construct an excellent TTL-compatible clock, as shown in
Fig. 7.8. This clock circuit is well known and widely used. Two inverters are used to constrnct a two-stage
amplifier with an overall phase shift of 360° between pins 1 and 6. Then a portion of the signal at pin 6 is
fed back by means of a crystal to pin 1, and the circuit oscillates at a frequency detennined by the crystal.
Since the feedback element is a crystal, the frequency of oscillation is very stable. Here's how the oscillator
works.
Inverter 1 has a 330-Q feedback resistor (R 1) connected from output (pin 2) to input (pin 1). This forms a
current-to-voltage amplifier with a gain of A 1 = V0 I Ii= R1. In this case, the gain is A 1 = -330 V/ A, where
the negative sign shows 180° of phase shift. For instance, an increase of 1 mA in I;, will cause a negative-
going voltage of 1 mA x 330 = 330 m Vat V,,.
Inverter 2 is connected exactly as is inverter 1. Its gain is A2 = -R2 . The two amplifiers are then ac-coupled
with 0.01-µF capacitor to form an amplifier that has an overall gain of A= A 1 x A 2 = R 1R2 . Notice that the
overall gain has a positive sign, which shows 360° of phase shift. In this case, A = 330 x 330 = 1.09 x 105
V/A. For instance, an increase of 45 µA at Ji will result in a positive-going voltage of 5. 0 V at pin 6 of inverter
2. Now, if a portion of the signal at pin 6 is fed back to pin 1, it will augment I; (positive feedback) and the
circuit will oscillate.
A series-mode crystal is used as the feedback element to return a portion of the signal at pin 6 to pin 1. The
crystal acts as a series RLC circuit, and at resonance it ideally appears as a low-resistance element with no
phase shift. The feedback signal must therefore be at resonance, and the two inverters in conjunction with the
crystal form an oscillator operating at the crystal resonant frequency.
With the feedback element connected, the overall gain is sufficient to drive each inverter between
saturation and cutoff, and the output signal is a periodic waveform as shown in Fig. 7.8. Typically, the output
clock signal will transition between O and +5 V, will have rise and fall times of less than 10 ns, and will be
essentially a square wave. The frequency of this clock signal determined by the crystal, and values between
1 and 20 MHz are common.
Inverter 3 is used as an output buffer amplifier and is capable of driving a load of 330 Q in parallel with
100 pF while still providing rise and fall times ofless than 10 ns.
A TTL clock circuit as shown in Fig. 7.8 is said to provide a 5-MHz clock frequency with a
stability better than 5 parts per million (ppm) over a 24-h time period. What are the frequency
limits of the clock?
Solution A stapility of5 parts per mHlion means that a· I-MH~ clock will have a frequency of l,000,000 plus .or
minus 5 Hz. So, this clock will have a frequency ofS,000,000 plus or minus 25 Hz. Over any 24-h period the .clock
frequency will be somewhere between 4,999,975 and 5,000,025 Hz:
R1 330Q R2 = 330 Q
Crystal
-
iI
#I
l.6 -7404
2
Vo
0.01 µF
5
#2
l. _7404
6
+Vee J1JU
6
II 10 GND
#3 Clock
output
Simulated load
TTL clock circuit
4. Why must the crystal in Fig, 7.8 be a series mode and not a parallel mode?
5. Are the l 00-pF and 330-Q loads necessary in Fig. 7 .8?
7.3 SCHMITT TRIGGER
A Schmitt trigger is an electronic circuit that is used to detect whether a voltage has crossed over a given
reference level. It has two stable states and is very useful as a signal-conditioning device. Given a sinusoidal
waveform, a triangular wave, or any other periodic waveform, the Schmitt trigger will produce a rectangular
output that has sharp leading and trailing edges. Such fast rise and fall times are desirable for all digital
circuits.
Figure 7.9 shows the transfer function V
0
(V0 versus V;) for any Schmitt trigger. The
value of Vi that causes the output to jump
from low to high is called the positive-
going threshold voltage VT+· The value High state I
of Vi causing the output to switch from I
I
high to low is called the negative-going I
threshold voltage VT-· +

The output voltage is either high or
low. When the output is low, it is neces- Low s t a t e - - ~ -....
sary to raise the input to slightly more o---~-~------11;
than VT+ to produce switching action. Vr_ Vr+
0
The output will then switch to the high
state and remain there until the input is Schmitt-trigger transfer characteristic
reduced to slightly below Vy_. The output
will then switch back to the low state. The arrows and the dashed lines show the switching action.
The difference between the two threshold voltages is known as hysteresis. It is possible to eliminate
hysteresis by circuit design, but a small amount of hysteresis is desirable because it ensures rapid switching
action over a wide temperature range. Hysteresis can also be a very beneficial feature. For instance, it can be
used to provide noise immunity in certain applications (digital modems for example).
The TTL 7414 is a hex Schmitt-trigger inverter. The hex means there are six Schmitt-trigger circuits in one
DIP. In Fig. 7.lOa, the standard logic symbol for one of the Schmitt-trigger inverters in a 7414 is shown along
with a typical transfer characteristic. Because of the inversion, the characteristic curve is reversed from that
shown in Fig. 7.9. Looking at the curve in Fig. 7.10b, when the input exceeds 1.7 V, the output will switch to
the low state. When the input falls below 0.9 V, the output will switch back to the high state. The switching
action is shown by the arrows and the dashed lines.
The TTL 74132 is a quad 2-input NAND gate that employs Schmitt-trigger with a similar hysteresis
characteristics as described before for 7414. Figure 7.10c shows the standard logic symbol for one Schmitt-
trigger NAND gate.
Vo
(V)
3.4 I I
I I
I I
I I
I n ~
V ; ~ V0 t t ~Output
Input 2
(a) 0.2 (c)
0 - - ! - - - - ' - - ' ' - - - - - - V;
0.9 1.7
0
(b)
(a) Logic symbol of Schmitt-trigger inverter, (b) 7 414 hysteresis characteristics,

and (c) Logic symbol of Schmitt-trigger 2-input NAND gate
A sine wave with a peak of 2 V drives one of the inverters in a 7414. Sketch the output
voltage.
Solution When the sinusoid exceeds 1.7 V, the output goes from high to fow; The output stays in the low state until
the input sinusoid drops below 0.9 V. Then the output jumps back to the high state. Figure 7.11 shows the input and
output waveforms. This illustrates the signal-conditioning action of the SchmitHrigger inverter, It has changed the
sine wave into a rectangular pulse with fast rise and fall times. The same action would occur for any other periodic
waveform.
Noisy Signals
The hysteresis characteristic of a Schmitt trigger is very useful in changing noisy signals, or signals with
slow rise times, into more nearly ideal digital signals. A noisy signal is illustrated in Fig. 7 .12a. Applying this
signal to the input of a 7404 inverter will produce multiple pulses at its output, as shown in Fig. 7.12b. Each
time the input signal crosses the threshold of the 7404, it will respond, and the multiple output transitions are
the result. When used with an edge-triggered circuit, this will produce numerous unwanted PTs and NTs. The
0.2 V ----
O- - - - - - - - - - - - - - - - - - - - -
(a) A noisy signal

(b)
I
I
':+--1 -=====:::t-t.
(c)
Schmitt trigger will eliminate these multiple transitions, as shown in Fig. 7. l 2c. When the input rises above
Vr+, the output will go low. However, the output will not again change state until the input falls below Vr-·
Thus, multiple triggering is avoided! A Schmitt trigger is occasionally incorporated in an IC, for instance, the
74121, which is discussed in the next section.
Clocks and Circuits
6. What is the meaning of hysteresis when appliedto a Schmitt trigger'?

7. What is the difference between an inverting and a noninverting Schmitt trigger?
8. Schmitt triggers can be used as simple inverters. What is another good application for a Schmitt
trigger?
7.4 555 TIMER-ASTABLE
The 555 timer is a TTL-compatible integrated circuit (IC) that can be used as an oscillator to provide a clock
waveforn1. It is basically a switching circuit that has two distinct output levels. With the proper external
components connected, neither of the output levels is stable. As a result, the circuit continuously switches
back and forth between these two unstable states. In other words, the circuit oscillates and the output is a
periodic, rectangular waveform. Since neither output state is stable, this circuit is said to be astable and is
often referred to as a fi·ee-running multivibrator or as table multivibrator. The frequency of oscillation as
well as the duty cycle are accurately controlled by two external resistors and a single timing capacitor. The
internal circuit diagram ofLM 555 timer is shown in Fig. 7.13(a). Note that the two comparators inside have
two different reference voltages Vccf3 and 2 Vccf3 for comparisons, if Vccf3 is the voltage between pin 1
and 8. Also note how they are connected to + and - input of the comparator. The Set Reset flip-fl.op sets or
resets the output based on these comparator outputs in its usual operation. If required, it can be separately
reset by asserting pin 4. More about this flip-flop will be discussed in next chapter. In this section, we show
how 555 can be connected to get an astable multivibrator and in next section, we will discuss how it can be
used in monostable mode.
The logic symbol for an LM555 timer connected as an oscillator is shown in Fig. 7 .13. The timing capacitor
C is charged toward+ Vcc through resistors RA and Rs. The charging time t 1 is given as
t1 = 0.693(RA + Rs)C
This is the time during which the output is high as shown in Fig. 7.13.
The timing capacitor C is then discharged toward ground (GND) through the resistor Rs. The discharge
time t2 is given as
t2 = 0.693RsC
This is the time during which the output is low, as shown in Fig. 7.13.
The period T of the resulting clock waveform is the sum of t 1 and t2. Thus
T= ti+ t2 = 0.693(RA + 2Rs)C
The frequency of oscillation is then found as
1 1.44
f = T =(RA +2Rs)C
Determine the frequency ofoscillation for the 555 timer in Fig. 7.13, givenR.1 =Rs= 1 kQ and
C= 1000 pF.
t1 = 0.693 (RA+ Ra) C

t2 = 0.693 RaC
1.44
t=-----
(RA + 2Ra) C
t7 Ra
Duty cvcle = - - - = - - " - -
. t1 + t2 RA + 2Ra
+Vee
SET/RESET
FLIP-FLOP 4 8 7
2 Rs
- - - - - - ; 3 LM 555 6 1----e----'
o"~{M ~~~-5~ C
(a) (b) Logic diagram
,-._
1-L,
2,
.,.,
10 1->.---l---------l---l
<.)
§
·u
"'§-- 0.1
<.)
u 0.01 - - - - - - ~.........- -............
10 100 lk 10k 100k

f- free-running frequency (Hz)
(c) Nomograph
(a) Internal diagram of LM 555, (b) LM 555 in astable mode, (c) Nomograph
Solution Using the relationship given above, we obtain

1.44
f = [1000 + 2(1000)} X 10-9 480 kHz
The output of the 555 timer when connected this way is a periodic rectangular wavefonn but not a
square wave. This is because t 1 and t2 are unequal, and the waveform is said to be asymmetrical. A mea-
sure of the asymmetry of the wavefonn can be stated in terms of its duty cycle. Here we define the duty
cycle to be the ratio of t2 to the period.
Thus
Duty cycle = --"--

ti +t2
As defined, the duty cycle is always a number between 0.0 and. LO but is often expressed as a percent
For instance, if the duty cycle is 0.45 (or45percent), the signal is at GNDlevel 45 percent of the time and
at high level 55 percent of the time.
(a) Given Rs 750 Q, determine values for RA and C in Fig. 7.13 to provide a 1.0-MHz clock that has a duty cycle
of 25 percent.
(b) What change in the circuit shown in Fig. 7 .13 gives duty cycle approximately 50%?
Solution
(a) A I-MHz clock has a period of 1 µs. A duty cycle of25 percent requires ti= 0.75 µ.sand t2 = 0.25 µs. Solving
the expression
for R.4 yields

RA = Rs 750 - .2 x 750 = 1.::i·oo""
= - 2Rs =-0.25 ,. .
Duty cycle
Solving t2 = 0.693 RsC for C yields
·'-6
C= . t2 0.25 x10 = 480 F
0.693Rs 0.693 x750 . p
(b) Connect a diode across Rs pointing from pin 7 to 6 so that it conducts while charging capacitor C and make RA
= Rs. Then while charging, Rs is bypassed as diode is forward biased but discharging is through Rs as diode
remains reverse biased and does not conduct. Thus we get same charging and discharging currenCNegiecting
small voltage drop across forward biased diode we approximately gate 50% duty cycle,
The nomogram given in Fig. 7. l 3b can be used to estimate the free-running frequency to be achieved
with various combinations of external resistors and timing capacitors. For example, the intersection of the
resistance line 10 kQ =(RA+ 2Rs) and the capacitance line 1.0 µF gives a free-running frequency of just over
100 Hz. It should be noted that there are definite constraints on timing component values and the frequency
of oscillation, and you should consult the 555 data sheets.
9. Whatis an astable circuit?

10. A 555 timer can be connected to form an oscillator. (Tor F)
11. The oscillation frequency in astable 555 is (directly, inversely) proportionalto the external
timing capacitor.
~ Digital Principles and Applications
7.5 555 TIMER-MONOSTABLE
With only minimal changes in wiring, the 555 timer discussed in Sec. 7.4 can be changed from a free-running
oscillator (astable) into a switching circuit having one stable state and one quasistable state. The resulting
1110nostable circuit is widely used in industry for many different timing applications. The normal mode of
operation is to trigger the circuit into its quasistable state, where it will remain for a predetermined length
of time. The circuit will then switch itself back (regenerate) into its stable state, where it will remain until it
receives another input trigger pulse. Since it has only one stable state, the circuit is characterized by the term
monostable multivibrator, or simply monostable.
The standard logic symbol for a monostable is shown in Fig. 7.14a. The input is labeled TRIGGER, and
the output is Q. The complement of the Q output may also be available at Q. The input trigger circuit may
be sensitive to either a PT or an NT. In this case, it is negative-edge-triggered. Usually the output at Q is low
when the circuit is in its stable state.
A typical set of waveforms showing the proper operation of a monostable circuit is shown in
Fig. 7.14b. In this case, the circuit is sensitive to an NT at the trigger input, and the output is low when the
circuit rests in its stable state. Once triggered, Q goes high and remains high for a predetermined time t and
then switches back to its stable state until another NT appears at the trigger input.
1
TR1GGER ~ ~
TRlGGER~
Dl- Q I
I
I
Q~~~
(a) Logic symbol (b) Waveforms
Monostable circuit
A 555 timer wired as a monostable switching circuit (sometimes called a one-shot) is shown in Fig. 7.15
on the next page. In its stable state, the timing capacitor C is completely discharged by means of an internal
transistor connected to Cat pin 7. In this mode, the output voltage at pin 3 is at ground potential.
A negative pulse at the trigger input (pin 2) will cause the circuit to switch to its quasistable state. The
output at pin 3 will go high and the discharge transistor at pin 7 will tum off, thus allowing the timing
capacitor to begin charging toward Vcc·
When the voltage across Creaches 2/ 3 Vee, the circuit will regenerate back to its stable state. The discharge
transistor will again tum on and discharge C to GND, the output will go back to GND, and the circuit will
remain in this state until another pulse arrives at the trigger input. A typical set of waveforms is shown in
Fig. 7.15b.
The output of the monostable can be considered a positive pulse with a width
t= 1.1 RAC
Take care to note that the input voltage at the trigger input must be held at+ Vee, and that a negative pulse
should then be applied when it is desired to trigger the circuit into its quasistable or timing mode.
Find the output pulse width for the timer in Fig. 7.15 given RA = IO kQ and C = 0.1 µF.
+5 V to +15 V
,-,-----R.-e-se-t--.------e----o+f'cc
I
I
I I 1 I
I
I
I
: Trigger 4 8 Discharge
Normally~ 2 7------ 1111 1111 111r 1111 1111 1111
"on" RL
load Threshold
LM555 6
Control
Output voltage I I I I
3 5 C I I I
Normally o.oi Vcc=5V Top trace: input 5 V/DlV
"'off' µF Time=O.l ms/DIV Middle trace: output 5 V/DIV
load RA 9.1 k..Q Bottom trace: capacitor voltage
2 V/DIV
C=O.l µF
-
(a) Monostable (b) Monostable waveforms
100
G:' 10
2,
~
~
·u
"' 0.1
g. 1---+t--cri-
u
I
u O.ot ,____,..._,,..._.__,.+---+>--1--.....-----1
0.001 '---'-'-----'"---"--~~-~~
lOµs lms lOOms IOs
100 µs 10 ms Is 100 s
(c) Time delay, t = 1.1 R;1C
LM555 connected as a monostable circuit
Solution The pulse width is found as
Find the value of C necessary to change the pulse width in Example 7. 7 to 10 ms.
Solution The timing equation can be solved for C as
=0.909µF
The nomograph shown in Fig. 7. l 5c can be used to obtain a quick, if not very accurate, idea of the sizes of
RA or C required for various pulse-width times. You can quickly check the validity of the results of Example
7.8 by following the RA= IO kQ line up to the C = 0.1 µF line and noting that pulse-width time is about 1
ms.
Once the circuit is switched into its quasistable state (the output is high), the circuit is immune to any other
signals at its trigger input. That is, the timing cannot be interrupted and the circuit is said to be nonretriggerable.
However, the timing can be interrupted by the application of a negative signal at the reset input on pin 4. A
voltage level going from + Vcc to GND at the reset input will cause the timer to immediately switch back to
its stable state with the output low. As a matter of practicality, if the reset function is not used, pin 4 should
be tied to + Vcc to prevent any possibility of false triggering.
12. What is a monostable?

13. A 555 timer can be connected as a one-shot (Tor F)
14. Is the stable output state of a 555 timer connected in a monostable mode high or low?
7.6 MONOSTABLES WITH .INPUT lOGiC
The basic monostable circuit discussed in the previous section provides an output pulse of predetermined
width in response to an input trigger. Logic gates have been added to the inputs of a number of commercially
available monostable circuits to facilitate the use of these circuits as general-purpose delay elements. The
74121 nonretriggerable and the 74123 retriggerable monostables are two such widely used circuits.
The logic inputs on either of these circuits can be used to allow triggering of the device on either a high-
to-low transition (NT) or on a low-to-high transition (PT). Whenever the value of the input logic equation
changes from false to true, the circuit will trigger. Take care to note that a transition from false to true must
occur, and simply holding the input logic equation in the true state will have no effect.
The logic diagram, truth table, and typical waveforms for a 74121 are given in Fig. 7.16. The inputs to the
74121 are A1 , A2 , and B. The trigger input to the monostable appears at the output of the AND gate. Here's
how the gates work:
1. If Bis held high, an NT at either A1 or A2 will trigger the circuit (see Fig. 7.16c). This corresponds to
the bottom two entries in the truth table.
2. If either A1 or A2 , or both are held low, a PT at B will trigger the circuit (see Fig. 7.16d).
This corresponds to the top two entries in the truth table. A logic equation for the trigger input can be
written as
T= (A1 + A2)BQ
Note that for T to be true (high), either A I or A 2 must be true-that is, either X1 or A2 at the gate input
must be low. Also, since Q is low during the timing cycle (in the quasistable state), it is not possible for a
transition to occur at T during this time. The logic equation for T must be low if Q is low. In other words,
once the monostable has been triggered into its quasistable state, it must time out and switch back to its stable
state before it can be triggered again. This circuit is thus nonretriggerable.
.------Vee A1 A2 B Result
R
C L X t Trigger
X L t Trigger
11 10 t= 0.69 RC
t H H Trigger
6 -l I- H f H Trigger
Q SL
Note: Triggering can occur only when Q is H
74121 (not in timing cycle)
1 L=Low
0--
Q H=High
GND X= Don't care
7 t = Low to high transition
t High to low transition
(a) Logic diagram (b) Truth table
- 1--, r----1 - 1
A1 0 y A10----------
A
2
6_ _,___~i---u-----
I
- 1----------
A2 0
,
n
I
B l -~---11------ B I
0
I
o--\1--------
} I I
r1 A
TO~~ o__J,'~-------
1 I I 1 ,.,...,_--.
Qo~~ Qo__J--c-r::..i~~~~
(c) Negative triggering (d) Positive triggering
74121 nonretriggerable monostable
The output pulse width at Q is set according to the values of the timing resistor R and capacitor C as
t= 0.69RC
For instance, if C = 1 µF and R = 10 kQ, the output pulse width will be t = 0.69 x 104 x 10-6 = 6.9 ms.
The 74121 monostable in Fig. 7.16 is connected withR = 1 kQ and C= 10,000 pF. Pins 3 and
4 are tied to GND and a series of positive pulses are applied to pin 5. Describe the expected
waveform at pin 6, assuming that the input pulses are spaced by (a) 10 µsand (b) 5 µs.
The logic diagram and truth table for a 74123 retriggerable monostable are given in Fig. 7.18. There are
actually two circuits in each 16-pin DIP, and the pin numbers are given for one of them. The input logic is
-I 5µs I-
BI
0
Q 1 Q 1
0 0
- j 6.9 µs 1- - j 6.9 µs 1-
(a) Triggers on every pulse at B (b) Triggers on every other pulse at B
simpler than for the 74121. The inputs are A, B, and R, and the truth table summarizes the operation of the
circuit. The fi~t entry in the truth table shows that the circuit will trigger if R and B are both high, and an
NT occurs at A .
The second truth table entry states the circuit will trigger if A is held low, R is held high, and a PT occurs
atB.
In the third truth table entry, if A is low and B is high, a PT at R will trigger the circuit.
The last two truth table entries deal with direct reset of the circuit. Irrespective of the values of A or B, if
the R input has an NT, or is held low, the circuit will immediately reset.
The logic equation for the trigger input to the monostable can be written T = AB R. Notice that the state
of the output Q does not appear in this equation (as it does for the 74121 ). This means that this circuit will
trigger ever)' time there is a PT at T. In other words, this is a retriggerable monostable!
The output pulse width at Q for the 74123 is set by the values of the timing resistor Rand the capacitor C.
It can be approximated by the equation
t = 0.33RC
The waveforms in Fig. 7.19c show a series of negative pulses used to trigger the 74123. Notice carefully
that the circuit triggers (Q goes high) at the first high-to-low transition on A, but that the next two negative
pulses on A retrigger the circuit and the timing cycle t does not begin until the very last trigger!
The 74123 in Fig. 7.18 is connected with A at GND, R at +Vee, R = 10 kQ, and C =
10,000 pf. Describe the expected waveform at Q, assuming that a series of positive pulses
are applied at Band the pulses are spaced at (a) 50 µsand (b) 10 µs.
Solution The -Output pulse widtbwill be aboµt

t=033x I04 xl0.,..s=33µs
11; The circuit xvill trigger and tim<:out \Vith every pulse l!.S s.hownin Fig. 7..l9a.
b. The.circuit will trigger with the first pulse and then retrigger with every following pulse. The timing cycle will
be re.set with eyery input pulse, and Qwill simply remain high since the drcuhwill never be alloxved to time out
(see Fig.7.19b).1f the pulses at Bare stopped, Q will be allowed to time out and will go fow 33 µs aft;erthe last
pulseatB.
t=0.33 RC
13
-l 1- A B R Q
..JL
T (1/2)
Q t H H Trigger
74123 4 L t H Trigger
R Q L H t Trigger H=High
3 X X L Reset L=Low
X= Don't care
X X t Reset += Low to high transition
R t = High to low transition
(a) Logic diagram (b) Truth table
- 1
A 0
B I
0
-1-~---~------
Ro :
I
Q ~_j ~ t ~'----
(c) Waveforms
74123
B~~~
: :...-t-1
Q I
0
-J f-
Q~_j jTl-
33µs -1 33µs 1-
(a) (b)
15. The 74121 is a (retriggerable, nonre¢ggerable)monostahle.

16. The input logic used with a 74-12 lutilizes a Schmitt .trigger. (Tor .F)
17. The output pulse wilith of a 74121 is RCmultiplied by _ __
7.7 PULSE-FORMING CIRCUITS
The monostable circuits discussed in the previous sections have pulse-width times that are predictable to
around 10 percent. As such, they do not represent precise timing circuits, but they do offer good short-term
stability and are useful in numerous timing applications.
One such application involves the production of a pulse that occurs after a given event with a predictable
time delay. For instance, suppose that you are required to generate a I-ms pulse exactly 2 ms after the
operation of a push-button switch. Look at the waveforms in Fig. 7 .20b. If the operation of the switch occurs
when the waveform labeled SWITCH goes high, the desired pulse is shown as OUTPUT. In this case, the
delay time t I will be set to 2 ms, and the time of the pulse width t2 will be I ms.
The two monostables in the 74123 shown in Fig. 7.20a are connected to provide a delayed pulse. The first
circuit provides the delay time as t1 = 0.33R I x C1, while the second circuit provides the output pulse width as
t2 = 0.33R2 x C2 . The PT at the INPUT triggers the first circuit into its quasistable state, and its output at ~
goes low. After timing out t 1, Q1 goes high, and this transition triggers the second circuit into its quasistable
state. The OUTPUT thus goes high until the second circuit times out t2 , and then it returns low.
The input to the circuit in Fig. 7.20a is changed to a 100-kHz square wave. It is desired to
produce a 1-µs pulse 2 µs after every positive transition of the input as shown in Fig. 7.21.
Find the proper timing capacitor values, given that both timing resistors are set at 500 n.
Solution Th.e capacitor value for the pulse width is found using t = 0.33 RC Thus:
C= 1.0-6 =6000pF
0.33x500
The pulse delay capacitor is twice this value, or 0.012 µF.
Glitches
Whenever two or more signals at the inputs of a gate are undergoing changes at the same time, an undesired
signal may appear at the gate output-this undesired signal is called a glitch. For example, in Fig. 7.22a, the
gate output at X should be low except during the time when A = B = C = I as shown. However, there is the
possibility of a glitch appearing at the output at two different times. At time T1, if C happens to go high before
A and B go low, a narrow positive spike will appear at the gate output-a glitch! Similarly, a glitch could
occur at time T2 if B happens to go high before A goes low.
A glitch is an unwanted signal generated usually because of different propagation delay times through
different signal paths, and they generally cause random errors to occur in a digital system. They are to be
avoided at all costs, and a logic circuit designer must take them into account. One method of avoiding glitches
in the instance shown in Fig. 7.22a is to use a strobe pulse.
It is a simple matter to use a pulse delay circuit such as the one shown in Fig. 7.20 to generate a strobe pulse.
Consider using the waveform A in Fig. 7 .22a as the input to the pulse delay circuit, and set the monostable
times to generate a strobe pulse at the midpoint of the positive half cycle of A, as shown in Fig. 7.22b. If the
inputs to the AND gate are now A, B, C, and the strobe pulse, the output will occur only when A = B = C = l,
and a strobe pulse occurs. The glitches are completely eliminated!
An interesting variation of the pulse delay circuit in Fig. 7.20 is shown in Fig. 7.23a. Here, we have simply
connected the Q output of the second circuit back to the input of the first circuit. This is a form of positive
5
QI Q2 OUTPUT
INPUT T (112) T (112)
74123_ 74123_
QI 4 Q2
R R
(a) A 74123 with DIP pin numbers
1
SWITCH
0 I
I
I
QI LJ
0 I
I
n
I
OUTPUT
0
l- 11-I t2J--
(b) Delayed pulse at OUTPUT
Delayed pulse generator
j-lOµs--1
,-----,
-
100 kHz INPUT
0 i i
l..-2µs I
n
I I I
1
OUTPUT -fl-1µs
0
A _n_n__n_s1_
A _n_n__n_s1_
AD-
I I
I I I I
A D_
BC
-_B ~
X
I: L C I I
E X
STROBE
B ~
I I
STROBf::
I I
C I L
X f t fl X
I
I fL
T1 T2
(a) Glitches at T1 and T2 (b) Use of STROBE to remove glitches
Digital Pn'ncip/es and Applications
feedback. As a result, the circuit will oscillate-it becomes astable and generates a rectangular waveform as
shown in Fig. 7.23. Here's how it works. The first circuit triggers into its quasistable state. When it times
out t 1, the positive transition at Qi will trigger the second circuit. When it times out t2, the positive transition
at Q2 will retrigger the first circuit and the cycle will repeat.
+Vee +Vee
R, R2
14 6 7
5
Q, Q2 OUTPUT
T (1/2) T (1/2)
74123_ 74123_ 12
Q, Q2
4
R R
(a) Two monostable circuits connected to form an astable free-running oscillator
- 1
QI 0
I22 0
-
OUTPUT-0 l
- 2 0
!-t,+t2-J
(b) Waveforms
Independent adjustment of high and low levels of the output waveform is possible by setting the delay
times of each individual monostable. Take care to note that since each circui~ is edge-triggered, if a transition
is missed by either circuit, oscillation will cease!
18. Whatis a glitch?

19. What is a strobe pulse?
PROBLEM SOLVING WITH MULTIPLE MEJHODS

Design a 100 kHz pulse generator with 40 percent duty cycle.
Solutiou We can.use 55$ timerwor:l<.irig inastablemQ4e to generate tbis,Also, we can use monostable circuits
7412 lor 74123 and>pQsitive feeelhack for.this.•
If tL are tH are the times within T, during whiclipulse remain LO Wand HIGH respectively
Duty cycle = _ti_= = 0.4

ti+tH T
Thus, ti =0.4x 10 =4 µs
tH = T·- ti= J0,..,4=6 µs
In Method-1, we sbow . the c~Jculation required for 555 based pulse generator that uses a cir~uit as
shown in Fig,7,13a,
tL = 0.693 RsC
IJf =0.693(RA +Rs)C
RA+RB . RA 6
Taking ratio, -=-.,..;;;.. = 1 +-=- Thus,Rs=2RA
Rn Rs 4
lf we choose, RA =.WOO Q then Rs= 2000 Q
Substituting this in say, ti calculation: 4 x 10-6 = 0.693.x2000 x C
or, C ="2:9nf
In M~thod~2, ·.we show the calculation required for74l23..based pulse generator..thatuses.a.circuit
as shownin Fig,7.23a.
Select say Ci =
In Method•3; . we .show the calculation required for
74121based pulse generator that uses a circuit
similar to Fig. 7.23a where retriggerable 74123 is replaced by non-retriggerable 74121. From Section
7.6,
= 0.69 R1C1 = 4 µs
tH = 0.69 R2C2 = 6 µs
ThenRl= 5.8 kQ and R2 = 8.7 kQ
Asystem.·clocksignal··.isa.periodic warveJEori::n(us1lalll;r:a1squai,e.\lt,t,~e)thathai:;.stablehig}:1carldlQw'le'!l¢J:s,fg(
very $~Ott rise and fall times, <lrl4
good frequency. .. circuit widely used tp. 15~n,.er.1tea g~;le,..
stable, TIL-compatible clock wa:eforrn isthe crystal-controlled .circuit shown in
ASc~mitt triggerisa switchingdrct1itllaving two mp:ut thresholdvoltage levels.
and isusefulin cleaning up noisy signals; ·
The 555 timer is a digital tiliring circuitthatcan be connected as either a monostable or an astable circuit
It is widely used in a number of different applications. The 7412land 74123 monostable circuits boili>have
logic circuits at their inputs that increase th~ numbl:!r of possibleapp!ications.
A pulse delay circuit,and a free-running astable with adjustable duty cycle are only a few of the many
circuits that can be constructed iviili .the use of basic m<'mostable vircuits.
• astable Having two output states, neither of " negative-edge trigger An input sensitive to
which is stable. high-to-low signal transitions.
" asynchronous Referring to random events, " one-shot Another term for a monostable
not coordinated closely with a system clock. circuit.
" clock A periodic waveform (usually a square " PT Positive transition.
wave) that is used as a synchronizing signal in " positive-edge trigger An input sensitive to
a digital system. low-to-high signal transitions.
" clock cycle time The time period of a clock " propagation delay time The time required for
signal. a signal to propagate through a circuit, input
" clock stability A measure of the frequency to output.
stability of a waveform; usually given in parts " rise time The time required for a signal to
per million (ppm). transition from 10 percent of its maximum
• contact bounce Opening and closing of a set of value up to 90 percent of its maximum.
contacts as a result of the mechanical bounce " Schmitt trigger A bistable circuit used to
that occurs when the device is switched. produce a rectangular output waveform.
" dynamic inp11t indicator A small triangle used • TTL clock A circuit that generates a clock
on an input signal line to indicate sensitivity waveform that is compatible with standard
to signal transitions-edge triggering. TTL logic circuits.
" fall time The time required for a signal to 11 1 Opercent point A point on a rising or falling
transition from 90 percent of its maximum waveform that is equal to 0.1 times its highest
value down to 10 percent of its maximum. value.
• glitch Very narrow positive or negative pul::e " 90 percent point A point on a rising or falling
that appears as an unwanted signal. wavefonn that is equal to 0.9 times its highest
• monostable A circuit that has two output value.
states, only one of which is stable. 11 555 timer A digital timing circuit that can be
• NT Negative transition. connected as either an astable or a monostable

circuit.
a. 10MHz b. 6MHz
C. 750 kHz
7.1 Calculate the clock cycle time for a system that 7.2 What is the clock frequency if the clock cycle
uses a clock that has a frequency of: time is 250 ns?
7 .3 What is the maximum clock frequency that can 7.12 Draw the transfer curve for a Schmitt trigger
be used with a logic gate having a propagation if Vr+ = +1.0 V, Vr- = -1.0 V, high state= +5
delay of75 ns? Vde, and low state = 0 V de.
7.4 You are selecting logic gates that will be 7.13 Draw the output voltage for the Schmitt trigger
used in a system that has a clock frequency in Prob. 7.12 if Vi= 2 sin mt V.
of 8 MHz. What is the maximum allowable
propagation delay?
7.5 What would be the 10 and 90 percent points
7 .14 Determine the frequency of oscillation for
on the waveform in Fig. 7.3c if the amplitude
goes from Oto +4.5 V? the 555 timer in Fig. 7.13, given RA =RB=
47 kQ and C = 1000 pF. Calculate the values
of ti and t2, and carefully sketch the output
waveform.
7.6 Find the upper and lower frequency limits of 7.15 Detennine the frequency of oscillation for the
a 5-MHz clock signal that has a stability of 10 555 timer in Fig. 7 .13, given R.4 = 5000 Q, RB
ppm. = 7500 Q, and C = 1500 pF. Calculate values
7. 7 A TTL clock uses a series-mode crystal having for t1 and t2, and carefully sketch the output
a resonant frequency of 3.5 MHz. The circuit waveform.
provides a 24-h stability of 8 ppm. Calculate 7 .16 Use the nomogram in Fig. 7.13b to find (RA
the oscillator frequency limits. + 2RB), given C = 0.1 µF and that the desired
7.8 The TTL clock shown in Fig. 7.8 uses a crystal frequency is 1 kHz. Check the results by using
that has frequency of7 .5 MHz. Draw the clock the formula given for the frequency.
output waveform if+ Vcc is set at+ 5 V. What 7 .17 Calculate the duty cycle for the circuit in Prob.
is the stability in ppm if the upper limit on the 7.13. For Prob. 7.14.
clock frequency is 7,499,900 Hz? 7.18 Derive the expression
7.9 The NAND gate in Example 7.2 has a Duty cycle= RBl(R.4 + 2RB)
propagation delay of 50 ns, and A is a 15-MHz
clock. Make a careful sketch of the waveform 7 .19 It is desired to have a duty cycle of 25 percent
at the Y output. Assume that B is always high. for the circuit in Prob. 7 .15. Find the correct
(Hint: Be sure to consider the propagation values for the hvo resistors.
delay time.)
7 .20 Calculate the output pulse width for the timer

7.10 Draw the input and output waveforms for the in Fig. 7 .15 for a 4, 7-kQ resistor and a 1.5-µF
Schmitt trigger in Fig. 7 .10, assuming that the capacitor.
input voltage is V= 3.0 cos lOOOt. 7 .21 Calculate the output pulse width for the circuit
7 .11 Draw carefully the waveforms at points A, B, in Problem 7.20, assuming that the resistor is
and C in Fig. 7.24. halved.
7.22 Calculate the output pulse width for the circuit
in Problem 7.20, assuming that the capacitor
2-MHz
sine wave
oscillator
----<
A is doubled.
7.23 Find the capacitor value necessary to generate
C a 15-ms pulse width for the monostable in Fig.
(2.5 V peak)
7.15, given RA= 100 kQ.
7.24 A 500-Hz square wave is used as the trigger
input for the circuit described in Example 7. 7.
Make a careful sketch of the input and output 7.33 Using the circuit described in Prob. 7.31,
wavefonns (similar to those in Fig. 7.15b). make a careful sketch of the input and output
7.25 Repeat Prob. 7.24, assuming that the trigger waveforms if the input square wave has a
input is changed to a 1-kHz square wave. frequency of:
a. 1 kHz b. 5 kHz
7.26 In the 74121 in Fig. 7.16, R = 47 kQ and C =

10,000 pF. Calculate the output pulse width. 7.34 The input to the circuit in Fig. 7.20 is a 250-
7.27 Redraw the 74121 logic diagram in Fig. 7.16a kHz square wave. Determine the proper
and show how to connect the circuit such that timing capacitor values to generate a string of
it will trigger on the positive transitions of positive-going, 0.1-µs pulses, delayed by 2.0
a square wave. For R = 51 kQ, detem1ine a µs from the rising edges of the input square
value of C such that the output pulse will have wave. Assume R1 = R2 = l kQ.
a width of750 µs. 7.35 Draw the waveforms, input and output, for
7.28 Repeat Prob. 7.27, but make the circuit trigger the circuit in Fig. 7.20, given that both timing
on negative transitions of the square wave. resistors are 470 Q, C1 = 0.1 µF, C2 = 0.01 µF,
7.29 Using the circuit described in Prob. 7.27, and the input waveform has a frequency of 20
make a careful sketch of the input and output kHz.
wavefom1s, assuming the input square wave 7.36 Show how to use the circuit in Fig. 7.20 to
has a frequency of: generate a 0.2-µs strobe pulse centered on the
a. 1 kHz b. 5 kHz positive half cycle of a 200-kHz square wave
7.30 In the 74123 in Fig. 7.19, R = 47 kQ and C= (similar to Fig. 7.22b). Draw the complete
10,000 pF. Calculate the output pulse width. circuit and calculate all timing resistor and
7.31 Redraw the 74123 logic circuit shown in Fig. capacitor values. Assume R1 = R2 = 1 kQ.
7.18 and show how to connect the circuit such 7.37 Calculate values for the timing resistors and
that it will trigger on positive transitions of a capacitors in Fig. 7.23 to generate a clock
square wave. Given R = 51 kQ, determine a waveform that has:
value of C such that the output pulse will have a. A frequency of 100 kHz and a duty cycle
a width of750 µs. of 25 percent
7.32 Repeat Problem 7.31, but make the circuit b. A frequency of 500 kHz and a duty cycle
trigger on negative transitions of the square of 50 percent
wave.
AIM: The aim of this experiment istoimple- Refer to Fig. 7.23a. 7412Jessentiallyisamo~
ment •a 100 ·kHz pulse generator with 40 per- nostable and can be used in positive feedback.
cent duty cycle. It follows the relation
The<>ry: Refer to Fig.).13b. The 555.based t1 = 0.33 R1 Ci
ptllsegeneratorfollowsthe following two rela- tu= 0.33 R2C.2
tions.
Apparatus: 5 VDC Power supply, Multime-
t1 = 0.693 RsC ter, Bread Board, a.ndQscilloscope.
tu= 0.693(RA +Rs)C
_ _ _ _ _ _ _ _ _ _ _ _ _ _c_to_ck_s_a_n_d_Ti_m_in_g_C_irc_u_its_ _ _ _ _ _ _ _ _ _ _ _ _ _ ( ; )
6
4
5
2 Q2 OUTPUT
T (112)
74123__ 12
Q2
Work element: Study the working the oscilloscope reading and compare
555 and 74123, and understand the di:tltere,nt theoretical value. Conduct similar exer-
input outputs. From above relations, calculate cise for 74123 based circuit as shown. Repeat
the resistance and capacitance· values. See the the experiment with other combinations of re-
waveform in oscilloscope. Calculate duty cy- sistance andcapacitance values.
1. An inpt1! is sensitiv~ t~ Pis, an~. the drcllit

output changes synchronously with PTs:
(110 phase shi:ft):Inverting: 180° phase shift
between input and outpi1t
afo
The·circuit output changes in synchronism 8. Schmitt ~g~ers ca11 be ?s~d clean up a
withNTs. noisy signal or t~ cha11ge signalhaving
a
2. It means that Circuit inputis sensitive to aslow rise time into one having a fast rise
PTs. (See Fig. 7.6b.) time.
3. The logic symbolfor an input sensitive to A circuit has two output states, neithe! of
NTs isa bubblein_fro~tof a dynamic input which is stable.
indicator. (See Fig. 7.7b.) 10. True
4. A. . . . series mode ___ ()ff~rslow . impedanct? 11. Inversely
at resonance, thus providing positive 12. A circuit has two output states, one of
feedback for ·oscillation.. A.parallel mode which is stable.
offers high .impedance at resonance, and True
thus provides insufficient. feedback to The stable state is low.
ptoduce··oscilfation. Nonretriggerable
Unnecessa:fy, True
condition, 0.69
61 · lf ;1:1e~s th~t. tM: circuit lias>two input Glitclies are the unwanted pulses appearing
tl)re~~~ld • voltage .• l~veis-:--an upper . • atthe output of a gate when ,two or mote
tllr:s~~ld an~ •.
a ~~\¥er threshold, By
fOnttast,. a: simple inverter has only a single
inputs change state simultaneously.
Astrobe pulse·isa pulsetimedtodiminate
threshold voltage level. glitches.
·Noninvemnt:>the input····and output··. are
both high (or. both low) at the same time
Flip-Flops
+ Describe the operation of the basic RS flip-flop and explain the purpose of the
additional input on the gated (clocked) RS flip-flop
+ Show the truth table for the edge-triggered. RS flip-flop, edge-triggered D flip-flop,
and edge-triggered JK flip-flop
+ Discuss some of the timing problems related to flip-flops
+ Draw a diagram of a JK master-slave flip-flop and describe its operation
+ State the cause of contact bounce and describe a solution for this problem
+ Describe characteristic equations of Flip-Flops and analysis techniques of sequential
circuit
+ Describe excitation table of Flip-Flops and explain conversion of Flip-Flops as synthesis
example
The outputs of the digital circuits considered previously are dependent entirely on their inputs. That is, if
an input changes state, output may also change state. However, there are requirements for a digital device
or circuit whose output will remain unchanged, once set, even if there is a change in input level(s). Such
a device could be used to store a binary number. A flip-flop is one such circuit, and the characteristics of
the most common types of flip-flops used in digital systems are considered in this chapter. Flip-flops are
used in the construction of registers and counters, and in numerous other applications. The elimination of
switch contact bounce is a clever application utilizing the unique operating characteristics of flip-flops. In a
sequential logic circuit flip-flops serve as key memory elements. Analysis of such circuits are done through
truth tables or characteristic equations of flip-flops. The analysis result is normally presented through state
Flip-Flops
table or state transition diagram and also through timing diagram. Conversion of flip-flop from one kind to
another can be posed as a synthesis problem where flip-flop excitation tables are very useful.
8.1 RS FUP-flOPS
Any device or circuit that has two stable states is said to be bistable. For instance, a toggle switch has two
stable states. It is either up or down, depending on the position of the switch as shown in Fig. 8.la. The switch
is also said to have memo,y since it will remain as set until someone changes its position.
Aflip-fiop is a bistable electronic circuit that has two stable states-that is, its output is either O or +5
V de as shown in Fig. 8.1 b. The flip-flop also has memory since its output will remain as set until something
is done to change it. As such, the flip-flop (or the switch) can be regarded as a memory device. In fact, any
bistable device can be used to store one binary digit (bit). For instance, when the flip-flop has its output set
at OV de, it can be regarded as storing a logic Oand when its output is set at +5 Vde, as storing a logic l. The
flip-flop is often called a latch, since it will hold, or latch, in either stable state.
+Vee -Vee
Output Output
I Output ~t OVdc
+
+5 Vdc
1~ J l -• l -•
State O State 1 State O State 1
(a) Toggle switch (b) Flip-flop
Bistable device~
Basic Idea
One of the easiest ways to construct a flip-flop is to connect two inverters in series as shown in Fig. 8.2a. The
line connecting the output of inverter B (INV B) back to the input of inverter A (INV A) is referred to as the
feedback line.
For the moment, remove the feedback line and consider V1 as the input and V3 as the output as shown in
Fig. 8.2b. There are only two possible signals in a digital system, and in this case we will define L = 0 = 0
V de and H = 1 = +5 V de. If V1 is set to OV de, then V3 will also be OV de. Now, if the feedback line shown in
Fig. 8.2b is reconnected, the ground can be removed from Vi, and V3, will remain at OVdc. This is true since
once the input of INVA is grounded, the output of INV B will go low and can then be used to hold the input
ofINV A low by using the feedback line. This is one stable state-V3 = 0 Vdc.
Conversely, if Vi is +5 Vdc, V3 will also be +5 Vdc as seen in Fig. 8.2c. The feedback line can again be
used to hold Vi at + 5 V de since V3 is also at + 5 Vde. This is then the second stable state- V3 = + 5 V de.
NOR-Gate latch
The basic flip-flop shown in Fig. 8.2a can be improved by replacing the inverters with either NAND or NOR
gates. The additional inputs on these gates provide a convenient means for application of input signals to
Feedback line
(a) Bistable circuit
V1 =OVdc V2 =+5 Vdc V3 = 0 Vdc
(b)
V1 = +5 V de V2 = 0 V de V3 =+5 Vdc
+Vee INVA"X>-------lJNVB
(c)
Bistable circuit
switch the flip-flop from one stable state to the other. Two 2-input NOR gates are connected in Fig. 8.3a to
fom1 a flip-flop. Notice that if the two inputs labeled R and Sare ignored, this circuit will function exactly as
the one shown in Fig. 8.. 2a.
R
5 NORA
S
v;;-J..
v3
.
NORB
NORB
(a) (b)
NOR-gate flip-flop
This circuit is redrawn in a more conventional form in Fig. 8.3b. The flip-flop actually has two outputs,
defined in more general terms as Q and Q. It should be clear that regardless of the value of Q, its complement
is Q. There are two inputs to the flip-flop defined as R and S. The input/output possibilities for this RS flip-
flop are summarized in the truth table in Fig. 8.4. To aid in understanding the operation of this circuit, recall
that an H = I at any input of a NOR gate forces its output to an L = 0.
I. The first input condition in the truth table is R = 0 and S = 0. Since a O at the input of a NOR gate has
no effect on its output, the flip-flop simply remains in its present state; that is, Q remains unchanged.
2. The second input condition R = 0 and S = I forces the output of NOR gate B low. Both inputs to NOR
gate A are now low, and the NOR-gate output must be high. Thus a I at the S input is said to SET the
flip-flop, and it switches to the stable state where Q = 1.
Flip-Flops
3. The third input condition is R = I and S = 0. This R s Q Action

condition forces the output of NOR gate A low, and
0 No change
since both inputs to NOR gate B are now low, the
output must be high. Thus a 1 at the R input is said 0 SET
to RESET the flip-flop-'-and it switches to the stable 0 0 RESET
state where Q = 0 (or Q = 1).
? Forbidden
4. The last input condition in the table, R = 1 and S =
1, is forbidden, as it forces the outputs of both NOR Truth table for a NOR-
gates_!o the low state. In other words, both Q = 0 gate RS flip-flop
and Q = 0 at the same time! But this violates the
basic definition of a flip-flop that requires Q to be the complement of Q, and so it is generally agreed
never to impose this input condition. Incidentally, if this condition is for some reason, imposed and the
next input is R = 0, S = 0 then the resulting state Q depends on propagation delays of two NOR gates.
If delay of gate A is less, i.e. it acts faster, then Q = 1 else it is 0. Such dependence makes the job of a
design engineer difficult, as any replacement of a NOR gate will make Q unpredictable. That's why R
= 1, S = 1 is forbidden and truth table entry is ? .
It is also important to remember that TTL gate inputs are quite noise-sensitive and therefore should
never be left unconnected (floating). Each input must be connected either to the output of a prior
circuit, or if unused, to GND or + Vcc-
Use the pinout diagram for a 54/7427 triple 3-input NOR gate and show how to connect a
simple RS flip-flop.
Solution One possible arrangement is shown in Fig. 8.5. Notice that pins 3 and 4 are tied together, as are pins 10
and 11; thus no input leads are left unconnected and the two gates simply function as 2-input gates. The third NOR
gate is not used. (It can be a spare or can be used elsewhere.)
54/7427
... __ .,
+Vee
2 13
54/7427
The standard logic symbols for an RS flip-flop are shown in Fig. 8.6 along with its truth table. The truth
table is necessary since it describes exactly how the flip-flop functions.
R s Q
n: !l
0 0 Last state
0 I
0 0
Q - ? (Forbidden)
IEEE symbol Logic symbol
(a) (b) Truth table
RS flip-flop
NANO-Gate latch
A slightly different latch can be constructed by using NAND gates as shown in Fig. 8.7. The truth table for
this NAND-gate latch is different from that for the NOR-gate latch. We will call this latch an RS flip-flop.
To understand how this circuit functions, recall that a low on any input to a NAND gate will force its output
high. Thus a low on the S input will set the latch (Q = 1 and Q = 0). A low on the R input will reset it
(Q = 0). If both R and S are high, the flip-flop will rem~n in its previous state. Setting both Rand S low
simultaneously is forbidden since this forces both Q and Q high.
s
:n: IEEE symbol
R s Q
Last state
n
0
0 0
0 0 ? (Forbidden)
R Logic symbol
(a) NAND gate latch (b) (c) Truth table
is flip-flop
Show how to convert the RS flip-flop in Fig. 8.7 into an RS flip-flop.
Solution By placing an inverter at each input as shown in Fig. 8.8, the 2 inputs are now R and S, and the resulting
circuit behaves exactly as the RS flip-flop in Fig. 8.6. A single 54/7400 (quad 2-input NAND gate) is used.
Simple latches as discussed in this section can be constructed from NAND or NOR gates or obtained as medium-
scale integrated circuits (MSI). For instance, the 74LS279 is a quad RS latch. The pinout and truth table for this
circuit are given in Fig. 8.9. Study the truth table carefully, and you will see that the latches behave exactly like the
RS flip-flop discussed above.
Flip-Flops
s Q R s Q
0 0 Last state
R
(a) 54/7400
Q
n
(b) Logic symbol
An RS flip-flop (latch)
0
0 0
? (Forbidden)
(c)
Vee R Q
16
0 0 0 ? Forbidden
0 X
X 0
0 0
? Forbidden
R :S\ S2 R S1 GND X=Don'tcare
(a) Pinout 74S279A (b) Truth table
Quad SET-RESET latch
The NOR-gate flip-flop in Fig. 8.3 is seen to be

an active-high circuit because an H = I at either the S
or R input is required to change the output Q. On the
other hand, the NAND-gate flip-flop in Fig. 8.7 can
be considered an active-low circuit because an L = 0
at either input is required to change Q. The NAND
gates in Fig. 8. 7 can be changed to bubbled-input OR
gates as shown in Fig. 8.10. This circuit is equivalent
to the NAND-gate latch in Fig. 8.7 and functions in Rs flip-flop
exactly the same way. However, the bubbled inputs
more clearly express circuit operation. Bubbled OR-gate equivalent of
Fig. 8.7
8.2 GATED fUP-fLOPS

Two different methods for constructing an RS flip-flop were discussed in Sec. 8.1. The NOR-gate realization
in Fig. 8.3b is an exact equivalent of the NAND-gate realization in Fig. 8.8a, and they both have the exact
same symbol and truth table as given in Fig. 8.6. Both of these RS flip-flops, or latches, are said to be
transE_arent; that is, any change in input infom1ation at R or S is transmitted immediately to the output at Q
and Q according to the truth table.
Clocked RS Flip-Flops
The addition of two AND gates at the R and S inputs as shown in Fig. 8.1 I· will result in a flip-flop that can be
enabled or disabled. When the ENABLE input is low, the AND gate outputs must both be low and changes in
neither R nor Swill have any effect on the flip-flop output Q. The latch is said to be disabled.
When the ENABLE input is high, information at the R and S inputs will be transmitted directly to the
outputs. The latch is said to be enabled. The output will change in response to input changes as long as the
ENABLE is high. When the ENABLE input goes low, the output will retain the information that was present
on the input when the high-to-low transition took place.
In this fashion, it is possible to strobe or clock the flip-flop in order to store information (set it or reset it) at
any time, and then hold the stored information for any desired period oftime. This flip-flop is called a gated
or clocked RS jlip:flop. The proper symbol and truth table are given in Fig. 8.11 b. Notice that there are now
three inputs--R, S, and the ENABLE or CLOCK input, labeled EN. Notice also that the truth-table output is
not simply Q, but Q11 + 1• This is because we must consider two different instants in time: the time before the
ENABLE goes low Q11 and the time just after ENABLE goes low Q11 + 1. When EN= 0, the flip-flop is disabled
and R and Shave no effect; thus the truth table entry for R and Sis X (don't care).
Explain the meaning of Q11 the truth table in Fig. 8.11 b.
EN s R Q11+I
s 0 0 Q11 (no change)
U
o 0 0
ENABLE 0
Q ? (Illegal)
R
0 X X Q11 (no change)
(a) Logic diagram (b) IEEE symbol and truth table
Clocked RS flip-flop
Solution For the nip-flop to operate properly, there must be a PT on the EN input. While EN is high, the information
on R and S causes the latch to set or reset. Then when EN transitions back to low, this infom1ation is retained in the
latch, When this NT occurred, both Rand S inputs ;were low (0), and thus there was no change of state. In other words,
the value of Q at time n + l is the same as it was at time n. Remember that time n occurs just before the NT on EN,
and time n + I, occurs just after the transition.
The logic diagrams shown in Fig. 8. l2a and b illustrate two different methods for realizing a clockRS flip-flop.
Both realizations are widely used in medium- and large-scale integrated circuits, and you will find them easy to
recognize. You might like to examine the .logic diagrams for a 54LS109 or a 54LS74, for instance.
Flip-Flops
s s
EN EN
R R
(a) (b)
Two different realizations for a clocked RS flip-flop
Figure 8.13 shows the input wavefom1s R, S, and EN applied to a clocked RS !lip-flop. Explain
the output waveform Q.
ti f2 f3 14 t5 16 t7 Is
Time - - -
'
-
I
- - - - - - - - - - - -! -! - - -
EN 0l _l-i.----
l
I
~--~h'. . ___
... -
R 0--..,..,-~
:
I
·n.....__ __
I
l
s 0 .____.,__,rL_n....._____
Q l
0
Solution Between t2 and t3 both R and S change states, but since EN is low, the flip-flop is still disabled and Q
remains at I.
Between t3 and 16, the flip-flop will respond to any change in Rand S since EN is high. Thus at t3 Q goes low, and
at t4 it goes back high. No change occurs atts. At t6 the value Q = 1 is latched and no changes in Q occur between ft,
and t1 even though both R and S change.
Between t 7, and ts no change in Q occurs since both Rand Sare low. Initially, the flip-flop is reset (Q 0). At time
t 1 EN goes high; the flip-flop is now enabled, and it is immediately set (Q = l) since R = 0 and S = 1. At time t2 EN
goes low and the flip-flop is disabled and latches in the stable state Q = 1.
Clocked D Flip-Flops
The RS flip-flop has two data inputs, R and S. To store a high bit, you need a high S; to store a low bit, you need
a high R. Generation of two signals to drive a flip-flop is a disadvantage in many applications. Furthermore,
the forbidden condition of both R and S high may occur inadvertently. This has led to the D flip-flop, a circuit
that needs only a single data input.
Figure 8.14 shows a simple way to build a D (Data) flip-flop. This flip-flop is disabled when EN is low, but
is transparent when EN is high. The action of the circuit is straightforward, as follows. When EN is low, both
AND gates are disabled; therefore, D can change value without affecting the value of Q. On the other hand,
when EN is high, both AND gates are enabled. In this case, Q

is forced to equal the value of D. When EN again goes low, Q
retains or stores the last value of D.
There are many ways to design D flip-flops. In general, a D
flip-flop is a bistable circuit whose D input is transferred to the
output when EN is high. Figure 8.15 shows the logic symbols
used for any type of D flip-flop. A D Flip-flop
In this section we're talking about the kind of D flip-flop in
which Q can follow the value of D while EN is high. In other words, if the data bit changes while EN is high,
the last value of D before EN return low is the value of D that is stored. This kind of D flip-flop is often called
aD latch.
Figure 8.15b shows the truth table for a D latch. While (EN) is low, Dis a don't care (X); Q will remain
latched in its last state. When EN is high, Q takes on the last value of D. If D is changing while EN is high,
it is the last value of D that is stored.
=fi-o~ EN D
0 X
Qn+I
Q11 (last state)
[J-Q ~ 0 0
IEEE symbol Logic symbol

(a) D flip-flop logic symbol (b) Truth table
D Flip-flop logic symbol
The idea of data storage is illustrated in Fig. 8.16. D3 D2 Di Do

Four D latches are driven by the same clock signal. Clock
When the clock goes high, input data is loaded into the
flip-flops and appears at the output. Then when the clock DEN DEN DEN DEN
goes low, the output retains the data. For instance, sup-
pose that the data input is
Q Q Q Q Q Q Q Q
D3D2D1Do = 0111
When the clock goes high, this word is loaded into
Q3 Q2 QI Qo
the D latches, resulting in an output of
Q3Q2Q1Qo = 0111 Storing a 4-hit word
After the clock goes low, the output data is retained,
or stored. As long as the clock is low, the D values can change without affecting the Q values.
The 7475 in Fig. 8.17 is a TTL MSI circuit that contains four D latches; it's called a quad bistable latch.
The 7475 is ideal for handling 4-bit nibbles of data. If more than one 7475 is used; words of any length can
be stored.
4. What does an entry X mean ina flip-flop truth table?

5. What could you do to disable the flip-flop in Fig. 8.11?
6. \Vhich flip-flop is easier to use, the RS of the D, as a clocked or gated latch to store data?
Flip-Flops
+Vee
7 6 3 2
D3 D2 D1 Do
4
Vee EN 1
7475
GND EN2
12 13
-
Q3 Q3 Q2 Q2 QI QI Qo Qo
9 8 10 11 15 14 16
(a)
EN D
(b)
4-bit bistable latch: (a) Pinout, (b) Logic diagram (each latch)
8.3 EDGE-TRIGGERED RS f UP-flOPS

The simple latch-type flip-flops presented in Sec. 8.1 are completely transparent; that is, the output Q
immediately follows any change of state at the input (R, S, or D). The gated or clocked RS and D flip-flops in
Sec. 8.2 might be considered semitransparent. That is, the output Q will change state immediately provided
that the EN input is high. If any of these flip-flops are used in a synchronous system, care must be taken to
ensure that all flip-flop inputs change state in synchronism with the clock. One way of resolving the problem
for gated flip-flops is to allow changes in R, S, and D input levels only when EN is low (or require fixed levels
at R, S, and D any time EN is high). At the very least, these are highly inconvenient restrictions, and at the
worst they may in fact be impossible to realize. From the previous chapter, we know that virtually all digital
systems operate in a synchronous mode. Thus the edge-triggeredflip-flop was developed to overcome these
rather severe restrictions.
Positive-Edge-Triggered RS Flip-flops
In Fig. 8.18a, the clock (C) is applied to a positive pulse-forming circuit (discussed in Sec. 7.1). The PTs
developed are then applied to a gated RS flip-flop. The result is a positive-edge-triggered RS flip-flop, with the
IEEE symbol given in Fig. 8.18b. The small triangle inside the symbol (dynamic input indicator) indicates
that Q can change state only with PTs of the clock (C). Each PT of the clock in Fig. 8.18c produces a very
narrow PT that is applied to the AND gates. The AND gates are active only while the PT is high (perhaps
25 ns), and thus Q can change state only during this short time period. In t11is manner Q changes state in
synchronism with the PTs of the clock.
fr:
tl-Q
(a) Logic diagram (b) IEEE symbol
PT ---J'--_,._____.,___...c__...,___
10 t1 t, t3 t4
C s R Q,,+J Action i
I
+ 0 0 Q,, No change I
+ 0 0 RESET
+ 0 SET
t ? Illegal Q----'
(c) Truth table (d) Positive-edge-triggered RS flip-flop
Positive-edge-triggered RS flip-flop
This flip-flop is easy to use in any synchronous system! Another way of expressing its behavior is to say
the flip-flop is transparent only during PTs; it is not transparent for the remainder of the time. In other words,
S and R inputs affect Q only while the positive pulse is high, and they need to be static only during this very
short time.
The truth table for the edge-triggered RS flip-flop is given in Fig. 8.18c. The small vertical arrows under
C ( clock) mean that changes of state (Q) occur according to the R and S levels, but only during PTs of the
clock. Look at the wavefonns in Fig. 8.18d. Note that when Q changes state, it does so in exact synchronism
with PTs of the clock C.
Use the positive-edge-triggered RS flip-flop truth table to explain Q changes of state with time
in Fig. 8.18d.
Solution Here's what happens at each pointin time:

Time t0: S = O, R = 0, no change in Q(Q remains O)
0
Time t1: S = 1, R = O, Q changes from Oto l

Time t2: S = O, R = l, Q resets to 0
Time t3: S = 1,R = 0, Q sets to 1
Time t4: S = O, R = 0, no change in Q(Q remains 1)
Notice that either R or S, or both, are allowed to change state at any time, whether C is high or low. The only time
both R and S must be stable (unchanging) is during the short PTs of the dock.
Negative-Edge-Triggered RS Flip-Flops
The symbol in Fig. 8.19a is for a negative-edge-triggered RS flip-flop. The truth table in Fig. 8.19b shows that
Q changes state according to the R and S inputs, but only during NTs of the clock. On the IEEE symbol, the
small bubble on the clock input ( C) means active-low. This bubble, along with the dynamic input indicator,
n:
C s R Q11+ l Action
t 0 0 Qll No change
t 0 1 0 RESET
Q
t 0 SET
t ')
Illegal
(a) IEEE symbol (b) Truth table
Negative-edge-triggered RS flip-flop
means negative-edge triggering. This flip-flop behaves exactly like the positive-edge-triggered RS flip-flop,
except that changes inoutput Qare synchronized with NTs of the clock (C).
Use the negative-edge-triggered RS flip-flop truth table to explain Q changes of state with
time in Fig. 8.20.
Solution Here's what happens at each point in time: C

Time to: S= 0, R = 0, no change in Q(Q remains 0) PT
Time t1 : S = 1, R = 0, Q changes from Oto 1
to ti t2 t3 t4
Time t2: S = 0, R =l, Q resets to 0 I
I
Time t3: S=l, R =O, Q sets to 1 s

Time t4: S = O, R = O, no change in Q(Q remains 1) R
Notice that either R or S, or both, are allowed to change state at Q
any time, whether C is high or low. The only time both R and S must
be stable (unchanging) is during the short NTs of the clock.
7. What does it mean to say that a flip-flop is transparent?

8. What is positive-edge triggering?
9. How does an RS latch differ from an edge-triggered RS flip-flop?
8.4 EDGE-TRIGGERED D fUP-flOPS
Although the D latch is used for temporary storage in electronic instruments, an even more popular kind of
D flip-flop is used in digital computers and systems. This kind of flip-flop samples the data bit at a unique
point in time.
Figure 8.21 shows a positive pulse-forming circuit at the input of a D latch. The narrow positive pulse
(PT) enables the AND gates for an instant. The effect is to activate the AND gates during the PT of C, which
is equivalent to sampling the value of D for an instant. At this unique point in time, D and its complement
hit the flip-flop inputs, forcing Q to set or reset (unless Q already equals D). Again, this operation is called
edge triggering because the flip-flop responds only when the clock is in transition between its two voltage
states. The triggering in Fig. 8.21 occurs on the positive-going edge of the clock; this is why it's referred to
as positive-edge triggering.
C D Qn+I
0 X Q11 (last state)
t O 0
+
(a) Circuit diagram (c) Truth table
Positive-edge-triggered D flip-flop
The truth table in Fig. 8.21 b summarizes the action of a positive-edge-triggeredD flip-fl.op. When the clock
is low, D is a don't care and Q is latched in its last state. On the leading edge of the clock (PT), designated by
the up arrow, the data bit is loaded into the flip-flop and Q takes on the value of D.
When power is first applied, flip-flops come up in random states. To get some computers started, an
operator h<1s to push a RESET button. This sends a CLEAR or RESET signal to all flip-flops. Also, it's
necessary in some digital systems to preset (synonymous with set) certain flip-flops.
Figure 8.22 shows how to include both functions in a D flip-flop. The edge triggering is the same as
previously described. Depressing the RESET button will set Q to I with the first PT of the clock. Q will
remain high as long as the button is held closed. The first PT of the clock after releasing the button will set
Q according to the D input. Furthermore, the OR gates allow us to slip in a high PRESET or a high CLEAR
when desired. A high PRESET forces Q to equal 1; a high CLEAR resets Q to 0.
+Vee
RESET~ PRESET
CLEAR
PRESET and CLEAR functions
The PRESET and CLEAR are called asynchronous inputs because they activate the flip-flop independently
of the clock. On the other hand, the D input is a synchronous input because it has an effect only with PTs of
the clock.
Figure 8.23a is the IEEE symbol for a positive-edge-triggered D flip-flop. The clock input has a small
triangle to serve as a reminder of edge triggering. When you see this symbol, remember what it means; the D
input is sampled and stored on PTs of the clock.
Sometimes, triggering on NTs of the clock is better suited to the application. In this case, an internal
inverter can complement the clock pulse before it reaches the AND gates. Figure 8.23b is the symbol for a
negative-edge-triggered D flip-flop. The bubble and triangle symboiize the negative-edge triggering.
Flip-Flops
Figure 8.23c is another commercially available D flip-flop (the 54/74175 or 54/74LS 175). Besides having
positive-edge triggering, it has an inverted CLEAR input This means that a low CLR resets it. The 54/74175
has four of these D flip-flops in a single 16-pin dual in-line package (DIP), and it's referred to as a quad D-
type flip-flop with clear.
flQ
¥Q
(a) (b) (c)
Dflip-flopsymbols: (a) Positive-edge-triggered, (b) Negative-edge-triggered,

(c) Positive-edge-triggered with active low clear
The Cinput to the D 'flip~ftop in Fig. 8,2ljs held low. What effect does the D inputhave?
'J!o pre:setthe: flip-flop in Fig. 8.22, what level>is required at the preset input. What is the
resulting state of QJ ·
8S EDGE-lRIGGEREDJK··fUP-fl.OPS
Setting R = S = I with an edge-triggered RS flip-flop forces both Q and Q to the same logic level. This is an
illegal condition, and it is not possible to predict the final state of Q. The JK flip-flop accounts for this illegal
input, and is therefore a more versatile circuit. Among other things, flip-flops can be used to build counters.
Counters can be used to count the number of PTs orNTs of a clock. For purposes of counting, theJK flip-flop
is the ideal element to use. There are many commercially available edge-triggered JK flip-flops. Let's see
how they function.
Positive-Edge-Triggered JK Flip-Flops
In Fig. 8.24, the pulse-forming box changes the clock into a series of positive pulses, and thus this circuit
will be sensitive to PTs of the clock. The basic circuit is identical to the previous positive-edge-triggered RS
flip-flop, with two important additions:
1. The Q output is connected back to the input of the lower AND gate.
2. The Q output is connected back to the input of the upper AND gate.
This cross-coupling from outputs to inputs changes the RS flip-flop into a JK flip-flop. The previous S
input is now labeled J, and the previous R input is labeled K. Here's how it works:
1. When J and Kare both low, both AND gates are disabled. Therefore, clock pulses have no effect. This
first possibility is the initial entry in the truth table. As shown, when J and K are both Os, Q retains its
last value.
2. When J is low and K is high, the upper gate is disabled, so there's no way to set the flip-flop. The only
possibility is reset. When Q is high, the lower gate passes a RESET pulse as soon as the next positive
@) ______________ D_ig_it_al_P_n_·nc_ip_le_s_a_n_d_A_pp_ll_·ca_t,_·on_s_ _ _ _ _ _ _ _ _ _ _ __
C J K Qn+I Action
+ 0 0 Q11 (last state) No change
C t 0 0 RESET
+ 0 SET
t Q11 (toggle) Toggle
(a) One way to implement a JKflip-flop (b) Truth table
A positive-edge-triggered JK flip-flop
clock edge arrives. This forces Q to become low (the second entry in the truth table). Therefore, J = 0
and K = I means that the next PT of the clock resets the flip-flop (unless Q is already reset).
3. When J is high and K is low, the lower gate is disabled, so it's impossible to reset the flip-flop. But you
can set the flip flop as follows. When Q is low, Q is high; therefore, the upper gate passes a SET pulse
on the next positive clock edge. This drives Q into the high state (the third entry in the truth table). As
you can see, J = 1 and K = 0 means that the next PT of the clock sets the flip-flop (unless Q is already
high).
4. When J and Kare both high (notice that this is the forbidden state with an RS flip-flop), it's possible
to set or reset the flip-flop. If Q is high, the lower gate passes a RESET pulse on the next PT. On the
other hand, when Q is low, the upper gate passes a SET pulse on the next PT. Either way, Q changes
to the complement of the last state (see the truth table). Therefore, J = I and K = I mean the flip-flop
will toggle (switch to the opposite state) on the next positive clock edge.
Propagation delay prevents the JK flip-flop from racing (toggling more than once during a positive dock
edge). Here's why. In Fig. 8.24, the outputs change after the PT of the clock. By then, the new Q and Q
values are too late to coincide with the PTs driving the AND gates. For instance, if tP = 20 ns, the outputs
change approximately 20 ns after the leading edge of the clock. If the PTs are narrower than 20. ns, the
returning Q and Q arrive too late to cause false triggering.
Figure 8.25a shows a symbol for a JK flip-flop of any design. When you see this on a schematic diagram,
remember that on the next PT of the clock:
I. J and K low: no change of Q.
2. J low and K high: Q is reset low.
3. J high and K low: Q is set high.
4. J and K both high: Q toggles to opposite state.
You can include OR gates in the design to accommodate PRESET and CLEAR as was done earlier. Figure
8.25b gives the symbol for a JK flip-flop with PR and CLR. Notice that it is negative-edge-triggered and
requires a low PR to set it or a low CLR to reset it.
£1-o
¥
Q Q
.
=E_J--Q Q Q
(a) Basic symbol (b) 74LS76A (c) 74LS73A
JK flip-flop symbols
Flip-Flops
Figure 8.25c is another commercially available JK flip-flop. It is negative-edge-triggered and requires a low
CLR to reset it. The output Q reacts immediately to a PR or CLR signal. Both PR and CLR are asynchronous,
and they override all other input signals.
Toggle flip-flop, popularly known as T flip-flop has following input-output relation. When
input T = 0, the output Q does not change its state. For T = 1, the output Q toggles its value.
Derive T flip-flop from JK flip-flop.
Solution From Fig. 8.24b we find for input J = K = 0, tbe output Qn+ 1 = Q,,, i.e. output does not change its state.
And forJ=K= l, tbe output Qn+l = Q,;, i.e. output toggles. Thus, ifwe tieJandKinputs of JKflip-flop together and
make a common input T=J=K, the resulting circuit will behave as.Tflip-fl.op.
12. What is the primary difference between aJKand an.RS flip-flop?

13. How could you change an edge-triggered RS flip-flop into an edge-triggered JK flip-flop?
8.6 fUP~fLOP TIMING
Diodes and transistors cannot switch states immediately. It always takes a small amount of time to tum a
diode on or off. Likewise, it takes time for a transistor to switch from saturation to cutoff, and vice versa. For
bipolar diodes and transistors, the switching time is in the nanosecond region.
Switching time is the main cause of propagation delay, designated fp. This represents the amount of time
it takes for the output of a gate or flip-flop to change states after the input changes. For instance, if the data
sheet of an edge-triggered D flip-flop lists Ip= 10 ns, it takes about 10 ns for Q to change states after D has
been sampled by the clock edge. This propagation delay time has been used to construct the "pulse-fom1ing
circuit" used with edge-triggered flip-flops. When flip-flops are used to construct counters, the propagation
delay is often small enough to be ignored.
Stray capacitance at the D input (plus other factors) makes it necessary for data bit D to be at the input
before the clock edge arrives. The setup time fsetup is the minimum amount of time that the data bit must be
present before the clock edge hits. For instance, if a D flip-flop has a setup time of 15 ns, the data bit to be
stored must be at the D input at least 15 ns before the clock edge arrives; otherwise, the manufacturer does
not guarantee correct sampling and storing.
Furthermore, data bit D has to be held long enough for the internal transistors to switch states. Only after
the transition is assured can we allow data bit D to change. Hold time thold is the minimum amount of time
that data bit D must be present after the PT of the clock. For example, if tsetup = 15 ns and thold = 5 ns, the
data bit has to be at the D input at least 15 ns before the clock edge arrives and held at least 5 ns after the
clock PT.
Typical waveforms for setting a 1 in a positive-edge-triggered flip-flop are shown in Fig. 8.26.
Discuss the timing.
Solution The lower line in Fig. 8.26 is tbe time line with..critical times marked on it. Prior to t 1, the data can be a 1
or a 0, or can be changing. This is shown by drawing lines for both high and low levels on D. From time ti to t2, the
<l11ta .Iin~D·mustbe lield.steady {in this case a 1). This is1the setuptime tsetup·· Data is shifted into the flip:-flop· at time
t2 but aoes not appear at Q untiltime The time from t2 to t3 is the propagation time Ip. In order to guarantee proper
operation, the data line must be held steady from time t2 until t4; this is to
states-shown by the doubll.1 lines.
We have seen how edge triggering of flip-flops can be achieved by pulse forming circuit (Section 7.1). This
requires application of a very narrow pulse which is generated using differential propagation delays of two
signal flow paths while the flip-flops themselves are level triggered. An alternate way of achieving edge
triggering is to implement a kind of lock out of the input so that it is not able to enforce a change atoutput
which itself is level triggered. This is to say that the effect of change in input is allowed only at the edge and
not after the edge. Let us see how this is possible by implementing a positive edge triggered D type flip-flop.
This requires three NAND latches as shown in Fig. 8.27 with one NAND gate (number 3) having three inputs
and the rest are all two input NAND gates. Note that for a NAND gate output to be 0, all the inputs must be
at 1, else the output is 1. The output latch behaves like an SR flip flop where no change in output occurs if S
=1,R=l.
Now, if the clock input is held at O then irrespective of what is present at D input, the NAND logic makes
both S = 1, R = 1 and thus there could be no change in the output If Clock = 1 then SR can always change if
other inputs ofNAND gates 2 and 3 change and thus the output is essentially level triggered. We will now
explain how input lock out makes the circuit as a whole a positive edge triggered circuit
Consider the case when Clock= 0 and D = 0 (Fig. 8.27a). Since, for a NAND gate, 0 is the forcing input,
the intermediate outputs are S = 1, R = 1 arid A = 1 which make B = 0. Now, clock makes a transition from 0
~ I. D = 0 forces A = 1 and B = 0 keeps R = 1. Thus, after this transition, S = 0, R = l, A = 1 and B = 0. This
makes Q = 0 irrespective of the previous state and one can see that the value at D, i.e. 0 is transferred to Q
after the clock trigger. Next, we see if at Clock = 1, D is changed, then whether Q is changed. This is shown
in Fig. 8.27b as a follow-up of Fig. 8.27a. Before D makes a transition Clock= 1, D = 0 and intermediate
outputs S = 0, R = I, A = I, B = 0 and Q = 0. When D goes to 1, 4 111 NAND gate is only directly affected as D
is not connected elsewhere. However, the output A of this gate does not change as it is kept held at 1 by the
Flip-Flops
other input coming from S = 0. Thus, S = 0, R = 1, A = 1, B = 0 and Q = 0. This is the lock out of input we
were referring to. Note that clock going from 1 to O does not change Q as that transition makes S = 1, R = I.
Next, consider the case when Clock= 0 and D = l. This is shown in Fig. 8.27c. S = 1, D = I make A= 0
which in turn makes B = 1. Now, clock makes a transition from O-t 1. A = 0 maintains S = 1. Both the inputs
of 2nd NAND gate being 1, R = 0. S = 1, R = 0 make Q = 1 irrespective of previous state and thus after positive
clock trigger, the logic value of D arrives at Q for D = l case, too. With Clock= 1, if input D changes from
1 to 0, will the output Q change? This 4th possibility is shown in Fig. 8.27d. D = 0 makes A= 1 but R = 0
maintains B = 1 and S = 1. Thus, after the transition, SR remains at where it was and input D remaines locked
out, i.e. unable to effect any change in the output at Clock = 1.
Q Q
Clock Clock
0-; I I
Q Q
Q Q
Clock Clock
0-; I I
Q
(c)
Positive edge triggering of D type flip-flop through input lock out

8.8 JK MASTER-SLAVE. FLIP-FLOPS
Figure 8.28 shows one way to build a JK master-slave flip-flop. Here's how it works.
1. To begin with, the master is positive-level-triggered
and the slave is negative-level-triggered. Therefore, the
C--<11>---i
master responds to its J and K inputs before the slave.
If J = 1 and K = 0, the master sets on the positive clock K Qt---+---<K Q
transition. The high Q output of the master drives the J
input of the slave, so on the negative clock transition,
the slave sets, copying the action of the master. Master-slave flip-flop
2. If J = 0 and K = I, the master resets on the PT of the
clock. The high Q output of the master goes to the K input of the slave. Therefore, the NT of the clock
forces the slave to reset. Again, the slave has copied the master.
3. If the master's J and K inputs are both high, it toggles on the PT of the clock and the slave then toggles
on the clock NT. Regardless of what the master does, therefore, the slave copies it: if the master sets,
the slave sets; if the master resets, the slave resets.
4. If J = K = 0, the flip-flop is disabled and Q remains unchanged.
The symbol for a 7476 master-slave flip-flop is PR
shown in Fig. 8.29. Either it can be preset to Q = H
by taking PR low, or it can be reset to Q = L by taking J "l Q
CLR low. These two inputs take precedence over all C J K Q,,+1 Action
other signals! C JL L L No change
QI/
There is something different however. First of all, Q Sl L H L RESET
notice that the clock ( C) is not edge-triggered. The TL H L H SET
master does in fact change state when C goes high. .TL H H Q/1 Toggle
CLR
However, while the clock is high, any change in J or
K will immediately affect the master flip-flop. In other (a) Symbol (b) Trnth table
words, the master is transparent while the clock is
7476 JK master flip-flop.
high, and thus J and K must be static during this time.
The truth table in Fig. 8.29b reveals this action by means of the pulse symbol CnJ.
Second, the symbol l appearing next to the Q and the Q outputs is the IEEE designation for a postponed
output. In this case, it means Q does not change state until the clock makes an NT. In other words, the
contents of the master are shifting into the slave on the clock NT, and at this time Q changes state.
To summarize: The master is set according to J and K while the clock is high; the contents of the master
are then shifted into the slave (Q changes state) when the clock goes low. This particular flip-flop might be
referred to as pulse-triggered, to distinguish it from the edge-triggered flip-flops previously discussed.
There are numerous pulse-triggered master-slave flip-flops in use today. However, because edge-triggered
flip-flops have overcome the restriction of holding J and K static when the clock is high, most new designs
incorporate edge-triggered devices. Some of the more popular pulse-triggered flip-flops you might encounter
include the 7473, 7476, and 7478. Their more modem, edge-triggered counterparts include the 74LS73A, the
74LS76A, and the 74LS78A.
The JK master-slave flip-flop in Fig. 8.29 has its J and K inputs tied to+ Vee and a series
of pulses (actually a square wave) are applied to its C input. Describe the waveform at Q.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _F_lip_-F_lo_p_s _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~
Solution Since J=K = l, the flip-flop simply toggles each time the clock
goes low. The waveaform at Q has a period twice that of the C \vaveform. In
otherwords,.the frequency of Q is only one-half that of C.Thiscircuit acts
as a frequency dlvider~the.ouiputfrequency is equal to th.e input frequency
divided by 2. Note that Q changes state on NTs of the clock. The waveforms
are given in Fig. 8.30.
14. What is the main. difference between an edge-triggered and a pulse-triggered JK flip-flop?
15. Explain the operation ofthe master-slave flip-flop in Fig, 8.29.
8.9 SWITCH CONTACT BOUNCE CIRCUITS
In nearly every digital system there will be occasion to use mechanical contacts for the purpose of conveying
an electrical signal; examples of this are the switches used 011 the keyboard of a computer system. In each
case, the intent is to apply a high logic level (usually +5 Vdc) or a low logic level (0 Vdc). The single-pole-
single-throw (SPST) switch shown in Fig. 8.3 la is one such example. When the switch is open, the voltage at
point A is +5 V de; when the switch is closed, the voltage at paint A is OVde. Ideally, the voltage wavefonn at
A should appear as shown in Fig. 8.31 b as the switch is moved from open to closed, or vice versa.
In actuality, the waveform at point A will appear more or less as shown in Fig. 8.31 c, as the result of a
phenomenon known as contact bounce. Any mechanical switching device consists of a moving contact ann
restrained by some sort of a spring system. As a result, when the ann is moved from one stable position to
the other, the arm bounces, much as a hard ball bounces when dropped on a hard surface. The number of
bounces that occur and the period of the bounce differ for each switching device. Notice carefully that in
this particular instance, even though actual physical contact bounce occurs each time the switch is opened or
closed, contact bounce appears in the voltage level at point A only when the switch is closed.
+5 Vdc
Switch position Open~
Closed
J
Voltage at A +sv
0
~J ~
R
(b) Ideal voltage at A
A
Open~
Switch position
SPST \
switch i Closed ~j -I I- Bounce
Voltage at A +5VwUL~
0 -II- -II-
Bounce Bounce
(a) (c) Voltage at A showing contact bounce
If the voltage at point A is applied to the input of a TTL circuit, the circuit will respond properly when
the switch is opened, since no contact bounce occurs. However, when the switch is closed, the circuit will
respond as if multiple signals were applied, rather than the single-switch closure intended-the undesired
result of mechanical contact bounce. There is a need here for some sort of electronic circuit to eliminate the
contact bounce problem.
A Simple RS latch Debounce Circuit

The RS latch in Fig. 8.32 will remove any contact bounce due
to the switch. The output (Q) is used to generate the desired
switch signal.
When the switch is moved to position H, R = 0 and S = 1.
Bouncing occurs at the S input due to the switch. The flip-flop
"sees" this as a series of high and low inputs, settling with a
high level. The flip-flop will immediately be set with Q = 1
at the first high level on S. When the switch bounces, losing (a) Switch contact bounce eliminator
contact, the input signals are R = S = 0, therefore the flip-flop
remains set (Q = 1). When the switch regains contact, R = 0 Switch H
position L_r----i__
and S = 1; this causes an attempt to again set the flip-flop. But
since the flip-flop is already set, no changes occur at Q. The ~ _illl[fswitch1J .
result is that the flip-flop responds to the first, and only to the ~
first, high level at its S input, resulting in a "clean" low-to-high Q_r----i__
signal at its output (Q).
When the switch is moved to position L, S = 0 and R = 1. (b) Switch bounce
Bouncing occurs at the R input due to the switch. Again, the Debounce circuit
flip-flop "sees" this as a series of high and low inputs. It simply
responds to the.first high level, and ignores all following transitions. The result is a "clean" high-to-low signal
at the flip-flop output. The waveforms in Fig. 8.32b illustrate the behavior.
16. Whatis switchcontact bounce?

17. Why is switch contact bounce important to account for in a digital system?
8.10 VARIOUS REPRESENTATIONS Of fUP-flOPS

There are various ways a flip-flop can be represented, each one suitable for certain application. Considering
basic flip-flop truth table as starting point, this section derives these representations.
Characteristic Equations of Flip-flops

The characteristic equations of flip-flops are useful in analyzing circuits made of them. Here, next output
Q11+ 1 is expressed as a function of present output Q11 and input to flip-flops. Karnaugh Map can be used to get
the optimized expression and truth table of each flip-flop is mapped into it. This is shown in Fig. 8.33 for all
types of flip-flops. The logic equations are presented in SOP form by forming largest group of 1's for each
Flip-Flops
SR D JK T
Q/1 00 0l l l I0 Q/1 0 QI/ 00 0l l I 10 Q/1 0 l
0 0 0 X 1 0 0 0 0 0 I1 I I 0 0 OJ
l ::1J 0 X 11- 0 I ::1J 0 0 rr:: 1 OJ 0
(a) Q11 + 1 =S+ R Q11 (b) Q11 + 1 =D (c) Qn+ 1 =JQ" + K Q11 (d) Q11 + 1 = TQ11 + TQ11
Characteristic equations of (a) SR flip-flop, (b) D flip-flop, (c) JK flip-

flop, (d) T flip-flop
flip-flop. For SR flip-flop, since S = R = I input is not allowed we have don't care states in corresponding
locations in Karnaugh Map. This means, it does not matter if Q11+1 is O or 1 if SR= 11 as such a combination
at input side will never arise.
The equation for SR flip-flop and all others thus can be represented in a summarized form as
SR flip-flop: Q11 +1 =S+R'Q11
JK flip-flop: Q11 + J = J Q11' + K' Q11
D flip-flop: Q11 + 1 = D
Tflip-flop: Q11 +1 = TQ,; + T'Q 11
Flip-Flops as Finite State Machine

In a sequential logic circuit the value of all the memory elements at a given time define the state of that circuit
at that time. Finite State Machine (FSM) concept offers a better alternative to truth table in understanding
progress of sequential logic with time. For a complex circuit a truth table is difficult to read as its size
becomes too large. In FSM, functional behavior of the circuit is explained using finite number of states. State
transition diagram is a very convenient tool to describe an FSM. In Fig. 8.34 all the flip-flops are represented
as finite state machine through their state transition diagrams.
10 1
i ~~oo
0 1 \._,,.~ I 0 ~~I
0 I 0
(a) SR flip-flop (b) D flip-flop
I0
I 1 1
{i~oo
01 ~ 1 0
01
r~o I
11
( c) JK flip-flop (d) T flip-fl op
State transition diagram of (a) SR flip-flop, (b) D flip-flop, (c) JK flip-

flop, (d) T flip-flop
Let us see how state transition diagram for SR flip-flop is developed from its truth table or characteristic
equation. Each flip-flop can be at either ofO or I state defined by its stored value at any given time. Application
of input may change the stored value, i.e. state of the flip-flop. This is shown by directional arrow and the
corresponding input is written alongside. If SR flip-flop stores 0, then for SR = 00 or OI the stored value does
not change. For SR= l 0, flip-flop output changes to 1. Note that, SR= 11 is not allowed in SR flip-flop. When
SR flip-flop stores 1, application of SR= 00 or 10 does not change its value and only when SR= 01, output
changes to 0. State transitions on application of all possible combination of inputs at every state are shown in
Fig. 8.34(a) for SR flip-flop. The state transition diagrams are developed in a similar way for D, JK, Tflip-
flops and are shown in Figs. 8.34 (b ), (c ), (d) respectively. We see, the timing relation implicit in flip-flop truth
tables are brought to the forefront by FSM concept and state transition diagram.
Flip-Flop Excitation Table

In synthesis or design problem excitation tables are very useful and its importance is analogous to that of truth
table in analysis problem. Excitation table of a flip-flop is looking at its truth table in a reverse way. Here,
flip-flop input is presented as a dependent function of transition Q11 ~Q11 + 1 and comes later in the table. This
is derived from flip-flop truth table or characteristic
equation but more directly from its state transition Q"-+ Q11+I s R J K D T
diagram. Figure 8.35 gives a summary presentation 0 0 0 X 0 X 0 0
of excitation tables of all the flip-flops. 0 1 l 0 I X I I
I 0 0 l X 1 0 1
From Fig. 8.34(a), one can see if present state l I X 0 X 0 l 0
is O application of SR = Ox does not alter its value
where 'x' denotes don't care condition in R input. Excitation table of flip-flops
State O to 1 transition occurs when SR = 10 is pres-
ent at the input side while state 1 to O transition occurs if SR = 01. Present state l is maintained if SR = 0,
i.e. SR = 00 or SR = 01. This is shown in Fig. 8.35 along SR column. Excitation table for other flip-flops are
obtained in a similar way.
Note that, JK flip-flop has maximum number of don't care 'x' conditions and D flip-flop input simply
follows the value to which transition is made.
18. What is characteristic equation of a flip-flop?

19. What is a Finite State Machine?
20. How is excitation table different from flip-flop truth table?
A fictitious flip-flop with two inputs A and B functions like this. For AB= 00 and 11 the output
becomes O and 1 respectively. For AB= 01, flip-flop retains previous output while output
complements for AB= IO. Draw the truth table and excitation table of this flip-flop.
Solution The truth table and corresponding excitation tables are presented in Figs. 8.36(a) and (b) respectively'.
For 0-t O transition we see 4B need to be 00 or O1. Hence, we write AB = Ox in that place and similarly for other
transitions.
A B Qn+I Q11'""""7Qn+l A B
0 0 0 0'"""70 0 X
0 1 Qn 0 '"""71 X
1 0 Qn I '"""7 0 X 0
l > 1 1 1 X
(a) (b)
Solution for example 8~10: (a) Truth table, (b) Excitation table
8.11 ANALYSIS Of SEQUENTIAL CIRCUITS
A sequential logic circuit contains flip-flops as memory elements and may also contain logic gates as
combinatorial circuit elements. Analysis of a circuit helps to explain its performance. We may use truth tables
of each building block or corresponding equations for this purpose. In this section, we look at important
issues in an analysis problem through an example. In subsequent chapters, more analysis examples will be
taken up.
Consider, the sequential circuit shown in Fig. 8.37. It has only input CLK in the fonn of fixed
frequency binary pulses that triggers both the flip-flops. An output Xis generated from flip-
flop outputs as shown. Analysis of this circuit will give how flip-flop values (or states) and
more importantly output X change with input CLK. The steps are as follows.
CLK B
A sequential logic circuit for analysis purpose
Note from the circuit diagram flip-flop input relations: SA= A,;, RA= An and Ss AnB,;, Rs= A11Bn.
Next, using characteristic equation of SR flip-flop (Section 8.9) we can write,
for flip-flop A
An+I =SA+RAAn
=A,;+ A,;An (Substituting SA= A,; and RA= An)
=A,;
and for flip-flop B
Bn+l =Ss+RifB,,
= AnB,; + (A 11 B 11 )'B11 (Substituting Ss = A 11 B,; and Rs= AnB11)
= A,,B,; +(A,;+ B,;)Bn (Following De Morgan's Theorem)
=AnB; + A,;B11
=A11EBB11
Now the output from the given circuit, X,, = A 11B11
The equation shows that present (given by time index n) values of A and B flip-flop, also
called states of the sequential circuit determine present output and next (given by time index
n + 1) flip-flop values or state of the circuit. Thus, if present state is B11 = 0, A11 = 0 then present output X,,
= AnBn = 0.0 = 0 and at the end of first clock cycle we get next state is B11 +1 = 0 EB O = 0, An+ 1 = O' = 1. In
next clock cycle present state is nothing but next state of previous cycle or Bn = 0, An= 1. The output now
is generated asXn = 0.1 = 0 and next state is determined as B11 + 1 = 0 EB 1 = 1, A 11 + 1 = 1' = 0. Continuing this
exercise we arrive at state analysis table also called state table as shown in Table 8.1.
State Analysis Table for Analysis Example
Present Present Input Next State Present

State Output
B,, A,, Ss =A,,B,; Rs=A,,B,, S,t =A,; Rs=A,, Bn+I =An@B11 An+I =A,; X=AnBn
0 0 0 0 1 0 0 1 0
0 1 1 0 0 l 1 0 0
1 0 0 0 1 0 1 1 0
1 I 0 1 0 I 0 0 1
0 0 0 0 1 0 0 I 0
0 I ... ... . .. Repeats
We find that the states as well as output of the above

circuit repeat after every four clocking periods and at
every fourth clock period the output remains I for one
clock period. The circuit thus behaves like a counter that
counts number of clock pulses that has arrived at its in-
put and signals when there is a count of four. A pictorial
presentation of the performance of the circuit showing
state transitions with each clock is shown in Fig. 8.38.
The values within the circle follow syntax: B,,A,/X,1• State transition diagram
Flip-flop outputs defining current state is shown to the of the sequential circuit
left of '/' and current output appears at right. Such cir- given in Fig'. 8.37
cuit where output is directly derived from current state
only and not from current inputs are called Moore circuit. If current inputs are also used in output forming
logic it is called Mealy circuit. More about these are discussed in Chapter 11. Often, a state transition diagram
of a sequential circuit serves better than the word description and is presented as final output of an analysis
exercise.
Analysis of a sequential circuit can also be done through timing diagram where all the input, output and
if necessary intermediate variables are plotted against some reference signal say, clock input. The timing
diagram obtained by analyzing circuit of Fig. 8.37 is shown in Fig. 8.39. The method followed is given
next.
Flip-Flops
CLK
SB BA
Rs=AB
SA=A
R.A =A
I I I I
X=AB
---'-----'-----'n'--:-'---'-----'n·~_
Timing diagram of the circuit given in Fig. 8.36
We start with an initial state B = 0, A= 0 and note that this state can only change when negative edge of the
clock comes. The next state values of Band A are dependent on current inputs Ss, Rs and SA, RA at the time of
clock trigger. As done before, these input values are derived following relations given in the circuit diagram,
i.e. SA =A',RA =A andSs=AB',Rs=As (suffix n can be ignored). For B =O,A =Owe getS,4 = 1,RA = O,Ss
= 0 and Rs = 1 and these values can change only when B and A change, i.e. in next clock cycle. Thus above
values of SR inputs of two flip-flops continue till next negative edge of the clock. ForSs = 0 and Rs= 1, at the
negative edge of clock B remains at O (from truth table of SR flip-flop). Similarly for SA = I, RA = 0 flip-flop
A moves to 1. Thus we get B and A value of next clock cycle. Following above relation we now calculate SR
input values of these flip-flops as SA= 0, RA= I, Ss = 1 and Rs= 0 and these again remain constant up to
next negative edge of the clock Here as Ss = I and Rs= 0, B moves to 1 and as SA= 0, RA= 1, A moves to
0 and remains constant till next clock trigger. SR inputs are again calculated and this process is continued for
subsequent clock cycles. In each of these clock cycles we calculate and draw the output following relation
X= AB. The timing diagram shows the states get repeated as 00~01 ~ IO~ 11 ~00, and so on. Repetition
occurs after every fourth clock cycle. The outputX= AB, accordingly shows repetition as O~O~O~ 1 ~O
and remains high for one clock period every time flip-flop output becomes B = 1, A= l.
A detailed analysis of various configurations of counter and its timing diagram will be presented in Chapter
10.
2 L What is analysis ofsequential citcuit?

22. Which oftruth table and excitation table is useful for analysis of a sequential circuit?
Explain the function of the circuit shown in Fig. 8.40 through state transition diagram.
Solution The D flip-flopJnput can be written asD == XEBQ11 and output Y == XQ,;. Figure 8.4 l(a) sh?ws the state 1.able
and Fig, SAI (b) its.state transition diagrnm. Note that, the circuit follows Mealy model and at any given state output is
generated from input to that. state. Thus,

outputs are shown by the side of the in-
put in state transition diagram to right of
the input and is separated by a '/' sign.
On careful observation, we can see
something interesting in above circuit. If
we ignore Y, then the D flip-flop block y
with Ex-OR gate as connected behaves
like a Tflip-flop where T= X.
State· transition diagram of Example 8.11
Q/1 X D=XEB Q11 Qn+l Y=XQ 11

1/1
0 0 0 0 0
0 l l I I 0/0~0/0
I 0 l l 0
1/0
l 1 0 0 0
(a) (b)
Solution to Example 8.11: (a) State table, (b) State transition diagram
8.12 CONVERSION OF FUP.. fl.OPS:

A SYNTHESIS EXAMPLE
Knowledge about how flip-flop of one type can be converted to another may be useful on various count. Say,
when we have designed the circuit with one type and for implementation we get a different type from the
store or the market. Redesign of the problem with available type of flip-flops may take considerable amount
of time if the circuit is very complex. Instead one can convert the available type using few basic gate to the
type in which design is done and implement the existing design.
Conversion of JK to SR, D, T is fairly straightforward as we see from their respective truth tables or
characteristic equations. For example, one need not do anything extra to replace SR flip-flop from a design
if SR flip-flop is not available, by JK flip-flop. This is because their truth tables are same except for input
combination 11, which in design with SR flip-flop is taken care of not to appear in the input side. Hence,
replacing SR with JK flip-flop does not pose any problem. However, the reverse is not true. In design with
JK flip-flop there remains possibility of 11 appearing at input side and that combination of input is forbidden
for SR flip-flop. Again, comparing truth tables or characteristic equations of JK and D flip-flops we see that
putting an inverter from .J to K (K = J') we get D flip-flop from JK flip-flop where J = D. T flip-flop can be
obtained from JK flip-flop by making T = J = K.
We show here how to convert an SR flip-flop to a JK flip-flop through a systematic approach, as a general
methodology for synthesis or design of sequential logic circuit. A detailed study on various design problems
and related issues are presented in Chapter 11.
In step one of this method, we look into JK flip-flop truth table and specifically note, Qn~Qn+ 1 transitions
for a given combination of inputs JK and present state Q11 • Since the synthesis element is SR flip-flop we shall
Flip-Flops
refer to its excitation table to identify SR input combination for a required Q11 -,Q11+ 1 transition. Table 8.2
shows truth table of JK flip-flop as well as necessary SR inputs for Q,,-,Q,,+ 1transitions. Such tables are also
known as state synthesis table.
State Synthesis Table for SR to JK Flip-Flop Conversion
J,, Kn Qn ~Qn+I s,, Rn

0 0 0 0 0 X
0 0 l 1 X 0
0 1 0 0 0 X
0 l l 0 0 l
1 0 0 1 l 0
l 0 1 1 X 0
I l 0 1 l 0
I I 1 0 0 l
The next step is to write SR inputs as a function of JK inputs and present state Qn- Kamaugh Map derived
from Table 8.2 for SR inputs are shown in Fig. 8.42 along with their design equations.
JK
II 11
JK
11 11
Q,, 00 0l 11 10 Qn 00 01 11 10
0 0 0 11 1I 0 X X 0 0
l X 0 0 X 1 0 11 1I 0
Sn =J,, Qn Rn =K11Q11
Karnaugh Map and Design equations for SR inputs
The final synthesized circuit devel- ~-----------------------------,

I I
I I
oped from these equations, are shown I
I
I
I
in Fig. 8.43. The functional block with- : s Q : Q

in dotted lines made up of an SR flip- J I
I
I
flop and two AND gates, behave like a CLK--i------<:l I
I
JK flip-flop. I
I
K--i----1 I
Thus conversion between flip-flops, R Q 1--+-'--:- Q
in simple cases can be done comparing I
I
I
their respective truth tables. For other I I
cases, the steps shown above can be '-----------------------------'

followed. Refer to Example 8.13 and Conversion of SR flip-flop to JK flip-flop.
Problems 8.30 to 8.32.
23. Why flip-flop conversion is needed?

24. Whafis the basic difference between analysis and synthesis steps?
25. What is the difference between state analysis table and state synthesis table?
Show how a D flip-flop can be converted to SR flip-flop.
Solution Note characteristic equation of two flip-flops.

For SR flip-flop: Q11 +1 ""'S +R'Q11 and for D flip-flop: Q~+i ~D
Thus with D ""S+ R'Q11 we get circuit shown in Fig. 8.44 which behaves like an SR flip-flop but made from a D
flip-flop and basic logic gates: Method as shown in Section 8J 1 also gives same solution.
r----------------------------------
1
s-:'-------4---.._,_ D
l
I
I
I
CLK-----~1•---~>
R-i---o-,
I
I
I
:_ _________________________________
J I
~
Solution for_ Example 8.11. _D flip-flop converted to SR flip-flop
8.13 HDLIMPlEMENTATION Of fllP-fLOP
We continue our discussions on HDL from earlier chapters and in this section we look at how to represent
a flip-flop using Verilog HDL. As discussed before, behavioral model is preferred for sequential circuit and
always keyword is used in all these circuits. Since, sequential logic design also includes combinatorial design
at some places we may use dataflow model for that. To start with let us see how a D latch (Fig. 8.15) and SR
latch (Fig. 8.11) are expressed in HDL. We have used characteristic equation corresponding flip-flops given
in Section 8.9. The explanation of the codes are simple. IfEN = 1, output changes according to equation and
if EN = 0, output does not change, i.e. remains latched to previous value.
modu1e {D,EN, Q); module SRLatch(S,R,EN,Q);

input S,R,EN;
Q; output Q;
reg Q;
always @ _( EN or D) always@ (EN or Sor R)
if (EN} Q=D; if (EN) I (-R&Q) ;
//from characteristic equation
I I from characteristic equation
endmodule endmodu1e
Next we discuss how to describe a clocked flip-flop. The following Verilog code describes a D flip-flop
with positive edge trigger, negative edge trigger and positive edge trigger with reset (CLR) given in Figs. 8.23
(a), (b) and (c) respectively. Here, the CLR input is active low, i.e. it clears the output (Q = 0) when CLR is 0.
We use keywords posedge and negedge for this. With keyword always it ensures execution of always block
once every clock cycle at corresponding edge. For asynchronous CLR we use a particular nomenclature of
Verilog HDL. The always sensitivity list (after@) contains any number of edge statements including clock
_ _ _ _ _ _ _ _ _ _ _ _F_lip_-F_lop_s _ _ _ _ _ _ _ _ _ _ _ ( ; )
and asynchronous inputs. The always block puts all asynchronous conditions in the beginning through else
or else if and the last else statement responds to clock transition.
module DFFpos(D,C,Q); module DFFneg(D,C,Q); module DFFpos_clr(D,C,CLR,Q);

input D,C; //C is clock input D,C; //C is clock input D,C,CLR; //C is clock
output Q; output Q; output Q;
reg Q; reg Q; reg Q;
always@ (posedge C) always@ (negedge Cl always@ (posedgeCornegedgeCLR)
Q=D; Q=D; if (-CLR) Q=l'bO;
endmodule endmodule /IQ stores 1 binary bit 0
else Q=D;
endmodule
Write a Verilog code that converts an D flip-flop to an SR flip-flop following Fig. 8.43 of
Section 8.11.
Solution The code is given as follows. See how combinatorial logic part of the circuit is expressed by assign
statement
module SRFFneg(S,R,C,Q);
input S,R,C; //C is clock
output Q;
wire DSR;
assign DSR = SI (-R&Q); //combinatorial logic shown in flg.8.45
DFFneg Dl(DSR,C,Q); //instantiates negative edge triggered D FF
endmodule
module DFFneg(D,C,Q);
input D,C; //C is clock
output Q;
reg Q;
always@ (negedge C)
Q=D;
endmodule
Explain the use of following Verilog code in test bench preparation of sequential logic
circuit.
Initial
begin
elk= l'bO;
repeat (20)
#50 elk= -elk;
end
Solution The keyword initial says following code is run for once. The variable 'elk' is of 1 binary digit and is
initialized with Oat time = 0, Keyword repeat ensures repetition of following statement 20 times, In that statement,
variable elk is comple111.ented after a delay of 50 ns. Thus, elk toggles between 1 and O every 50 ns and for 20times
generating l O cycles of 50 + 50 = l 00 ns duration each. ID a test bench, clkean be fed asClock input to simulate a
sequential circuit for a finite duration. The number of clock pulse generated can be changed by changing number after
repeat and clock period can be changed by changing delay after# sign.
The Verilog code given in first column generates output given in second column and
corresponding timing waveform is given next. Draw the digital circuit diagram from Verilog
code and explain the output.
module CKT_XYZ(Q,Q_BAR,D,CLK);
output Q,Q_BAR;
input D,CLK;
wire X,Y;
nand Ul (X,D,CLK) 0 CLK 0, D 1, Q = X
nand 02 (Y,X,CLK) 10 CLK 0, D 0, Q = X
nand U3 (Q,Q_BAR,X); 20 CLK 1, D 0, Q 0
nand U4 (Q_BAR,Q,Y); 40 CLK 0, D 1, Q 0
endmodule 60 CLK 1, D 1, Q 1
module TestCKT XYZ; 70 CLK 1, D 0, Q 0

wire Q, • Q_BAR; 80 CLK 0, D 0, Q 0
reg D, CLK; 100 CLK 1, D 1, Q 1
CKT XYZ xyz(Q, Q_BAR, D, CLK); 120 CLK 0, D 1, Q 1
initial
begin
$monitor($time, "CLK %b, D= %b,
Q= %b\nu,CLK,D,Q);
D=l;CLK=O;
#10 D = 0; #30 D = 1; #30 D = 0;
#30 D = 1;
#40 $finish; /* the module will terminate after
140ns*/
end
always
#20 CLK -CLK;
endmodule
ions I
;20ns
I I
:40ns
I I
i60ns
I I ' I I120ns i r i
i
!
TestCKT XYZ.Q ( \ ·-
TestCKT XYZ.Q BAR \ j \
TestCKT XYZ.D ~ - r \
TestCKT XYZ.CKL I I \ I \ i \
Solution The circuit diagram from the structural model given in the code is shown in Fig. 8.45. The test bench
displays in the monitor. time elapsed and CLK, D, Q (in binary) through first.statement after begin. D initially 1
toggles after a delay oflOns, 30 ns, 30 ns, 30ns. Simulation stops after.further40 ns faking a.total time oflO+ 30+.
30 +30 + 40 140ns. Clock toggles at every 20 ns starting with a value 0.
Flip-Flops
The circuit $hows·.~tif (;I.,K,.5 ·O~JJl ~d \'.12 outp1.1tg

are l.jrrespective.of other inputs. and Q, Q_BARremains
latched to pr~vious value· thr?ugh crosg c?upled U3 .and
.U4. WhenCLK. "". l,D canchangepl011tpu~such ~tX
:=D' also final outputQ =B. Jhe timing dia~shows
Q__B~a: Q'. "fhus the circuit behaves like a high level
triggeredD flip-Flop.
Circuit diagram of Verilog
code given in Example 8.16

Analyze the circuit shown in Fig. 8.46 and find the output Y. Consider that the flip-flops are
initially reset.
T Q T Q y
CLK Q CLK Q
A T flip-flop based circuit for analysis purpose
Sobliion We followthree different methods tri analyze the circuit and identify the performance of Y.
0
111 Method4, .· we use statetafile approach. Wemak: use ofthe factthat a Tflip-flop does not change
its stateifT=.O but.ittoggli;isw:hen T=.·l at the clock trigger.
Letus name the first ftip ..flop asX andits inputand output as. TxandXrespectively. Similarly, let the
· second flip-fl9p be n~med Y: andits inp~t is Tr: while its output is already assigned as Y. Then, the state
tableiS shown il1Fig, 8,47. !e fin1thiltthe cir~~its lll9ye .from states 00, 0 l, 10, 00, ... repetitively and
the 9utpt1l Ygoes HIGH once in tht-ee cycles and remains HIGH for one clock period.
1
0
0
By following similar Xand Y naming oftwo flip-flops as in Method-I, we find that

For Xflip-flop, input: Tx =Xi,+ Yn
output: X 11 + 1 = (X11 + Yn)X,; +·(Xn + Yn}' Xi,
= Ynx,; + XitY,;X11
=Y11 X,;
For Y flip-flop, input: Tr = x,;
outputY,1+1 =X,; Y,; + (X,;)'Y11
=X,; Y,;+X11 Yn
The final solution is shown in Fig. 8.48.
Xn Yn Xn+1 = Y,1 x;1 Y,i+ I = X~ y;; + Xn Y,,

0 0 0 1
0 1 1 0
1 0 0 0
0 0 repeats
Solution using Method-2
In Method-3, we make use of the timing diagram as shown in Fig. 8.49. We note that the flip-flops
are positive edge triggered. The T input just before the positive edge decides output of the flip-flop in
next cycle.
Solution using Method-3
We start withinitialXf== 00. Then we draw Tx byORingXand Ywaveforms and Tyby inverting
Y waveform. Tx and Ty before positive edge decide value of X and Y respectively in next clock cycle
(from Tflip-flop truth table).
Flip-Flops
A flip-flop is an electronic circuit that has two stable states. It is said to be bistable. A basic RS flip-flop,
or latch can .be constructed by connecting two NAND gates or two NOR gates in series with a feedback
connection. A signal at the set input of an RS flip-flop will force the Q output to become a 1, while a signal
at the reset input will force Q to become a 0.
A simple RS flip-flop or latch is said to be transparent-that is, its output changes state whenever a
signal appears at the R or S inputs. An RS flip-flop can be modified to form a docked RS flip-flop whose
output can change states only in synchronism with the applied dock.
An RS flip-flop can also be modified to form a D flip-flop. In a D latch, the stored data may be changed
while the dock is high, The last value of D before the clock returns low is the data that is stored. With edge-
triggered D flip-flops, the data is sampled and stored on either the positive or negative dock edge.
The values of Jand K determine what a JK flip-flop does on the next clock edge. When both are low, the
flip-flop retains its last state. When J islow and K is high, the flip-flop resets. When J is high and K is low,
the flip-flop sets. When both are high, .the flip-flop toggles. In this last mode, the JK flip-flop can be used as
a frequency divider.
There are various ways to represent a flip-flop like truth table, characteristic equation, state transition
diagram or excitation table. Flip-flop treated as a finite state machine highlights its functional aspect.
Analysis of a sequential circuit helps to understand performance of a given circuit in a systematic manner
and through synthesis we develop circuit diagram for a specified problem.
• latch Another term for an RS flip-flop.

• asynchronous Independent of clocking. The
• Mealy model output is dependent both on
output can change without having to wait for
cunent state and input to the circuit.
a clock pulse.
• Moore model output is dependent only on
• bistable Having two stable states.
current state of the circuit.
• bistable multivibrator Another term for an RS
• propagation delay The amount of time it takes
flip-flop.
for the output to change states after an input
• buffer register A group of memory elements,
trigger.
often flip-flops, that can store a binary word.
• setup time The minimum amount of time
• characteristic equation logic expression
required for data inputs to be present before
describing a flip-flop.
the clock arrives.
• edge triggering A circuit responds only when
• state the set of memory values at any given
the clock is in transition between its two
time for a sequential logic circuit.
voltage states.
• synchronous When outputs change states
• finite state machine functional description of
in time with a clock. A clock signal must be
sequential circuit.
present in order for the outputs to change
• flip-flop An electronic circuit that has two
states.
stable states.
• transparent The condition that exists when
• hold time The minimum amount of time that
the flip-flop output changes immediately after
data must be present after the clock trigger
its inputs (R, S, J, K, D) change state.
arrives.
8.8 The waveforms in Fig. 8.51 drive a D latch

as shown in Fig. 8.15. What is the value of D
8.1 List as many bistable devices as you can think stored in the flip-flop after the clock pulse is
of--either electrical or mechanical. (Hint: over?
Magnets, lamps, relays, etc.)
8.2 Redraw the NOR-gate flip-flop in Fig. 8.3b
and label the logic level on each pin for R = S
= 0. Repeat for R = S= I, for R = 0 and S= 1,
and for R = I and S = 0.
8.3 Redraw the NAND-gate flip-flop in Fig. 8.7a
and label the logic level on each pin for R =
S = 0. Repeat for R = S = I, for R. = 1, and
S = 0, and for R = 0 and S = 1. 8.9 What is the advantage offered by an edge-
8.4 Redraw the NAND-gate flip-flop in Fig. triggered RS flip-flop over a clocked or gated
8.8a and label the logic level on each pin for RS flip-flop?
R = S = 0. Repeat for R = S = I, for R = 0 and 8.10 The waveforms in Fig. 8.18d illustrate the
S = 1, and for R = 1 and S = 0. typical operation of an edge-triggered RS
flip-flop. This circuit was connected in the
laboratory, but the R and S inputs were
mistakenly reversed. Draw the resulting
8.5 The wavefonns in Fig. 8.50 drive the clocked waveform for Q.
RS flip-flop in Fig. 8.11. The clock signal goes 8.11 An edge-triggered RS flip-flop will be used
from low to high at points A, C, E, and G. If Q to produce the waveform Q with respect to
is low before point A in time: the clock as shown in Fig. 8.52a. First, would
a. At what point does Q become a 1? you use a positive-edge- or a negative-edge-
b. When does Q reset to O? triggered flip-flop? Why? Draw the waveforms
necessary at R and S to produce Q.
CLK __fl__flJl__fL_
ABCDEFGH c ~
s___Il__ I
: to
I
:tI
I
: !2
Q ~
R___Il_
(a)
c ~ I I I I
8.6 Use the infom1ation in the preceding problem :to :t1 :12 :t3
and draw the waveform at Q.
Q ~
8.7 Prove that the flip-flop realizations in Fig.
(b)
8.12 are equivalent by writing the logic level
present on every pin when R = S = 0 and the
clock is high. Repeat for R = S = I, for R = l
and S = 0, and for R = 0 and S = l. Describe 8.12 An edge-triggered RS flip-flop will be used to
what happens when the clock is low. produce the waveform Q with respect to the
Flip-Flops
clock as shown in Fig. 8.52b. First, would

you use a positive-edge- or a negative-edge-
triggered flip-flop? Why? Draw the waveforms 8.21 Draw two flip-flops like the one shown in Fig.
necessary at R and S to produce Q. 8.25b and show how to connect them such
that a 500-kHz square wave applied to pin 1
will result in a 125-kHz square wave at pin 11.
Give a complete wiring diagram (show each
8.13 A positive-edge-triggered D flip-flop has the pin connection).
input waveforms shown in Fig. 8.51. What is 8.22 Explain the meaning of the symbol l in Fig.
the value of Q after the clock pulse? 8.29a.
8.14 A negative-edge-triggered D flip-flop is driven 8.23 What is the significance of the symbol_n_ in
by the waveforms shown in Fig. 8.51. What is the trnth table of Fig. 8.29?
the value of D stored in the flip-flop? 8.24 Why do most modem designs incorporate
8.15 A D flip-flop has the following data sheet edge-triggered JK flip-flops rather than pulse-
infom1ation: setup time = 5 ns; hold time = 10 triggered JK flip-flops?
ns; propagation time = 15 ns.
a. How far ahead of the triggering clock
edge must the data be applied?
b. How long after the clock edge must the 8.25 Show how to use a simple RS latch to
data be present to ensure correct storage? eliminate switch contact bounce (see Fig.
c. How long after the clock edge before the 8.32a).
output changes? 8.26 There is contact bounce present with the
SPDT switch in Fig. 8.53 just as with the
SPST switch discussed in Fig. 8.31. However,
the RS latch used in Fig. 8.53 will remove all
8.16 Redraw the JK flip-flop in Fig. 8.23a. Connect contact bounce, and V0 will be high with the
J = K = l. (This can be done by connecting switch in position 1 and low with the switch in
the J and K inputs to + Vee) Now, begin with position 2. Explain exactly how this debounce
Q = 1, and show what logic level results on circuit works. You might use waveforms as an
each pin after one positive clock pulse. Allow aid. Incidentally, the 54/74279 can be used to
·one more positive clock pulse and show the construct four of these circuits.
resulting logic level on every pin.
8.17 In the JK flip-flop in Fig. 8.25a, J = K = 1. A
I-MHz square wave is applied to its C input.
It has a propagation delay of 50 ns. Draw the
input square wave and the output waveform
expected at Q, Be sure to show the propagation
delay time.
8.18 Repeat Prob. 8.17, but use the flip-flop in Fig.
8.25c.
8.19 In Prob. 8.17, what is the period of the clock?
What are the period and frequency of the
1/4--74279
output waveform at Q?
8.20 Repeat Prob. 8.17, assuming that the C input Debounce circuit
has a frequency of 10 MHz.
J Qt-----iJ Q
8.27 (a) Derive the characteristic equation and (b)

draw state transition diagram of the fictitious K
flip-flop described in Example 8.10. y
8.28 Explain the difference between Mealy and
Moore model of sequential circuit. Fig. 8.54
8.29 Analyze the following circuit and explain
what it does. 8.31 Convert T flip-flop to D flip-flop.
8.32 Convert SR flip-flop to Tflip-flop.
8.30 Show how to convert D flip-flop to JK flip-

flop.
LABORATORY EXPERIMENT
AIM: The aim of this experiment is to study Kl QI Ql'GND K2 Q2 Q2' J2

D flip-flop and JK flip-flop and use them for
analysis of sequential logic circuits. 16 15 14 13 12 ll IO 9
Theory: The truth table of D flip-flop and 7476

2 3 4 5 6 7 8
JK flip-flop are as follows.
C D Qn+l CK! CLRI PRE! JI SY CK2 CLR2PRE2
0 X Q11 (Last state)
i 0 0
i 1
y
Q J Q
C J K Q,,+J Action K
i 0 0 Q,, (Last state) No change CLK Q CLK Q

i 0 0 RESET
i 0 SET --~-----~
Clock
i Q11 (toggle) Toggle JKflip-flop: Qn+l =JQ,;+K'Q11

Their characteristic equations are:
Apparatus: 5 VDC Power supply, Multime-
D flip-flop: Q11 + 1 = D 11 ter, Bread Board, Clock Generator, and Oscil-
loscope
5V CLR2 D2 CK2PRE2 Q2 Q2'
Work element: IC 7474 is a dual, edge
14 13 12 ll 10 9 8
clocked, D flip-flop with both PRESET and
CLEAR input while 7476 is a dual, edge
7474 clocked, JK flip-flop that too, has both PRE-
2 3 4 5 6 7
SET and CLEAR input. Verify the truth table
of IC 7474 and 7476. Find if it is positive or
CLRl DJ CKlPREl QI QI' GND
Flip-Flops
negative,,~~&~/!1',lgger~d. Appreciate the func- Connect 7476 and 7432 (OR gate) as shown,
tion of J>'(U3~~!;,~~f LEAR ifit is asynchro~ so that the analysis circuit is realized; Use
CLEAR to initialize both the flip-flops to 00.
nous or synchronous with clock. The clock
rnay be available from dock generator or you Then apply clock, and see the clock and Y in
rnay use555 based pulse generator developed a dual trace oscilloscope. Use 7474 to prepare
in laboratory experiment of previous (;:ha.pter1 an SR flip-flop as shown in Fig. 8.43 and find
its truth table.
l. R stands for RESET(Q = L). S stands fQr C goes low, the contents of the master
SET(Q=H). shift into the slave, and Q is SET-RESET
2. Quad means "four." There are four flip~ accordingly.
flops in this IC. 16. Switch contact bounce is the bouncing that
3, ANAND-gate latch is considered active- occurs when a mechanical, spring-actuated
low because a low input signal is required device is operated.
to change Q. 17. The. bouncing action produces multiple
4. Xmeans don't care-'-this input atthis time PTs and NTs, which may introduce
has no effect. unintentional signals!
5. · . Simply hold the EN inputloW{atOVde). 18. Logic ·relation showing next state as
.I!
6. Jh~ flip-flop is et1Sier to use because it a function of current state and cmTent
· requires only one input (D). inputs.
7, !t.~f~S. t~~Q~tput responds .immediately 19. That explains the functional behavior of
toinputsignals. a sequential· circuit through finite .number
8. A.fircajtis activated by the leading edge of states and its transition from one state to
the clock. another.
9. Jh71atfll.istrat1spa:re~t. The.edge,-trigsere,:l 20. It is truth table written in a reverse way
flip-flop only changes state. in synchronism such that inputs are shown dependent on a
with the clock. particular state transition.
10. None.The.flip,.fl.op is disabled with C held 21. Finding what a given circuit does.
low. 22. Truth table.
lL PRESET is active high. A high level at 23. By this one need not redesign the
PRESET will set Q high. whole circuit if flip-flop one kind is not
12. Jhe JK flip-flop has an additional input available.
condition---,- J = K = H. This causes the 24. In analysis,problem begins with a circuit
flip-~op to< toggle \¥ith the dock The R = S diagram and.· ends in state•. transition
=11c ~put condition is· not allowed with an diagram or. perfonnance description.. It
Rfflip-flop. uses flip-flop truth table or characteristic
13. Crostco~ple the. outputSback to the input equation in this process. In synthesis, the
ANDt 1,;ates.. < . . · ....· . . ·. ... ·.. · . . . ·
The andK inputs are transparent in a
path is reverse and we use excitation table
instead of truth table.
pulse'-triggered flip~flop. Thus, Jand K 25. In state analysis table, input of the flip-
must be<statfo while the· clock is high, flops used in the circuit is written first
15. WhHe C is high, the master is SET-RESET followed by state transition whereas in
according to the J•and K inputs, When state synthesis table it is other way.
Registers
+ Understand serial in-serial out shift registers and be familiar with the basic features
of the 74LS91 register
+ Understand serial in-parallel out shift registers and be familiar with the basic features
of the 74164 register
+ Understand parallel in-serial out shift registers and be familiar with the basic features
of the 74166 register
+ Understand parallel in-parallel out shift registers and be familiar with the basic
features of the 74174 and 7495A registers
+ Understand working of Universal shift register with the basic features of the 74194
register.
+ State various uses of shift registers
A register is a very important digital building block. A data register is often used to momentarily store binary
information appearing at the output of an encoding matrix. A register might be used to accept input data from
an alphanumeric keyboard and then present this data at the input of a microprocessor chip. Similarly, registers
are often used to momentarily store binary data at the output of a decoder. For instance, a register could be
used to accept output data from a microprocessor chip and then present this data to the circuitry used to drive
the display on a CRT screen. Thus registers form a very important link between the main digital system and
the input-output channels. A universal asynchronous receiver transmitter (UART) is a chip used to exchange
data in a microprocessor system. The UART is constructed using registers and some control logic.
A binary register also forms the basis for some very important arithmetic operations. For example, the
operations of complementation, multiplication, and division are frequently implemented by means of a
register. A shift register can also be connected to form a number of different types of counters. Shift registers
Registers
as sequence generator and sequence detector and also as parallel to serial converters offers very distinct
advantages.
The many different applications of registers, along with the myriad of techniques for using them, are
simply too numerous to be discussed here. Our intent is to study the detailed operation of the four basic types
of shift registers. With this knowledge, you will have the ability to study and understand exactly how a shift
register is used in any specific application encountered.
9~1 TYPES OF REGISTERS
A register is simply a group of flip-flops that can be used to store a binary number. "There must be one flip-
flop for each bit in the binary number. For instance, a register used to store an 8-bit binary number must
have eight flip-flops. Naturally the flip-flops must be connected such that the binary number can be entered
(shifted) into the register and possibly shifted out. A group of flip-flops connected to provide either or both of
these functions is called a shift register.
The bits in a binary number (let's call them the data) can be moved from one place to another in either
of two ways. The first method involves shifting the data 1 bit at a time in a serial fashion, beginning with
either the most significant bit (MSB) or the least significant bit (LSB). This technique is referred to as serial
shifting. The second method involves shifting all the data bits simultaneously and is referred to as parallel
shifting.
There are two ways to shift data into a register (serial or parallel) and similarly two ways to shift the data
out of the register. This leads to the construction of four basic register types as shown in Fig. 9.l-serial in-
serial out, serial in-parallel out, parallel in-serial out, and parallel in-parallel out. All of these configurations
are commercially available as TTL MSI/LSI circuits. For instance:
Serial in-serial out-54/74LS91, 8 bits
Serial-s
_data 8 bits.· .
mput
Serial-@ · - ·· · > Serial
_data ... · ..8 bits · · data MSB LSB
mput ..·. . . ...· output '------r----1
Parallel data outputs
(a) Serial in-serial out (b) Serial in-parallel out
Parallel data inputs

,------A--,
MSB LSB
Parallel data inputs
OJ
,------A--,
MSB LSB
Serial
data
output MSB LSB
'------r----1
(c) Parallel in-serial out (d) Serial in-parallel out
Shift register types

Digital Principles and Applications ·
Serial in-parallel out-54/74164, 8 bits

Parallel in-serial out-54/74165, 8 bits
Parallel in-parallel out-54/74198, 8 bits
We now need to consider the methods for shifting data in either a serial or parallel fashion ..Data shifting
techniques and methods for constructing the four different types of registers are discussed in the following
sections.
9.2 SERIAL IN-SERIAL OUT
In this section we discuss how data is serially entered or exited from a shift register. The flip-flops used to
construct registers are usually edge-triggered JK, SR or D types. We begin our discussion with shift registers
made from D type flip-flops and then extend the idea to other types.
Consider four D flip-flops connected as shown in Fig. 9.2a forming 4-bit shift register. A common clock
provides trigger at its negative edge to all the flip-flops. As output of one D flip-flop is com1ected to input of
the next at every Clock trigger data stored in one flip-flop is transferred to the next. For this circuit transfer
takes place like this Q ~ R, R ~ S, S ~ T and serial data input is transferred to Q. Let us see how actual
data transfer takes place by an example.
Assume, all the flip-flops are initially cleared. Let a binary waveform, as shown along D of
Fig. 9.2b be fed to serial data input of the shift register. Corresponding Q, R, S, Tare also shown in the
figure.
At clock edge A, flip-flop Q has input O from serial data in D, flip-flop R has input O from output of Q,
flip-flop S has input Ofrom output of Rand flip-flop Thas input Ofrom output of S. When clock triggers, these
inputs get transferred to corresponding flip-flop outputs simultaneously so that QRST= 0000. Thus at clock
trigger, values at DQRS is transferred to QRST.
A B C D
Time
+ + i t
r
l
Clock~
Q I I I I
I 1 I 1
I
LL
1
s,riru
1
I
I
:I
I
I 1
data 1 1
R J s
son,, {
data
input K 1
0 :I
I
1
f:
I
I
I 1
input
K s Q l ~
Q J I I I
I I
Clock I I
I I
11
1
Rl 1 1 1
1 1 I
0 I I
I 1 1
I 1 I
SI
0
1
I
1
1 :o
(a) (b)
4-bit serial input shift register

Registers
At clock edge B, serial data in= 0, i.e. DQRS = 0000. So after NT at B, QRST= 0000. Serial data becomes
1 in next clock cycle.
At clock edge C, DQRS = 1000 and after NT QRST= 1000. Serial data goes to O in next clock cycle such
that at clock edge D, DQRS = 0100 and after NT QRST = 0100. Example 9 .1 will give another illustration
of such data transfer.
A shift register made up of JK or SR flip-flops has non-inverting output Q of one flip-flop connected to J or
S input of next flip-flop and inverting output Q' connected to Kor R input respectively. For the first flip-flop,
between J and K (or Sand R) an inverter is connected and J (or S) input is treated as serial data in. Note that,
in this configuration both JK and SR flip-flops effectively act like a D flip-flop.
Show how a number 0100 is entered serially in a shift register shown in Fig. 9.2a using state
table.
Soh1tion Figure 93 presents the state table. The timing diagram corresponding to this is discussed in this section.
Note how the data flow across the flip-flops is highlighted by arrow direction.
Clock Serial input Q R s T
0 0
o~o~o~o
o~o~o~o
2 0
l~O~O~O
0
O~l~O~O
0 0 l 0
Datil transfer through serial input in .a shift register
Draw the waveforms to shift the number 0100 into the shift register shown in Fig. 9.3 on the
next page.
Solution The waveforms for this register will appear exactly as in Fig. 9.2 provided the waveform labeled K is
eliminated and waveform J is labeled D.
4-bit serial input shift register
At this point, we have developed the ideas for shifting data into a register in serial fonn; the serial data
input can be classified as either JK or D, depending on the flip-flop type used to construct the register. Now,
how about shifting data out of the register?
Let's take another look at the register in Fig. 9.3a, and suppose A B C D
Time--~--.--~-~-
that it has the 4-bit number QRST = 1010 stored in it. If a clock sig- I I I I
1 I I I I
nal is applied, the waveforms shown in Fig. 9.4 will be generated. Clock~
Here's what happens: 0 I I I I
I I I I
Before Time A The register stores the number QRST= 1010. The t + t t
LSB (a 0) appears at T. DI
0 I I
At Time A The entire number is shifted one flip-flop to the right. I I
AO is shifted into Q and the LSB is shifted out the right end and lost.
The register holds the bits QRST= 0101, and the second LSB (a I)
Q~t] I I I
!o
I
l I I I I
appears at T. R ~
Q I I I I
At Time B The bits are all shifted one flip-flop to the right, a 0 I I I I
shifts into Q, and the third LSB (a 0) appears at T. The register holds
QRST= 0010.
s~~ I I I I
I I I J
At Time C The bits are all shifted one flip-flop to the right, a 0 T~~
shifts into Q, and the MSB (a I) appears at T. The register holds
QRST= 0001.
At Time D The MSB is shifted out the right end and lost, a Oshifts
into Q, and the register holds QRST = 0000.
To summarize, we have caused the number stored in the register to appear at T (this is the register output)
1 bit at a time, beginning with the LSB, in a serial fashion, over a time period of four clock cycles. In other
words, the data stored was shifted out of the register at flip-flop Tin a serial fashion. Thus, not only is this a
serial-input shift register, it is also a serial-output shift register. It is important to realize that the stored number
is shifted out of the right end of the register and lost after four clock times. Notice that the complement of the
output data stream is also available at f.
The pinout and logic diagram for a 74LS9 l shift register are shown in Fig. 9.5. This is an
8-bit TTL MSI chip. There are eight RS flip-flops connected to provide a serial input as well as a serial output.
14 13 12 11 10 9 8
Q Q B GND A CLK
74LS9I
Vee
2 3 4 5 6 7
(a) DIP pinout
A
B
(b) Logic diagram
74LS91 8-bit shift register

Registers
The clock input at each flip-flop is negative-edge-trigger-sensitive. However, since the applied clock signal is
passed through an inverter, data will be shifted on the positive edges of the input clock pulses.
The inverter connected between R and Son the first flip-flop means that this circuit functions as a D-type
flip-flop. So, the input to the register is a single line on which the data to be shifted into the register appears
serially. The data input is applied at either A (pin 10) or B (pin 12). Notice that a data level at A (or B) is
complemented by the NAND gate and then applied to the R input of the first flip-flop. The same data level
is complemented by the NAND gate and then complemented again by the inverter before it appears at the S
input. So, a 1 at input A will set the first flip-flop (in other words, this 1 is shifted into the first flip-flop) on a
positive clock transition.
The NAND gate with inputs A and B simply provides a gating function for the input data stream if desired.
If gating is not desired, simply connect pins 10 and 12 together and apply the input data stream to this
connection.
Examine the logic levels at the input of a 74LS91 and show how a 1 and then a Oare shifted
into the register.
Solution .The input logic and the firstflip-flop are redrawn in Fig. 9.6a, and a l is applied at the data input A. The
..R>illputis 0, .the Sjnput is 1, and the flip,,fiop y,,m clearly be set when the clock goes high. In other words, the 1 at the
~t!lfaputwill shift int() the ilip-fiop. fafig. ~.6b, a Ois applied at the datajnput A. The R input is 1, the S input is 0,
and the flip-flop will be resetwhenthe~lock goes high. The inputO is thus shifted into the flip-flop.
(b) Logic levels shown by arrows will

reset the flip-flop
l. Whalisthelai;gestdecim~l nuniber that can be stored (in binary form) in a 74LS91 register?
Is a 74LS9hegister sensitive to PTs or to NTs?
9.3 SERIAL IN....PARALlEl OUT
The second type of register mentioned in Sec. 9 .1 is one in which data is shifted in serially, but shifted out in
parallel. In order to shift the data out in parallel, it is simply necessary to have all the data bits available as
outputs at the same time. This is easily accomplished by connecting the output of each flip-flop to an output
pin. For instance, an 8-bit shift register would have eight output lines-one for each flip-flop in the register.
The basic configuration is shown in Fig. 9.lb.
~ _ _ _ _ _ _ _ _ _ _ _ _ _ _D_ig_it_al_P_n_·nc_ip_le_s_a_n_d_A_pp_lt_·ca_t,_·on_s_ _ _ _ _ _ _ _ _ _ _ __
The 54/74164 is an 8-bit serial input-parallel output shift register. The pinout and logic diagram for this
device are given in Fig. 9.7. It is constructed by using RS flip-flops having clock inputs that are sensitive to
NTs. A careful examination of the logic diagram in Fig. 9. 7b will reveal that this register is exactly like the
74LS9 l discussed in the previous section-with two exceptions: (1) the true side of each flip-flop is available
as an output-thus all 8 bits of any number stored in the register are available simultaneously as an output
(this is a parallel data output); and (2) each flip-flop has an asynchronous clear input. Thus a low level at the
clear input to the chip (pin 9) is applied through an amplifier and will reset (clear) every flip-flop. Notice that
this is an asynchronous signal and can be applied at any time, without regard to the clock waveform and also
that this signal is level sensitive. As long as the clear input to the chip is held low, the flip-flop outputs will all
remain low. (The register will contain all zeros!)
Shifting data into the register in a serial fashion is exactly the same as the previously discussed 74LS91.
Data at the serial inputs may be changed while the clock is either low or high, but the usual setup and hold
times must be observed. The data sheet for this device gives setup time as 30 ns minimum and hold time as
Data C
outputs L
0
C
K
54/74164
B QA
~ '------~---..J
Data Data
inputs outputs
(a) DIP pinout
CLEAR
CLOCK
A
B

(b) Logic diagram
54/7 4164 8-bit shift register

Registers
0.0 ns. Since data are shifted into the register on PTs, the data input line must be stable from 30 ns before the
PT until the clock transition is complete.
Let's take a look at the gated serial inputs A and B. Suppose that the serial data is connected to A; then B
can be used as a control line. Here's how it works:
B is Held High The NAND gate is enabled and the serial input data passes through the NAND gate
inverted. The input data is shifted serially into the register.
B is Held Low The NAND-gate output is forced high, the input data stream is inhibited, and the next
positive clock transition will shift a O into the first flip-flop. Each succeeding positive clock transition will
shift another O into the register. After eight clock pulses, the register will be full of zeros!
How long will it take to shift an 8-bit number into a 54164 shift register if the clock is set at
IO MHz?
Solution A minimum of eight clock periods will be required since the data is entered serially. One clock period is
100 ns, so it will require 800 ns minimum.
For the register in Example 9.4, when must the input data be stable? When can it be
changed?
Solution The data must be stable from 30 ns before a positive clock transition untiHhe positive transition occurs.
This leaves 70 ns during which the data may be changing(~~e Fig. 9.8).
IOOns · .· t PT
clock period --J
Clock
Q--,.--,-__.
I . ·. · 70-ns . I_30-ns_ l
r::::= data =:i-setu~
transition time time ·
The waveforms shown in Fig. 9.9 show the typical response of a 54/74164. The serial data is input at A
(pin 1), while a gating control signal is applied at B (pin 2). The first clear pulse occurs at time A and simply
resets all flip-flops to 0.
The clock begins at time B, but the first PT does nothing since the control line is low. At time C the control
line goes high, and the first data bit (a 0) is shifted into the register at time D.
The next 7 data bits are shifted in, in order, at times E, F, G, H, I, J and K. The clock remains high after
time K, and the 8-bit number 0010 1100 now resides in the register and is available on the eight output lines.
This assumes that the LSB was shifted in first and appears at QH- Notice that the clock must be stopped after
its positive transition at time K, otherwise shifting will continue and the data bits will be lost.
Finally, another clear pulse occurs at time L, the flip-flops are all reset to zero, and another shift sequence
may begin. Incidentally, the register can be cleared by holding the control line at B low and allowing the clock
to run for eight PTs. This simply shifts eight Os into the register.
Digital Pdnciples and Applications
AB CD EFG HI J K L
Titne~~1~ - , - ~ - . - . , - - - , . ~ - r - ~ - - . - ~ . - - - - , ~ - , - ~ . - ~ ~ ~ ~ - , -1 ~
Clear -1_J-+--,..-;---,.---;.--;--...;i--;--..;--;.-----u--
' II I
Data (A) L.l.STl- - ' - - - ! - - - - - - , . . . -

I I
Control (B)
-----
Clock ,
I
!...o....._______.
QA -=--....
I I
0
QB =-,_;0____________. :o
I
I
Qc --: O
- ,..,
I
----------- ~
I
QD --: 0 : 0
- ;-," - - - - - - - - - - - - - " " " " I
QE=-: 0 I
..----.:-!-----;~
~,"--------------~
I
I
I
!0__________11
Qp=-...... L£_
I I I
QG ==: 0
I
:0
I
: 0
I
QH =: =::;...o________________""":_o____...;:_o....,..
In prior sections, the ideas necessary for shifting data into and out of a register in serial have been developed.
We can now use these same ideas to develop methods for the parallel entry of data into a register. There are a
number of different techniques for the parallel entry of data, but we shall concentrate our efforts on commer-
cially available TTL At first glance, the logic diagrams for some of the shift registers seem rather formidable
(see, for instance, the block diagram for the 54/74166); but they aren't really. The 54/74166, for instance, is
an 8-bit shift register, and the same circuit is repeated eight times. So, it's necessary to study only one of the
eight circuits, and that's what we'll do here.
The pinout and logic block diagram for a 54/74166 are given in Fig. 9.10. The functional description given
on the TTL data sheet says that this is an 8-bit shift register, capable of either serial or parallel data entry,
and serial data output. Notice that there are eight RS flip-flops, each with some attached logic circuitry. Let's
analyze one of these circuits by starting with the RS flip-flops and then adding logic blocks to accomplish
oµrneeds.
Registers
Clear
Serial input - - ~
Shift/load
A (2)
Parallel Parallel inputs

Shift/ Input O u t p u t ~
load H QH G F E Clear
15
Shift/ H QH G F E
load
Serial input
CK
Serial A B Clock Clock GND

input ~----v---- inhibit
Parallel inputs
Positive logic: see description

(a) Pinout
(14)
Clock H-+(7,,..)--1:---..
Clock inhibit (6) >:>-------+-'
(b) Logic diagram
54/74166
First recognize that the clocked RS flip-flop and the attached inverter given in Fig. 9.1 la fonn a type D
flip-flop. If a data bit Xis to be clocked into the flip-flop, the complement of X must be present at the input.
For instance, if X = 0, then R = 0 and S = 1, and a 1 will be clocked into the flip-flop when the clock transi-
tions.
Q (X) Q (X)
s s
~--+--tR ~--+--tR
Clock---~ Clock---~
(a) Type D flip-flop (b) NOR-gate added
.----.uo
s Q
Control
Clock----'
(c) Control logic added
Q (1)
Control= 1
(d) Example 9.5
Now, add a NOR gate as shown in Fig. 9.11 b. If one leg of this NOR gate is at ground level, a data bit X
at the other leg is simply inverted by the NOR gate. For instance, if X = 1, then at the output of the NOR gate
X = 0, allowing a 1 to be clocked into the flip-flop. This NOR gate offers the option of entering data from
two different sources, either X 1 or X 2. Holding X2 at ground will allow the data at X 1 to be shifted into the
flip-flop; conversely, holding X 1 at ground will allow data at X2 to be shifted in.
The addition of two AND gates and two inverters as shown in Fig. 9. llc will allow the selection of data
X 1 or dataX2. If the control line is high, the upper AND gate is enabled and the lower AND gate is disabled.
Thus X 1 will appear at the upper leg of the NOR gate while the lower leg of the NOR gate will be at ground
level. On the other hand, if the control line is low, the upper AND gate is disabled while the lower AND gate
is enabled. This allows X 2 to appear at the lower leg of the NOR gate while the upper leg of the NOR gate is
at ground level. You should now study this circuit until your understanding is crystal clear! Consider writing
0 or l at each gate leg in response to various inputs. To summarize:
CONTROL is High Data bit atX1 will be shifted into the flip-flop at the next clock transition.
CONTROL is Low Data bit atX2 will be shifted into the flip flop at the next clock transition.
0
Registers
For the circuit in Fig. 9.11 c, write the logic levels present on each gate leg if CONTROL= 1,
X1 = 1, andX2 = I.
Solution The cone(.lt1evels are given in parentheses in Fig, Sl.l l d, The data value J atX1is ,,hift,,,lin1to tl,,, nro~11on
when the clock transitions.
A careful examination will reveal that exactly eight of the circuits given in Fig. 9 .11 c are connected
together to form the 54/74166 shift register shown in Fig. 9.10. The only question is: how are they connected?
The answer is: they are connected to allow two different operations: (1) the parallel entry of data and (2) the
operation of shifting data serially through the register from the first flip-flop QA toward the last flip-flop QH,
If the data input labeled X 2 in Fig. 9. llc is brought out individually for each flip-flop, these eight inputs
will serve as the parallel data entry inputs for an 8-bit number ABCD EFGH. These eight inputs are labeled
A, B, C, D, E, F, G, and Hin Fig. 9.10. The control line is labeled shift/load. Holding this shift/load control
line low will enable the lower AND gate for each flip-flop, and the 8-bit number will be LOADED into the
flip-flops with a single clock transition-PARALLEL input.
Holding the shift/load control line high will enable the upper AND gate for each flip-flop. If the input from
this upper AND gate receives its data from the prior flip-flop in the register, each clock transition will shift ·
a data bit from one flip-flop into the following flip-flop-proceeding in a direction from QA toward QH. In
other words, data will be shifted through the register serially! In the first flip-flop in the register, the upper
AND-gate input is labeled serial input. Thus data can also be entered into this register in a serial fashion. To
summarize:
Shift/Load is Low A single clock transition loads 8 bits of data (ABCD EFGH) into the register in parallel.
Shift/Load is High Clock transitions will shift data through the register serially, with entering data applied
at the SERIAL INPUT.
Notice that the clock is applied Inputs Internal Levels Outputs
through a two-input NOR gate. When
Shift/ Clock Parallel
clock inhibit is held low, the clock Clear
load inhibit
Clock Serial
A ... H
QA and QB QH
signal passes through the NOR gate
inverted. Since the register flip-flops L X X X X X L L L
respond to NTs, data will shift into H X L L X X QAO QBO QHO
the register on the PTs of the clock.
H L L t X a ... h a b h
When clock inhibit is high, the NOR-
gate output is held low, and the clock
- - - - - - - - ,-- - - - -
H H L t H X H QA,, QGn
--
is prevented from reaching the flip- H H L t L X L QAn QGn
flops. In this mode, the register can
H X H t X X QAO QBO QHO
be made to stop and hold its contents.
A low level at the clear input can X = Irrelevant, H = High level, L = Low level
be applied at any time without regard t = Positive transition
a ... h = Steady state input level at A . . .H respectively
to the clock, and it will immediately
QAO• QBO = Level at QA, QB ..• before steady state
reset all flip-flops to 0. When not in
QA,,, QG,, Level of QA or QB before most recent transition ( ) t
use, it should always be held high.
The truth table in Fig. 9.12 sum- 54/7 4166 truth table
maiizes the operation of the 54/74166
8-bit shift register. You should study this table in conjunction with the logic diagram to understand clearly
how the register can be used.
Which entry in the truth table in Fig. 9.12 accounts for the parallel entry of data?
(3)
9.5 PARALLEL IN-PARALLEL out D1
CK
The fourth type of register discussed in the intro- Clear
ductory section of this chapter is designed such that
data can be shifted either into or out of the register D (4)
2
in parallel. In fact, simply adding an output line from
each flip-flop in the 54/74166 discussed in the previ- CK
ous section would meet the parallel in-parallel out re- Clear
quirements. [It would, of course, require a larger dual
in-line package (DIP)-say, a 24-pin package.] D (6)
3
CK
The 54/74174
Clear
The 74174 in Fig. 9.13 is an example of a parallel
in-parallel out register. The Texas Instruments data D (11)
sheet refers to it as a hex D-type flip-flop with clear. 4
It is simply a parallel arrangement of six D-type flip- CK

flops. Each flip-flop is negative-edge-triggered, and Clear
thus a PT will shift data into the register. The six data
bits, D 1 through D 6 are all shifted into the register in D (13)
5
parallel. The stored data is immediately available, in
parallel, at the outputs, Q 1 through Q6. This type of CK
register is simply used to store data, and is sometimes Clear
called a data register, or data latch. Notice that it is
not possible to shift stored data either to the right or to iJ c14>
6
the left. A low level at the clear input will immediately
CK
reset all flip-flops low. The clear input is asynchro-
nous-that is, it can be done at any time and it takes
precedence over all other inputs.
The 74LS174 data sheet gives

54/74174
a setup time of 20 ns and a hold
Registers
time of 5 ns. What is the minimum required width of the data input levels (D1 ... D6) for the
74LS174 in Fig. 9.13?
?S
Solution The data inputs m11.i,t be S:te~dy at least 20 before the PT of the clock, and they must be held for a
minimum of 5 ns after the PT. Thus,.the da1;a inputlevels must be held steady fora minimum of25 ns (see Fig. 8.24
for comparison).
The 54/74198
The 54/74198 is an 8-bit TTL MSI having both parallel input and parallel output capability. The DIP pinout
for this device is given in Fig. 9.14 on the next page. It uses positive edge-triggered flip-flops, as indicated
by the small triangle at pin 11. Notice that a 24-pin package is required since 16 pins are needed just for the
input and output data lines. Not only does this chip satisfy the parallel input-output requirements; it can also
be used to shift data through the register in either direction-referred to as shift right and shift left. All the
registers previously discussed have the ability to shift right, that is, to shift data serially from the data input
flip-flop toward the right, or from a flip-flop QA toward flip-flop Qs. We now need to consider how to shift
left.
Shift
left
serial Input Input Input
Vee input H QH G QG F QF QE Clear
24
S1 L H QH G QG F QF E QE
So 54/74198 Clear
CK
12
So Shift Input Input QB Input Qe Input QD Clock GND
right A B C D
serial
input
54/74198, 8-bit shift register. Parallel input-parallel output
There are a number of 4-bit parallel in-,-parallel out shift registers available since they can be conveniently
packaged in a 16-pin DIP. An 8-bit register can be created by either connecting two 4-bit registers in series
or by manufacturing the two 4-bit registers on a single chip and placing the chip in a 24-pin package ( such as
the 54/74198). Let's analyze a typical 4-bit register, say, a 5417495A.
The data sheet for the 5417495A describes it as a 4-bit parallel-access shift register. It also has serial data
input and can be used to shift data to the right (from QA toward Qs) and in the opposite direction-,to the left.
The DIP pinout and logic diagram are given in Fig. 9.15. The basic flip-flop and control logic used here are
exactly the same as used in the 54/74164 as shown in Fig. 9.llc.
The parallel data outputs are simply the Q sides of each of the four flip-flops in the register. In fact, note
that the output QD could be used as a serial output when data is shifted from left to right through the register
(right shift).
Outputs Clock 2
~--~'~--~Clock I L shift
Vee QA QB Qe QD R shift (load)
14
CKI CK2
Serial input
A B C D Mode
1
Serial A B D Mode GND
input ~ - - - . , . . - - ~ control
Inputs
(a) Pinout
Data inputs
A B
(2)(14) (3)(2) (4)(3) (5)(5)
Clock I
right shift
Clock2
left shift (8)(8)
(12)(12)
QB
Note: The pin numbers in parentheses correspond to
the ('95A, 'LS95) ('L95), respectively. Outputs
(b) Logic diagram
54/7495A
When the mode control line is held high, the AND gate on the right input to each NOR gate is enabled
while the left AND gate is disabled. The data at inputs, A, B, C and D will then be loaded into the register on
a negative transition of the clock-this is parallel data input.
When the mode control line is low, the AND gate on the right input to each NOR gate is disabled while
the left AND gate is enabled. The data input toflip-flop QA is now at serial input; the data input to Qs is QA
and so on down the line. On each clock NT, a data bit is entered serially into the register at the first flip-flop
QA, and each stored data bit is shifted one flip-flop to the right (toward the last flip-flop Qv). This is the serial
input of data (at serial input), and also the right-shift operation.
Registers
In order to effect a shift-left operation, the input data must be connected to the D data input as shown in
Fig. 9.16 below. It is also necessary to connect QD to C, Qc to B, and QB to A as shown in Fig. 9.16. Now,
when the mode control line is held high, data bit will be entered into flip-flop QD, and each stored data bit
will be shifted one flip-flop to the left on each clock NT. This is also serial input of data (but at input D) and
is the left-shift operation. Notice that the connections described here can either be hard wired or can be made
by means of logic gates.
Serial data input
(95, 'LS95) ('L95) Data inputs

A B C D
(2)(14) (3)(2) (4)(3) (5)(5)
Clock I
right shift
Clock 2
left shift
(12)(12) (11 )(10) (10)(9)

QB Qc QD
Outputs
54/7 495A wired for shift left
There are two clock inputs--clock 1 and clock 2. This is to accommodate requirements where the clock
used to shift data to the right is separate from the clock used to shift data to the left. If such a requirement is
unnecessary, simply connect clock 1 and clock 2 together. The clock signal will then pass through the AND-
OR gate combination noninverted, and the flip-flops will respond to clock NTs.
Draw the waveforms you would expect if the 4-bit binary number l Ol O were shifted into a
5417495A in parallel.
Solution The mode control line must be high, The data. input line~ must be stable for more than 10 ns prior to the
clockNTs (setup timefor the data sheet information). A single clock NT will enter the data. (The waveforms are given
in Fig. 9 .17.) If the clock is stopped after the transition time T, the levels on the input data lines may be changed,
However, if the clock is not stopped, the input data line levels must be maintained.
At this point, it simply cannot be overemphasized that the input control lines to any shift register must be
controlled at all times! Remember, the register will do something every time there is a clock transition. What
it does is entirely dependent on the levels applied at the control inputs. If you do not account for input control
levels, you simply cannot account for the behavior of the register!
Mode ~
Clock i_._ Jn L _ _ _
0 !
A I
0
B 1
0----'-------
Outputs Mode
c 1 selection
0 QD Clock S 1 S0
D 1 12 11 10 9
o---~,-----,-
Q '
1-------+:~~~~-
A 0-------~
I
I
I--------<
QB :
0-------+--~~~~-
I
Qc 1-------:
0-------~ 2 3 4 5 6 7 8
I
1-------~ Clear Serial A B C D Serial GND
QD : input, input,
0-------~~~~~- inputs,
I
1
right left
Time----- - - - - shift shift
T
74194 pinout
Example 9.8
How can the. 7495A,. a 4~bit register, b.e used to store 8-bi.t numbers?
Why does the 7495A have two separate dock inputs?
9.6 UNIVERSAL SHIFT REGISTER

In Section 9 .1, we have seen that for basic types of shift register, the following operations are possible-serial
in-serial out, serial in-parallel out, parallel in-serial out, and parallel in-parallel out. Serial in or serial out
again can be made possible by shifting data in any of the two directions, left shift (QA +- Qs +- Qc +- Qn +-
Data in) and right shift (Data in ~ QA~ Qs ~ Qc ~ QD). A universal shift register can perform all the four
operations and is also bidirectional in nature. 7495A, described in previous section, is quite versatile except
for the fact that it is in-built for right shift; the left shift is achieved through parallel loading (Fig. 9 .16) and
thus requires external wiring.
The 74194 is a4-bit universal shift register in 16 pin package with pinout diagram as shown in Fig. 9.18.
A, B, C and Dare four parallel inputs, and QA, Q8, Qc and QD are corresponding parallel outputs. There are
two separate inputs for serial data for left and right shift. In addition, there are two mode control inputs which
Registers
select the mode of operation for the universal shift register according to Table 9 .1. The subscript n and n + 1
represent two consecutive states and in between them, there is a clock trigger. In the function table, next state
QA, n+l takes the value Qs,n at clock-trigger which means whatever was the value of Qs at n-th state becomes
the value of QA at (n + 1)-th state.
To understand how this universal shift register is implemented, refer to logic circuit diagram of74194 in
Fig. 9.19. You may identify four 4 to 1 multiplexer blocks in the circuit (one is shown with dotted lines). Two
selection inputs of each of these four multiplexers, understandably, are mode selection inputs S1S0 . For S 1S0
= 00, the second AND gate output which is nothing but the previous value of the corresponding flip-flop is
transferred to the output. Thus, the flip-flop output does not change and this is the 'Hold' mode. For S 1S0 =
01, the fourth AND gate output is transferred which corresponds to 'Shift right'. For S 1S0 = 10, the first AND
gate output is transferred which corresponds to 'Shift left'. Finally, for S 1S0 = 11, the third AND gate output
is selected which effects parallel 'Load' synchronized with clock. The input 'Clear' is active low and resets
all the flip-flops asynchronously when activated. Note that the 'Clock' is positive edge-triggered due to two
inversions (bubble) in the circuit diagram.
The 74299 is an 8-bit universal shift register in 20 pin package with a similar function table as the 74194.
To save number of pins, the input and output pins are made common here. This is achieved by tristating and
using additional control input that make these pins bidirectional.
Mode Next State (n+ I-th state)

So QA,n+J Qs,n+I Qc,n+I Qv.n+I
0 QA,11 Qs,11 Qc,n Qv,n
Data in QA,n Qs.11 Qc.11
(Pin 2)
0 Qs,11 Qc,n Qv.n Data in
(Pin 7)
A B C D
9.7 APPUCATl(JNS Of SHIFT REGISTERS

Shift registers are used in almost every sphere of a digital logic system. In this section we discuss few such
applications. Shift register can be used to count number of pulses entering into a system as ring counter or
switched-tail counter. As ring counter it can generate various. control signals in a sequential manner. Shift
register can also generate a prescribed sequence repetitively or detect a particular sequence from data input. It
can also help in reduction of hardware by converting parallel data feed to serial one. Serial adder is one such
application discussed in this section.
Ring Counter
Let's begin with a simple serial shift register such as the 54/74164. One of the most logical applications of
feedback might be to connect the output of the last flip-flop QH back to the D. input of the first flip-flop A
(Fig. 9.20a). Notice that the A and B data inputs are connected together. Now, suppose that all flip-flops are
reset and the clock is allowed to run. What will happen? The answer is, nothing will happen since the D
input to the first flip-flop is low (the input at A and B). Therefore, every time the clock goes high, the zero
(11)
Clock
(I)
Clear
(7) S1S9________ ~ _t_~ _!. ~-~!~i_I?!:~er
Serial input
for left shift ---~~~
,__,___.___,___.... D Q (12) 0
(6) -D
D ---------+--+--+-----+-,___.
CK
Clear
Q (13) 0
'1------1--+---iD
-c
CK
Clear
>----t-+-----,D Q
CK
Clear
(15) O
>----+--+----iD Q -A
CK
Clear
Serial input (2)
for right shift --------------<
74194, 4-bit universal shift register
in each flip-flop will be shifted into the next flip-flop, while the zero in the last flip-flop H will travel around
the feedback loop and shift into the first flip-flop A. In other words, all the flip-flops are in a reset state, each
clock PT resets them again, and each flip-flop output simply remains low. Consider the register as a tube full
of zeros (ping-pong balls) that shift round and round the register, moving ahead one flip-flop with each clock
PT.
Registers
Clear---n
Clock
(a) 54/74164 8-bit shift register with feedback line from QH to A-B
t t
Clock
QA
QD
-----~
QE __._ ______ _,
QF
~-------~
QG ~~~~~~~~r--l~---,-~~~~~~~r-1_____
QH
(b) Waveforms when register has a single one, and seven zeros
Ring counter
In an effort to obtain some action, suppose that QA is high and all other flip-flops are low, and then allow
the clock to run. On the very first clock PT, the 1 in A will shift into B and A will be reset, since the O in H
will shift into A. All other flip-flops will still contain Os. The second clock pulse will shift the 1 from B to C,
while B resets. The third clock PT will shift the 1 from C to D, and so on. Thus this single 1 will shift down the
register, traveling from one flip-flop to the next flip-flop each time the clock goes high. When it reaches flip-
flop H, the next clock PT will shift it into flip-flop A by means of the feedback connection. Again, consider the
register as a tube full of ping-pong balls, seven "white" ones (Os) and one "black" one (a 1). The ping-pong
balls simply circulate around the register in a clockwise direction, moving ahead one flip-flop with each clock
PT. This configuration is frequently referred to as a circulating register or a ring counter. The waveforms
present in this ring counter are given in Fig. 9.20b.
Waveforms of this type are frequently used in the control section of a digital system. They are ideal for
controlling events that must occur in a strict time sequence-that is, event A, then event B, then C, and so on.
For instance, the logic diagram in Fig. 9.21 shows how to generate RESET, READ, COMPLEMENT, and
WRITE (a fictitious set of control signals) as a set of control pulses that occur one after the other sequentially.
The control signals are simply the outputs of flip-flips A, B, D, and E as shown in Fig. 9 .20.
There is, however, a problem with such ring counters. In order to produce the waveforms shown in Fig.
9 .20, the counter should have one, and only one, 1 in it. The chances of this occurring naturally when power
is first applied are very remote indeed. If the flip-flops should all happen to be in the reset state when power
(QA) RESET _fl_ _ _ __

RESET
(Qe) READ -W"l--
READ } Output ' I I
Control logic
COMPLEMENT signals (QD) COMPLEMENT _j_jJ__Il__
I J : I I
WRITE (Q.)WRITE , , : , n
E ~~
Time '
is first applied, it will not work at all, as we saw previously. On the other hand, if some of the flip-flops come
up in the set state while the remainder come up in the reset state, a series of complex waveforms of some kind
will be the result. Therefore, it is necessary to preset the counter to the desired state before it can be used.
Example 9 .10 shows one scheme how to do presetting when power is first applied.
Switched-Tail Counter or Johnson Counter

We have seen in ring counter what happens if non-inverting output of the first flip-flop is fed back to first :flip-
flop of the shift register. Ifwe instead feed inverting output back (or switch the tail) as shown in Fig. 9.22a for
a 4-bit shift register we get switched tail counter, also known as twisted tail counter or Johnson counter. The
-----<D
1 R D S
R s
CLK-~----t-'-----~---~
y
(a)
Clock Serial in= T Q R s T Y=Q'T'

0 1 0 0 0 0 1
1 1 1 0 0 0 0
2 1 1 1 0 0 0
3 I I I I 0 0
4 0 I 1 l l 0
5 0 0 I l I 0
6 0 0 0 I I 0
7 0 0 0 0 I 0
8 1 0 0 0 0 I
9 I I 0 0 0 0
repeats
(b)
(a) 4-bit switched tail counter, (b) Its state table

Registers
circuit is explained through state table similar to Fig. 9.3 of Section 9.2. Assume all the flip-flops are cleared
in the beginning. Then all the flip-flop inputs have Oexcept the first one, serial data in which is complement
of the last flip-flop, i.e. 1. When clock trigger occurs flip-flop stores QRST as I 000. This makes 1100 at the
input of QRST when the next clock trigger comes and that gets transferred to output at NT. Proceeding this
we complete state table of Fig. 9.22b. Note that output Y = Q'T' and state of the circuit repeats every eighth
clock cycle. Thus this 4-bit shift register circuit can count 8 clock pulses or called modulo-8 counter.
Following above logic and preparing state table for any N-bit shift register we see switched-tail configuration
can count up to 2N number of clock pulse and gives modulo-2N counter. The output Y, derived similarly by
AND operation of first and last flip-flop inverting outputs gives a logic high at every 2N-th clock cycle.
This two-input AND gate which decodes states repeating in the memory units to generate output that signals
counting of a given number of clock pulses is called decoding gate. For switched-tail counter of any modulo
number we need only a 2-inputAND gate. Observing the state sequences in Fig. 9.22b we find logic relation
like Y = QR' or Y = RS' or Y = ST', etc. can also be used for decoding purpose as they generate Y = I only
once during 2N clock cycles. Note that for ring counter we don't need any decoding gate and clock pulse
count can directly be obtained from any one flip-flop output. We shall discuss other counter design techniques
in Chapter 10, which require less number of flip-flops for a particular modulo number. But, there decoding
complexity increases with increasing number of flip-flops. For example, a modulo-8 counter is possible to
design with log28 = 3 number of flip-flops but we need a 3 input AND gate to decode the counter. Similarly,
modulo-16 counter requires 4 flip-flops and 4 input AND gate for decoding.
There is another important issue related with ring counter and switched tail counter. An n-bit register
has 211 different combination of states. But, the counter is to be initialized with one of the valid state of the
counting sequence on which the design is based. Otherwise, the counter will follow a completely different
state sequence (mutually exclusive) and decoding will not be proper. Solve Problem 9.25 to get an idea
on what happens if circuit in Fig. 9.22a is initialized with a word outside the state sequence appearing in
Fig. 9.22b.
Sequence Generator and Sequence Detector

Sequence generator is useful in generating a sequence pattern repetitively. It may be the synchronizing hit
pattern sent by a digital data transmitter or it may be a control word directing repetitive control task. Sequence
detector checks binaiy data stream and generates a signal when a particular sequence is detected.
Figure 9.23a gives the basic block diagram of a sequence generator where shift register is presented as
pipe full of data and each flip-flop represents one compartment of it. The leftmost flip-flop is connected to
serial data in and rightmost provides serial data out. The clock is implied and data transfer takes place only
when a clock trigger arrives. Note that the shift register is connected like a ring counter and with triggering
of clock the binary word stored in the clock comes out sequentially from serial out but does not get lost as it
is fed back as serial in to fill the register all over again. Sequence generated for binary word 1011 is shown in
the figure and for any n-bit long sequence to be generated for this configuration we need to store the sequence
in an n-bit shift register.
The circuit that can detect a 4-bit binary sequence is shown in Fig. 9.23b. It has one register to store the
binary word we want to detect from the data stream. Input data stream enters a shift register as serial data
in and leaves as serial out. At every clocking instant, bit-wise comparisons of these two registers are done
through Ex-NOR gate as shown in the figure. Two input Ex-NOR gives logic high when both inputs are low
or both of them are high, i.e. when both are equal. The final output is taken from a four input AND gate,
which becomes 1 only when all its inputs are 1, i.e. all the bits are matched. Figure 9.23b shows a situation
~~-~-0-~-~~~ -------- lQlllQll

(a)
Serial data in _ _....,
Sequence to be detected
(b)
(a) 4-bit sequence generator, (b) 4-bit programmable sequence detector
when data received so far is O111 and word to be matched is 1011. The first two bits are mismatched and
corresponding Ex-NOR outputs are low, so also final output Y. Now, as the next bit in the serial data stream is
1 when a clock trigger comes the first flip-flop of the shift-register stores 1 and O11 gets shifted to 2nd to 3rd
flip-flops. With this both registers store 1011 and the first flip-flop of the shift-register stores 1 and 011 gets
shifted to 2nd to 3rd flip-flops and Y = l completing sequence detection.
Note that Fig. 9.23b can be used as a programmable sequence detector, i.e. ifwe want to change the binary
word to be detected we simply load that in the bottom register. For a fixed sequence detector, we can reduce
hardware cost by removing bottom register and directly connect Ex-NOR input to +Vee or GND depending
on whether we need a 1 or a Oto be detected in a particular position.
Serial Adder
The addition operation and full adder (FA) circuit is discussed in detail in Chapter 6. We have seen for 8-bit
addition we need 8 FA units (Fig. 6.6). There the addition is done in parallel. Using shift register we can
convert this parallel addition to serial one and reduce number of FA units to only one. The benefit of this
technique is more pronounced if the hardware unit that's needed to be used in parallel is very costly. Figure
9.24 shows how serial addition takes place in a time-multiplexed manner and also provides a snapshot of the
register values at 3rd clock cycle:
Two 8-bit numbers, to be added (A 7A6 ...A 1A0 and B7 B6···B 1Bo) are loaded in two 8-bit shift registers A
and B. The LSB of each number appears in the rightmost position in two registers. Serial data out of A and B
are fed to data inputs of full adder. The carry-in is fed from its own carry output delayed by one clock period
Registers
Serial in ~ r
SI So A7 A6 A5 A4 A3 A2
Serial out
~A
Full adder
I S; -
s2
B2
B;
c-
I
C;-1 C; ,_. C
2
Serial in
"
>
X X B7 B6 B5 B4 B3 B2
-Serial out
- Q D -
<o--
CLK
Serial addition of two 8-bit numbers (Register values shown are at 3rd
clock cycle)
by a D flip-flop, which is initially cleared. Both registers and D flip-flop are triggered by same clock. The sum
(S) output ofFA is fed to serial data in of Shift Register A.
The serial addition takes place like this. The LSBs of two numbers (Ao and Bo) appearing at serial out
of respective registers are added by FA during 1st clock cycle and generate sum (S0) and carry (C0). S0 is
available at serial data input of register A and C0 at input of D flip-flop. At NT of clock shift registers shift
its content to right by one unit. S0 becomes MSB of A and C0 appears at D flip-flop output. Therefore in the
second clock cycle FA is fed by second bit (A I and B 1) of two numbers and previous carry ( C0). In second
clock cycle, S 1 and C 1 are generated and made available at serial data in of A register and input of D flip-flop
respectively. At NT of clock S 1 becomes MSB of A and So occupies next position. A 2 and B 2 now appear
at FA data input and carry input is C 1. In 3rd clock cycle, S2 and C2 are generated and they get transferred
similarly to register and flip-flop. This process goes on and is stopped by inhibiting the clock after 8 clock
cycles. At that time shift register A stores the sum bits, S7 in leftmost (MSB) position and So in rightmost
(LSB) position. The final carry is available at D flip-flop output.
The limitation of this scheme is that the final addition result is delayed by eight clock cycles. In parallel
adder the result is obtained almost instantaneously, after nanosecond order propagation delay of combinato-
rial circuit. However, using a high frequency clock the delay factor can be reduced considerably.
The register in Fig. 9.20 can easily be cleared to all Os by using the clear input. Show one
method for setting a single 1 and the remaining Os in the register.
So,lutiofi( The simple I>~wer-o~-re~et drc~it lllFig. 9 25a on the next page is widely used togenerate th~ equivalent
ot·.a· narr1c>w negative pulse that occurs when power (+ Vcc) is first applied to the system.. Before the application of
power, voltage across the capacitor is zero. When + Vcc is applied, the capactt.or Voltage charges 1:owa1'd + Vcc
w~~RCtillleconstru.l.t,andthe~remains ~t +Vee as·lon~as ~hegyste111powerremains, asseen ~y the.waveform
inthefigt1re. IfpolntAis then~onnected to the clearinput of the 54/74164,all flip-flops will automatically be reset
to Os when+ Vcc is first applied.
To CLEAR
----A
Power
ON
(a) Power-on-reset circuit
From Power-on-reset above
CLEAR --1111---a
CLOCK
A
'--------1R X
(b)
54/7 4164 with logic to preset a single 1 and seven Os
The logic added in the feedback path in Fig. 9.25b will now cause a single I to be set into the register. Here's how
it works:
The power-on-reset pulse is inverted and used to initially set flip-flop X This causes the output of the OR gate
to be a 1, and the first clock PT will shift this 1 into QA.
2. When QA goes high, this will reset flip-flop X At this point, the register contains a 1 in QA, and O's in all other
flip-flops. X will remain low as long as power is applied, and the data from QH will pass through the. OR gate
directly to the data input AB. The single 1 and the seven Os will now shift around the register, advancing one
position with each clock transition as desired.
Since the ring counter in Fig. 9.20 can function with more than a single 1 in it, it might be desirable
to operate in this fashion at some time or other. It can, for example, be used to generate a more complex
control waveform. Suppose, for instance, that the wavefom1 shown in Fig. 9.26 were needed. This waveform
Registers
could easily be generated by simply presetting the Clock

counter in Fig. 9.20 with a l in A, a 1 in C, and
all the other flip-flops reset. Notice that it is really Control
waveform
immaterial where the two 1s are set initially. It is desired
necessary only to ensure that they are spaced one
flip-flop apart.
How would you preset the ring counter in Fig. 9.20 to obtain a square-wave output which is
one-half the frequency of the clock? How about one-fourth the clock frequency?
Solution It is necessary only to preset a l in every other flip-flop, while the remaining flip-flops are all reset. This
will generate a waveform at each flip :flop output that is high for one clock period and then low for one clock period.
The period of the output waveform is then two clock periods; therefore, the frequency is one-halftl1e clock frequency.
An output signal at one-fourth the clock frequency can be generated by presetting tl~e shift register with two 1s, then
two Os, then two ls, and then two Os.
9. What is a ring counter?

lO. What is a power-on-reset circuit usedfor?
11. What is a switched tail counter?
12. How does a serial adder work?
9.8 REGISTER IMPLEMENTATION IN HDl
In this section, we see how to describe a register using HDL. The parallel in parallel out register, primarily
used for storage purpose is described for IC 741174 (Fig. 9.15) in Verilog code in the first colunm. We use
vector notation for convenience. When Clear is activated (active LO\v) all 6 outputs of Qare reset.
In second column, we show code for shift right register shown in Fig. 9.5 where Tis the final output and Q,
R, Sare internal outputs. Since they are outputs of always block they have to be defined as reg and not wire.
Note that, we use a new assignment operator<= within always block which unlike = operator executes all
associated statements concurrently. If we had used= instead of<=, the D input through sequential execution
would have reached final output in one clock cycle (unlike 4 clock cycles required in 4-bit shift register), also
all the flip-flops within the register will have same value that of serial data input. Often, use of = operator
is called blocking mode operation and use of<= is called non blocking mode. In column 3, we show a 4-bit
serial in parallel out right shift register where all the flip-flop outputs are available externally. We use vector
notation for convenience wherever possible.
module SR2(D,Clock,Q);
input D; // input D; //Clear as
input Clock; output T; / / Clear as in output [3:0J Q; //in 74174
input reg T; // LHS to reg [3 :OJ Q;
output initia.lize
reg[5:0] Q; reg Q,
always@ (negedge Clock always @ (negedge Clock) always @ .(negedge

or negedge Clear)
if (-Clear) Q=6'b0; begin begin
/IQ stores 6 0 Q <= D; Q [OJ <= D.;
else Q=D; R <= Q· Q [ 1 l <= Q[O];
'
endmodule s <= R; Q[2] <= Q[1];
T <= S; Q[3] <= };
end end
endmodule endmodule
Write Verilog code for switched tail counter shown in Fig. 9.24.
Solution The code is similar to Shift Register description given above in second column. The serial data inputhere
is taken from inverse of final flip-flop output. Output is generated from decoding logic Y = Q' T'.
module STC(Clock,Clear,Y); //Switched Tai.l Counter

input Clock, Clear;
output Y;
reg Q,R,S,T; I/internal outputs of flip-flops
assign Y= (-Q)&(-T);
always@ (negedge Clock)
begin
if (-Clear) Q=6'b0; /IQ stores 6 0
else
begin
Q <= "'T; is switched and to
R <= Q;
S <= R;
T <= S;
end
endmodule
PROBLEM sotVING WITH MU[TIPU: METHODS

Design an 8-bit sequence generator that generates the sequence 11000 l 00 repetitively using
shift register.
Solution We use ring counter and switched-tail counter derived from shift registers for this purpose.
In Method-1, we load an 8.-bit ring counter as shown in Fig. 9.27a with the given sequence and.at
the output, the sequence will be repetitively generated.
In Method-2, we consider a modulo-8 switched-tail counter developed from 4-bit shift re~ister.
Let it be initially loaded with 0000. Then the 8 repetitive states of the cotmtcr will be as shown in Fig.
9.27b and is reproduced in Fig. 9.27c. We then design a combinatorial circuit which for each of the
state generates one bit of the sequence. The KamaughMapforthisis shown in Fig. 9.27& Note that the
unused states can be considered as 'don;t care'. The logic equation of the combinatorial circuit realized
as Fig. 9 .27b can be written as Y =A' D' +A'B + AB'
0 0 0 0
A B C D
I I I I IOI
O O O O
hktput. r
Combi.natmial
Circuit ---
Output, Y
(a) (b)
Counter Sequence Generator

A B CD Output, Y
CD 00 01 11 10
1 0 0 0 l AB
00 0 A'D'
1 1 0 0 0
I I 1 0 0 01 A'B
l 1 1 ] 0
() I 1 1 1 11 0 X 0 0
0 0 1 1 0
0 0 0 1 0
IO :-1-
i __
X
---
-X- X
_ _ _ _ _ _I
1
AB'
0 0 0 0 Y=A'D'+A'B+AB'
(c) (d)
(a) Solution with Method-1, (b)-(d) Solutfonwith Method-2, (b) Targeted

realization, (c) Counter sequence vs. sequence generator output, (d)
Karnaugh Map to generate logic equation
Note that Method-2 can be used with any other types of counter and is not restricted to shift register
based counter. T!J.is is shown with Example 10.15 in next Chapter.
Shift registers are important digital building blocks that can be used to store binary data. They can accept
data bits in either a serial or a parallel format and can, likewise, deliver data in either serial or parallel.
There are thu~ four basic register types; serial input-serial output, serial input-parallel output, parallel
input-serial output, and parallel input-parallel output.
In one application, a register can be used to change data from a serial format into a parallel format, or vice
versa. As such,. shift registers can be regarded as data format changers. The UART is a good example of a data
changer.There are a great many other shift register applications-arithmetic operations, logic operations,
and com:1ters, to name only a few. Our intent has not been to discuss all the possible applications of shift
registers, but rather to consider in detail how each type ofregister functions; With this knowledge, one can
then discover the many and varied practical applications in existing digital designs.
• Johnson counter Refer to switched-tail transitions are needed to shift an n-bit binary
counter. number.
• parallel shift Data bits are shifted simultane- • sequence detector Detects a binary word from
ously with a single clock transition. input data stream.
• register capacity Determined by the number • sequence generator Generates a binary data
of flip-flops in the register. There must be sequence.
one flip-flop for each binary bit; the register • serial adder Converts parallel data to serial
capacity is 2'1, where n is the number of flip- and use adder block sequentially.
flops. • switched tail counter Shift register with
• ring counter A basic shift register with direct inverting output of last flip-flop fed to first
feedback such that the contents of the register flip-flop input. For n-bit shift register can give
simply circulate around the register when the modulo 2N counter.
clock is running. • shift register A group of flip-flops connected
11 serial shift Data bits are shifted one after the
in such a way that a binary number can be
other in a serial fashion with one bit shifted shifted into or out of the flip-flops.
at each clock transition. Therefore, n clock • UART Universal asynchronous receiver-
transmitter.
PROBLEiviS
9 .1 Determine the number of flip-flops needed to 9 .4 Draw the waveforms to shift the binary
construct a shift register capable of storing: number 1010 into the register in Fig. 9.2.
a. A 6-bit binary number 9 .5 Draw the waveforms to shift the binary
b. Decimal numbers up to 32 number 1001 into the register in Fig. 9.3.
c. Hexadecimal numbers up to F 9.6 The register in Fig. 9.2 has 0100 stored in it.
Draw the waveforms for four clock transitions,
9.2 A shift register has eight flip-flops. What
assuming that both J and Kare low.
is the largest binary number that can be
9. 7 Draw the waveforms showing how the decimal
stored in it? Decimal number? Hexadecimal
number 68 is shifted into the 54/74LS91 in
number?
Fig. 9.5. Show eight clock periods.
9.3 Name the four basic types of shift registers,
9.8 The hexadecimal number AB is stored in
and draw a block diagram for each.
the 54/74LS91 in Fig. 9.5. Show the
Registers
waveforms at the output, assuming that the in:

clock is allowed to run for eight cycles and a. Parallel b. Serial
thatA =B =O.
9.18 Redraw the 5417495A shift register in Fig.

9.9 How long will it take to shift an 8-bit binary 9.15 showing only those gates used to shift
number into the 54/74164 in Fig. 9.7 if the data into the register in parallel. If a gate is
clock is: disabled, don't draw it.
a. 1 MHz b. 5 MHz 9.19 Repeat Prob. 9.18, assuming that the data is
9.10 For the 54/74164 in Fig. 9.7, B is high, shifted in serially.
clear is high, a 1-MHz clock is used to shift 9.20 Draw the waveforms necessary to enter, and
the decimal number 200 into the register shift to the right a single 1 through the shift
at A. Draw all the waveforms (such as in register in Fig. 9.15.
Fig. 9.9). 9.21 Repeat Prob. 9.20, but do a left shift.(See Fig.
9.11 On the basis of information in Example 9.16.)
9.5, what is the maximum frequency of the
clock if the minimum data transition time is
30 ns? 9.22 Draw the waveforms that would result if the
9.12 In Fig. 9.9, if control is taken low at time K, circulating register (ring counter) in Fig. 9.20
will the data stored in the register remain even had alternate 1s and Os stored in it and a 1-
if the clock is allowed to run? Explain. MHz clock.were applied.
9.23 The register in Fig. 9.20 can easily be cleared
to all Os by using the clear input. See if you
9.13 For the circuit in Fig. 9.llc, write the logic can design logic circuitry to set the register
levels on each gate leg, given: with alternating ls and Os.
9.24 Explain the operation of the 54/74165
a. Control= 1, X1 = 0, X2 = l
shift register. Redraw one of the eight flip
b. Control= 0, X1 = 0, X2 = 1
flops along with its two NAND gates, and
9.14 Redraw the 54/74166 in Fig. 9.10 showing analyze:
only those gates used to shift data into the
a. Parallel data entry
register in parallel. If a gate is disabled, don't
draw it. b. Shift right
9.15 Redraw the 54/74166 in Fig. 9.10 showing c. Serial data entry
only those gates used to shift data into the The logic diagram is given in Fig. 9.28 on the
register in serial. If a gate is disabled, don't next page.
draw it. 9.25 Show how modulo-8 switched tail counter works
9.16 Explain the operation of the 54/74166 for each if is initialized with '100 I'. How to decode this
ofthe six truth table entries in Fig. 9.12. counter?
9.17 Draw all the input and output waveforms for 9.26 Show the circuit diagram for an 8-bit sequence
the 54/74166 in Fig. 9.10, assuming that the detector which has to detect a fixed pattern
decimal number 190 is shifted into the register '100111 IO' from incoming binary data stream.
~ _ _ _ _ _ _ _ _ _ _ _ _ _ _D_ig_it_al_P_n_·nc_ip_le_s_a_n_d_A_pp_ll_·ca_t1_·on_s_ _ _ _ _ _ _ _ _ _ _ __
Parallel
inputs
Pin numbers shown are for J and N packages.

(a) Logic diagram (positive logic)
Clock
CLKJNH
L
SER----------'------------------
SH/LD
r:
D
Data
E
F
I
G _Jfi:il
I
I
H_lTm
I
I
----
QH ---- H H
QH ~=== L L
I-Inhibit - - - - - - - - Serial shift ~ - - - - ' - - - - ' - + i

Load
(b) Typical shift, load, and inhibit sequences
54/74165, 8-bit shift register

Registers
AIM: The aim ofthisexperimentisto study another in a sequential manner. The loading of
Shift Register and u.se it fo. get Ring Counter shift register may be done serially or parallely.
and Johnson Counter. In serial loading as many number of clock
cycles are required as the size ofthe register to
The9ry.: The ~hifi register is a.special kind load it fully. h1 parallel loading,. all the memory
of register, i.e. gr(}up of memory units where units are loaded simultaneously in one clock
binary.data can.be shifted from.one unit to cycle. The data within·· the register can be
Outputs Clock2
Clock l L shift
Vee Q.4 QB Qe QD R shift (load)
9 8
Q.4 QB Qe QD CKI CK2
Serial input 7495

A B C D Mode
Serial A B Mode GND

input control
Inputs
Serial data input
(95, 'LS95) ('L95) Data inputs

A D
(2)(14) (5)(5)
Clock 1
right shift - - - i - - ; _ _ . . /
Clock 2 ----L-J
left shift
(13)(13) (12)(12) (11)(10) (10)(9)

QA QB Qe QD
Outputs
Work element: IC 7495 js a 4-bit shift

register with a mode control that.allows
1. 255 9. A dh;ect-feedback shift register-the

2. PTs 1::011tents.of the register circulate around. the
3. 30 ns registerw~en the. clock is running.
4. Eight; one 10. A power-9n.creset circuit is used
The shift/load line on the 74166 allows t?
fiip-flopg ~Y desired states.
either serial or parallel data entry. Swit5hedtailcounter .. shift registerwith
6. PTs inv?rting oµtput ofJast flip-flop fed to fkst
7. Two.7495As connectedinserieswiUstore fiip,.flopdnput. For• n-'bif shift Jt:~ster this
8 bit numbers. configuration .can.give modulo 2Ncounter;
8. Tl1t1.7495:A, llas geparate clock inpµts to 12. Serial.adder.converts.~araUeldatato serial
accommodate separate %hift..rigl1t and using shift register and. performs addition
shift-left signals. sequentialli•·~in~.a~ ru.i<lerblock,
Counters
+ Describe the basic construction and operation of an asynchronous counter

+ Determine the logic circuit needed to decode a given state from the output of a given
counter
+ Describe the synchronous counter and its advantages
+ See how the modulus of a counter can be reduced by skipping one or more of its
natural counts
+ Understand how to design counter as a finite state machine
A counter is probably one of the most useful and versatile subsystems in a digital system. A counter driven
by a clock can be used to count the number of clock cycles. Since the clock pulses occur at known intervals,
the counter can be used as an instrument for measuring time and therefore period or frequency. There are
basically two different types of counters-synchronous and asynchronous.
The ripple counter is simple and straightforward in operation and its construction usually requires a
minimum of hardware. It does, however, have a speed limitation. Each flip-flop is triggered by the previous
flip-flop, and thus the counter has a cumulative settling time. Counters such as these are called serial, or
asynchronous.
An increase in speed of operation can be achieved by use of a parallel or synchronous counter. Here, every
flip-flop is triggered by the clock (in synchronism), and thus settling time is simply equal to the delay time of
a single flip-flop. The increase in speed is usually obtained at the price of increased hardware.
Serial and parallel counters are used in combination to compromise between speed of operation and
hardware count. Serial, parallel, or combination counters can be designed such that each clock transition
advances the contents of the counter by one; it is then operating in a count-up mode. The opposite is also
possible; the counter then operates in the count-down mode. Furthermore, many counters can be either
"cleared" so that every flip-flop contains a zero, or preset such that the contents of the flip-flops represent any
desired binary number.
Now, let's take a look at some of the techniques used to construct counters.
10.1 ASYNCHRONOUS COUNTERS

Ripple Counters
A binary ripple counter can be constructed using clocked JK flip-flops. Figure 10.1 shows three negative-
edge-triggered, JK flip-flops connected in cascade. The system clock, a square wave, drives flip-flop A. The
output ofA drives B, and the output of B drives flip-flop C. All the] andK inputs are tied to +Vee· This means
that each flip-flop will change state (toggle) with a negative transition at its clock input.
+Vee
Negative State
_n_n_ J A J B J C clock or
Clock transitions C B A count
K A K lJ K c 0 0 0 0
A B C a 0 0
Outputs b 0 0 2
(a) Three-bit binary ripple counter C 0 1 3
a b d e .r g h j d 0 0 4
r
C
Time
t i l i i l l t l e I 0 5
Clock
A
.r 1 0 6
g 1 7
B
h 0 0 0 0
C
(b) Waveforms (c) Truth table
When the output of a flip-flop is used as the clock input for the next flip-flop, we call the counter a ripple
counter, or asynchronous counter. The A flip-flop must change state before it can trigger the B flip-flop, and
the B flip-flop has to change state before it can trigger the C flip-flop. The triggers move through the flip-flops
like a ripple in water. Because of this, the overall propagation delay time is the sum of the individual delays.
For instance, if each flip-flop in this three-flip-flop counter has a propagation delay time of 10 ns, the overall
propagation delay time for the counter is 30 ns.
The waveforms given in Fig. 10.l b show the action of the counter as the clock runs. Let's assume that the
flip-flops are all initially reset to produce O outputs. If we consider A to be the least-significant bit(LSB) and
C the most-significant bit (MSB), we can say the contents of the counter is CEA = 000.
Every time there is a clock NT, flip-flop A will change state. This is indicated by the small arrows ( .! ) on
the time line. Thus at point a on the time line, A goes high, at point b it goes back low, at c it goes back high,
and so on. Notice that the waveform at the output of flip-flop A is one-half the clock frequency.
Counters
Since A acts as the clock for B, each time the wavefonn at A goes low, flip-flop B will toggle. Thus at point
b on the time line, B goes high; it then goes low at point d and toggles back high again at point f Notice that
the waveform at the output of flip-flop Bis one-half the frequency of A and one-fourth the clock frequency.
Since B acts as the clock for C, each time the waveform at B goes low, flip-flop C will toggle. Thus C goes
high at point don the time line and goes back low again at point h. The frequency of the waveform at C is
one-half that at B, but it is only one-eighth the clock frequency.
What is the clock frequency in Fig. I 0.1 if the period of the waveform at C is 24 µs?
Solution Since there are eight clock cycles in one cycle of C, the period of the clock must be 24/8 = 3 µs. The clock
frequency must then be l/(3 x 10""6) = 333 kHz.
Notice that the output condition of the flip-flops is a binary number equivalent to the number of clock
NTs that have occurred. Prior to point a on the time line the output condition is CBA = 000. At point a on the
time line the output condition changes to CBA = 001, at point b it changes to CBA = 010, and so on. In fact, a
careful examination of the wavefom1s will reveal that the counter content advances one count with each clock
NT in a "straight binary progression" that is summarized in the truth table in Fig. 10.1 c.
Because each output condition shown in the truth table is the binary equivalent of the number of clock
NTs, the three cascaded flip-flops in Fig. 10.1 comprise a 3-bit binary ripple counter. This counter can be
used to count the number of clock transitions up to a maximum of seven. The counter begins at count 000 and
advances one count for each clock transition until it reaches count 111. At this point it resets back to 000 and
begins the count cycle all over again. We can say that this ripple counter is operating in a count-up mode.
Since a binary ripple counter counts in a straight binary sequence, it is easy to see that a counter having
n flip-flops will have 211 output conditions. For instance, the three-flip-flop counter just discussed has 23 = 8
output conditions (000 through 111). Five flip-flops would have 25 = 32 output conditions (00000 through
11111 ), and so on. The largest binary number that can be represe:1ted by n cascaded flip-flops has a decimal
equivalent of 211 - 1. For example, the three-flip-flop counter reaches a maximum decimal number of 23 - 1.
The maximum decimal number for five flip-flops is 2 5 - l = 31, while six flip-flops have a maximum count
of 63.
A three-flip-flop counter is often referred to as a modulus-8 (or mod-8) counter since it has eight states.
Similarly, a four-flip-flop counter is a mod-16 counter, and a six-flip-flop counter is a mod-64 counter. The
modulus of a counter is the total number of states through which the counter can progress.
How many flip-flops are required to construct a mod-128 counter? A mod-32? What is the
largest decimal number that can be stored in a mod-64 counter?
Solution Amod-1!8 c.ounter must have seven flip flol)s, since 27 = 128, Five flip-flopsar~ needed to construct a
0
modl32 coi.mter. The1argestdecima1 numbenhatcan be stored ina six-mp-flop cou~ter{mod-64)is1mn = 63.

Note carefully the difference between the modulus (total number of states) and the maximum· decimal number.
The 54/7493A
The logic diagram, DIP pinout, and truth table for a 5417493A are given in Fig. 10.2. This TTL MSI circuit is
a 4-bit binary counter that can be used in either a mod-8 or a mod-16 configuration. If the clock is applied at
input CKB, the outputs will appear at Qs, Qc, and Qn, and this is a mod-8 binary ripple counter exactly like
that in Fig. 10.L In this case, flip-flop QA is simply unused.
('93A) ['L93] 7493A Qe

(12)
J Q QA
CKA (14)
CK
K
CKB RO(I) R0(2) NC Vee NC
(9) Positive logic: see function tables
fl)
J Q QB NC - No internal connection
CKB · CK
(b) DIP pinout
K
'L93A, 'L93, 'LS93 Count
sequence
Count Output
Qe QD Qe QB QA
0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
K 8 H L L L
9 H L L H
IO HLHL
11 H L H H
12 H H L L
13 H H L H
14 H H H L
15 H H H H
(a) Logic diagram (c) Truth table
7493A
On the other hand, if the clock is applied at input CKA and flip-flop QA is connected to input CKB, we
have a mod-16, 4-bit binary ripple counter. The outputs are QA, QB, Qc, and QD. The proper truth tablefor
this connection is given in Fig. 10.2c.
All the flip-flops in the 7493A have direct reset inputs that are active low. Thus a high level at both reset
inputs of the NAND gate, Ro(I) and Rocz), is needed to reset all flip-flops simultaneously. Notice that this reset
operation will occur without regard to the clock.
Draw the correct output waveforms for a 7493A connected as a mod-16 counter.
Solution .The correct waveforms are shown. in Fig.1 o.t The fu11fents Of'tlie C\Jlltif~r is 0000 afpoirlt bon'ilie tint(·.
line. With each negative clock transition, the counter is advanced· by one '1Util the. counter contents.are H 1. l at ~int·.
Counters
counting :.eque11ce rep~ts. Clti,arly, this is a mod-1.6

the.maKimtum decimal number that can be stored in the
An interesting and useful variation of the 3~bit ripple counter in Fig. 10.1 is shown in Fig. 10.4. The
system clock is still used at the clock input to flip-flop A, but the complement of A, A, is used to drive flip-
flop B, likewise; B is used to drive flip-flop C. Take a look at the resulting waveforms.
+~~-----------~
Count C B A
7 1 1
6 0
A B 5 0 1
(a) 4 0 0
---
3 0
a b C d e f g h
Time • 2 0 1 0
Count l l l l l l l l t 1 0 0
clock 0 0 0 0
A
---
7
B_j
C
(b) (c)
A down counter
Flip-flop A simply toggles with each negative clock transition as before. But flip-flop B will toggle each
time A goes high! Notice that each time A goes high, A goes low, and it is this negative transition on A that
triggers B. On the time line, B toggles at points a, c, e, g and i.
Similarly, flip-flop C is triggered by B and so C will toggle each time B goes high. Thus C toggles high at
point a on the time line, toggles back low at point e and goes back high again at point i.
The counter contents become ABC= 111 at point a on the time line, change to 110 at point b, and change to
101 at point c. Notice that the counter contents are reduced by one count with each clock transition! In other
words, the counter is operating in a count-down mode. The results are summarized in the truth table in Fig.
10.4c. This is still a mod-8 counter, since it has eight discrete states, but it is connected as a down counter.
A 3-bit asynchronous up-down counter that counts in a straight binary sequence is shown in
Fig. 10.5. It is simply a combination of the two counters discussed previously. For this counter to progress
through a count-up sequence, it is necessary to trigger each flip-flop with the true side of the previous flip-flop
(as opposed to the complement side.). If the count-down control line is low and the count-up control line high,
this will be the case, and the counter will have count-up waveforms such as those shown in Fig. 10.1.
A B C
Note: The J and K inputs are all tied to +Vcc·

The counter outputs are A, B, and C.
3-bit binary up-down counter
On the other hand, if count-down is high and count-up is low, each flip-flop will be triggered from the
complement side of the previous flip-flop. The counter will then be in a count-down mode and will progress
through the waveforms as shown in Fig. 10.4.
This process can be continued to other flip-flops down the line to form an up-down counter of larger
moduli. It should be noticed, however, that the gates introduce additional delays that must be taken into ac-
count when detem1ining the maximum rate at which the counter can operate.
1. What is the largest binary number representable by a mod-6 ripple counter?

2. How many flip-flops are required to construct a mod- I 024 ripple counter?
10.2 DECODING GATES
A decoding gate can be connected to the outputs of a counter in such a way that the output of the gate will
l,t high (or low) only when the counter contents are equal to a given state. For instance, the decoding gate
connected to the 3-bit ripple counter in Fig. 10.6a will decode state 7 ( CBA = 111 ). Thus the gate output will
be high only when A = 1, B = I, and C = 1 and the waveform appearing at the output of the gate is labeled
7. The Boolean expression for this gate can be written 7 = CBA. A comparison with the truth table for this
counter (in Fig. IO.I) will reveal that the condition CBA = 111 is true only fo.· state 7.
The other seven states of the counter can be decoded in a similar fashion. It is only necessary to examine
the truth table for the counter and then the proper Boolean expression for each gate can be written. For
instance, to decode state 5, the truth table reveals that CBA = 101 is the unique state. For the gate output to
be high during this time, we must use C, B, and A at the gate inputs. Notice carefully that if B = 0, then B
.:iJ ! The correct Boolean expression is then 5 = CB A, and the desired gate is that given in Fig. 10.6c. The
""Nf<Jrm is again that given in Fig. 10.6b and is labeled 5.
Counters
J1SL J A J B J C
Clock
K A K B K c
7
(a) Decoding gate for state 7
Clock
A
B __ __,
c ______.... ' '

I I I I
~--~r-L
5
_______
7 _ _ _ _ _ _ _...___,___,,l.___ _ _ _ _ _
__,
(b) Wavefonns (c) Gate to decode state 5
All eight gates necessary to decode the eight states of the 3-bit counter in Fig. 10.1 are shown in Fig. 10. 7a.
The gate outputs are shown in Fig. 10. 7b. These decoded waveforms are a series of positive pulses that occur
in a strict time sequence and are very useful as control signals throughout a digital system. If we consider
state O as the first event, then state 1 will be the second, state 2 the third, and so on, up to state 7. Clearly the
counter is counting upward in decimal notation from O to 7 and then beginning over again at 0.
iD-o iD- iD-2 iD-3

C C C C
iD-4 'D- ~D-6 ~D-7

C C C C
(a) Gates
Clock
A
B _ ___.
c _____ ~
0 0
1 _ _ _ _ _ _ _ _ ___,
1
2 _ ___, 2 _ _ _ _ _ _ _ _....
3 _ _ _ __. 3 _ _ _ _ _ ____.
4 _ _ _ _ ___, 4 _ _ _ _ ! L _ __ _ _ _ _ _ __
s ________, s ___. . . . . .,
6 _ _ _ _ _ _ _ __,
? _ _ _ _ _ _ _ _ _...........,
6 __ __,
7
(b) Count-up mode ( c) Count-down mode
Decoding gates for a 3-bit binary ripple counter

If these eight gates are connected to the up-down counter shown in Fig. 10.5, the decoded waveforms will
appear exactly as shown in Fig. 10. 7b, provided the counter is operating in the count-up mode. If the counter
is operated in the count-down mode, the decoded waveforms will appear as in Fig. 10. 7c. In this case, if state
0 is considered the first event, then state 7 is the second event, then state 6, and so on, down to state 1. Clearly
the counter is counting downward in decimal notation from 7 to O and then beginning again at 7.
Show how to use a 54LS11, triple 3-input AND gate to decode states !, 4, and 6 of the
counter in Fig. 10.5.
Solution The logic diagram and pinout for a54LS 11
in
is given Fig. 10.8. The correct Boolean expressions
forthedesireqst!lt~s are l = CBA ,4 = <7BA,and.6=
CB.A. Wu:itlgsfrom the counterftip-ifop outputs to the
chip is given in Fig. 10.8.
Let's take a more careful look at the waveforms
g?J.~r!lted l>y th~ ~ounter in Fig. l05 as it operates
in the count~up ·mode. The dock and each flip-flop
output are redrawn in Fig. J0.9, and the propagadon
delay time of each flip-flop is taken into account. N0,;-.,
tic~ ca~efyllY th~t}lle clockjs the ~gge~ !or flip-flop
1
~rand. the wavefornds thus delayed by fp frolll the
· negative clock"transition. For reference purposes,
complementofA, A, is also shown. Naturall)'itis the
exactmirrorimageofA,
Since A acts as the trigger for B, the B waveform is
delayed.by onefiip-'flop del!ly time.from the ~eg!lti~e
transition of A, ·Simil,irly, 1the G'wayeform isdelayed
by tp from each neglltive transition ofB,
At first glance,th se delay times wo~ld~eem to . offer no Inore sedoµs. problem than a s11eed limitation ·for the
7
counter, but a closer examiriatio11 reveals a much ll}Ore serious pr?bl~m- When the de~?ging gates in Fig. 10.7 artl
connected to this counter (or, indeed,when decoding gates arr connected to any ripple counter}, glitcnes may appear
at the outputs of one ormore of the gates. Consider, for insfance; the gate used to decode state 6/fhe proper Bo0lean
expressio11 CB A.. So, in Fig. I0.9the correct output waveform gate is hlghonlywllen C= l, B =
and.A=l .
.•. . ·. J3ut l<>ok at the glitcll that occurs when the counter progresses fyom state 7 t<> state 0. On the tim(l!in.e, A goes 1?\V
(,A goes high) atpoint a. Because pf ffip-flqp delay. time, however, B does not goiow until P?int b 011the time line!
Thus between points aandb on the time line we.have the condition C= 1,B = l, and A = I-therefore, the gate output
is µigb., and we have aglitchJLookatthe w1.1.veform 6 =CB.A. .
.Depending <>n fi?wthe decoder gate outputs are used, the ~itches (or unwanted pulstls) may(lr may'not be a
problem, Admittedly.~e g!Itches are only. a f(:w nanosecondswideand may. e.ven be very.diffic~lt to observe.on an
Ol>cilloscope, But TIL is veryf~,, ;md TIL circuits will respon<i to (lyen tlle smallest .glitclles...:.:..us®lly wlle11 you
~~~t.l;l;pecti~ W1d !!1'vay~ lit un\\'.anted tiilles! Tlierefore, you Illust l)erv~e t(} ayoi<i this condition, i1lere ~e.,1tleast
1,,V? ~olutiq~to tlle ?liti;fipr<;>bl!!ll};i)n~ ll}ethod in.volves. strobin.g the gates;w~ discuss that technique her~. A second
metho~isto use synchronous counters; we consider that topic in the next section. . . . .
a Ill is
c:onsi<ier using 4-i11put. AND gate tl:l ctec()de· state 6 as shown Fi~.. m:91>, wheret1ie. cloc~ now. ~~~as a
§ttobe, An e"'~Wll~i<>~.o{~~ }V<LV!!forms in this figure clearly reveals that the•.fl<>Gk:Js 1())-YPet,rfen points a and b on
the timeJine. Since the clock must be high for the gate output to be high, the glitch cann9t possibly occur! On the other
Counters
The ripple counter is the simplest to build, but there is a limit to its highest operating frequency. As previously
discussed, each flip-flop has a delay time. In a ripple counter these delay times are additive, and the total
"settling" time for the counter is approximately the delay time times the total number offlip-flops. Furthermore,
there is the possibility of glitches occurring at the output of decoding gates used with a ripple counter. The
first problem fully and the second problem, to some extent can be overcome by the use of a synchronous
parallel counter. The main difference here is that every flip-flop is triggered in synchronism with the clock.
Note that strobing as the solution to glitches has been discussed before in a separate subsection of Section
7.7 of Chapter 7.
The construction of one type of parallel binary counter is shown in Fig.10.10, along with the truth table
and the waveforms for the natural count sequence. Since each state corresponds to an equivalent binary
number (or count), we refer to each state as a count from now on. The basic idea here is to keep the J and K
Clock~~--<1t--+-i:x:>
_n_n_
(a)
C B A Count
0 0 0 0 a b c d e f g h i
0 0 I I Time
Count O t 1 t 2 t 3 t 4 t 5 t 6 t 7 t O t
0 1 0 2
0 I 1 3 Clock
-----
l
---
0
--
0
-----·
4 A
1 0 I 5
1 I 0 6 B
1 l l 7 C
0 0 0 0
(b) (c)
Mod-8 binary counter with parallel clock input
inputs of each flip-flop high, such that the flip-flop will toggle with any clock NT at its clock input. We then
use AND gates to gate every second clock to flip-flop B, every fourth clock to flip-flop C, and so on. This
logic configuration is often referred to as "steering logic" since the clock pulses are gated or steered to each
individual flip-flop.
The clock is applied directly to flip-flop A. Since the JK flip-flop used responds to a negative transition
at the clock input and toggles when both the J and K inputs are high, flip-flop A will change state with each
clock NT.
Whenever A is high, AND gate X is enabled and a clock pulse is passed through the gate to the clock
input of flip-flop B. Thus B changes state with every other clock NT at points b, d,f, and hon the time line.
Since, there is an additional AND gate delay for the clock at B flip-flop in comparison to A flip-flop, it is not
a parallel counter in a strict sense of the term.
Since AND gate Y is enabled and will transmit the clock to flip-flop Conly when both A and B are high,
flip-flop C changes state with every fourth clock NT at points d and h on the time line.
Examination of the waveforms and the truth table reveals that this counter progresses upward in a natural
binary sequence from count 000 up to count 111, advancing one count with each clock NT; This is a mod-8
parallel or synchronous binary counter operating in the count-up mode.
Let's see if this counter configuration has cured the glitch problem discussed previously. The waveforms
for this counter are expanded and redrawn in Fig. 10.11, and we have accounted for the individual flip-flop
propagation times. Study these waveforms carefully and note the following:
1. The clock NT is the mechanism that toggles each flip-flop.
2. Therefore, whenever a flip-flop changes state,· it toggles at exactly the same time as all the other flip-
flops-in other words, all the flip-flops change states in synchronism! ·
3. As a result of the synchronous changes of state, it is not possible to produce a glitch at the output of a
decoding gate, such as the gate for 6 shown in Fig. 10.11. Therefore, the decoding gates need not be
strobed. All the decoding gates in Fig. 10.7 can be used with this counter without fear of glitches!
Counters
Time
Clock
A
,,,, ,,,,
B :1
I :1 L
""
I
I
You should take time to compare these waveforms with those generated by the ripple counter as shown
in Fig. 10.9.
A parallel up-down counter can be constructed in a fashion similar to that shown in Fig. 10.12. In any
parallel counter, the time at which any flip-flop changes state is determined by the states of all previous flip-
flops in the counter. In the count-up mode, a flip-flop must toggle every time all previous flip-flops are in a 1
state, and the clock makes a transition. In the count-down mode, flip-flop toggles must occur when all prior
flip-flops are in a O state.
The counter in Fig. 10.12 is a synchronous 4-bit up-down counter. To operate in the count-up mode, the
system clock is applied at the count-up input, while the count-down input is held low. To operate in the count-
down mode, the system clock is applied at the count-down input while holding the count-up input low.
Count D
up
Count
down D
Note : All J and K inputs are tied to +Vcc-

(a) Logic diagram
Clock
A
B
C ______
--~ _,
D
(b) Count up waveforms
a b c d e f g h i J k I m n o P q
Time --.~~.-~.-~,--,~~+--+-~+--f~~f-~,--,-~t-~+-~+-~+--,,_,,.•
Clock
C
D
(c) Count down waveforms
Synchronous, 4-bit up-down counter
Holding the count-down input low (at ground) will disable AND gates Y1, Y2 , and Y3 • The clock applied
at count-up will then go directly into flip-flop A and will be steered into the other flip-flops by AND gates Xi,
X 2, and X 3. This counter will then function exactly as the previously discussed parallel counter shown in Fig.
10.10. The only difference here is thatthis is a mod-16counter that advances one count with each clock NT,
beginning with 0000 and ending with 1111. The correct waveforms are shown in Fig. 10.12b.
If the count-up line is held low, the upper AND gates X 1, X2, and X:1 are disabled. The clock applied at
input count-down will go directly into flip-flop A and be steered into the following flip-flops by AND gates
Y1, Y2, and Y3.
Flip-flop A will toggle each time there is a clock NT as shown in Fig. 10.12c. Each time A is high, AND
gate Y1 will be enabled and the clock NT will toggle flip-flop Bat points a, c, e, g, and so on. Whenever both
A· and B are high, AND gate Y2 is enabled, and thus a clock will be steered into flip-flop C at points a, e, i,
m, and q. Similarly, AND gate Y3 will steer a clock into flip-flop D only when A, B, and C are all high. Thus
flip-flop D will toggle at points a and i on the time line. The waveforms in Fig. l 0.12c clearly show that the
counter is operating in a count-down mode, progressing one count at a time from 1111 to 0000.
If you examine the logic diagram for the 54/74193 TTL circuit shown in Fig. 10.13, you will see that
it uses steering logic just like the counter in Fig. 10.12. This MSI circuit is a synchronous 4-bit up-down
Inputs
Data Data
C D
'192, '193, 'LSI92, 'LS193. 9
(Top view)
A Clear Borrow Carry Load C
B 74193 D
Count Count
down up
Logic: low input to load sets QA = A,

QB= B, QC= C, and QD = D 8
Data QB QA CountCount Qc QD GND
B ~down u p ~
Input Outputs '----v-'--' Outputs
Inputs
(a) Pinout
54/74193
Counters
'193, 'L193, 'LS193 (13). Borrow output

'io------
........Ffr--=--t-- J (IZ) Carry output
lW=i$tW~==' i o - - - - -
\(.1~5)!__--;::±:l:t:l=!=l=ffffr=L!"~ I ~
Data input A_:_ I L:=._ _ _ r--I Q,, 3
--,. ( ) Output QA
Countdown (4) '->D--1--tt-H-tftm---, ~· T
Count up (5) '>o----t--t-l-f-t-J-r-i-i--r-i--~-
10
Data input C _;_<< ~~)-u:ttl+l=t=f=rr~..J
c:!e:=::.J"
___I _ T
::::j
1Qc ~..---(6) Output Qc
>-+--,--.,T -
r Qc, •
nJJ_
~@H-++====~=
'
~(11) I
Load
It=====~--~
(b) Logic
(Continued)
'193, 'Ll93, 'LS193 Binary counters

Typical clear, load, and count sequences
Illustrated below is the following sequence.
l. Clear outputs to zero.
2. Load (preset) to binary thirteen.
3. Count up to fourteen, fifteen, carry, zero, one, and two.
4. Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
Clear
Load
I
A _J L__ _____________________________________________ _
I
B
Data ~-;-..-;.-~f--!~·----------------------------------------------
C _J L__ _____________________________________________ _
I
_J L__ _____________________________________________ _
D
I
'
Count up
Count down
I
I
I
Outputs W- I
Carry
Borrow
I
I I I I 1
I '
IOI 1131 I 15 O
14 I 1 0 15 14 1:
Sequence illustrated ~ ,--A-.,
Clear Preset
~ Count up I- Count down
Notes: A. Clear overrides load, data, and count inputs.

B. When counting up, count-down input must be high; when counting down, count-up input must be high.
(c) Waveforms for 54/74193
(Continued)
counter that can also be cleared and preset to any desired count-attributes that we discuss later. For now, you
should carefully examine the steering logic for each flip-flop and study the OR gate and the two AND gates
at the input of the OR gate used to provide the clock to each flip-flop.
The waveforms for the 54/74193 are exactly the same as those shown in Fig. 10.12, except that the flip-
flop outputs change states when the clock makes a low-to-high transition. Note carefully that the external
clock (applied at either the count-up or the count-down input) passes through an inverter before being applied
to the AND-OR-gate logic of each flip-flop clock input.
Write a Boolean expression for the AND gate connected to the lower leg of the OR gate that
drives the clock input to flip-flop QD in the 54/74193.
Counters
Solution The correct expression is

x= (count~upclock) (QA)(Qs)(Qc)
A parallel.upcdown counter can be formed by using a slightly differe11t.logic scheme, as. sh.ow!linFig. }0:14.
Remember that in a parallel counter, the time at which any flip-flop changes state is determined by the states of all
previous flip~fiops in the counter. In the count up mode, a :flip•ffop musttoggle every time all previous fiip~flops are
0
in a 1 state, and the clock makes atra11sition. In the. eount-down mode, flip-flop toggles must occµr when all prior
:flip-flops are in a O state.
This particular counter works in an inhibit mode, since each flip-flop changes state on a clock NT pro-
vided its J and K inputs are both high; a change of state will not occur when the J and K inputs are low. We
Count u p ~ - - . - - - - ~ - ~ ~ - - - . - - - - - - - - - - - - - - - ,
+Vee
-1lSL
Clock----<11-1------------;--------<11------+-----~
(a)
Count up D C B A Count
l l
Countdown
0
0
0
0
0
0
0
0
0
0
1
1
0
l
0
l
0
1
2
3
0 l 0 0 4
0 l 0 l 5
0 l 1 0 6
0 I l 1 7
l 0 0 0 8
I 0 0 l 9
1 0 1 0 10
l 0 1 1 11
1 1 0 0 12
1 1 0 1 13
l 1 1 0 14
l 1 1 1 15
0 0 0 0 0
(b)
Parallel up-down counter

~ _ _ _ _ _ _ _ _ _ _ _ _ _ _D_ig_it_al_P_n_·nc_ip_le_s_a_n_d_Ap_p_l1_·ca_tt_·on_s_ _ _ _ _ _ _ _ _ _ _ __
might consider this is "look-ahead logic," since the mode of operation occurs in a strict time sequence as
follows:
I. Establish a level on the J and K inputs (low or high)
2. Let the clock transition high to low
3. Look at the flip-flop output to determine whether it toggled.
To understand the logic used to implement this counter, refer to the truth table shown in
Fig. 10.14b.
A is required to change state each time the clock goes low, and flip-flop A therefore has both its J and K
inputs held in a high state. This is true in both the count-up and count-down modes, and thus no other logic
is necessary for this flip-flop.
In the count-up mode, B is required to change state each time A is high and the clock goes low. Whenever
the count-up line and A are both high, the output of gate X 1 is high. Whenever either input to Z 1 is high, the
output is high. Therefore, the J andK inputs to flip-flop B are high whenever both count-up and A are high.
Then, in the count-up mode, a clock NT will toggle B each time A is high, such as in going from count I to
count 2, or 3 to 4, and so on.
In the count-down mode, B must change state each time A is high and the clock goes low. The output
of gate Y1 is high, and thus the J and K inputs to flip-flop B are high whenever A and count-down are high.
Thus, in the count-down mode, B changes state every time A is high and the clock goes low-going from 0
to 15, or from 14 to 13, etc.
In the count-up mode, a clock NT must toggle C every time both A and B are high (transitions 3 to 4, 7
to 8, 11 to 12, and 15 to 0). The output of gate X 2 is high whenever both A and B are high and the count-up
line is high. Thus, the J and K inputs to flip-flop Care high during these times and C changes state during the
needed transitions.
In the count-down mode, C is required to change state whenever both A and B are high. The output of
gate Y2 is high any time both A and B are high, and the count-down line is high. Thus the J and K inputs to
flip-flop Care high during these times, and C then changes state during the required transitions-that is, 0 to
15, 12 to 11, 8 to 7, and 4 to 3.
In the count-up mode, D must toggle every time A, B, and C are all high. The output of gate X 3 is high,
and thus the J and K inputs to flip-flop D are high whenever A, B, and C and count-up are all high. Thus D
changes state during the transitions from 7 to 8 and from 15 to 0.
In the count-down mode, a clock NT must toggle D whenever A, B, and Care all high. The output of gate
Y3 is high, and thus the J and K inputs to flip-flop D are high whenever A, B, and C and count-down are all
high. Thus D changes state during the transitions from Oto 15 and from 8 to 7. The count-up and count-down
waveforms for this counter are exactly like those shown in Fig. 10.12.
Take a look at the logic diagram for the 54/7 4191 TTL MSI circuit shown in Fig. 10 .15. This is a
synchronous up-down counter. A careful examination of the AND-OR-gate logic used to precondition the J
and K inputs to each flip-flop will reveal that this counter uses look-ahead logic exactly like the counter in
Fig. I 0.14. Additional logic allows one to clear or preset this counter to any desired count, and we study these
functions later. For now, carefully compare the logic diagram with the counter in Fig. 10.14 to be certain you
understand its operation.
Notice carefully that the clock input passes through an inverter before it is fed to the individual flip-flops.
Thus the outputs of the four master-slave flip-flops will change states only on low-to-high transitions of the
input clock. Typical waveforms are given in Fig. 10.15. Incidentally, these are precisely the same waveforms
one would expect when using the 54/74193 discussed previously.
Counters
Write a Boolean expression for the 4-input AND gate connected to the lower leg of the OR
gate that conditions the J and K inputs to the QD flip-flop in a 54/74191.
Solution The correct logic expression is

x = (down-up)(QA)(Qs)(Qc)(enable)
Inputs . ·Oµtputs Inputs
~ .... ,-~~"-~---
Data Ripple Maxi Data Data
A Clock clock min Load C D
J or N dual-in-line 15 14 13 11 9
or W flat package
(top view)
B 74193 D
Asynchronous inputs:
low input to load
sets QA=A, QB= B,
Qc= C, and QD = D;
Data QB QA EnableDown/ Qc QD GND
B ~.·G up·~
'--v--' Outputs .'--v---=-' Outputs
Input Inputs
54/74191 (continued on next page)
5. How does a parallel (synchronous) counter differ from a serial (asynchronous} counter?
6. Why are decoding gate glitches eliminated in a synchronous· counter?
7. Does the 74193 change state withPTs or with: NTs?
10.4 CHANGING THE COUNTER MODULUS
Counter Modulus
At this point, we have discussed asynchronous (ripple) counters and two different types of synchronous
(parallel) counters, all of which have the ability to operate in either a count-up or count-down mode. All of
these counters progress one count at a time in a strict binary progression, and they all have a modulus given
by 2n, where n indicates the number of flip-flops. Such counters are said to have a "natural count" of2".
A mod-2 counter consists of a single flip-flop; a mod-4 counter requires two flip-flops, and it counts
through four discrete states. Three flip-flops form a mod-8 counter, while four flip-flops form a mod-16
counter. Thus we can construct counters that have a natural count of 2, 4, 8, 16, 32, and so on by using the
proper number of flip-flops.
It is often desirable to construct counters having a modulus other than 2, 4, 8, and so on. For example, a
counter having a modulus of 3, or 5, would be useful. A small modulus counter can always be constructed
'191, 'LS 191 Binary counters

(14)
Clock
Down/up
(5) -FrLJo----
.. ..,.,---..,_ (13) ~ - - -
Ripple clock
I 11
>----1--+-<11_1--------Max/min output
0 2)
(15) I
Data input A--+-l-~-----!-1-+-+-+-+-+-+--~,-')-io-,11------+--+----.,I,
Preset (3)
(4) - -,-- J QA 1--...---0utput QA
Enable G ---+-~------1_-+_---+--+-+-+-+-,1--t-+--a ; > - - - - t - - - - - tH > CK
_,J J- - ,- K QA -
Clear
'f
_r
(I)
Data input B ------+--+--+--+-+-+-f--!--!-+--+--r
1 r ),
(10)
Data input C
l'D-----------,J,
Preset (6)
·-+--1 1 J Qc i-- 1---0--- Output Qc
--LH>CK
I
-K QC._
Clear
y
_F
(9)
DatainputD------+--+-+--1--+-+-+-!--!-+--+-~l,-,,_
~J---
.--1-HH-t--t--t--t-+-i--i_ _,,110-------1......----1---,1
Preset (7)
le- J QD 1---9-- ()utput QD
T Le.> CK_
L......_K QD-
Clear
.· y
Load (II)
(Continued)
Counters
'191, 'LS191 Binary counters

Typical load, count and inhibit sequences
1. Load (preset) to binary thirteen.
2. Count up to fourteen, fifteen (maximum), zero, one, and two.
3. Inhibit
4. Count down to one, zero (minimum), fifteen, fourteen, and thirteen.
I I
ArH--------------------------------------------·
I I
B : ~---------------------------------------------
C~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Data inputs
D__r--t--t~-~~~----~--~--~--~~~--~--------------------·
. I I
Down/up
0 ----,
-B ___ l_J:
I
Q c----
___ J
QD~~~~ :I
I
Max/min~~~.J : ll~----1-----1--,---,11~-----
Ripple clock ;
'
: LJ LJ
----1131114 15 0 121 2 12 1 0 15 14 13
I 11-- Count up -r-Inhibit...j 1-- Count down - I
~
Load
(Continued)
from a larger modulus counter by skipping states. Such counters are said to have a modified count. It is first
necessary to determine the number of flip-flops required. The correct number of flip-flops is determined
choosing the lowest natural count that is greater than the desired modified count. For example, a mod-7
counter requires three flip-flops, since 8 is the lowest natural count greater than the desired modified count
of7.
Indicate how many flip-flops are required to construct each of the following counters: (a)
mod-3, (b) mod-6, and (c) mod-9.
Solution
a. The lowest natural count greate~ than 3 is 4. Two flip-flops provide a natural count of 4. Therefore, it requires at
least two flip-flops to construct a mod-3 counter.
b. Construc1:ion of a mod-6 counter requires at least three flip-flops, since 8 is the lowest natural count greater than
6.
c. A mod-9 counter requires at least four flip-flops, since 16 is the lowest natural coU11t greater than 9.
A single flip-flop has a natural count of2; thus we could use a single flip-flop to construct a mod-2 counter,
and that's all. However, a two flip-flop counter has a natural count of 4. Skipping one count will lead to a
mod-3 counter. So, two flip-flops can be used to construct either a mod-4 or mod-3 counter.
Similarly, a three-flip-flop counter has a natural count of 8, but by skipping counts we can use three flip-
flops to construct a counter having a modulus of 8, 7, 6, or 5. Note that counters having a modulus of 4 or 3
could also be constructed, but these two counters can be constructed by using only two flip-flops.
What modulus counters can be constructed with the use of four flip-flops?
Solution A four~flip-flop counter has a natural count of 16. We can thus construct any counter that has a modulus
between 16 and 2, inclusive..We might choose to use four flip-flops only for co1IDters having a modulus between 16
and 9, since only. three flip-flops are required for a modulus of less than 8, and only two are required for a modulus
ofless than 4.
A Mod-3 Counter
There are a great many different methods for consh-ucting a counter having a modified count. A counter
can be synchronous, asynchronous, or a combination of these two types; furthermore, there is the decision
of which count to skip. For instance, if a mod-6 counter using three flip-flops is to be constructed, which
two of the eight discrete states should be skipped? Our purpose here is not to consider all possible counter
configurations and how to design them; rather, we devote our efforts to one or two designs widely used in
TTL MSI. A mod-3 counter is considered in this section and a mod-5 in the next section, and then we consider
the use of presettable counters to achieve any desired modulus.
The two flip-flops in Fig. 10.16 have been connected to provide a mod-3 counter. Since two flip-flops have
a natural count of 4, this counter skips one state. The waveforms and the truth table in Fig. 10.16 show that
this counter progresses through the count sequence 00, 01, 10, and then back to 00. It clearly skips count 11.
Here's how it works:
1. Prior to point a on the time line, A = 0 and B = 0. A negative clock transition at a will cause:
a. A to toggle to a 1, since its J and K inputs are high
b. B to reset to O (it's already a 0), since its J input is low and its K input is high
2. Prior to point b on the time line, A = I, and B = 0. A negative clock transition at b will cause:
a. A to toggle to a 0, since its J and K inputs are high
b. B to toggle to a 1, since its J and K inputs are high
3. Prior to point c on the time line, A = 0 and B = I. A negative clock transition at c will cause:
a. A to reset to O (it's already 0), since its J input is low and its K input is high
b. B to reset to O since its J input is low and its K input is high
4. The counter has now progressed through all three of its states, advancing one count with each negative
clock transition.
This two-flip-flop mod-3 counter can be considered as a logic building block as shown in Fig. 10.16d.
It has a clock input and outputs at A and B. It can be considered as a divide-by-3 block, since the output
Counters
a b C
Time-------•
J A i--e-------j t t t
Clock -----<» Clock _Il___fl__fl_Jl
A ____r--i___.r-
B~
A B
(a) Logic diagram (b) Waveforms
B A Count
0 0 0 Clock Mod-3
0 1 1
0 2
-------
0 0 0
A B
(c) Truth table (d) Logic block
Mod-3 counter
waveform at B ( or at A) has a period equal to three times that of the clock-in other words, this counter
divides the clock frequency by 3. Notice that this is a synchronous counter since both flip-flops change state
in synchronism with the clock.
A Mod-6 Counter
Ifwe consider a basic flip-flop to be a mod-2 counter, we see that a mod-4 counter (two flip-flops in series) is
simply two mod-2 counters in series. Similarly, a mod-8 counter is simply a 2 x 2 x 2 connection, and so on.
Thus a great number of higher-modulus counters can be fonned by using the product of any number of lower-
modulus counters. For instance, suppose that we connect a flip-flop at the B output of the mod-3 counter in
Fig. 10.16. The result is a (3 x 2 = 6) mod-6 counter as shown in Fig. 10.17. The output of the single flip-flop
is labeled C. Notice that it is a symmetrical waveform, and it also has a frequency of one-sixth that of the
input clock. Also, this can no longer be considered a synchronous counter since flip flop C is triggered by
flip-flop B; that is, the flip-flops do not all change status in synchronism with the clock.
Clock
A B C
(a) 3 x 2 Mod-6 counter (b) Waveforms
Draw the wavefonns you would expect from the mod-6 counter by connecting a single
flip-flop in front of the mod-3 counter in Fig. 10.16.
Solution The resulting counter is a 2 x 3 = mod~6 counter thathas the waveforms shown in Fig. l OJ 8. Notice that
B now has a period equal to six clock periods, buf it is not symmetrical.
Clock
input
Mod-3
Q A B
(a) 2 x 3 Mod-6 counter
A __ ___,
B _ _ _ _ _~
(b) Waveforms
The 54/7492A
The 5417492A ('92A) in Fig. 10.19 is a TTL divide-by-12, MSI counter. A careful examination of the logic
diagram will reveal that flip-flops Qs, Qc, and QD are exactly the same as the 3 x 2 counter in Fig. 10.17.
Thus if the clock is applied to input B of the '92A and the outputs are taken at Qs, Qc, and QD, this is a mod-6
. counter.
On the other hand, if the clock is applied at input A and QA is connected to input B, we have a 2 x 3 x 2
mod-12 counter. The proper truth table for the mod-12 configuration is given in Fig. 10.19b. Again, this must
be considered as an asynchronous counter since all flip-flops do not change states atthe same time. Thus there
is the possibility of glitches occurring at the outputs of any decoding gates used with the counter.
Use the truth table for the '92A to write a Boolean expression for a gate to decode count 8.
Solution The correct expressionis "8" = QnQcQsQx-
At this point, we can construct counters that have any natural count (2, 4, 8, 16, etc.) and, in addition, a
mod-3 counter. Furthermore, we can cascade these counters in any combination, such as 2 x 2, 2 x 3, 3 x 4,
and so on. So far we can construct counters having a modulus of 2, 3, 4, 6, 8, 9, 12, and so on. Therefore, let's
consider next a mod-5 counter.
_ _ _ _ _ _ _ _ _ _ _ _ _c_o_un_te_rs_ _ _ _ _ _ _ _ _ _ _ _ _ @)
'92A, 'LS92 Count sequence
(See Note C)
Output
Count
'92A, 'LS92
QD QC QB QA
(14) 0 L L L L
Input A - - - - - - - a > CK I L L L H
(CK.A) K 2 L L H L
3 L L H H
4 L H L L
5 L H L H
(1) 6 H L L L
Input B _ _ _...,._,._..--a> CK H
7 L L H
(CKB) K 8 H L H L
9 H L H H
10 H H L L
11 H H L H
(b) Truth table
'92A, 'LS92, (Top view)

Input A
(CK.A) NC QB GND Qc QD
14 13
CK A
K B
R00 l ~"..r .___,_
Ro(2) o----~
2
Input B NC NC NC Vcc R0(1) R0(2)
(CKB) Positive logic: See function tables.
Note: Output QA connected to input B
(a) Logic (c) Pinout
54/7492A
8. How many flip-flops are required to construct a mod-12 counter?

9. Three flip-flops are available. What modulus counters couldbe constructed?
10.5 DECADE COUNTERS
A Mod-5 Counter
The three-flip-flop counter shown in Fig. 10.20 has a natural count of 8, but it is connected in such a way that
it will skip over three counts. It will, in fact, advance one count at a time, through a strict binary sequence,
beginning with 000 and ending with 100; therefore, it is a mod-5 counter. Let's see how it works.
C B A Count
0 0 0 Count O 1 2 3 4 0
0
0 0 1 1 Clock~
0 1 0 2 A ~
0 1 1 3 B
--~
1 0 0 4 C
0 0 0 0
(a) (b)
+Vee a---+-----------------~
Clock Mod-5
A B C
(c) (d) Logic block
Mod-5 binary counter
The waveforms show that flip-flop A changes state each time the clock goes negative, except dming the
transition from count 4 to count 0. Thus, flip-flop A should be triggered by the clock and must have an inhibit
during count 4-that is, some signal must be provided during the transition from count 4 to count 0. Notice
that C is high during all counts except count 4. If C is connected to the J input of flip-flop A, we will have
the desired inhibit signal. This is true since the J and K inputs to flip-flop A are both true for all counts except
count 4; thus the flip-flop triggers each time the clock goes negative. However, during count 4, the J side is
low and the next time the clock goes negative the flip-flop will be prevented from being set. The connections
which cause flip-flop A to progress through the desired sequence are shown in Fig. 10.20.
The desired waveforms (Fig. 10.20b) show that flip-flop B must change state each time A goes negative.
Thus the clock input offlip-flop B will be driven by A (Fig. 10.20c).
If flip-flop C is triggered by the clock while the J input is held low and the K input high, every clock pulse
will reset it. Now, if the J input is high only during count 3, C will be high during count 4 and low during all
other counts. The necessary levels for the J input can be obtained by ANDing flip-flops A and B. Since A and
Bare both high only during count 3, the J input to flip-flop C is high only during count 3. Thus, when the
clock goes negative during the transition from count 3 to count 4, flip-flop C will be set. At all other times,
the J input to flip-flop C is low and is held in the reset state. The complete mod-5 counter is shown in Fig.
10.20.
In constructing a counter of this type, it is always necessary to examine the omitted states to make sure that
the counter will not malfunction. This counter omits states 5, 6, and 7 during its normal operating sequence.
There is however, a very real possibility that the counter may set up in one of these omitted (illegal) states
when power is first applied to the system. It is necessary to check the operation of the counter when starting
from each of the three illegal states to ensure that it progresses into the normal count sequence and does not
become inoperative.
Counters
Begin by assuming that the counter is in state 5 (CBA = 101). When the next clock pulse goes low, the
following events occur:
1. Since C is low, flip-flop A resets. Thus A changes from a I to a 0.
2. When A goes from a 1 to a 0, flip-flop B triggers and B changes from a O to a I.
3. Since the J input to flip-flop C is low, flip-flop C is reset and C changes from a 1 to a 0.
4. Thus the counter progresses from the illegal state 5 to the legal state 2 ( CBA = 010) after one clock.
Now, assume that the counter starts in the illegal state 6 ( CBA = 110). On the next negative clock transi-
tion, the following events occur:
1. Since C is low, flip-flop A is reset. Since A is already a 0, it just remains a 0.
2. Since A does not change, flip-flop B does not change and B remains a 1.
3. Since the J input to flip-flop C is low, flip-flop C is reset and C changes from a 1 to a 0.
4. Thus the counter progresses from the illegal state 6 to the legal state 2 after one clock transition.
Finally, assume that the counter begins in the illegal state 7 (CBA = 111 ). On the next negative clock
transition, the following events occur:
1. Since C is low, flip-flop A is reset and A changes from a 1 to a 0.
2. Since A changes from a 1 to a 0, flip-flop B triggers and B changes from a l to a 0.
3. The J input to flip-flop C is high; therefore, flip-flop C toggles from a 1 to a 0.
4. Thus the counter progresses from the illegal count 7 to the legal count Oafter one clock transition.
None of the three illegal states will cause the counter to malfunction, and it will automatically work itself
out of any illegal state after only one clock transition.
A Mod-10 Counter
This mod-5 counter configuration can be considered as a logic block as shown in Fig. 10.20d and can be used
in cascade to construct higher-modulus counters. For instance, a 2 x 5 or a 5 x 2 will form a mod-10 counter,
or decade counter.
Show a method for constructing a 5 x 2 (mod-10) decade counter.
Solution AdeC!,1,decountercan be constntctedbyusing the mod-5 counter in Fig. 10.20.andadding an additional

fli})'-flrip, labeled D, as shown in Fig. 10.21, The appropriate waveforms and truth table are included. Notice that the
counter progresses through a biquinary count sequence and does not count in a straight binary sequence,
A decade counter could be fonned just as easily by using the mod-5 counter in Fig. 10.20 in conjunction
with a flip-flop, but connected in a 2 x 5 configuration as shown in Fig. 10.22. The truth table for this
configuration, and the resulting waveforms are shown. This is still a mod-10 (decade) counter since it still
has 10 discrete states. Notice that this counter counts in a straight binary sequence from 0000 up to 1001, and
then back to 0000.
The 7490A
The 5417490A is a TTL MSI decade counter. Its logic diagram, truth table, and pinout are given in Fig. 10.23.
A careful examination will reveal that flip-flops QB, Qc, and QD form a mod-5 counter exactly like the one in
Fig. 10.20. Notice, however, that flip-flop QD in the '90A is an RS flip-flop that has a direct connection from
its Q output back to its R input. The net result in this case is that QD behaves exactly like a JK flip-flop.
~ _ _ _ _ _ _ _ _ _ _ _ _ _D_ig_it_al_P_rin_c_ip_le_s_a_nd_A_p_pl_ic_at_io_ns_ _ _ _ _ _ _ _ _ _ _ __
Clock ----11--il>-+-«>
SUl_
(a)
D C B A State
0 0 0 0 0
0 0 0 I I
State 0 2 3 4 5 6 7 8 9 0
0 0 I 0 2
Clock
0 0 I I 3
0 1 0 0 4
1 0 0 0 5
I 0 0 1 6
I 0 1 0 7
I 0 I 1 8
1 I 0 0 9
0 0 0 0 0
(b) (c)
A decade counter
D C B A Count
0 0 0 0 0
0 0 0 1 1
0 0 I 0 2 Count 0 2 3 4 5 6 7 8 9 0
0 0 I 1 3 Clock
0 1 0 0 4 A
0 1 0 1 5 B
0 1 I 0 6 C
0 1 1 I 7
D
1 0 0 0 8
1 0 0 l 9
0 0 0 0 0
(a) (b)
Clock ----1---a>
__n_n_
(c)
A decade counter
'90A, 'L90, 'LS90
Counters
'90A, 'L90, 'LS90

®
'90A, 'L90, 'LS90
BCD count sequence Bi-quinary (5-2)
(See note A) (See note B)
(12) QA Output Output
Input (14) Count Count
A QD Qe QB QA QA QD Qe QB
0 L L L L 0 L L L L
L L L H 1 L L L H
2 L L H L 2 L L H L
(9) 0 3 L L H H 3 L L H H
Input (1) -B 4 L H L L 4 L H L L
B 5 L H L H 5 H L L L
K 6 L H H L 6 H L L H
7 L H H H 7 H L H L
8 H L L L 8 H L H H
9 H L L H 9 H H L L
(b) Truth table
'90A, 'L90, 'LS90 (Top view)

(8) Qe
InputA NC QA QD GND QB Qe
14 13 12 9 8
K
QA QD QB
A Qe
7490A
B R9(2)
RO(!) Ro(2) R9(1)
(11) QD
4 5 7
Input B Ro(!) Ro(2) NC Vee R9(1) R9(2)
Positive logic: See function tables
Note: A output QA connected to input B
B output QD connected to input A
(a) Logic (c) Pinout
54/7490A
Reset pulse
D
C
B
7490 JUlSl
A
Hundreds Tens Units
Cascaded 7490's can count to 999

If the system clock is applied at input A and QA is connected to input B, we have a true binary decade
counter exactly as in Fig. 10.22. On the other hand, if the system clock is applied at input B and Qv is
connected to input A, we have the biquinary counter as discussed in Example l 0.11. Take time to study the
logic diagram and the truth table for the '90A; it is widely used in industry, and the time spent will be well
worth your while.
An interesting application using three 5417490A decade counters is shown in Fig. 10.24. The three '90A
counters are connected in series such that the first one (on the right) counts the number of input pulses at its
clock input. We call it a units counter.
The middle '90A will advance one count each time the units counter counts 10 input pulses, because D
from the units counter will have a single negative transition as that counter progresses from count 9 to 0. This
middle block is then called tens counter.
The left '90A will advance one count each time the tens counter progresses from count 9 to 0. This will
occur once for every 100 input pulses. Thus this block is called the hundreds counter.
Now the operation should be clear. This logic circuit is capable of counting input pulses from one up to
999. The procedure is to reset all the '90As and then count the number of pulses at the input to the units
counter. This cascaded arrangement is widely used in digital voltmeters, frequency counters, etc., where a
decimal count is needed.
It should be pointed out that the 5417490A is only one of a number of TTL MSI decade counters.
In particular, the 54/74176 is another popular asynchronous decade counter, and the 54/74160,
54/74162, 54/74190, and 54/74192 are all popular synchronous decade counters. Each has particular attributes
that you should consider, and a study of their individual data sheets would be worthwhile.
10. What is a decade counter?

11. What is tb,e difference between theS x 2 decade counterjn Fig. 10.21 and>the 2 X 5 decade
counter in Fig. 10.22?
10.6 PRESETTABLE COUNTERS
Up to this point we have discussed the operation of counters that progress through a natural binary count
sequence in either a count-up or count-down mode and have studied two counters t)lat have a modified
count-a mod-3 and a mod-5. With these basic configurations, and with cascaded combinations of these
basic units, it is possible to construct counters having moduli of 2, 3, 4, 5, 6, 7, 8, 9, 10, and so on. The ability
to quickly and easily construct a counter having any desired modulus is so important that the semiconductor
industry has provided a number of TTL MSI circuits for this purpose. The presettable counter is the basic
building block that can be used to implement a counter that has any modulus.
Nearly all the presettable counters available as TTL MSI are constructed by using four flip-flops, and
they are generally referred to as 4-bit counters. They may be either synchronous or asynchronous. When
connected such that the count advances in a natural binary sequence from 0000 to 1111, it is simply referred
to as a bina,y counter. For instance, the 54/74161 and the 54/74163 are both synchronous binary counters
that operate in a count-up mode. The 54/74191 and the 54/74193 are also synchronous binary counters, but
they can operate in either a count-down or count-up mode.
Counters
Since the decade counter is a very important and useful configuration, many of the "basic 4-bit counters
are internally connected to provide a modified count of 10-a mod-10 or decade counter. For instance,
the 54/74160 and the 54/74162 are synchronous decade counters that operate in the count-up mode. The
54/74190 and the 54/74192 are also synchronous decade counters but they can operate in either a count-up
or count-down mode.
The counters mentioned above are all TTL MSI circuits, and as such we have little control over the
internal logic used to implement each counter. Our concern is directed at how each unit can be used in a
digital system. Thus we consider each of these counters as a logic block, and our efforts are concentrated
on inputs, outputs, and control signals. Even so, the logic block diagram is given for each counter, since a
knowledge of the internal logic gives a depth of understanding that is invaluable in practical applications.
Synchronous Up Counters
The pinout and logic diagram for a 54/74163 synchronous 4-bit counter are given in Fig. 10.25. The pinout
contains a logic block diagram for this unit. The power requirements are+ Vcc and GROUND on pins 16 and
8, respectively. The "clock" is applied on pin 2, and you will notice from the diagram that the outputs change
states on positive clock transitions (PTs).
The four flip-flop outputs are QA, QB, Qc, and QD, while the CARRY output on pin 15 can be used to
enable successive counter stages (e.g. in a units, tens, hundreds application).
The two ENABLE inputs (Pon pin 7 and Ton pin 10) are used to control the counter. If either ENABLE
input is low, the counter will cease to advance; both of these inputs must be high for the counter to count.
A low level on the CLEAR input will reset all flip-flop outputs low at the very next clock transition,
regardless at the levels on the ENABLE inputs. This is called a synchronous reset since it occurs at a
positive clock transition. On the other hand, note that the 54/74161 has an asynchronous clear, since it occurs
immediately when the CLEAR input goes low, regardless of the levels on the CLOCK, ENABLE, or LOAD
inputs.
When a low level is applied to the LOAD input, the counter is disabled, and the very next positive clock
transition will set the flip-flops to agree with the levels present on the four data inputs (D, C, B, and A). For
instance, suppose that the data inputs are DCBA = 1101, and the LOAD input is taken low. The very next
positive clock transition will load these data into the counter and the outputs will become QDQcQBQA = 1101.
This is a very useful function when it is desired to have the counter begin counting from a predetermined
count.
For the counter to count upward in its normal binary count sequence, it is necessary to hold the ENABLE
inputs (P and T), the LOAD input, and the CLEAR input all high. Under these conditions, the counter
will advance one count for each positive clock transition, progressing from count 0000 up to count 1111
and then repeating the sequence. Since the flip-flops are clocked synchronously, the outputs change states
simultaneously and there are no counting spikes or glitches associated with the counter outputs. The state
diagram given in Fig. 10.26a show the normal count sequence, where each box corresponds to one count (or
state) and the arrows show how the counter progresses from one state to the next.
The count length can be very easily modified by making use of the synchronous CLEAR input. It is a
simple matter to use a NAND gate to decode the maximum count desired, and use the output of this NAND
gate to clear the counter synchronously to count 0000. The counter will then count from 0000 up to the
maximum desired count and then clear back to 0000. This is the technique that can be used to construct a
counter that has any desired modulus.
~ _ _ _ _ _ _ _ _ _ _ _ _ _ _D_ig_it_al_P_ri_nc_ip_le_s_a_n_dA_p_p_li_ca_ti_on_s_ _ _ _ _ _ _ _ _ _ _ __
SN54163, SN74163 Synchronous binary counters
SN54161, SN74161 Synchronous binary counters are similar;
however, the CLEAR is asynchronous as shown for the
SN54160, 74160 decade counters at left.
Load _(9_)_ _ _ _ _ _ _--a
(13) 0
J QB -B
CK
(4)
DataB K
(2)
Clock
J Qc (12) QC
CK
(5)
DataC K
,__ ___
(15) Ripple
carry
54/74161 and 54/74163
For instance, if a maximum count of 9 is desired, we connect the inputs of the NAND gate to decode
count 9 = DCBA = 1001. We then have a mod-10 counter, since the count sequence is from 0000 up to 1001.
The NAND gate used to decode count 9 along with the modified state diagram are shown in Fig. 1026b
and c, respectively. Notice that it was necessary to use two inverters to obtain Q8 and Qc. The modified
Counters
J or N dual-in-line or W flat package (Top view)

Outputs
,.------''-----... Enable
QB T Load
9
Carry QA QD Enable
output T
Clear 54/74163 Load
CK
8
Clear Clock A B C D Enable GND
'--------..,------' p
Data inputs
Positive logic: See description.
(Continued)
From QB
To Clear input
(Pin I)
FromQc
(a) Mod-16 counter state diagram (b) Gate to decode count 9 (1001)
,---1 ,---1 .---,
: 12: : 11 : : IO:
L--- L--- 1---
(c) Modified state diagram for Mod- IO counter
state diagram has solid boxes for states in the modified, mod-10 counter, and dashed boxes for omitted
states.
What are the NAND-gate inputs in Fig. 10.26b if this fi!:,rure is to be used to construct a
mod-12 counter?
Solution The counter must progress from 0000 up to 1011 (decimal ll); the NAND-gate inputs must then be Qn,
Qc, QB, and QA.
A set of typical waveforms showing the clear, preset, count, and inhibit operations for a 54/74163 (and
54/74161) is given in Fig. 10.27. You should take time to study them carefully until you understand exactly
how these four operations are controlled.
SN54161, SN54163, SN74161, SN74163 Synchronous binary counters
Typical clear, preset, count, and inhibit sequences
1. Clear outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one, and two.
4. Inhibit.
Clear (SN54161, SN74161) µ (Asynchronous)

Clear (SN54163, SN74163) -1-JJ (Synchronous)
Load
A -------------------------------------------
1
B -------------------------------------------
1
Data inputs
C _J
D _J
Clock (SN54161, SN74I6l)
Clock (SN54163, SN74163)

ENABLE?
ENABLE T ---1---+--'
I
QA =======~-'--,...-~
Outputs
QC ------- I
QD =======-,
Carry
112 113 14 15 0 21
I Count -----i--- Inhibit -
Clear Preset
Counters
The logic diagram and a typical set of waveforms for the 54/74160 and the 54/74162 are given in Fig.10.28.
(The pinout is identical for the previously given 54/74163.) These two counters have been modified internally
and are decade counters. Other than that, the input, output, and control lines for these two counters are
identical with the previously discussed 54/74163 and 54/74161. These counters advance one count with each
positive clock transition, progressing from 0000 to 1001 and back to 0000. The state diagram for these two
units would appear exactly as shown in Fig. 10.26c; this is the state diagrnm for a mod-10 or decade counts.
SN54160, SN74160 Synchronous decade counters
SN54162, SN74162 Synchronous decade counters are similar;
however, the clear is synchronous as shown for the
SN54163, SN74163 binary counters at right
(9)
Load
µ ,---,_J_.,, J
(14)
QA 1--e-- QA
""- I --<>CK
(3)
DataA ~ -1 K
J_ JP-4->---+-1:..._.,11 Clear
'f
(2)
Clock
'rP J ' J (12)

Qc,..._.,.___Qc
(5)
""- l >-+rrri.-_./, CK
Data C -'--'------11-1-+-+-------,1-~-r--..,,S l ~lear
'f
DataD
(6)
(1)
~~1:>i
_LJ":.
-J
l
J QD
>CK
K QD
Clear
'f
Clear
-
~
(7)
ENABLE; - I )- (15) Ripple
(10) T >----
_J carry
(a)
54/74160 (continued on next page)

(!i) ______________ D_ig_i_ta_lP_n_·n_c_ip_le_s_a_nd_A_p_p_li_ca_t1_·on_s_ _ _ _ _ _ _ _ _ _ _ _ __
SN54160, SN54162, SN74160, SN74162 Synchronous binary counters

Typical clear, preset, count, and inhibit sequences
1. Clear outputs to zero.
2. Preset to BCD seven.
3. Count to eight, nine zero, one, two, and three.
4. Inhibit.
Clear (SN54160, SN74160) µ (Asynchronous)

Clear (SN54162, SN74162) -u~(-Sy_n_c_hr_o_n_o-us-·)---------------
Load
A _J
[==========================================
B _J
Data inputs [==========================================
C _J
[-=========================================
------------------------------------------
D -----'---~------------------------------------------
Clock (SN54160, SN74I60)
Clock (SN54162, SN74I62)

ENABLE?
Outputs
I
QD =======~-;_ _,____,
Carry
17 18 9 0 1 2 31
I Count - - - + . - - - Inhibit -
Clear Preset
(b)
(Continued)
Synchronous Up-Down Counters

The 54/74193 is a 4-bit synchronous up-down binary counter. It has a master reset input and can be reset to
any desired count with the parallel load inputs. The logic symbol for this TTL MSI is shown in Fig. I 0.29a.
Pin PL is a control input for loading data into pins PA, Ps, Pc, and PD. When the device is used as a counter,
these four pins are left open and PL must be held high. Pin MR is the master reset, and it is nonnally held
low. (A high level on MR will reset all flip-flops.)
Counters
Outputs TCu and TCD are to be used to drive the following units, such as in a cascade arrangement. The
clock inputs are CPu and CPD. Placing the clock on CPu will cause the counter to count up, and placing the
clock on CPD will cause the counter to count down. Notice that the clock should be connected to either CPu
or CPD, but not both, and the unused input should be held high. The outputs of the counter are QA, Q 8 , Qc
and QD·
A state diagram is a simple drawing which shows the stable states of the counter, as well as how the
counter progresses from one count to the next. The state diagram for the 54/74193 is shown in Fig. 10.29b.
Each box represents a stable state, and the arrows indicate the count sequence for both count-up and count-
down operations. This is a 4-bit counter, and clearly there are 16 stable states, numbered 0, 1, 2, ... , 15.
PL P.4 Ps Pc PD
CPu TCu --Count up
54/74193
- - - - Count down
CPD TCD
MR QA QB Qc QD
(a) (b)
4-bit binary counter (presettable)
The 54/74193 has a parallel-data-entry capability which permits the counter to be preset to the number
present on the parallel-data-entry inputs (P,1, P 8 , Pc, and PD). Whenever the parallel load input (PL) is low,
the data present at these four inputs is shifted into the counter; that is, the counter is preset to the number held
by PDPcPsPA.
Now, here is another technique for modifying the count. Simply use a NAND gate to detect any of the
stable states, say, state 15 (1111 ), and use this gate output to take p L low. The only time p L will be low is
when QD, Qc, Q8 , and Q,1 are all high, or state 15( 1111 ). At this time, the counter will be preset to the data
PvPcPsPA.
For example, suppose that PvPcPsPA = 1001 (the number 9). When the clock is applied, the counter will
progress naturally to count 15(1111). At this time, PL will go low and the number 9 (1001) will be shifted
into the counter. The counter will then progress through states 9, 10, 11, 12, 13, and 14, and at count 15 it
will again be preset to 9.
The count sequence is easily shown by the state diagram in Fig. 10.30 on the next page. Notice that count
15 (1111) is no longer a stable state; it is the short time during which the counter is preset. The stable states
in this example are 9, 10, 11, 12, 13, and 14. This is, then, a mod-6 counter. Notice that this technique is
asynchronous since the preset action is not in synchronism with the clock. Therefore, you should be aware
that counting spikes or glitches may be associated with the outputs of this presetting arrangement.
Suppose that the counter just discussed is still preset to I 001 (the number 9) but the clock
is applied to count down rather than count up. What are the counting states? What is the
modulus?
Solution The counter will count down to 15, then preset back to 9, and repeat. The resulting state diagram is given
in Fig. l 0.31. The modulus is clearly 10.
0 2 3 4
(is) 5
~ 6
12. Name two popular synchronous binary counters.

13. What is the difference between the 74161 binary counter and the74191binary counter?
14. What is the modulus of the 74160 counter?
15. Can a 74160 counter be used to count down?
10.7 COUNTER DESIGN AS A SYNTHESIS PROBLEM

Section 8.11 of Chapter 8 presents a systematic approach to-
wards sequential logic circuit design using FSM concept. In
this section, we consider counter as a state machine and discuss
counter design steps through an example.
Let us try to design a modulo-6 counter, the counting states
(memory values) of which are shown in state transition dia-
gram of Fig. I 0.32. We need three memory elements or flip-
flops for this as with n flip-flop we can get at most 2" number
of different counting states.
Now with three flip-flop, 8 different states are possible but State sequence of a
in our design states 110 and 111 are not used in the counting modulo-6 counter
Counters
sequence. To start with we shall assume the counter is always initialized with one of the valid states and not
110 or 111. We decide to use three JK flip-flops labeled A, B and C as memory element for this design.
The next step to be taken is to form a state synthesis table as shown in Table 10.1. In this, the first column
represents current state of the counter and second column, as shown in the next state of the counter state
transition diagram. We fill up next three columns using excitation table of JK flip-flop given in Fig. 8.34 of
Chapter 8. Excitation table gives inputs need to be present when clock triggers a certain Qn~Q,,+ 1 transition
of the flip-flop. In the first row, we see both C and B make transition O~O and hence corresponding JK
inputs should be Ox from excitation table. For flip-flop A, transition is 0~ I and input should be Ix. This is
continued to fill up other five rows of input columns for three flip-flops.
State Table for Design of Modulo-6 Counter Given in Fig. 10.32
c,, B,, A,, Cn+J Bn+l An+l Jc Kc ls Ks JA K,1

0 0 0 0 0 l 0 X 0 X 1 X
0 0 l 0 l 0 0 X 1 X X l
0 1 0 0 1 1 0 X X 0 1 X
0 I I 1 0 0 I X X 1 X 1
I 0 0 l 0 1 X 0 0 X l X
I 0 1 0 0 I X I 0 X X l
Our next objective is to get logic equation for each flip-flop input as a function of present state of the
counter. We use Kamaugh Map for this as shown in Fig. 10.33. Note that values corresponding to unused
states 110 and 111 appear as don't care 'x'. We have not shown Kamaugh Map for JA and K._4 as it is obvious
from Table 10.1 thatJA =KA= I.
BnAn Bn-A"
e" 00 0I 11 I0 e11 00 0I l 1 10
-
0 0 0 1 0 0 X X X X
I X X X X I 0 I X X
-
Kc=A 11
BA
n n BIIA,,
e/l 00 01 I1 I0 e" 00 0I l I 10
0 0 I1 xi X 0 X X 0
1 0 0 X X X X X X
Ks=A,,
Derivation of design equations from Karnaugh Map
The final step is to draw the circuit diagram from these design equations, which is shown in
Fig. 10.34. The decoding output is obtained from a three input AND gate which goes high every time the
counter goes to a valid state CBA = 000 and that occurs in every 6th clock cycle.
Note that the method we have explained is a general one and can be used to design counter of any
modulo number and that can follow any given counting sequence. An irregular counter is the one which
( ; ) _ _ _ _ _ _ _ _ _ _ _ _ _ _D_ig_it_al_P_n_·nc_ip_le_s_a_n_d_A_pp_lJ_·ca_t_io_ns_ _ _ _ _ _ _ _ _ _ _ __
does not follow any regular binary sequence but has N number of distinct states and thus qualifies as a
modulo-N counter. In Example 10.15, we present a modulo-4 irregular counter.
One question can be raised at this point for the above circuit. What happens if the circuit for any reason
goes to one of the unused state? Does it come back to any of the valid counting state or in the worst case gets
locked as shown in Fig. 10.35a? Initializing the designed circuit with 110 or 111 unused state we find that
they get back to counting sequence as shown in Fig.10.35b. However, a designer may not leave unused states
to chances and want them to follow certain course if the circuit accidentally enters into one of them. Example
10.14 shows how to handle unused states in a counter design problem.
A
JA Jc C
A B
K.1 A B
c
CLK
Circuit diagram of modulo-6 synchronous counter described in Fig. 10.32
(a) (b)
(a) Lock-in conditions, (b) Full state transition diagram for circuit in Fig. 10.34
Desig,1 a self-correcting rnodulo-6 counter as described in Fig. 10.32 in which all the
unused state leads to state CEA = 000.
For this we have to add two more rows as given next for two unused states
Counters
Accordingly, Kamaugh Map giving design equations changes to as given in Fig. 10.36.
BA
11 11 BA
11 11
BA
11 Tl
C11 00 01 11 10 C/l 00 01 11 10 CI! 00 01 11 10
Ix xi
~
0 0 0 1 0 0 X X 0 0 I1 xi X
1 X X
~
X X 1 0 I1 1I 1 1 0 0 X X
Kc=A 11 + B,, Js=C11An
B,,A,, BA 11
/l
BA
I! 11
c 11 oo 01 11 10 CII 00 01 l 1 l0 C/l 00 01 11 10
0 X X 0 0 1 X X 1 I 0 X 1 1 X
X X 1 l X X 0 1 X 1 l X
Kn=A 11 +C11
Design equations for Example 10.14
Note the difference between Fig. 10.33 and 10.36. Unused states 110 and 111 can no longer be considered as don't
care. This type of design is called self-correcting as the circuit comes out on its own from an invalid state to a valid
counting state sequence. The final circuit diagram from design equations are shown in Fig.10.37.
Circuit diagram for Example 10.14
Design a modulo-4 irregular counter with following counting sequence using D flip-flop.
00-10-11-01
Soliitidn Using state excitation table of D flip-flop (Fig. 8.34), the state table can be formed as shown in Table
10.2.
State Table for Design of Irregular Counter
Bn An B,,+1 A,,+1 Ds D.4

0 0 1 0 l 0
0 l 0 0 0 0
1 0 l I
l 0 0
Design equations from Kamaugh Map can be derived as shown in Fig. 10.38(a), and con-esponding logic
circuit is shown in Fig. I0.38(b).
A B
B,, B,, D Q ~---iD Q

An 0 An 0
0 0 0 Flip-flop A Flip-flop B
0 0 0 CLK Q CLK Q
Ds=A,, D;1=Bn Clock

(a) (b)
(a) Deriving design equations for Example 10.15, (b) Circuit diagram
Show how a modulo-4 counter designed with two flip-flops can generate a repetitive
sequence of binary word '1101' with minimum number of memory elements?
Solution Let the counting sequence oftwo flip-flops B and A be 00 -+ 0 I -+ l O ~ 11.-+ 00 ... , Le. a modulo-4
synchronous up counter. The corresponding output is I-+ 1-+ 0-+..l-+ L .. As shown in Fig. 10.39(a) the sequence
'1101' will be generated.repetitively by Y. Figure 10.39(b) gives Kamaugh Map representation of Y and we get
Y = A + B'. A standard modulo-4 up counter and an 2sinput OR gate connected as shown in Fig. 10.39(c) generates
the given sequence.
Note that for N-bit sequence generator we need modulo-N counter. Modulo-N synchronous counter
requires m number of flip-flops where mis the lowest integer for which 2 N. The design procedure remains
111
:::::
the same as discussed in Example 10.16. Output Y now is a function of m state variables representing m
memory elements.
Compare this design with shift register based sequence generator design discussed in Chapter 9 ·that
requires N number of memory elements for N-bit sequence generator. Though shift register based design does
not require any combinatorial circuit to generate output logic the overall hardware cost is more and it is more
pronounced for large N.
A similar design for sequence detector circuit with minimum number of flip-flops is discussed in
Chapter 11.
16. What is lock-out of a counter?

17. For 48-bit sequence generator what is the minimum number of memory elements reqµired?
Counters
A
0
B
0
y
1
AWO
0 1
I
0
0 1 I
1 1 1
I 0 0
1 l 1 Y=A+B
(a) (b)
------10 ll 10 ll
'--v---' '--v---'
J A i--~~-1_. J
y
CLK-,----0!>
K A K
(c)
Sequence generator circuit using synchronous counter, (a) State Table,

(b) Output equation, (c) Circuit diagram
10.8 A DIGITAl CLOCK
A very interesting application of counters and decoding arises in the design of a digital clock. Suppose that
we want to construct an ordinary clock which will display hours, minutes, and seconds. The power supply
for this system is the usual 60-Hz 120-Vac commercial power. Since the 60-Hz frequency of most power
systems is very closely controlled, it is possible to use this signal as the basic clock frequency for our system.
Note that in several countries commercial power supply is 50-Hz and not 60-Hz. There one can use standard
variable frequency signal generator, set at 60-Hz, as input.
In order to obtain pulses occurring at a rate of one each second, it is necessary to divide the 60-Hz power
source by 60. lfthe resulting 1-Hz waveform is again divided by 60, a one-per-minute waveform is the result.
Dividing this signal by 60 then provides a one-per-hour waveform. This, then, is the basic idea to be used in
forming a digital clock.
A block diagram showing the functions to be performed is given in Fig. 10.40. The first divide-by-60
counter simply divides the 60-Hz power signal down to a 1-Hz square wave. The second divide-by-60
counter changes state once each second and has 60 discrete states. It can, therefore, be decoded to provide
signals to display seconds. This counter is then referred to as the seconds counter.
60Hz
-c:P'- +60
1 cycle/s
__n_n_
+60 ~r+60 ~k_cy_c_le_/h-r .ff~
Seconds Minutes Hours
counter counter counter
Block diagram of digital clock

The third divide-by-60 counter changes state once each minute and has 60 discrete states. It can thus be
decoded to provide the necessary signals to display minutes. This counter is then the minutes counter.
The last counter changes state once each 60 minutes (once each hour). Thus, if it is a divide-by-12 counter,
it will have 12 states that can be decoded to provide signals to display the correct hour. This, then, is the hours
counter.
As you know, there are a number of ways to implement a counter. What is desired here is to design the
counters in such a way as to minimize the hardware required. The first counter must divide by 60, and it need
not be decoded. Therefore, it should be constructed in the easiest manner with the minimum number of flip-
flops.
For instance, the divide-by-60 counter could be implemented by cascading counters (12 x 5 = 60, or 10 x 6
= 60, etc.). The TTL MSI 7490 decade counter can be used as a divide-by-IO counter, and the TTL MSI 7492
can be used as a divide-by-6 counter. Cascading these two will provide a divide-by-60 counter as shown in
Fig. 10.41. The amplifier at the input provides a 60-Hz square wave of the proper amplitude to drive the 7490.
The 7492 is connected as a divide-by-12 counter, but only outputs QA, Q8 , and Qc are used. In this fashion,
the 7492 operates essentially as a divide-by-6 counter.
/ / 60Hz 6Hz 1 Hz
~ Ampli- ...IlSL ...IlSL ...IlSL
fier (Qc)
[/
Divide-by-60 counter
The seconds counter in the system also divides by 60 and could be implemented in the same way. However,
the seconds counter must be decoded. We are interested in decoding this counter to represent each of the 60
s in 1 min. This can most easily be accomplished by constructing a mod~ IO counter in series with a mod-6
counter for the divide-by-60 counter. The mod- IO counter can then be decoded to represent the units digit of
seconds, and the .mod-6 counter can be decoded to represent the tens digits of seconds.
Since both the 7490 and the 7492 count in straight 8421 binary, a 7447 decoder-driver can be used with
each to drive two 7-segment indicators, as shown in Fig. I 0.42. Notice that the 7492 is connected as a divide-
by-12 counter; but only outputs QA, Q8 , and Qc are used to drive the 7447 decoder-driver.
The minutes counter is exactly the same as the seconds counter, except that it is driven by the one-per-
minute square wave from the output of the seconds counter, and its output is a one-per-hour square wave, as
shown in Fig. 10.42.
The divide-by-12 hours counter must be decoded into 12 states to display hours. This can be accomplished
by connecting a mod-IO (54/74160) decade counter in series with a single flip-flop E as shown in Fig. 10.43.
This forms a divide-by-20 (10 x 2 = 20) counter. Feedback is then used to form a mod-12 counter.
The hours counter must count through states 00, 01, 02, ... , 11, and then back to 00. The NAND gate in
Fig. 10.43 will go low as the counter progresses from count 11 to count 12, and this will immediately clear
the 74160 to 0000 and reset the flip-flop E to 0. The counter actually skips from count 11 to count 00 omitting
the eight counts in between. This is the mod-12 hours counter; the 74160 will provide the units of hours while
the flip-flop will provide the tens of hours. Notice that the 74160 is reset asynchronously and there might then
be glitches at the outputs of the decoding gates. However, this is one case where these glitches will have no
effect, since they are too narrow to cause a visible indication on the light emitting diodes (LEDs).
Counters
(1 Hz)
(1 cycle/min) +6 + 10 _n__n_
7492 7490
(1 cycle/h) (1 cycle/min)
QD QC QB QA QD QC QB QA
7447 7447
,-1 /-/
/_/ LED I I LED
Tens Units
A 1O x 6 mod-60 counter with units and tens decoding
RESET
I cycle/h
+ 10 __n__n_
CLR 74160
QD QC QB QA
7447 7447
Tens Units
Mod-12 hours counter
Finally, some means must be found to set the clock because the flip-flops will assume random states when
the power is turned off and then turned back on again. Setting the clock can be quite easily accomplished by
means of the SET push-buttons shown in Fig. 10.44. Depressing the SET HOURS button causes the hours
counter to advance at a one-count-per-second rate, and thus this counter can be set to the desired hour. The
minutes counter can be similarly set by depression of the SET MINUTES button.
Set Set Set

Hours hours Minutes minutes Seconds seconds
+60 + 60 lHz 60Hz

+ 12 +60
-...._,_.,e:---, 10 X 6 --:S.Z...J.J,lt---, 10 X 6
,-, lol
/_/ ~
Tens Units Tens Units
Digital clock
Depression of the SET SECONDS button removes the signal from the seconds counter, and the clock can
thus be brought into synchronization.
By means of large-scale integration (LSI), it is possible to construct a digital clock entirely on one
semiconductor chip. Such units are commercially available, and they perfom1 essentially the function shown
in the logic diagram in Fig. 10.43 (the seven-segment indicators are, of course, separate). The National
Semiconductor 5318 is one such commercially available LSI digital clock. It is available in a 24-pin dual in-
line (DIP) package measuring 0.54 x 1.25 in.
10.9 COUNTER DESIGN USING HDl
Counter design in HDL is straight forward if one uses arithmetic operator+ and - that corresponds to binary
addition and subtraction respectively. We show a modulo-8 up counter design in the example given in first
column. It is left to the compiler to decide which flip-flop is to be used. If one wants to ensure use of a
particular type of flip-flop say, JK then the code should be written in a manner shown in second column for
modulo-3 up counter shown in Fig. 10.16a.
module UC(Clock, Reset,Q); module UCJK(A,B,Clock,Reset);

input Clock, Reset;
output [2:0] Q; requires 2 flip-flop
//modulo 8 requires 3 flip-flop wire JA, JB, KA, KB;
reg [ 2 : 0 J Q; as.sign
always@ (negedge Clock
or negedge Reset) assign KA=l'bl;
if Q"'3'b0;
else Q= Q+l;
endmodule
Counters
module JKFF(Q,J,K,Clock,Reset);
input·· .J, K, Clock, Reset;
output Q;
reg Q;
always@ (negedge or negedge
if{,-Reset) Q=l'bO;
else Q <= (J&-Ql I (-K&Q);
endmodule
Design a modulo-8 up down counter which counts in upward direction if input MODE =
0, else counts in downward direction. It should also have a parallel load facility. When PL
= 1, a 3-bit number Dis asynchronously loaded to the cmmter. The counter counts at the
negative edge of CLOCK and its output is represented by Q.
Solution The Verilog HDL code for the problem is given below. We have used a new keyword integerJQ hold a
value temporarily. This helps us in writing both up and down count in one single statement that responds to clock
within always block.
MODE,D, Down
input CLOCK,PL,MODE; pa.rallel load
input[2:0]
output [ OJ Q; //modulo
reg J2:0J Q;
integer updown.;. //updown -1 dependi.ng on MODE
always (negedge·.CLOCK)
·begin
if
The code in the first column when executed with modulo-3 JK counter, UCJK described
in this section generates monitor output as shown in column 2 and timing diagram as
shown below. Show how the test bench verifies Verilog code UCJK is that of a modulo-3
counter.
60 .Clock= 0, A=O B=O

70 1, A=O B=O
0, B=O
1, B=O
Clock= O, A""'O B=l
//Clock
%b,A= B=%_b\n"_,
Clock,A,B);
end
end!aodw.e
Ons 1IOns j2?ns 1 130ns 140ns !50ns 16,0~s ' 17?~s, i80ns 190ns 1100ns
I l I l i i ! ! \ !
' I
' l I ' ' i
' l I
' I \ I l I
testUC.A I \ I \
'
testUC.B I \
testUC.Clock I \ I \ I \ I \ I \_
testUC.Reset J
Solution The test bench, given in the code above runs the simulation for 5 + WO = 105ns duration. At every l Ons
clock toggles giving a· l O + l O = 20 ns clock cycle time. So we have 5 negative edges of the clock (I to, 0 transition)
from start at20, 40, 60, 80 and l OOns: Ifwe look at the timing diagram and monitor output we gee JK, flip :!lop output
changes valueatnegative.edges as BA= 00 (initially reset by 'Reset'), 01, 10, 00, 01,lOetc. These show that .three
counting states 00, 01, 10 get repeated. Hence, the code of module UCJKbehaves like a modulo~3 counter.

Design a self correcting modulo-3 down counter.
Solution We need2 fiip-flop8:, sayB and A for this purpose which has 4 states. Let the down counter count like
10 4 01 4 00 --410, .. and undesired state 11 corrects itself to 10. The excitation tabl.e of Fig. 8.35 is used for
the design purpose.
In MethruM, we use SR flip-flop for design pwpose. Figure 10.45a shows the state table and in the
second column, necessary inputsfor the two SR flip-flops are given. Figure 10.45b shows the use of
Karnaugh Map to get the design equations.
In A.,te~Qd.:2, \V~ use JK:flip-flop for desigu purpose. The fourth column shows necessary. inputsfor
tile twp JKflip.flops. Figure 10.45c shows the use of Kamaugh Map to get the design equations.
In Method<J, we use.D flip-flop for design purpose. The third column shows necessary inputs for the
two D flip-flops, Fig.10.45d shows the use ofKamaugh Map to get the design equations.
_________________c_o_un_te_rs_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~
In Method-4, we use T flip-flop for design purpose. The last column shows necessary inputs for the
two D flip-flops. Figure 10.45e shows the use of KamaughMap to get the design equations.
..
Present State Next State

BnAn Bn+1An+1
SsRB S,iRA DB DA JJ/(B JAKA TB TA
0 0 10 10 OX 1 0 1X ox 1 0
0 I oO OX 0 l 0 0 ox XI 0 1
10 0 l 0 1 1 0 0 1 Xl 1 X 1 1
I I 10 XO 0 l l 0 XO X 1 0 1
(a)
An A A
0 1 11 0 l 11 0 1
Bn B 11 Bn
0 1 0 0 0 X 0 0 0
I
1 0 X l 1 0 1 1 0 1 0 I 1I
1_J
(b)
A,, 0 1 An O 1
B,, -,.....--,--, Bil -,.---,--,
o rx: x I I
0 0 X
CC _x:
I I
l 'X'
1__ , X 1 '1'
, __1 0 1
(c)
A A
0 An
BJI " 0 1 B11
11 1 Bil
0 1
0 l 0 0 0 0 0 :r: I
0
1 0 1 1 1 0 ,__1 ,
I
I I
0 1
- - - L-
LLJJJ
(d) (e)
(a) State table for the self correcting modulo~3 counter and required inputs,
(b) Design with SR flip-flops, (c) Design with JK flip-flops, (d)Design with
D flip-flops, (e) Design with T flip-flops
A counter has a natural count of 2", where n is the number of flip-flops in the counter. Counters of any
modulus can beconstructed by incorporating logic which causes certain states to be skipped over or
omitted. One technique for skipping counts is to steer the clock pulses to certain flip-flops at the proper
tim~ 0 this is <;alloo steeringlogic. A.s1ccond teclmiqueisto preconditiortthe logicinputs to eachflip,-flopin

order to omit.certai11 states,'I'ltis is falledloqk-ahe.id]ogic. .. .
Logic can be inclt1ded. ·sucll that ti'ltc coi:tnter can operate in either a count-up or count-down mode.
Furthermore,logic ga,s bin.be de~igned, to uniquely decode each state of a counter.
. . .. Higher-modulus c<Jllllters ca11 be el'lSily co.nstructedby usin9 combinations of lower-modulus counters.
S.ich configurations repr~sent a C~!ll}'I'Omise between speed and hardware count.
The digital dock is an.interesting.applkation that illustrates some of the methods employing counters
and decoders.
• decoding gate A logic gate whose output is • parallel counter A synchronous counter
high ( or low) only during one of the unique in which all flip-flops change states
states of a counter. simultaneously since all clock inputs are
• glitch An undesired positive or negative pulse driven by the same clock.
appearing at the output of a logic gate. • presettable counter A counter incorporating
• lock out of a counter Counter getting locked logic such that it can be preset to any desired
into unused states. state.
• modulus Defines the number of states through • ripple counter An asynchronous counter in
which a counter can progress. which each flip-flop is triggered by the output
• natural count The maximum number of states of the previous flip-flop.
through which a counter can progress. Given • sequence generator Generates a binary data
by 2n, where n is the number of flip-flops in sequence.
the counter. • up-down counter A basic counter, synchronous
or asynchronous, that is capable of counting
in either an upward or a downward direction.
a. 7 b. 10
C. 8
IO.I Draw the logic diagram, truth table, and 10.5 See if you can draw the waveforms for a 10-
waveforms for a two-flip-flop ripple counter flip-flop ripple counter. What difficulties do
similar to that in Fig. IO.I. you encounter?
10.2 Draw the logic diagram, truth table, and 10.6 What is the largest decimal number that can
waveforms for a three-flip-flop ripple counter be stored in each counter in Prob. 10.4?
that uses JK flip-flops sensitive to a clock PT. 10. 7 Draw the waveforms at QB, Qc, and Qv for
10.3 What is the clock frequency if the period of B a 7493A, assuming that a I-MHz clock is
in Fig. 10.1 is 1000 ns? applied at inputB.
10.4 Determine the number of possible states in a 10.8 Draw the logic diagram, truth table, and
counter composed of the following number of waveforms for a two-flip-flop ripple counter
flip-flops: operating in the count-down mode.

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Digital Logic

2.1 THE BASIC GATES-NOT, OR, AND

The Inverter (NOT Gate)

(a) (b) (c) (d)

OR gate symbols: (a) Two-input, (b) Three-input, (c) Four input,

Work out the truth table for Fig. 2.9a.

Logic circuit and truth table of Example 2.3

Three Inputs Figure 2.11 a shows a 3-input AND A B C y

(a) (b) (c) (d)

AND gate symbols: (a) Two-input, (b) Three-input, (c) Four-input,

Work out the truth table for Fig. 2.15a.

A A B A' B' Y=A~B'

logic circuit and truth table of Example 2.4

Write the Boolean equation for Fig. 2.17b.

The :final output is

(a) AND-OR, {b) OR-AND network

What is the logic circuit whose Boolean equation is

(a) Intermediate, (b) Final logic circuit of Example 2.7

I. A system in which H= 1 and L = 0 is (positive, negative) logic.

4. Write an expression for an inverter, or NOT gate equivalent to Y = not A.

2.2 UNIVERSAL LOGIC GATES-NOR, NANO

NOR Gate Symbol

~=D-{)»-r ~=[>-r ~=§-r

NOR logic gate

Bubbled AND Gate

inversion that takes place before the AND operation.

analyzed this circuit in Example 2.4 and obtained

De Morgan's First Theorem

Universality of NOR Gate

(a) (b) (c)

Eye of the Beholder

Prove that Fig. 2.23c is logically equivalent to Fig. 2.23a.

Equivalence among logic circuits: Example 2.9

Convert Table 2.2 into a timing diagram.

;D-{>-y ;u-y ~=B-y

NANO logic gate

table in Fig. 2.9b. We see that output Y and inputs A

De Morgan's Second Theorem

Universality of NANO Gate

(a) (b) (c)

==c=>- =D- ¢=}

Useful logic equivalences

TTL NANO Gates

Standard TTL Gates

Type Quad 2-lnput Triple 3-lnput Dual 4-lnput Single 8-lnput

Prove that Fig. 2.29c is logically equivalent to Fig. 2.29a.

Equivalence of logic gates: Example 2.12

Show a timing diagram for the NAND-NAND circuit of Fig. 2.29a.

l 0. Write the Boolean expression for a 2 input NANJJ gate.

2.3 AND-OR-INVERT GATES

(a) AND-OR circuit, (b) NANO-NANO circuit, (c) AND-OR-INVERT circuit

Examples of AND-OR circuits

Expandable AND-OR-INVERT Gates

2.4 POSITIVE AND NEGATIVE LOGIC

Positive and Negative Gates

Voltage Definitions of Basic Gates

·•· ··.·· Gate ·. . . •

Here are some ideas that you should try to remember:

Assertion-level logic diagr.im ,showing the detectio., of zero and mir:ms