Design IP Datasheet

RX Controller IP for MIPI CSI-2 v2.1

Overview Customer Application

The Cadence® Receiver (RX) Controller IP for MIPI® Camera

Serial Interface 2 (CSI-2SM) is responsible for handling and

APB Slave
Pixel i/f 0

Pixel i/f 1

Pixel i/f 7
decoding CSI-2 protocol-based camera or other sensor data Reference
Camera
streams received via a MIPI D-PHYSM link and managing the

APB Slave

APB Slave
Subsystem
forwarding or unpacking of payload data to the pixel stream Cadence RX Controller IP for MIPI CSI-2
interfaces. The RX Controller IP for CSI-2 allows the selection
of multiple independent streams to support the control of

PPI Data 0

PPI Data 1

PPI Data 7
the destination for each data packet (for example, Bayer
input of ISP, RGB/YUV input of ISP, or DMA to memory). Cadence Controller IP
Cadence Design IP for MIPI D-PHY
for MIPI I2C/I3C
Developed by experienced teams with industry-leading domain

I2C/I3C SCL/SDA
expertise and extensively validated with multiple hardware
DP/DN

DP/DN

DP/DN
platforms, the RX Controller IP for CSI-2 is engineered to
quickly and easily integrate into any system-on-chip (SoC)
design, and to connect seamlessly to a Cadence or third-party

SCL /SDA
Camera Sensor
D-PHY via a standard PHY-Protocol Interface (PPI).

The RX Controller IP for CSI-2 is part of the comprehensive Figure 1: Example CSI-2 Receiver System
Cadence Design IP portfolio comprised of interface, memory,
analog, and system and peripheral IP.
Benefits
•• Full featured and highly configurable IP core
is area optimized for each application
•• Complete solution—both host and peripheral
IP available
•• Emulated on Palladium and validated in FPGA platforms.
•• Multi-stream pixel interface support
•• Automotive variant with Safety Manual

Key Features
• Compliant with MIPI CSI-2 v2.1 Specification • Support for MIPI D-PHY v2.1 specification, with 8-bit and
16-bit PPI data width and links with 1, 2, 4, or 8 data lanes

• Provides up to 8 independent stream output interfaces, • Protocol-only support (no stream modules) for raw
with a highly configurable range of options, including decode of CSI packets and error detection, providing
multiple pixel modes, various buffering modes, packed extremely low gate count
data mode, Data Type selection, and Virtual Channel or
Data Type interleaving

• Configurable internal data path width of 32 or 64 bits • 32-bit Arm® AMBA® APB Slave programming interface
to allow system clock frequency reduction

• LRTE – Efficient Packet Delimiter support (Option 1 and 2) • Support for external RAM/register or internal
register-based stream buffer

• Support for all primary and secondary data formats • Supports ULPS on all data lanes and clock lane
Product Details APB DUAL Port Ram

The RX Controller IP for CSI-2 consists of a lane management RX Controller IP for CSI-2

module that connects via the PHY-Protocol Interface (PPI) to a D-PHY Register Control
receiver module, an external register interface for configuration of
the receiver IP, a CSI-2 protocol module for protocol decode, and CSI2RX_Front
(Lane Management)
CSI2RX_Protocol CSI2RX_Stream 0
Stream
an optional CSI-2 stream modules for providing received CSI-2 packets CRC ECC Flow Control
Pixel
FCC Interface 0
Unpacking (pixel or
from the D-PHY and providing synchronization information and D-PHY
PPI Error
Detection
Filtering Monitor packed data)
pixels/packed data to the pixel stream interface. Each stream has Protocol
Decode CSI2RX_Stream 1 Stream
an external memory interface that can act as a line buffer or as a Interface 1
short buffer to minimise latency.
CSI2RX_Stream n Stream
Interface n
Lane Management Module
PPI Byte CLK System CLK Pixel CLK
The RX Controller IP for CSI-2 front module receives 8 or 16 bits
from each enabled D-PHY data lane via the PPI interface and packs
it into the 32-bit or 64-bit datapath for transfer to the CSI-2 protocol Figure 2: CSI-2 Receiver
module. The D-PHY deskew and ULPS entry/exit conditions are
monitored in this module. An optional descrambling block will Certain data types support multiple pixels per pixel clock cycle
decode any incoming scrambled data. to increase throughput. Three buffering modes are available:
• Full – Hold full line in buffer before transfer to pixel interface
Protocol Module
• Fill Level – A programmable watermark controls when data is
The RX Controller IP for CSI-2 protocol module decodes the CSI-2
transferred to the pixel interface
protocol stream coming from the camera/sensor interfaces. It also
performs error checking and correction and a cyclic redundancy check • Short – Data is passed to the pixel interface with low latency
(CRC) to ensure data integrity. The CSI-2 protocol module also
monitors the CSI-2 protocol stream for synchronization events. Monitor and Frame Capture Control Modules

Stream Module The RX Controller IP for CSI-2 provides stream channel monitors
that can be configured to track and observe frames, lines, bytes,
The RX Controller IP for CSI-2 stream module can provide packed and clock cycles on individual virtual channels within each stream.
data or pixel data in single, dual, quad, or octal pixel per clock
cycle to the system. The pixel interfaces support flow control The monitors can be configured with the virtual channel and with
to allow the system to stall the data stream. the expected frame length to detect whenever the number of
expected lines is truncated or exceeded, to count the number
The stream module formats data from CSI-2 packets into RAW of lines in a frame, and to count the number of clock cycles from
Bayer, RGB, YUV, and user-defined packed data formats. Up to a start or end of a frame.
eight highly configurable streams are available, all of which will
take the data received from the protocol module and provide data The frame capture control (FCC) function allows a specified frame
to the stream interface in packed or pixel format. number to be extracted from the incoming packet stream.

Related Products Deliverables

• Cadence Design IP for MIPI D-PHY • Unencrypted, synthesizable Verilog HDL
• Cadence TX Controller IP for MIPI CSI-2 • Cadence Genus™ Synthesis Solution scripts
• Cadence Display Controller IP for MIPI DSISM • Documentation—Integration and User Guide, Release Notes
• Cadence Master Controller for MIPI I3CSM • Sample verification testbench with integrated Cadence
• Cadence Slave Controller for MIPI I3C Verification IP (VIP)
• Software Driver

For more information, visit ip.cadence.com

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to create the innovative end products that are transforming the way people live, work, and play. The
company’s Intelligent System Design strategy helps customers develop differentiated products—from
chips to boards to intelligent systems. www.cadence.com
© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design
Systems, Inc. in the United States and other countries. Arm and AMBA are registered trademarks or trademarks of Arm Limited (or its subsidiaries)
in the US and/or elsewhere. MIPI, CSI-2, D-PHY, DSI, and I3C are registered trademarks or service marks owned by the MIPI Alliance. All other trademarks
are the property of their respective owners. 12454 08/19 SA/RA/PDF