EEE1002 EEE1010 Lecture Notes

EEE1002/EEE1010 - Electronics I
Analogue Electronics
Lecture Notes
S. Le Goff
School of Electrical and Electronic Engineering
Newcastle University
School of EEE @ Newcastle University
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Module Organization
Lecturer for Analogue Electronics: S Le Goff (module leader)

Lecturer for Digital Electronics: N Coleman
Analogue Electronics: 24 hours of lectures and tutorials (12 weeks  2 hours/week)
Assessment for analogue electronics:

 Mid-semester test in November, analogue electronics only, 1 hour, 8% of the final mark.
 Final examination in January, analogue & digital electronics, 2 hours, 50% of the final mark.
Recommended Books:
 Electronics – A Systems Approach, 4th Edition, by Neil Storey, Pearson Education, 2009.
 Analysis and Design of Analog Integrated Circuits, 5th Edition, by Paul Gray, Paul Hurst,
Stephen Lewis, and Robert Meyer, John Wiley & Sons, 2012.
 Digital Integrated Circuits – A Design Perspective, 2th Edition, by Jan Rabaey, Ananta
Chandrakasan, and Borivoje Nikolic, Pearson Education, 2003.
 Microelectronic Circuits and Devices, 2th Edition, by Mark Horenstein, Prentice Hall, 1996.
 Electronics Fundamentals – A Systems Approach, by Thomas Floyd and David Buchla,
Pearson Education, 2014.
 Principles of Analog Electronics, by Giovanni Saggio, CRC Press (Taylor & Francis Group),
2014.
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EEE1002/EEE1010 – Electronics I – Analogue Electronics 1
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1. Semiconductors
Solid materials may be divided, with respect to their electrical properties, into three categories:
1. Conductors
Conductors (e.g., copper, aluminium) have a cloud of free electrons at all temperature above
absolute zero. This is formed by the weakly bound “valence” electrons in the outermost orbits of
their atoms. If an electric field is applied across such a material, electrons will flow, causing an
electric current.
2. Insulators
In insulating materials, the valence electrons are tightly bound to the nuclei of the atoms and very
few of them are able to break free to conduct electricity. The application of an electric field does
not cause a current to flow as there are no mobile charge carriers.
3. Semiconductors
At very low temperatures, semiconductors have the properties of an insulator. However, at higher
temperatures, some electrons are free to move and the materials take on the properties of a
conductor (albeit a poor one). Nevertheless, semiconductors have some useful characteristics
that make them distinct from both insulators and conductors.
To understand the operation of diodes, transistors, and other electronic devices, we need to
understand the basic structure of semiconductors.
A few common semiconductor materials: silicon (Si), germanium (Ge), gallium arsenide (GaAs),
indium phosphide (InP), silicon carbide (SiC), silicon-germanium (SiGe).
The first transistors were made from germanium (Ge). Silicon (Si) types currently predominate but
certain advanced microwave and high performance versions employ the compound
semiconductor material gallium arsenide (GaAs) and the semiconductor alloy silicon germanium
(SiGe).
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Silicon and germanium fall in column IVa of the Periodic Table. This is the carbon family of
elements. The characteristic of these elements is that each atom has four electrons to share with
adjacent atoms.
Z Element No. of electrons/shell

6 carbon 2, 4
14 silicon 2, 8, 4
32 germanium 2, 8, 18, 4
50 tin 2, 8, 18, 18, 4
82 lead 2, 8, 18, 32, 18, 4
Let us have a closer look at silicon. The crystal structure of silicon is represented below.
Si Si Si
Covalent bond
Si Si Si Electrons on the outer

shells of two neighbouring
atoms
Si Si Si
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The nature of a bond between two silicon atoms is such that each atom provides one electron to
share with the other. The two electrons thus shared between atoms form a “covalent bond”. Such
a bond is very stable and holds the two atoms together very tightly. It requires a lot of energy to
break this bond.
All of the outer electrons of all silicon atoms are used to make covalent bonds with other atoms.
There are no electrons available to move from place to place as an electrical current. Thus, a pure
silicon crystal is quite a good insulator. Increasing the temperature results in some electrons
breaking free from their covalent bonds and this improves the conductivity of the silicon crystal.
To allow a silicon crystal to conduct electricity without having to increase the temperature, we
must find a way to allow some electrons to move from one place to the other within the crystal
despite the covalent bonds between atoms. One way to accomplish this is to introduce an impurity
such as arsenic or phosphorus into the crystal structure. Such process is called doping. These
elements are from column Va of the Periodic Table, and have five outer valence electrons to
share with other atoms.
Si Si Si
Free electron
Si P Si
Covalent bond
Si Si Si
Four of these five electrons bond with adjacent silicon atoms as before, but the fifth electron
cannot form a bond and is thus left “alone”. This electron can easily be moved with only a small
applied electrical voltage. Because the resulting crystal has an excess of current-carrying
electrons, each with a negative charge, it is known as "N-type" silicon.
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Such construction does not conduct electricity as easily as, say, copper or silver since it does
exhibit some resistance to the flow of electricity. It cannot properly be called a conductor, but at
the same time it is no longer an insulator. Therefore, it is known as a semiconductor.
We obtained a semiconductor material by introducing a 5-electron impurity into a matrix of 4-

electron atoms. We can also do the opposite and introduce a 3-electron impurity into such a
crystal. Suppose we introduce some aluminium (from column IIIa in the Periodic Table) into the
crystal. We could also use gallium which is also in column IIIa.
These elements only have three valence electrons available to share with other atoms. Those
three electrons do indeed form covalent bonds with adjacent silicon atoms, but the expected
fourth bond cannot be formed. A complete connection is impossible here, leaving a "hole" in the
structure of the crystal.
Si Si Si
Hole
Si Al Si
Covalent bond
Si Si Si
There is an empty place where an electron should logically go, and often an electron will try to
move into that space to fill it. However, the electron filling the hole has to leave a covalent bond
behind to fill this empty space, and therefore leaves another hole behind as it moves. Yet another
electron may move into that hole, leaving another hole behind, and so on. In this manner, holes
appear to move as positive charges through the crystal. Therefore, this type of semiconductor
material is designated "P-type" silicon.
In an N-type semiconductor, the electrons are often referred to as the majority charge carriers,
whereas the holes are called the minority charge carriers since they are actually also present but
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at much lower concentration. In a similar way, in a P-type semiconductor, the holes are referred to
as the majority charge carriers, whereas the electrons, which are present at much lower
concentration, are the minority charge carriers.
The role played by the minority charge carriers can sometimes be ignored for simplicity purposes.
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2. The PN Junction (Diode)
 Basic Operation
We have just seen that a crystal of pure silicon can be turned into a relatively good electrical
conductor by adding an impurity such as arsenic or phosphorus (for an N-type semiconductor) or
aluminium or gallium (for a P-type semiconductor). By itself, a single type of semiconductor
material is not very useful. But, something interesting happens when a single semiconductor
crystal contains both P-type and N-type regions.
Hereafter, we examine the properties of a single silicon crystal which is half N-type and half P-
type. The two types are shown separated, as if they were two separate crystals being put in
contact. In the real world, two such crystals cannot be joined together usefully. Therefore, a
practical PN junction can only be created by inserting different impurities into different parts of a
single crystal.
Mobile negative charges

Mobile positive charges
(free electrons)
(free holes)
N-type silicon P-type silicon
- - - + + +
+ + - - -
+
- - - + + +
+ + + - - -
Bound positive charges Bound negative charges
When we join the N- and P-type crystals together, an interesting interaction occurs around the
junction. The extra electrons in the N region will combine with the extra holes in the P region. This
leaves an area where there are no mobile charges, known as depletion region, around the
junction.
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Junction
- - - + + +
+ + - - -
+
- - - + + +
+ + + - - -
- - + +
+ + - - -
+
- - + +
+ + + - - -
Depletion region
Suppose now that we apply a voltage to the outside ends of our PN crystal.
Assume first that the positive voltage is applied to the N-type material. In such case, the positive
voltage applied to the N-type material attracts free electrons towards the end of the crystal and
away from the junction, while the negative voltage applied to the P-type end attracts holes away
from the junction.
Reverse bias V 0 volt
+ -
- - + +
+ + - - -
+
- - + +
+ + + - - -
The depletion region

becomes wider
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The result is that all available current carriers are attracted further away from the junction, and the
depletion region grows correspondingly larger. Therefore, there is no current flow through the
crystal because no current carriers can cross the junction. This is known as reverse bias applied
to the semiconductor crystal.
Assume now that the applied voltage polarities are reversed. The negative voltage applied to the
N-type end pushes electrons towards the junction, while the positive voltage at the P-type end
pushes holes towards the junction. This has the effect of shrinking the depletion region.
 0.7 volt
Forward bias V 0 volt

- +
- - + +
+ + - - -
+
- - + +
+ + + - - -
The depletion region becomes narrower as V

is increased, until eventually it disappears.
Once the applied voltage V has become large enough to make the depletion region completely
disappear, i.e. once the value of V becomes equal to the threshold voltage Vd of the PN junction
(Vd  0.7 volt for silicon and Vd  0.3 volt for germanium), current carriers of both types are finally
able to cross the junction into the opposite ends of the crystal. Now, electrons in the P-type end
are attracted to the positive applied voltage, while holes in the N-type end are attracted to the
negative applied voltage. This is the condition of forward bias.
The conclusion is that an electrical current can flow through the junction in the forward direction,
but not in the reverse direction. This is the basic property of a semiconductor diode.
It is important to realize that holes exist only within the crystal. A hole reaching the negative
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terminal of the crystal is filled by an electron from the power source and simply disappears. At the
positive terminal, the power supply attracts an electron out of the crystal, leaving a hole behind to
move through the crystal toward the junction again.
 Current-Voltage Characteristic of a Diode
Symbol of a diode
Cathode Anode
The Shockley diode equation, named after transistor co-inventor William Shockley, gives the
current–voltage characteristic of a diode in either forward or reverse bias. The equation is given
by
  qV     V  
I  IS  exp   1  IS  exp   1 ,
  kT    
 T 
V
where - Is: Saturation current of the diode (in the range 10-8 to 10-16 A, typically);
- : Emission coefficient. This is an empirical constant that varies from 1 to 2 depending
on the fabrication process and semiconductor material and in many cases is
assumed to be approximately equal to 1 (and thus omitted).
- q: Electron charge (= 1.60210-19 C);
- T: Temperature in degrees Kelvin;
- k: Boltzmann’s constant (= 1.3810-23 J/K);
- VT: Thermal voltage ( 25 mV at room temperature).
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This expression means that the current flowing through a diode varies exponentially with the
applied voltage.
Current I
V
Exponential
increase!
I
Voltage V
Reverse bias Forward bias
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This rather complicated equation is a bit difficult to use for manual circuit analysis. Electronic
engineers deal with this problem by simplifying things and using the much simpler model of the
diode given below.
Current I
Diode is “on”: Constant
voltage (V = Vd) across
Diode is “off”: Zero the diode, no constraint
current through the on the current
diode when V < Vd
Voltage V
Vd
Note that Vd is called threshold voltage or forward voltage drop of the diode. We have Vd  0.7 V
for a silicon diode, Vd  0.3 V for a germanium diode, and Vd  0.25 V for a Schottky diode.
In this model, the current is zero for any voltage below the threshold voltage Vd. In effect, the
diode is viewed as a switch which is open when we apply low or negative voltages across it but
which closes when we apply a voltage equal to Vd across it. It is important to understand that, with
this model, it is strictly impossible to get a voltage larger than Vd across the diode.
 Zener Diodes
With the application of sufficient reverse voltage, a diode experiences a breakdown and conduct
current in the reverse direction. Electrons which break free under the influence of the applied
electric field can be accelerated enough that they can knock loose other electrons and the
subsequent collisions quickly become an avalanche.
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Current I
Zener voltage
Vz
Voltage V
Vd
Reverse bias Forward bias

Avalanche
breakdown
When this process takes place, very small changes in voltage can cause very large changes in
current. The breakdown process depends upon the applied electric field. Thus, by changing the
thickness of the layer to which the voltage is applied, Zener diodes, named after the American
physicist Clarence Zener, can be formed which break down at voltages from about a few volts to
several hundred volts.
The useful feature here is that the voltage across the diode remains nearly constant even with
large changes in current through the diode. Such diodes find wide use in electronic circuits as
voltage regulators. To illustrate this point, let us consider the circuit shown below.
I
Zener
R diode
Poorly regulated V
in
voltage
Vz Vout
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In this circuit, the Zener diode is connected so that it is reverse-biased by the input signal. We can
write the following equation: Vin  R  I  Vout .
If Vin > Vz, the diode junction will break down and conduct, drawing current from the resistance R.
The diode prevents the output voltage Vout from going above its breakdown voltage Vz and thus
generates a constant output voltage Vout = Vz, irrespective of the value of the input voltage as long
as it remains higher than Vz.
Note that, in this case, the current flowing through the resistor is given by
Vin  Vout V  Vz
I  in .
R R
If Vin < Vz, the reverse-bias voltage is not sufficient to break down the junction. As a result, the
diode will conduct no current. The output voltage will be equal to the input voltage as there is no
voltage drop across the resistance, i.e. Vout = Vin. In this situation, the Zener diode has no effect
on the circuit.
Vout
Region of
voltage
regulation
Vz
Vin
Vz
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Tutorial 1 – Diode Circuits
V Two modes of operation
I
ON (forward-biased) OFF (reverse-biased)
V = Vd and I > 0 V < Vd and I = 0
Question 1: Half-Wave Rectifier
The primary function of a rectifier circuit is to change an AC input voltage into a voltage that is
only positive or only negative. In essence, a rectifier eliminates the unwanted polarity of the input
waveform. As an illustration, consider the circuit below called half-wave rectifier.
Vin(t) R Vout(t)
Find the output signal Vout(t) obtained with the input signal Vin(t) depicted below.
Vin(t)
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Question 2: Half-Wave Rectifier with Capacitor
We can modify the half-wave rectifier studied in Question 1 by placing a capacitor in parallel with
the resistor. We thus obtain a power supply circuit that accepts an AC voltage as its input and
provides a DC voltage as its output. This circuit can also be employed as a demodulator as part of
the receiver in amplitude-modulation (AM) communication systems.
Study the operation of the circuit depicted below assuming that the input signal is a sine wave.
C
Vin(t) R Vout(t)
Question 3: Diode Clipping
A diode-clipping circuit can be used to limit the voltage swing of a signal. Consider the circuit
depicted below and find the expression of the output voltage Vout(t) as a function of the input
voltage Vin(t). V1 and V2 designate two constant voltage sources (with V1 > 0 and V2 > 0).
2
Vin(t) - + Vout(t)
V2 V1
+ -
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Question 4: Power-Supply Circuit using a Full-Wave Bridge Rectifier
Consider the circuit shown below.
Bridge rectifier
Vin(t)
C
R Vout(t)
Study the operation of the circuit depicted below assuming that the input signal is a sine wave.
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3. The Bipolar Junction Transistor
The bipolar point-contact transistor was invented in 1947 at the Bell Telephone Laboratories
(USA) by John Bardeen and Walter Brattain under the direction of William Shockley. The junction
version known as the bipolar junction transistor (BJT), invented by Shockley in 1948, is the
version we are going to study hereafter. In acknowledgement of this accomplishment, Shockley,
Bardeen, and Brattain were jointly awarded the 1956 Nobel Prize in Physics "for their researches
on semiconductors and their discovery of the transistor effect."
John Bardeen, William Shockley and Walter Brattain at Bell Labs, 1948
A replica of the first working transistor
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The transistor (in its various forms, not only BJT) is the key active component in practically all
modern electronics. Many consider it to be one of the greatest inventions of the 20th century. Its
importance in today's society rests on its ability to be mass produced using a highly automated
process (semiconductor device fabrication) that achieves astonishingly low per-transistor costs.
Although several companies each produce over a billion individually packaged (known as
discrete) transistors every year, the vast majority of transistors now are produced in integrated
circuits, along with diodes, resistors, capacitors and other electronic components, to produce
complete electronic circuits.
 Basic Operation
A NPN BJT is a semiconductor device consisting of a narrow P-type region between two N-type
regions. The three regions are called the emitter (E), base (B), and collector (C), respectively. The
emitter region is heavily doped with the appropriate impurity, while the base region is very lightly
doped. The collector region has a moderate doping level. Note that the structure is not
symmetrical.
Base (B)
Emitter (E) Collector (C)

N+ P- N
Simplified cross section of a planar NPN bipolar junction transistor
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IC
Symbol of a NPN BJT
VBC
IB
VCE
VBE
IE
We consider throughout this chapter a device consisting of N, P, and N regions in order, but we
can also build equivalent devices in P, N, and P order instead. In fact, it is sometimes useful to
have both types of devices available.
Let us see what happens when bias voltages are applied to such device. Let us assume the use
of a silicon BJT.
Consider first that a forward bias is applied to the base-emitter junction and a reverse bias is
applied to the base-collector junction. These are the normal operating conditions of a bipolar
junction transistor. These conditions imply that VBE  0.7 V and VBC < 0.7 V. If we take the emitter
as a reference, these conditions can be re-written as VBE  0.7 volt and VCE = VCB + VBE = VBE -
VBC > 0 V.
Since we already know how a PN junction operates, we would expect to have electrons move
from emitter to base and leave the device through the base at that point. With the collector
junction reverse biased, we would expect no current to flow through that junction.
But something happens inside the base region. The forward bias on the base-emitter junction
does indeed attract electrons from the emitter into the base. As the base is very thin, electrons
entering the base find themselves close to the depletion region formed by the reverse bias of the
base-collector junction.
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While the reverse-bias voltage acts as a barrier to holes in the base, it actively propels electrons
across it. Thus, any electrons entering the junction area are swept across the depletion area into
the collector and give rise to a collector current.
Depletion
region
Flow of electrons
- - - - -
Emitter + Collector
- -
- - +
- -
- - -
- + -
-
Base
- + + -
VBE  0.7 V VBC < 0.7 V
VCE > 0
Careful design ensures that the majority of the electrons entering the base are swept across the
base-collector junction into the collector.
Thus the flow of electrons from emitter to collector is many times greater than the flow from
emitter to the base. In fact, the collector current IC is proportional to the base current IB:
IC  F IB ,
where F is a constant that can take its value in the range from approximately 50 to 300 for typical
bipolar technologies.
This current amplification phenomenon is known as the transistor effect.
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Depletion
region
Flow of electrons
IE = IC + IB = (F + 1) IB
- - - + - -
IE IC
- -
- - +
- -
- - -
- + -
-
IB
- + + -
VBE  0.7 V VBC < 0.7 V
VCE > 0
As previously mentioned, it is also possible to build a transistor with the region types reversed
(PNP structure). In this case, holes will be drawn from the emitter into the base region by the
forward bias, and will then be pulled into the collector region by the higher negative bias.
Otherwise, this device works the same way and has the same general properties as the one
described above. To distinguish between the two types of transistors, we refer to them by the
order in which the different regions appear. Thus, this is a PNP transistor while the device
described above is an NPN transistor.
However, PNP transistors often have lower F values and are slower (i.e., operate at lower
frequencies) than their NPN counterparts.
 Common-Emitter Configuration of a BJT
The BJT is viewed as a semiconductor device with an input and an output. Usually, the input
parameters are the current IB and the voltage VBE, whereas the output parameters are the current
IC and the voltage VCE. This particular arrangement is referred to as common-emitter configuration
because the emitter terminal is common to both input and output.
Note that common-collector and common-base configurations are also sometimes considered.
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IC
Output of the BJT
IB
VCE
Input of the BJT VBE
 The Four Different Modes of Operation of a Transistor
In 1954, Jewell Ebers and John Moll introduced their (static) model of a BJT. The Ebers-Moll
model is depicted below.
Collector
IC
 V  
IF  IS  exp BE   1 IR FIF
  VT  
IB
Base
 V  
IR  IS  exp BC   1 RIR
  VT   IF
IE
Emitter
In this model, F is the forward common-base current gain (typically ranging from 0.98 to 0.998 for
most BJT technologies, i.e. F slightly smaller than the unit), and R is the reverse common-base
current gain (typically, R  0.5).
We can write the general equations for the Ebers-Moll model:
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Base current: IB  IF  IR  F IF  R IR  1  F  IF  1  R  IR
Collector current: IC  F IF  IR
Emitter current: IE  IF  R IR  IB  IC
The physical phenomena behind the Ebers-Moll model are rather simple to understand:
1. Both diodes represent the base-emitter and base-collector PN junctions.
2. The parameter F represents the proportion of electrons coming from the emitter that are able
to reach the collector. The fact that F is very close to the unit implies that the majority of
electrons coming from the emitter do reach the collector, while the remaining electrons leave the
device through the base.
3. The parameter R represents the proportion of electrons coming from the collector that are able
to reach the emitter. The fact that the value of R is (typically) approximately equal to 0.5 means
that roughly half of the electrons coming from the collector end up leaving the transistor through
the emitter.
The difference in values between F and R is due to the inherent non-symmetrical physical
structure of a BJT.
Arrows showing the flows of electrons
- - + -
- I
F FI F IC
IE - - - + - - -
-
RIR - -
- IR -
- - +
- - - -
-
- - - - - + - - - -
(1-F)IF (1-R)IR
IB
A BJT has four modes of operation.
- First mode of operation: The transistor is in the cut-off mode when VBE < 0.7 V and VBC < 0.7 V.
In such case, we have IF  IR  0 , which leads to IB  IC  IE  0 .
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Two depletion regions

- - + -
- -
- IC = 0
IE = 0 - - - - + - -
- - -
- -
- + -
- -- - -
- - - + - - -
-
IB = 0
- Second mode of operation: The transistor is in the forward active mode when VBE  0.7 V and
VBC < 0.7 V (thus implying VCE > 0).
C IC
FIF
IB B
IF
IE
- - + -
- I
F FI F IC
IE - - - + - - -
- -
- - - -
- +
- - - -
-
- - - - - + - - - -
(1-F)IF
IB
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In the forward active mode, we have IR  0 , which yields IB  1  F  IF , IC  F IF , and IE  IF . By
combining those three expressions, we obtain IC  F IF  F IB  F IB .

1  F
The parameter F is known as the forward current gain. If we take 0.98 < F < 0.998, we have 49
< F < 499. Hereafter, we will adopt the value  F = 100.
IC Transfer characteristic
of a BJT
In the forward active
mode, the collector IC =  F IB
current IC is proportional
to the base current IB
IB
 VBE 
We can also notice that the emitter current is given by IE  IF  IS exp   IC  IB  F  1 IB .
 VT 
This result indicates that the base current varies exponentially with the voltage VBE:
V  V 
  IS  exp BE
IE I
IB   S exp BE  .
F  1 F  1  VT   VT 
This equation linking IB and VBE provides us with the input characteristic of a BJT in the forward
active mode. In fact, the equation corresponds to that of a diode as if the current IB was the
current flowing through the base-emitter junction.
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The forward active mode is the mode used for designing amplifiers in analogue electronics.
- Third mode of operation: The transistor is in the reverse active mode when VBE < 0.7 V and VBC
 0.7 V (thus implying VCE = VCB + VBE = VBE - VBC < 0).
C
IC
IR
IB
B
RIR
IE
E
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- - + -
-
- IC
IE - - - + - -
-
RIR - - -
- IR -
- - + -
- - -
- - - - + - - - -
-
(1-R)IR
IB
In the reverse active mode, we have IF  0 , which yields IB  1  R  IR , IC  IR , and

IB
IE  R IR  IB  IC . By combining these three expressions, we obtain IC  IR   and
1  R
R
IE  R IR   IB  R IB .
1  R
The parameter R is known as the reverse current gain. If we take R  0.5, we have R  1.
Since  R << F, it is clear that the transistor effect obtained in the reverse active mode is much
weaker that that achieved in the forward active mode. This is why the reverse active mode is of no
particular interest in practice.
In EEE1002/EEE1010, we will never have to consider the reverse mode of operation in any of our
circuits because the collector will always be on the side of the highest voltage whereas the emitter
will be on the side of the lowest voltage, thus implying that we will always have VCE  0 volt (which
contradicts the condition required for the reverse mode of operation).
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Highest voltage
IC
VCE  0 volt => No reverse mode
IE
Lowest voltage
- Fourth mode of operation: The transistor is in the saturation mode of operation when VBE  0.7 V
and VBC  0.7 V (thus implying VCE  0).
In the saturation mode, the expressions for the base, collector, and emitter currents are
complicated and, in fact, not very interesting. The most important thing to remember is that VCE 
0 volt in this mode of operation.
C
IC
IR FIF
IB
B
IF RIR
IE
E
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- - + -
- I
F FI F IC
IE - - - + - - -
-
RIR - - -
- IR -
- +
- - - -
-
- - - - - + - - - -
(1-F)IF (1-R)IR
IB
We now know enough to be able to understand the way the collector current IC varies with the
voltage VCE when the BJT is either in the saturation mode or in the forward active mode, i.e. when
VBE  0.7 volt.
When VCE is close to zero, the BJT is in the saturation mode. In this case, we could show that a
small increase in VCE above 0 volt results in a very large increase in the collector current. This
was not demonstrated earlier as it is of little interest to us.
In practice, the saturation mode corresponds to any value of the voltage VCE ranging from 0 to
roughly 0.2 volts.
This value of 0.2 volt can be explained as follows: Strictly speaking, the condition for the
saturation mode is that a current does flow through the base-collector junction (i.e., IR  0). In a
practical PN junction, a forward bias ranging from approximately 0.5 to 0.7 volt is often sufficient
for the existence of a non-negligible current (see figure below).
In other words, the condition VBC > 0.5 V can be considered sufficient for the BJT to be in the
saturation mode. It is thus reasonable to say that, for VCE = VBE - VBC < 0.2 V, the BJT is actually
in the saturation mode.
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Strictly speaking, the

current is not equal to zero
Once VCE is increased beyond VCE  0.2 volt, i.e. VBC < 0.5 volt, the current IR is completely
negligible, and the BJT is clearly in the forward active mode.
It may not always be easy to determine the exact value of the voltage VCE in the saturation mode
when performing the manual analysis of a circuit. However, we can make our life easier by simply
assuming that, in the saturation mode, the voltage VCE is a constant slightly greater than zero and
called VCE,sat.
Throughout these lecture notes, we will use the value VCE,sat  0.2 volt whenever the BJT is in the
saturation mode of operation. This simplification does not result in any significant error as the
actual value of VCE always lies somewhere between 0 volt and VCE,sat  0.2 volt.
We finally obtain the output characteristic of a BJT which shows the variation of the collector
current IC (output current) as a function of the voltage VCE (output voltage).
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Output characteristic of a BJT

IC
IB = 30 A
Saturation IB = 25 A
Forward active
IB = 20 A
IB = 15 A
IB = 10 A
VCE
VCE,sat
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Tutorial 2 – Bipolar Junction Transistors
Throughout this Tutorial, we use silicon BJTs with F = 100 and VCE,sat  0.2 volt.
Collector
IC
IB
Base VCE
VBE IE = IC + IB
Emitter
Three modes of operation
Cut-off Forward active Saturated

If VBE < 0.7 volt If VBE  0.7 volt and VCE > VCE,sat If VBE  0.7 volt and VCE = VCE,sat
 IC = IB = IE = 0  IB > 0, IC > 0, IE > 0  IB > 0, IC > 0, IE > 0
 IE  IC  IE ≠ IC
 IC = FIB  IC ≠ FIB
Question 1: The BJT as a Logic Inverter
Consider the circuit depicted below. VCC
IC
RC
IB RB
Vout
Vin
GND
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Find the DC transfer characteristic for this circuit. In other words, for each value of the input
voltage Vin ranging from 0 to VCC, determine the corresponding output voltage Vout.
Question 2: Design of a Linear Common-Emitter Amplifier
Modify the circuit studied in Question 1 in order to design a linear common-emitter amplifier with a
voltage gain Av = -5, using a power supply VCC = 10 V.
The amplifier will be biased for maximum symmetrical voltage swing at both its input and output,
and will therefore be suitable for applications where the input voltage Vin(t) to be amplified has
symmetrical positive and negative excursions.
In other words, the DC operating point will be positioned midway between VCE,sat and VCC. This is
ideal since it allows the output voltage Vout(t) = AvVin(t) to swing by nearly VCC/2 = 5 volts in either
direction without any distortion.
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4. Linear Amplifiers
An analogue circuit that acts as an amplifier reproduces changes in its input signal as
proportionately larger changes in its output signal. The term signal is used to denote the
information-carrying fluctuations of a given voltage or current.
The amplification function performed by the circuit can be either linear or non-linear. If the
amplification is linear, the output signal will be an amplified replica of the input signal (thus
implying that no distortion will be introduced during the amplification process). If the amplification
is non-linear, the output signal will be correlated to the input signal, but not an exact replica of it.
In EEE1002/EEE1010, we are only concerned with linear amplifiers for which the output signal is
proportional to the input signal. Linear amplifiers are used to amplify an analogue input signal
which can be either a voltage (voltage amplifier) or a current (current amplifier) or a power (power
amplifier). Usually, both voltage and current amplifiers also increase the power of the signal and
can thus be considered as power amplifiers.
Amplifiers are active circuits (unlike resistors, capacitors and diodes) since the output signal
magnitude is greater than the input signal magnitude. Such a result can be obtained only when
using active components such as transistors. The amplifier requires some form of power supply to
enable it to boost the input signal.
Power supply
(supply voltage)
Iin(t) Iout(t)
Signal source Load

(e.g., microphone) Vin(t) Amplifier Vout(t) (e.g., loudspeaker)
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The amplification produced by the circuit is described by its gains:

Vout t 
(1) Voltage gain: A v  ,
Vin t 
Iout t 
(2) Current gain: A i  ,
Iin t 
Pout t  Vout t  Iout t 

(3) Power gain: A p    A v Ai .
Pin t  Vin t  Iin t 
 Equivalent Model of an Amplifier
In order for the amplifier to perform some useful function, something (the source) must be
connected to the input to provide an input signal and something (the load) must be connected to
the output to make use of the output signal.
An ideal amplifier would always give an output signal that is determined only by the input signal
and gain, irrespective of what is connected to the output. Also, an ideal amplifier would not affect
the signal produced by the source. In fact, real amplifiers do not fulfil these requirements. This is
why it is necessary to introduce the concepts of input and output resistances of an amplifier. We
will see that the values of these resistances can strongly affect the overall gain when several
circuits/amplifiers are connected to each other.
To model the characteristics of the amplifier input, we need to describe the way in which it
appears to circuits that are connected to it. In other words, we need to model how it appears when
it represents the load of another circuit. In most cases, the input circuitry of an amplifier can be
modelled adequately by a single fixed resistance Rin which is termed input resistance.
To model the characteristics of the amplifier output, we need to describe the way in which it
appears to circuits that are connected to it. In other words, we need to model how it appears when
it represents a source to another circuit. In order to do so, we can use both Thévenin and Norton’s
theorems: Any circuit, no matter how complicated it is, can be seen as a voltage/current source in
series/parallel with a resistance Rout which is termed output resistance.
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 Voltage Amplifiers
Any voltage amplifier, no matter how complicated it is, can be replaced inside a larger circuit by
the following black box defined by its three parameters Av, Rin, and Rout.
Av is the voltage gain measured between the two output terminals when the load of the amplifier is
an open circuit (Iout(t) = 0). This is, in other words, the voltage gain of the amplifier in isolation. Av
is often referred to as unloaded voltage gain because it is the ratio of the output voltage to the
input voltage in the absence of any loading effects.
Input current Iin(t) Output current Iout(t)
Rout
+
Input voltage AvVin(t) Output voltage
Vin(t) Rin Vout(t)
-
Vin t 
The input resistance Rin can be computed as Rin  .
Iin t 
V
The output resistance Rout can be computed as Rout  test .
Itest Vin t   0
Itest
Rout
+ +
AvVin(t) = 0 Vtest
Vin(t) = 0 Rin
- -
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As an illustration, consider the circuit depicted below. The input of the amplifier is connected to a
voltage source Vs(t) with an output resistance Rs. The load resistance RL, that represents the input
resistance of the loading circuit, is connected to the output of the amplifier.
Rs Rout
+ +
Vs(t) Rin AvVin(t) Vout(t) RL
Vin(t)
- -
We can show that the voltage gain of the whole circuit is given by
~ V (t) Rin RL
A V  out  A V .
Vs ( t ) Rin  Rs RL  Rout
~
This expression clearly shows that, to maximise the overall gain A V , one must ensure that Rin is
~
as large as possible and Rout is as small as possible. In order to obtain A V  A V (as one might
have expected at first glance), we would need to have Rin = + and Rout = 0. These are the
characteristics of an ideal voltage amplifier.
A “good” voltage amplifier has a large input resistance, a low output resistance, and of course a
large unloaded voltage gain.
This example shows that, when an amplifier is connected to a source and a load, the resulting
output voltage may be considerably less than one might have expected given the source voltage
and the voltage gain of the amplifier in isolation.
The actual input voltage Vin(t) to the amplifier is less than the source voltage Vs(t) due to the
effects of the voltage divider formed by Rs and Rin. Similarly, the output voltage of the circuit is
affected by the load resistance RL due to the effects of the voltage divider formed by RL and Rout.
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The lower the load resistance applied across the output of a circuit, the more heavily it is loaded
as more current is drawn from it.
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5. Design of Linear Amplifiers using BJTs
Linear amplifiers are analogue circuits. Proper operation of any analogue circuit requires that DC
components (voltages or currents) are added to the voltages and currents inside this circuit. The
DC components exist independently of any signal fluctuations and do not constitute signal
information passing through the circuit.
The term signal is thus used to denote only the information-carrying fluctuations of a given voltage
or current. Any fixed DC levels upon which such signals are superimposed are called bias
components. The design and analysis of an analogue circuit generally requires that the total value
of a voltage or current (signal + bias) be considered, even though only the signal component may
be of interest.
Biasing is most often used in circuits that contain non-linear devices like diodes and transistors.
When properly implemented, biasing causes these non-linear elements to behave as linear
elements, thus greatly enhancing their usefulness.
Although the various characteristics of most semi-conductor devices are non-linear, many exhibit
linear behaviour over certain regions of operation. For instance, the transfer characteristic of a
BJT can be described by the linear equation IC = FIB in the forward active of operation.
The technique of biasing is employed by the circuit designer to confine a device’s operating point
to a region where its behaviour is linear (or at least approximately linear) while avoiding the gross
non-linearities in the device’s characteristics.
Throughout this Chapter, we consider the example of a common-emitter amplifier in order to show
how to design and study linear amplifiers using bipolar junction transistors (BJTs).
 Study of a Common-Emitter Amplifier
Consider the common-emitter amplifier below. As its name implies, this circuit can be used to
amplify an input signal vin(t) that is represented by the (small) variation of an input voltage with
time. For the time being, we assume that the mean of vin(t) is zero, i.e. vin(t) is an AC signal.
---------------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------------
VCC = 10 V
Ic(t)
RB = 910 k RC = 4.7 k Cout
Cin F = 100
Ib(t)
Vce(t)
Vout(t)
Input signal Vbe(t)
vin(t)
GND
AC signal => the mean of vin(t)

the signal is zero Small amplitude variations
Note that we use two capacitors Cin and Cout, called coupling capacitors, in this circuit.
Apart from the AC signal vin(t) to be amplified, the common-emitter amplifier has another input: the
supply voltage VCC. It is the DC (constant) voltage source that provides the amplifier with the
power necessary to boost the input voltage. It also allows the BJT to operate in the forward active
mode of operation.
Since there are two inputs, we can use the principle of superposition to determine the expressions
of the various currents and voltages in the circuit.
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
VCC
Ic(t)
RB RC Cout
Cin Ib(t)
Vce(t)
Vout(t)
vin(t) Vbe(t)
GND
vin(t) is “removed” VCC is “removed”
VCC GND
IC0 ic(t)
RB RC Cout RB RC Cout
Cin Cin
IB0 ib(t)
VCE0 vce(t)
Vout,0 vout(t)
VBE0 vin(t) vbe(t)
GND GND
DC Analysis AC Analysis
According to the principle of superposition, any signal X(t) in the circuit is therefore the sum of a
DC component X0 (mean of X(t)) and an AC component x(t), i.e. X(t) = X0 + x(t).
The quantity X0 is determined by the DC analysis of the circuit, whereas the expression of x(t) is
determined by the AC analysis of the circuit. For instance, we can write:
 Ib(t) = IB0 + ib(t) and Ic(t) = IC0 + ic(t) ;
 Vbe(t) = VBE0 + vbe(t) and Vce(t) = VCE0 + vce(t) ;
 Vout(t) = VOUT,0 + vout(t).
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
VCC = 10 V
IC0 + ic(t)
RB = 910 k RC = 4.7 k Cout
Cin
IB0 + ib(t)
VCE0 + vce(t)
VOUT,0 + vout(t)
vin(t) VBE0 + vbe(t)
GND
 DC analysis of our Common-Emitter Amplifier
We are now going to perform the DC analysis of our common-emitter amplifier. The main purpose
of the DC analysis is to determine whether or not the BJT is properly biased.
Bipolar transistors have four different modes of operation. A BJT must be and always remain in
the forward active mode when used to design an amplifier, whatever the value of the input signal
to be amplified. Biasing an amplifier circuit consists of connecting the BJT so that it operates in
the forward active mode.
VCC VCC
IC0 IC0
RB RC Cout RB RC
Cin
IB0 IB0
VCE0 VCE0
Vout,0 Vout,0
VBE0 VBE0
GND
GND
Open circuits
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
The base-emitter junction is on. We have VBE0  0.7 V. Therefore, the base current is given by
V  0.7
IB0  CC  10.2 A.
RB
Assume now that the BJT is in the forward active mode (we actually do not know it for the time
being, we will check later whether we were right or not). We also assume that the forward current
gain of the BJT is given by F = 100.
We can thus write IC0  F IB0  1.02 mA. Then, we can compute the value of the voltage VCE0 as
VCE0  VCC  RC IC0  5.2 V.
Since VCE0 > VCE,sat, we conclude that our assumption was right and the BJT is indeed in the
forward active mode.
Ideally biased midway

IC
between VCE,sat and VCC
IC0  1.02 mA
DC operating
points
IB VCE
IB0  10.2 A VCE,sat VCE0  5.2 V VCC
The bipolar transistor is

VBE0  0.7 V clearly in the forward
active mode of operation
VBE
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VCC = 10 V
IC0  1.02 mA
RB = 910 k RC = 4.7 k
IB0  10.2 A
VCE0  5.2 V
VBE0  0.7 V
GND
 Role Played by the Coupling Capacitors in DC Operation
The presence of both capacitances Cin and Cout protects the biasing circuit from any external
influence. In other words, any change in the external environment of the amplifier circuit does not
have any effect on the DC operating points. This is simply due to the fact that no DC current can
flow through a capacitance.
To clarify this point, let us assume that our common-emitter amplifier circuit is connected to a
source circuit and a load circuit, as shown below. Note that this will always be the case in
practice.
VCC
IC0
Zero DC
RB RC Cout
current
Cin
IB0
VCE0
Load
Source Zero DC circuit
VBE0
circuit current
GND
It clearly appears that, thanks to the presence of both coupling capacitors, the DC currents IB0 and
IC0 as well as the DC voltages VBE0 and VCE0 are independent of the parameters of the source and
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load circuits. This means that the DC operating points of our amplifier are not affected by those
parameters.
If no coupling capacitors were used, the DC currents IB0 and IC0 as well as the DC voltages VBE0
and VCE0 would depend on the parameters of the source and load circuits, which is unacceptable
in most cases.
Unfortunately, there is a price to pay for the use of coupling capacitors. The presence of both
coupling capacitances Cin and Cout puts a lower limit on the frequency of the signals that can be
amplified. This implies, in particular, that DC signals, which are zero-frequency signals, cannot be
amplified.
If there was a DC component in the input signal, it would be filtered out by Cin and ignored by the
amplifier circuit as a result of this.
Vin(t)
VIN is discarded by the amplifier
vin(t)
VIN
 AC analysis of our Common-Emitter Amplifier
Our bipolar transistor is properly biased and can therefore be used to amplify an input voltage
vin(t). We assume that vin(t) is an AC signal with small amplitude variations. As we have just seen,
if the input signal also contained a DC component, the latter would be filtered out by the coupling
capacitance Cin and would therefore be ignored by the amplifier circuit.
Any fluctuations of the AC signal vin(t) will induce corresponding AC variations of the various
voltages and currents inside the circuit around their DC values, as illustrated by the three
examples shown below.
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Ib(t)
DC operating point
(VBE0, IB0)
Vbe(t)
Ic(t)
DC operating point (IB0, IC0)
Ib(t)
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Ic(t)
Vce(t) = VCC – RC Ic(t) => Ic(t) = (VCC - Vce(t))/RC
VCC/RC
DC operating point (VCE0, IC0)
Vce(t)
Make sure not to VCC
enter the Make sure to stay
saturation region below VCC
The magnitude of vin(t) must be sufficiently small so that the variation of Vce(t) around VCE0 allows
the transistor to remain in the forward active mode of operation.
For the AC analysis of our common-emitter amplifier, we need to study the circuit depicted below.
GND
Cout
ic(t) ic(t)
RB RC Cout Cin ib(t)
Cin
ib(t)
RC vout(t)
vce(t) vin(t) RB vbe(t)
vout(t)
vin(t) vbe(t)
GND GND
It is possible to further simplify the circuit by getting rid of the coupling capacitances Cin and Cout.
To do so, we can assume that each coupling capacitance has a sufficiently high value to be
considered as a short circuit (perfect wire) at the frequency of the input signal.
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In other words, we can assume that both AC input and output signals vin(t) and vout(t) are passed
through the capacitances without being affected at all.
 Short circuits
Cout Impedance of a
ic(t)
Cin capacitance C at a
ib(t)
given frequency :
vce(t) Z = 1/jC
RC vout(t) vout(t)
vin(t) vin(t) RB vbe(t) If C is “large
enough”, Z  0
GND
ic(t)
We need to perform the AC ib(t)
analysis of this circuit:
vce(t)
RC vout(t)
vin(t) RB vbe(t)
GND
v out t 
The voltage gain of our common-emitter amplifier is defined as A v  .
v in t 
 Small-Signal Model of a BJT
In order to perform the AC analysis of the amplifier, we need to replace the BJT with an equivalent
model valid for a small-amplitude input signal (“small signal”). Obviously, this model is derived
assuming that the BJT is in the forward active mode of operation.
Replace the BJT with a linear

model valid for “small signals” ic(t)
ib(t)
vce(t)
RC vout(t)
vin(t) RB vbe(t)
GND
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The bipolar transistor is now seen as a “black box” with two inputs and two outputs.
ic ib ic
ib
Bipolar
vce vbe vce
vbe transistor
We can easily show that the (generic) small-signal model of a BJT is given below:
ib ic
vbe h11 Fib vce
The presence of a resistance h11 implies that the relation between vbe and ib is linear, which is not
the case (the base current is in fact an exponential function of the base-emitter voltage). However,
remember that the quantities vbe, vce, ib, and ic represent AC signals, i.e. fluctuations of the
corresponding voltages and currents around the DC operating points. The assumption that these
fluctuations are “small” allows us to approximate the expressions linking those quantities using
linear functions. After all, any mathematical function can be replaced by a straight line over a
sufficiently small interval.
The expression of the resistance h11 is thus obtained as follows:

vbe dVBE
h11   .
ib dIB VBE 0 ,IB0
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V 
The equation of the base-emitter junction characteristic is given by IB  IS  exp BE  (remember
 VT 
the input characteristic of a BJT).
I 
This expression is equivalent to VBE  VT  ln B  .
 IS 
VBE
Slope h11
vbe
ib
IB
IS
Around the DC point, the logarithmic
characteristic is equivalent to that of a
resistance => vbe = h11 ib
dVBE V V
Therefore, we can write h11   T  T.
dIB VBE 0 ,IB0 IB VBE 0 ,IB0 IB0
25 mV
At room temperature, the expression of the parameter h11 is thus given by h11  .
IB0
As for the common-emitter amplifier considered throughout this chapter, we have h11  2.45 k
(at room temperature) since IB0  10.2 A.
 Small-Signal AC Analysis of our Common-Emitter Amplifier
We can now replace the bipolar transistor with its small-signal model in order to determine the
expressions of the voltage gain, input resistance, and output resistance of our common-emitter
amplifier.
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We recall the values of the circuit parameters: RB = 910 k, h11  2.45 k, F = 100, RC = 4.7 k.
ib
+
vin(t) RB h11 Fib RC vout(t)
-
GND
 Voltage Gain
v in t 
We can show that v out t   RC F ib . Therefore, we obtain v out t   RC F .
h11
The small-signal voltage gain of our common-emitter amplifier is thus given by

v out t  R
Av   F C  -192.
v in t  h11
 Input Resistance
v in t  R h
The input resistance is given by rin   B 11  h11 since h11  RB . Its value is thus rin 
iin t  RB  h11
2.45 k.
iin ib
+
vin(t) RB h11 Fib RC vout(t)
-
GND
 Output Resistance
Vtest
The output resistance is given by rout   RC = 4.7 k.
Itest v in t   0
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Itest
ib = 0
+
RB h11 Fib = 0 RC Vtest
-
GND
 What is the actual voltage gain when the amplifier is connected to other circuits?
In practice, the input of our common-emitter amplifier is connected to a voltage source vs(t) with
an output resistance rs, whereas its output is connected to a loading circuit that is represented by
an input resistance rl.
ic(t)
rs ib(t)
vce(t)
+ RC rl vout(t)
vs(t) vin(t) RB vbe(t)
-
GND
Source circuit Load circuit
rs rout
Av  -192
+ +
vs(t) rin Avvin(t) rl vout(t) rin  2.45 k
vin(t)
- - rout = 4.7 k
GND
Source circuit Load circuit
We can show that the small-signal voltage gain of the whole circuit is given by
~ v (t) rin rl
A v  out  AV .
v s (t) rin  rs rl  rout
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~
Note that, if rin << rs and/or rl << rout, we have A v  A V . This result indicates that, in order to
avoid a drastic reduction in voltage gain when the amplifier is connected to other circuits, one
should maximise its input resistance rin and minimise its output resistance rout.
 Device Variability
The typical value of the forward current gain F for a general-purpose bipolar transistor is in the
range 50 to 300. However, this current gain varies considerably with temperature, component
aging, and operating conditions.
There is also a considerable spread of characteristics between devices of the same nominal type
and even within the same batch. This leads to problems in the design of circuits using BJTs and
greatly limits the usefulness of some amplifier circuits, such as the one we have just studied.
For instance, with our common-emitter amplifier, we have seen that the DC operating points and
the small-signal voltage gain both depend on the value of F. The DC analysis of the amplifier was
performed assuming F = 100, but this value may not be the exact value of the actual forward
current gain of the BJT.
With  F = 100, we found that IC0  F IB0  1.02 mA and then VCE0  VCC  RC IC0  5.2 V, which
leads to a DC operating point which is positioned midway between VCE,sat and VCC. This is ideal
since it allows the AC signal vce(t) to swing by nearly VCC/2 = 5 volts in either direction.
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Ic(t)
Maximum voltage swing without clipping
Vce(t)
VCE,sat VCC
If F is actually equal to 150 instead of 100, we can easily see that IC0  F IB0  1.53 mA and then
VCE0  VCC  RC IC0  2.8 V, permitting a maximum negative excursion of approximately 2.5 V
before the device enters saturation.
Ic(t)
Vce(t)
VCE,sat VCC
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The extreme case is reached with  F = 200 instead of 100. Here, the DC output voltage is only
VCE0  VCC  RC IC0  0.41 V which is at the edge of the saturation region, allowing no useful
output swing in the negative direction.
Ic(t)
Vce(t)
VCE,sat VCC
For values of the forward current gain above 200, the BJT is driven hard into saturation and the
circuit can no longer be used as an amplifier.
One apparent solution to this problem would be to measure the forward current gain of the
transistor to be used and design the circuit appropriately. This is however not an attractive
solution in a mass-production environment in which it would be impractical to design each circuit
uniquely to match individual components. It would also cause severe problems when a device
failed and needed to be replaced.
An alternative would be to select devices within a particular close range of parameters. This is
possible but expensive, particularly if a very narrow spread is required.
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The only practical solution to this problem is to design circuits that are not greatly affected by
changes in the forward current gain of the transistors within them. There are techniques to do so,
such as negative feedback for instance.
In Tutorials 3 and 4, we will study some amplifier circuits for which the biasing and/or the small-
signal voltage gain do not depend on the value of F.
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Tutorial 3 – Amplifier Circuits using BJTs (1)
Throughout this Tutorial, we use silicon BJTs with F = 100.
Question 1: Common-Emitter Amplifier with Negative Feedback
Consider the amplifier circuit depicted below.
VCC = 10 V
R1 = 27 k RC = 2.2 k
+
vin(t) vout(t)
- R2 = 10 k RE = 1 k
GND
The main difference with the amplifier circuit described in class is that we have added an emitter
resistor RE. The presence of this resistor makes various parameters of the circuit, such as the DC
operating points and the small-signal voltage gain, more stable, i.e. less dependent on the
transistor characteristics.
To understand the role played by RE, let us consider a simple example. Assume that the collector
current Ic(t) increases for any reason (e.g., because of an increase in F). In this case, the voltage
across RE, which is proportional to Ic(t) since Ic(t)  Ie(t), also increases. This results in a decrease
in the base current Ib(t) that tends to cancel the initial increase in Ic(t) since Ic(t) = F Ib(t).
This process, called negative feedback, does provide stability to the operation of the circuit.
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VCC
(5) Ic(t)  (2) Ic(t)  Negative feedback
(1) F
+ (4) Ib(t) 
vin(t) vout(t)
- RE (3) VE(t) 
GND
Perform the DC and AC analysis of this amplifier.
Compare your results with those you would obtain without negative feedback, i.e. by using the
same circuit with no emitter resistance (RE = 0). Note that, if RE = 0, the amplifier considered here
is a classical common-emitter amplifier similar to the one studied in the lecture notes.
Question 2: Common-Emitter Amplifier with Negative Feedback and Decoupling Capacitor
Consider the circuit depicted below.
VCC = 15 V
R1 = 82 k RC = 5.6 k
+
vin(t) CE vout(t)
R2 = 13 k RE = 1.3 k
-
GND
Decoupling capacitor
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In Question 1, we have seen that the use of negative feedback has several advantages. These
include the stabilisation of circuit parameters (e.g., DC operating points) which become less
affected by changes in the transistor’s characteristics. However, this is achieved at the expense of
a considerable reduction in voltage gain.
This fall in gain is a direct result of the negative feedback incorporated in the circuit. In some
applications, this reduction in gain is unacceptable and a decoupling capacitance is used to
reduce the amount of AC negative feedback while maintaining DC feedback. This increases the
small-signal gain of the circuit but does not affect the DC feedback, which provides stability to the
bias conditions of the circuit.
The decoupling capacitance CE is placed in parallel with the emitter resistance RE, providing a
low-impedance path for AC signals from the emitter to ground, but having no effect on the steady
bias voltages.
Perform the DC and AC analysis of the amplifier shown above. For the AC analysis, assume that
the decoupling capacitance CE is equivalent to a short circuit.
Question 3: Cascaded Amplifier
VCC = 15 V
R1 = RC = R1 = RC = 5.6 k
82 k 5.6 k 82 k
RS = 1 k
+
R2 = RL = vout(t)
vin(t) RE = R2 = RE =
13 k 10 k
- 1.3 k 13 k 1.3 k
GND
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This amplifier is obtained by cascading two common-emitter amplifiers strictly identical to that
studied in Question 2. The load resistance is RL = 10 k, whereas the source resistance is RS = 1
k.
Compute the small-signal voltage gain AV,C of this cascaded amplifier.
What would be the value of AV,C if the load resistance RL was equal to 10  instead of 10 k?
Question 4: Our First Amplifier Revisited
Perform the DC and AC analysis of the common-emitter amplifier circuit designed in Question 2 of
Tutorial 2.
Are the results you obtain coherent with the analysis performed in Question 2 of Tutorial 2?
Question 5: Design of a Common-Emitter Amplifier with Negative Feedback
Design a common-emitter amplifier with negative feedback.
The specifications of this circuit are as follows:

 Power supply VCC = 10 volts;
 Voltage gain AV  -9;
 The maximum output voltage swing must be as large as possible;
 The input resistance rin must not be too small;
 The output resistance rout must not be too large.
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Tutorial 4 – Amplifier Circuits using BJTs (2)
Throughout this Tutorial, we use silicon BJTs with F = 100.
Question 1: Common-Emitter Amplifier with Symmetrical Power Supplies
Consider the common-emitter amplifier circuit depicted below. Unlike the circuits we have studied
so far, this amplifier uses two symmetrical power supplies VCC = 10 volts and VEE = - 10 volts. This
arrangement provides several advantages such as a simplification of the biasing circuitry and a
significant increase in the input resistance.
VCC = 10 V
RC = 6.2 k
vout(t)
vin(t) GND
GND RE = 1.5 k
VEE = -VCC = -10 V
Perform the AC analysis of this amplifier. In particular, show that its input resistance is much
larger than those of the amplifiers previously studied in Tutorial 3.
Question 2: Common-Emitter Amplifier with an Output Stage
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This circuit is designed by cascading a common-emitter amplifier similar to that studied in

Question 1 with an emitter follower (also called common-collector amplifier) acting as an output
stage.
VCC = 10 V
RC = 4.7 k
T1 T2
vin(t)
vout(t)
GND RE,1 = 1.4 k RE,2 = 10 k
GND
VEE = -VCC = -10 V
Common-emitter amplifier Emitter follower

(common-collector amplifier)
The collector of T2 is connected directly to the positive voltage supply. The input signal is applied
between the base and ground, while the output signal is measured between the emitter and
ground, which explains why such arrangement is called a common-collector amplifier.
Perform the AC analysis of this amplifier. In particular, show that its output resistance is much
lower than that of a simple common-emitter amplifier (thanks to the use of a common-collector
amplifier at the output stage).
Question 3: Directly-Coupled (DC) Amplifier
The use of coupling and decoupling capacitors for designing amplifiers, although simple in
principle, does have some disadvantages. First, each capacitor limits the low-frequency response
of the amplifier (i.e., input signals with low frequencies cannot be amplified). Second, the
presence of capacitors make the circuit more expensive and less suitable for the production of
integrated circuits as capacitors require a large amount of area on a chip.
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If care is taken with the design of the circuit, it is possible to avoid using capacitors between the
stages of cascaded amplifiers by ensuring that the DC output voltage of one stage represents the
correct biasing voltage for the next stage. This not only removes the need for coupling capacitors
but also reduces the complexity of the biasing circuitry required.
A major advantage of this technique is that it removes the frequency limitations introduced by
capacitive coupling, allowing the design of amplifiers that can be used at frequencies down to DC.
These amplifiers are often referred to as directly coupled (DC) amplifiers.
Perform the DC and AC analysis of the directly coupled amplifier depicted below.
VCC = 10 V
RC,1 = 6.2 k
RC,2 = 4.7 k
VZ,2 = 7.9 V
RS = 1 k
T1 T2 T3
vin(t)
GND RL =
RE,1 = 1.5 k vout(t)
RE,2 = 1.4 k RE,3 = 10 k
10 k
VZ,1 = 7.3 V
GND
VEE = -VCC = -10 V
Assists in the biasing of T1
Provides DC level shifting. It allows vout(t) to be
biased around 0 volt, midway between VCC and VEE,
for maximal output voltage swing range.
This amplifier is obtained by cascading the common-emitter amplifier considered in Question 1

and the common-emitter amplifier with an output stage studied in Question 2. The load resistance
is RL = 10 k, whereas the source resistance is RS = 1 k.
What would be the value of the small-signal voltage gain if RL was equal to 10  instead of 10
k?
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6. The Field-Effect Transistor (FET)
 A Historical Perspective
The basic principle behind the field-effect transistor (FET) was proposed in a patent by Austrian-
Hungarian physicist Julius E Lilienfeld as early as 1925 and, independently, by German electrical
engineer Oskar Heil in England in 1935. Insufficient knowledge of the materials and gate stability
problems, however, delayed the practical usability of the device for a long time.
In 1947, John Bardeen and Walter Brattain, working at the Bell Labs (USA), succeeded in
creating a point-contact transistor that achieved amplification. They indeed observed that when
two gold point contacts were applied to a crystal of germanium, a signal was produced with the
output power greater than the input. William Shockley, who was then leading the Solid State
Physics Group at Bell Labs, understood the potential of such discovery and, over the next few
months, worked to expand the knowledge of semiconductors. When Bell Labs attempted to patent
their invention called “junction transistor”, they found Lilienfeld already holding a patent which was
worded in a way that would include all types of transistors. In any case, Bell Labs was able to
work out an agreement with Lilienfeld. It was at that time that the Bell Labs version was given the
name bipolar junction transistor, or simply junction transistor, and Lilienfeld's design took the
name field-effect transistor.
It is worth mentioning that, in 1948, the point-contact transistor was independently invented by
German physicists Herbert Mataré and Heinrich Welker while working at the Compagnie des
Freins et Signaux (France).
The next breakthrough was the invention of the integrated circuit in 1958 by the American
physicist Jack Kilby (working at Texas Instruments). He was awarded the Nobel Prize in Physics
for his discovery in 2000. His integrated circuit contained only a transistor and other components
on a slice of germanium. An integrated circuit is basically an electronic circuit manufactured by the
patterned diffusion of trace elements into the surface of a thin substrate of semiconductor
material. Additional materials are deposited and patterned to form interconnections between
semiconductor devices.
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Jack Kilby's original integrated circuit
The first integrated circuits were made using BJTs. For instance, the first commercial digital
integrated circuits were manufactured using the TTL (transistor-transistor logic) family, introduced
in 1962, which offered a relatively high integration density at that time. The TTL logic family was
so successful that it composed the largest fraction of the digital semiconductor market until the
1980s.
3-input ECL (emitter-coupled logic) logic gate, Motorola, 1966
During the 1950s and 1960s, several types of FETs were introduced. Among the most prominent
ones were the junction FET (junction FET, proposed by William Schokley in 1952 and built by G
Dacey and Ian Ross in 1953), the metal-semiconductor FET (MESFET, Carver Mead, 1966), and
the metal-oxide-semiconductor FET (MOSFET, Dawon Kahng and Martin Atalla, 1960). Today,
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the MOSFET is by far the most widely used type of transistor in integrated circuits. One can even
reasonably say that it has been the undisputed king of semiconductors since the early 1990s. This
is why we are going to focus throughout this chapter on the study of this particular transistor.
The first MOSFET was built by Dawon Kahng and Martin Atalla at Bell Labs in 1960.
Operationally and structurally different from the BJT, the MOSFET was a particular type of metal-
insulator-semiconductor FET using crystalline silicon (Si) for the semiconductor and a layer of
silicon dioxide (SiO2) for the insulator. What made the silicon MOSFET structure so special is that
it did not generate localized electron traps at the Si-SiO2 interface, and was thus inherently free
from the trapping and scattering of carriers that had impeded the performance of earlier field-
effect transistors.
MOSFET digital circuits started to take off a bit later than their BJT counterparts. It is in fact during
the early 1970s that digital circuits started being implemented using MOSFET transistors. For
instance, the first commercially available microprocessor (the Intel 4004 introduced in 1971) was
designed using about 2,300 P-channel MOSFETs (10-m manufacturing process). We can also
mention the Motorola 68000 (1979) which was implemented using approximately 68,000 N-
channel MOSFETs (4-m process).
Towards the beginning of the 1980s, complementary MOSFET (CMOS) logic, which employs both
N-channel and P-channel MOSFETs, finally became the technology of choice for designing
complex digital integrated circuits such as microprocessors, due to its very high integration
density. Today, the CMOS logic family represents more than 99% of the digital market. All other
logic families, including TTL, have now become history.
As an illustration of what can be achieved today using MOSFETs, the Oracle SPARC T4
microprocessor introduced in 2011 employs 855 million MOSFETs (40-nm process) on a chip of
403 mm2 and has a clock frequency of 3 GHz. This is the CMOS technology, i.e. the MOSFET
transistor, that has made the design of such extremely complex circuits possible.
The MOSFET's key advantages in digital circuits do not necessarily translate into supremacy in
analogue circuits. The reason is that analogue and digital circuits draw upon different features of
transistor behaviour. Digital circuits switch, spending most of their time outside the amplification
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region. On the other hand, the performance of analogue circuits depend on transistor behaviour in
the amplification region (remember the BJT logic inverter studied in Tutorial 2).
The Intel 4004 microprocessor (1971)
The BJT has traditionally been the analogue designer's transistor of choice for several reasons
such as its high transconductance for a given current, high intrinsic gain, and high speed.
However, at the present time, analogue integrated circuits are designed and fabricated in bipolar
technology, in MOSFET technology, and in technologies that combine both types of devices in
one manufacturing process (BiCMOS).
The necessity of combining complex digital functions with analogue functions on the same
integrated circuit has resulted in an increased use of digital MOS technologies for analogue
functions, particularly those functions such as digital-analogue conversion required for interfaces
between analogue signals and digital systems. However, despite the strong economic incentive to
use MOSFETs for both digital and analogue circuitry, bipolar technology will continue to be used
in a wide range of applications requiring high-current drive capability and the highest levels of
analogue performance.
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Cross-sections of MOS integrated circuits
 The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)
A traditional metal–oxide–semiconductor (MOS) structure is obtained by growing a layer of silicon

dioxide (SiO2) above a silicon substrate and depositing a layer of metal or polycrystalline silicon
(poly) on top of it. As silicon dioxide is a dielectric material (insulator), the MOS structure is thus
equivalent to a capacitor, with one of the electrodes replaced by a semiconductor.
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Gate (G)
Source (S) Drain (D)
tox
+ +
N L N
P-type substrate
Body (B)
In the 3D view and the cross-section of an N-channel MOSFET (hereafter referred to as NMOS
transistor) shown above, the parameters L and W denote the length and the width of the
transistor, respectively. The thickness of the layer of SiO2 is denoted as tox.
In this chapter, we are going to focus on the structure of an NMOS transistor, knowing that all
explanations are also valid for a P-channel MOSFET (PMOS transistor).
To construct an NMOS transistor, we start from a lightly-doped P-type silicon substrate, called the
body. In this P-type substrate, we implant two heavily-doped N-type regions, called the drain and
the source. A thin layer of silicon dioxide (SiO2), called the gate oxide, is used to cover the region
that separates the drain and the source.
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The gate oxide is itself covered by some metal or, traditionally, some conductive polycrystalline
silicon (polysilicon, for short). The conductive material above the thin layer of SiO2 forms the gate
of the transistor.
It is worth mentioning that, unlike the BJT, a MOSFET has a symmetrical physical structure in the
sense that the drain and source terminals are identical. In an NMOS transistor, the drain is
defined by convention as the terminal connected to the highest voltage, whereas the source is the
terminal connected to the lowest voltage. In other words, the current always flows from drain to
source in an NMOS transistor.
The MOSFET is a four-terminal device (gate, drain, source, and body). The symbol for the NMOS
transistor is shown below.
Drain (D)
Symbol of an NMOS
Gate (G) Body (B)
Source (S)
The (DC) current IG flowing through the gate is equal to zero due to the presence of the insulating
layer of SiO2. This is a very important (and attractive) feature of MOSFETs since it essentially
means that the input resistance of a MOSFET is infinite. Thus, using MOSFETs will allow us to
design electronic circuits with a very high input resistance. This is actually one of the key
advantages of MOSFETs over BJTs. Note that the infinite input resistance is a feature shared by
all types of FET (MOSFET, JFET, MESFET…).
The voltage applied to the gate terminal determines if and how much current flows between the
drain and the source. The body represents the fourth terminal of the transistor. Its function is
actually secondary because it only serves to modulate the device characteristics and parameters.
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Throughout these lecture notes, we will simply assume that the body terminal is connected to the
source, and therefore does not need to be shown. Note that, in practice, this is often (but not
always) the case.
Drain (D) Drain (D)
IG = 0 IG = 0
Gate (G) Body (B) Gate (G)
Source (S) Source (S)
At the most superficial level, the transistor can be thought of as a switch. When the voltage
applied to the gate is larger than a given value (the threshold voltage VTN, not to be confused with
the thermal voltage VT), a conducting channel is formed between drain and source. In the
presence of a voltage difference between the latter two (VDS > 0), an electrical current ID can then
flow between them.
The conductivity of the channel depends on the gate voltage: the larger the voltage between gate
and source (VGS), the smaller the resistance of the conducting channel and the larger the current
ID. When the gate voltage is lower than the threshold voltage (VGS < VTN), no such conducting
channel exists, and the switch is considered open.
Drain
ID
Gate VDS
VGS ID
Source
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 Common-Source Configuration of an NMOS Transistor
In most applications, the NMOS is viewed as a semiconductor device with an input and an output.
Usually, the input parameter is the voltage VGS, whereas the output parameters are the drain
current ID and the voltage VDS. This particular arrangement is referred to as common-source
configuration because the source terminal is common to both input and output.
Drain
ID
Output of the NMOS
Gate VDS
VGS ID
Input of the NMOS

Source
This is obviously very similar to the way we view a BJT in most electronic circuits. We therefore
have the following analogies between BJT and MOSFET: source  emitter, drain  collector, gate
 base, and collector current  drain current.
The main difference between both semiconductor devices is that the operation of the NMOS
transistor is actually simpler than that of the bipolar transistor because, with an NMOS, we must
only consider one input quantity (VGS) since the input (gate) current IG is always equal to zero.
With a BJT, there are two input quantities (IB and VBE) that need to be taken into account.
 Current-Voltage Characteristics of an N-Channel MOSFET (NMOS transistor)
Consider first the case in which gate, drain, source, and body are connected to ground. The drain
and source are connected by back-to-back PN junctions (substrate-source and substrate-drain).
Under the mentioned conditions, both junctions have a bias of 0 volt and are therefore reverse-
biased, which results in an extremely high resistance between drain and source.
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G
S VGS = 0 D
GND
GND GND
ID = 0
+ +
N N
P-type substrate
B
GND Depletion regions (no current can
flow between drain and source)
Assume now that a small positive voltage is applied to the gate (with respect to the source). We
recall that the gate and substrate form the plates of a capacitor with the gate oxide as the
dielectric (insulator). The positive gate voltage creates an electric field across the MOS
capacitance which manifests itself initially by repelling holes (the majority carriers in the P-type
silicon substrate). Hence, a depletion region is formed below the gate. This depletion region is
similar to the one occurring in a PN junction.
0 < VGS < VTN G

S D
GND GND
ID = 0
+ ++++++++++ +
N N
P-type substrate
B A depletion region is formed

GND below the gate oxide
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As the gate voltage increases, the potential at the silicon surface reaches a critical value at some
point, and the semiconductor surface inverts to N-type material. This point marks the onset of a
phenomenon known as strong inversion.
Further increases in the gate voltage results in additional electrons (the minority carriers in the P-
type silicon substrate) in the thin inversion layer directly under the gate oxide. Hence, an N-type
channel is formed between the source and drain regions, the conductivity of which is dependent
on the gate-source voltage VGS.
G
VGS > VTN D
S
GND GND
ID = 0
+
-------------- +
N - N
P-type substrate
B N-type region => A conducting channel

GND is created just under the gate oxide.
The value of VGS where strong inversion occurs (and a conducting channel is created) is called
the threshold voltage VTN. Typically, VTN is equal to few tenths of a volt. For instance, for a digital
circuit with a supply voltage VDD = 5 V, we would have VTN  0.8 V, whereas for VDD = 2.5 V, we
would rather have VTN  0.4 V. Note that the value of the threshold voltage can be adjusted during
the manufacturing process depending on the requirements of the circuit designer.
This parameter VTN is a function of several components, most of which are material constants,
such as the difference in work function between gate and substrate materials, the oxide thickness,
the Fermi voltage, the charge of impurities trapped at the surface between channel and gate
oxide, and the dosage of ions implanted for threshold adjustment. It can also be shown that VTN is
dependent on the voltage VSB between the source and body terminals.
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We can now define the first mode of operation of an NMOS: The transistor is in the cut-off mode
when VGS < VTN. In such case, there is no conducting channel and no current can flow from drain
to source, which leads to ID  0 .
Assume now that VGS > VTN and that a small voltage VDS is applied between drain and source.
The voltage difference causes a current ID to flow from drain to source.
At a point x along the channel, the voltage with respect to the source is denoted as V(x). The
gate-to-channel voltage VGx, i.e. the voltage across the MOS capacitance, at that point x is
therefore given by VGx = VGS + VSx = VGS – VxS = VGS - V(x).
S D
VDS > 0 (small)
GND
VGS > VTN G
ID ID
+ +
N N
V(x)
P-type substrate
B Larger depletion
x=0 x=L region at drain end
GND
x x + dx
The charge dQ(x) in the channel between points x and (x + dx) is given by
dQx   Cox W dx VGS  Vx   VTN  ,
where Cox designates the capacitance per unit area presented by the gate oxide, and is
ox
expressed as Cox  , where ox denotes the permittivity of the gate oxide ( ox = 3.5  10-11
t ox
F/m).
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dQx  dQx  dx dQx 

The current flowing from drain to source is given by ID    v n x  , where vn(x)
dt dx dt dx
designates the drift velocity of the electrons (which are the carriers in the channel) at point x.
Hence, we can write:
ID  Cox W VGS  Vx   VTN  vn x  .
The drift velocity of the electrons vn(x) at point x is proportional to the horizontal electric field E(x)
(created by the applied voltage VDS) in the channel at the same point x provided that the electric
field is small (E(x) << Esat).
We can thus write ID  n Ex  Cox W VGS  Vx   VTN  , where the constant n designates the
mobility of the electrons in the channel. The mobility depends on both the temperature and the
doping level but is almost constant for a wide range of normally used doping levels. Also, n is
sometimes called the surface mobility for electrons because the channel forms at the surface of
the silicon. Typical values range from about 500 cm2/V.s to about 700 cm2/V.s, which are much
less than the mobility of electrons in the bulk of the silicon (about 1400 cm 2/V.s) because surface
defects not present in the bulk impede the flow of electrons in MOS transistors.
vn (m/s)
vsat  105
We assume that
Slope n the transistor
operates in this
region
E (V/m)
Esat
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The electric field E(x) at point x is related to the voltage V(x) at the same point through the well-
known expression
dV x 
Ex   .
dx
As a result, we obtain the following expression: ID dx  n dVx  Cox W VGS  Vx   VTN  .
By integrating this equation over the length L of the channel, an expression of the current I D can
be obtained:
L VDS
 ID dx   n Cox W  VGS  Vx   VTN dV x 

0 0
V
W V x 2 
DS
 ID  n Cox VGS  VTN  V( x )  
L  2 
0
 ID  n Cox W  VGS  VTN  VDS  VDS .

L  2 
The mode of operation where this equation holds is called the linear mode of operation because
the NMOS transistor is somewhat equivalent to a voltage-controlled resistance in this mode.
In fact, for VDS << 2 (VGS – VTN), we even observe a perfectly linear dependence between VDS and
ID, and we can write
ID   n Cox
W
VGS  VTN  VDS .
L
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This indicates that, for small values of VDS, the transistor is equivalent to a resistance RNMOS given
by
1

V
RNMOS  DS  n Cox
W
VGS  VTN  .
ID  L 
W
To simplify the equations, we can introduce the parameter k n  n Cox called gain factor of the
L
transistor. A typical value of kn for W/L = 10, tox = 10 nm, n = 570 cm2/V.s, and ox = 3.5  10-11
11
F/m is k n  570  10  4  3.5  10  10  2 mA/V .
2
9
10  10
Note that the designer can change the value of the gain factor k n by simply changing the ratio
W/L, which is very convenient in practice.
As the value of VDS is further increased, the conducting channel narrows at the drain end (dQ(L)
 0). When VDS reaches the value VGS – VTN, the gate-to-channel voltage VGD = VGS – VDS at the
drain end becomes equal to the threshold voltage VTN, thus meaning that the channel is no longer
connected to the drain. In other words, the channel disappears. This phenomenon is called pinch-
off.
S D
VDS = VGS - VTN
GND
VGS > VTN G
ID ID
N+ N+
P-type substrate
B The charge is zero and the

channel is said to be pinched off
GND region at drain end
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
As VDS increases beyond VGS – VTN, the pinch-off point moves closer to the source. The voltage
difference over the conducting channel from the pinch-off point to the source remains fixed at VGS
– VTN. As a result, the drain current does no longer depend on VDS, but only on the voltage across
the channel which is equal to VGS – VTN. In other words, the drain current ID no longer increases
with VDS.
S D
VDS > VGS - VTN
GND
VGS > VTN G
ID ID
N+ N+
VGS - VTN
P-type substrate x = 0 x
B The channel disappears at point x

=> V(x) = VGS - VTN
GND
When VDS > VGS – VTN, the NMOS transistor is said to be in the saturation mode of operation. The
expression of the constant drain current is obtained by replacing VDS by VGS – VTN in the current
expression derived earlier:
 V 
ID  k n  VGS  VTN  DS  VDS , for VDS = VGS – VTN
 2 
 ID  k n  VGS  VTN  VGS  VTN  VGS  VTN 

 2 
 ID  n VGS  VTN 2 .
k
2
We can notice the square dependency of the constant drain current with respect to VGS.
As a summary, an NMOS transistor has three modes of operations:
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
- First mode of operation: The transistor is in the cut-off mode when VGS < VTN. In this case, the
drain current ID is equal to zero and the transistor is equivalent to an open switch since the drain
is not connected to the source.
- Second mode of operation: The transistor is in the linear mode when VGS  VTN and VDS < VGS -
VTN. In this case, the drain current ID is given by
 V 
ID  k n  VGS  VTN  DS  VDS .
 2 
In this mode, the transistor resembles a voltage-controlled resistance given by

dVDS 1
RNMOS   .
dID k n VGS  VTN  VDS 
- Third mode of operation: The transistor is in the saturation mode when VGS  VTN and VDS  VGS -
VTN. In this case, the drain current ID is given by
ID 
kn
VGS  VTN 2 .
2
In this mode, the transistor is equivalent to a voltage-controlled current source. The saturation
mode is traditionally used for designing MOS linear amplifiers in analogue electronics.
Output characteristic of an NMOS transistor
ID VDS = VGS – VTN

VGS = 6 V
Linear Saturation
VGS = 5 V
Quadratic
dependence
VGS = 4 V
VGS = 3 V
VGS = 2 V
VGS = 1 V
VDS
VGS  VTN
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
The output characteristic of an NMOS transistor somewhat looks like that of an NPN bipolar
junction transistor. The saturation mode for a BJT corresponds to the linear mode of an NMOS,
whereas the forward active mode for an NPN BJT (VCE > VCE,sat) is analogous to the saturation
mode for an NMOS (VDS  VGS - VTN).
Remember that we found the following analogies between BJT and MOSFET: source  emitter,
drain  collector, gate  base, and collector current  drain current. Therefore, there are also
analogies between the input voltages VBE and VGS, the output voltages VCE and VDS, and the
output currents IC and ID.
As for the transfer characteristic linking the output current (I C, ID) and the input voltage (VBE, VGS),
we notice that the drain current ID varies like the square of the voltage (VGS – VTN) in an NMOS
transistor, while the collector current IC varies exponentially with the voltage VBE in a BJT.
This indicates that a given variation of the input voltage (VBE, VGS) will result in a larger variation of
the output current (IC, ID) with a BJT than with a MOSFET. It thus seems that the BJT is inherently
more suitable than the MOSFET for the design of high-gain voltage amplifiers.
However, the MOSFET, like any other types of FET, has an infinite input resistance (recall that
the gate current is always equal to zero), which is not the case with the BJT. Therefore, if we want
to design a circuit with a very large input resistance, it will be preferable to employ a FET rather
than a BJT.
Transfer characteristic of an NMOS transistor

ID
The transistor is in
the saturation mode
Quadratic
VGS
VTN
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
 The NMOS Transistor as a Switch
Consider the circuit below. We propose to show that the NMOS transistor is equivalent to an
imperfect switch. We will assume that the voltage applied on the gate can be equal to either 0 V
(GND) or VDD (which is the supply voltage, i.e. the highest possible voltage in the circuit).
Gate (G)
Drain (D) Source (S)
ID = 0
VIN VOUT
GND GND
(1) The gate is connected to ground.
In this case, we can write VGS = 0 – VOUT = – VOUT and VDS = VIN – VOUT.
Since all voltage values in the circuit range from 0 to VDD, – VOUT is negative and thus smaller than
the threshold voltage VTN (which is always positive for an NMOS transistor, VTN is typically equal
to few tenths of a volt). This means that VGS < VTN. The NMOS transistor is in the cut-off mode of
operation and thus equivalent to an open switch since the drain is not connected to the source.
Gate connected to GND
Open switch
VIN VOUT
GND GND
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
(2) The gate is connected to the supply voltage VDD.
In this case, we can write VGS = VDD – VOUT and VDS = VIN – VOUT.
The transistor is in the cut-off mode when VGS < VTN, i.e. VOUT > VDD – VTN. In this case, the
transistor is equivalent to an open switch since the drain is not connected to the source.
The transistor is in the linear mode when VGS  VTN, i.e. VOUT  VDD – VTN, and VIN – VOUT < VDD –
VOUT – VTN, i.e. VIN < VDD – VTN. In this case, the drain current ID is given by
 V  VOUT 
ID  k n  VDD  VOUT  VTN  IN  VIN  VOUT   0
 2 
 
 VDD  VTN  IN  OUT  VIN  VOUT   0 .
V V

 2 2 
There are two possible solutions to this equation:

V V
(a) VDD  VTN  IN  OUT  0 => VOUT  2 VDD  VTN   VIN .
2 2
(b) VIN  VOUT  0 => VOUT  VIN .
The solution (a) must be discarded as it is incompatible with the conditions necessary for the
transistor to be in the linear mode. On the other hand, the solution (b) is compatible with those
conditions.
Our conclusion is that, when VOUT  VDD – VTN and VIN < VDD – VTN, we have VOUT  VIN and the
transistor is thus equivalent to a closed switch.
 Gate connected to VDD

 VIN & VOUT smaller than (VDD – VTN)
Closed switch
VIN VOUT = VIN
GND GND
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
Note that this closed switch exhibits a resistance R given by

dVDS 1
R  .
dID VDS  VIN  VOUT , VGS  VDD  VOUT k n VDD  VTN  VIN 
There is no voltage drop across this resistance because the current flowing through the switch is
equal to zero. Therefore, the presence of a non-zero resistance R is not an issue (as long as R
does not become infinite).
The transistor is in the saturation mode when VGS  VTN, i.e. VOUT  VDD – VTN, and VIN – VOUT 
VDD – VOUT – VTN, i.e. VIN  VDD – VTN. In this case, the drain current ID is given by
ID 
kn
VDD  VOUT  VTN 2  0 => VOUT  VDD  VTN .
2
We thus conclude that, when VOUT  VDD – VTN and VIN  VDD – VTN, we have VOUT  VDD  VTN
and the switch output is then constant.
As a summary, an NMOS transistor can be thought of as a switch controlled by its gate voltage.
The switch is closed when the voltage applied on the gate is high (e.g., equal to VDD), and is open
when this gate voltage is low (e.g., equal to 0 V). However, this switch is imperfect because, when
closed, it cannot pass voltage values that are above VDD – VTN.
VOUT
Gate connected to VDD The switch cannot
pass high voltage
values
VDD - VTN
The switch can pass

low voltage values
VIN
VDD - VTN VDD
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
This two-state operation (open switch/closed switch) makes MOS transistors particularly
amenable to digital electronics since it matches the concepts of binary digital logic.
 Current-Voltage Equations for a P-Channel MOSFET (PMOS transistor)
Throughout this chapter, we have extensively studied the N-channel MOSFET. In many circuits, it
is also necessary to employ P-channel MOSFETs, hereafter referred to as PMOS transistors. For
instance, since the 1980s, the dominant technology in the world of digital electronics has been the
CMOS (complementary) logic family that makes use of both NMOS and PMOS transistors on the
same silicon chip.
The cross-section and the symbol of a PMOS transistor are depicted below.
Gate (G)
Source (S) Drain (D)
tox
+ +
P L P
N-type substrate
Body (B)
Drain (D) Drain (D)
ID ID
IG = 0 IG = 0
Body (B)
Gate (G) Gate (G)
Source (S) Source (S)
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
The behaviour of the PMOS is very similar to that of an NMOS transistor, except that the polarities
of the various voltages and currents are reversed. In other words, for a PMOS, the voltages V TP
(threshold voltage), VGS, and VDS are negative, whereas the drain current ID flows from source to
drain, thus implying that the source is always connected to the highest voltage while the drain is
connected to the lowest voltage (VDS < 0).
A PMOS transistor has three modes of operation:
- First mode of operation: The transistor is in the cut-off mode when VGS > VTP (VGS < 0, VTP < 0).
In this case, there is no conducting channel between drain and source, and the drain current I D is
thus equal to zero. The transistor is equivalent to an open switch since the drain is not connected
to the source.
- Second mode of operation: The transistor is in the linear mode when VGS  VTP and VDS > VGS -
VTP (VGS < 0, VTP < 0, VDS < 0). In this case, the drain current ID is given by
 V 
ID  k p  VGS  VTP  DS  VDS ,
 2 
W
where k p  p Cox is called the gain factor of the transistor. A typical value of kp for W/L = 10,
L
11
tox = 10 nm, p = 260 cm2/V.s, and ox = 3.5  10-11 F/m is k p  260  10  4  3.5  10  10  0.9
9
10  10
mA/V . The parameter p designates the mobility of holes in the channel (since the current
2
carriers are holes in a PMOS transistor). Note that the mobility of holes is lower than that of
electrons. Due to the lower mobility of holes, the gain factor of a PMOS transistor is therefore
smaller than that of its equivalent NMOS transistor (with identical physical dimensions). In fact,
this explains why PMOS transistors do actually operate slower than NMOS transistors.
In this mode, the transistor resembles a voltage-controlled resistance given by

dVSD dV 1
RPMOS    DS   .
dID dID k p VGS  VTP  VDS 
- Third mode of operation: The transistor is in the saturation mode when VGS  VTP and VDS  VGS -
---------------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------------
kp
ID  VGS  VTP 2 .
2
In this mode, the transistor is equivalent to a voltage-controlled current source.
We will have a closer look at PMOS transistors in Tutorial 5.
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
Tutorial 5 – MOSFET Transistors

Question 1
Consider the circuit depicted below, which shows a PMOS transistor used as a switch. All voltage
values in the circuit vary from 0 (GND) to VDD (supply voltage).
Gate (G)
Drain (D) Source (S)
ID = 0
VIN VOUT
GND GND
We recall the three modes of operation for a PMOS transistor:
- First mode of operation: The transistor is in the cut-off mode when VGS > VTP (VGS < 0, VTP < 0).
In this case, there is no conducting channel between drain and source, and the drain current ID is
thus equal to zero. The transistor is equivalent to an open switch since the drain is not connected
to the source.
- Second mode of operation: The transistor is in the linear mode when VGS  VTP and VDS > VGS -
 V 
ID  k p  VGS  VTP  DS  VDS ,
 2 
where k p  p Cox W is called the gain factor of the transistor. In this mode, the transistor
L
resembles a voltage-controlled resistance given by
dVDS 1
RPMOS    .
dID k p VGS  VTP  VDS 
---------------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------------
- Third mode of operation: The transistor is in the saturation mode when VGS  VTP and VDS  VGS -
kp
ID  VGS  VTP 2 .
2
In this mode, the transistor is equivalent to a voltage-controlled current source.
Show that, when the gate is connected to VDD, the PMOS transistor is equivalent to an open
switch.
Show that, when the gate is connected to GND, the PMOS transistor is equivalent to an imperfect
closed switch.
Question 2
Design, using two MOS transistors, a switch that can be considered as perfect. When closed, this
switch should be able to pass all voltage values ranging from 0 to VDD, where VDD designates the
voltage supply.
Assume that the current flowing through the switch is equal to zero, which implies that the switch
output is connected to the gate(s) of other MOSFETs.
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
Question 3
Consider the five CMOS (complementary MOS) circuits depicted below.
VDD VDD
VDD
V2 V1
VOUT
VIN VOUT
V2
VOUT
V1
GND
(a) GND GND
(b) (c)
VDD
V1
V3 VOUT
V2
GND
(d)
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
VDD VDD
V1 V2 VOUT
GND GND
(e)
For each circuit, determine the output voltage Vout, assuming that the input voltages (denoted as
VIN, V1, V2 and V3) can be either low (equal to 0 volt) or high (equal to the supply voltage VDD). The
output of each circuit is connected to the gates of MOSFETs.
Determine the function performed by each circuit.
In each case, what is the value of the current drawn from the power supply? Comment on your
result.
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
7. Design of Linear Amplifiers using MOSFETs
The design methodology for linear amplifiers using FETs is identical to that used for bipolar linear
amplifiers. In both cases, we need to bias the transistor to make sure that it operates in the proper
mode (forward active for BJTs, saturation for FETs) and then we need to consider the small-signal
model of this transistor to analyze the performance of the amplifier thus obtained.
Hereafter, we are going to focus on the design of linear amplifiers using N-channel MOSFETS,
often referred to as NMOS transistors.
 Biasing of MOS Transistors
MOS transistors have three different modes of operation. The mode that is used to design MOS
amplifiers corresponds to the constant-current region of the output characteristic (as was also the
case with BJT amplifiers). This mode is the saturation mode of operation. A MOS transistor must
remain in the saturation mode when used to design an amplifier, whatever the value of the input
signal to be amplified. Biasing an amplifier circuit allows us to make sure that the MOS transistor
is in the saturation mode.
Biasing a circuit consists of applying a constant (DC) voltage across the circuit (supply voltage) to
ensure that the MOS transistor(s) inside this circuit always operate in the saturation mode.
Below is an example of biasing circuit for an amplifier using an NMOS transistor with a threshold
voltage VTN = 0.5 V and a gain factor kn = 8 mA/V2. We assume that this transistor is in the
saturation mode of operation. We will have to check later whether or not this assumption is right.
R2
Due to the voltage divider formed by R1 and R2, we can easily see that VGS0  VDD = 1 V,
R1  R2
and thus VGS0 - VTN = 0.5 V. Since VGS0 > VTN, the NMOS transistor is either in the linear mode or
the saturation mode.
---------------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------------
VDD = 6 V
ID0 = 1 mA
R1 = 5 M RD = 3 k
VDS0 = 3 V
R2 = 1 M VGS0 = 1 V
ID0 = 1 mA
GND
Once the value of VGS0 is known, we can determine the DC drain current by using the expression
ID0 
kn
VGS0  VTN 2 . We find ID0 = 1 mA.
2
Finally, we can compute the value of the DC voltage VDS0 as VDS0  VDD  RD ID0 = 3 V. Since VDS0
> VGS0 – VTN, we conclude that our assumption was right and the NMOS transistor is indeed in the
saturation mode.
ID
VDS = VGS – VTN
VGS VDS
VGS0 = 1 V VTN = 0.5 V VGS0 – VTN = 0.5 V VDS0 = 3 V
---------------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------------
 Design of a Common-Source Amplifier
Our NMOS transistor is properly biased and can therefore be used to amplify an input signal vin(t).
We assume that vin(t) represents a voltage variation that needs to be amplified. We can now study
the complete voltage amplifier circuit which is depicted below. Note that this is a common-source
configuration. The input voltage vin(t) is an AC signal with small amplitude variations.
AC signal => the mean of vin(t)

the signal is zero Small amplitude variations
VDD = 6 V
Id(t)
Coupling R1 = 5 M RD = 3 k
capacitors
Vds(t)
Vgs(t) Vout(t)
vin(t) R2 = 1 M
Id(t)
GND
The presence of both coupling capacitors protects the biasing circuit from any external influence.
In other words, any change in the external environment of the amplifier circuit does not have any
effect on the DC operating points.
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
If there was a DC component in vin(t), it would be filtered out by the capacitance and would not
affect the biasing of the circuit either. It is worthwhile mentioning that, as a result, the amplifier
described here cannot amplify a DC signal.
We assume that both coupling capacitances are sufficiently high to be considered as short circuits
(perfect wires) at the frequency of the input signal.
A variation of the input signal vin(t) will induce corresponding variations of the various voltages and
currents inside the circuit around their DC values. For instance, a small variation of vin(t) will
induce a corresponding variation of the drain current around its mean value ID0 =1 mA.
Any signal X(t) in the circuit is therefore the sum of a DC component X 0 (mean value of X(t)) and
an AC component x(t), i.e. X(t) = X0 + x(t). The quantity X0 was determined by the DC analysis of
the circuit. In particular, we have:
- Id(t) = ID0 + id(t) ;
- Vgs(t) = VGS0 + vgs(t) ;
- Vds(t) = VDS0 + vds(t).
VDD = 6 V
ID0 + id(t)
R1 = 5 M RD = 3 k
VDS0 + vds(t)
VGS0 + vgs(t) Vout(t)

vin(t) R2 = 1 M
ID0 + id(t)
GND
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
Note that the relationship between the drain current Id(t) and the voltage Vgs(t) is quadratic, and
therefore not linear. In other words, the amplification process will introduce some distortion of the
signal, which may be a problem in some applications. However, this distortion can generally be
considered negligible if the variation vgs(t) of the gate-source voltage around its DC value VGS0 is
sufficiently small (since quadratic curve  straight line over small intervals).
The magnitude of vin(t) is considered to be sufficiently small so that the variation of Vds(t) around
VDS0 allows the MOS transistor to remain in the saturation mode of operation.
v out t 
The voltage gain of this amplifier is defined as A v  .
v in t 
In order to compute the voltage gain of this amplifier, we now need to focus on the AC operation
of the amplifier circuit. From an AC perspective, the amplifier circuit is equivalent to the circuit
depicted below.
Remember that the supply voltage VDD is a voltage equal to zero (ground) for the AC operation of
the amplifier, thus implying that the resistance R1 is now connected between the gate of the
transistor and the ground.
GND
id(t)
RD = 3 k
vds(t)
vgs(t) vout(t)
vin(t) R1 R2
id(t)
GND
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
 Small-Signal Model of a MOSFET
In order to perform the AC analysis of the amplifier, we need to replace the NMOS transistor with
an equivalent model valid for a small-amplitude input signal (“small signal”). The NMOS transistor
is now seen as a “black box” with two inputs and two outputs.
ig id
NMOS
vgs vds
transistor
We can easily show that the (generic) small-signal model of a MOSFET is as follows:
ig id
gmvgs vds
vgs
The transconductance gm, expressed in siemens (S), of the NMOS transistor is given by
id d ID
gm   .
v gs dVGS VGS0 ,ID0
Around the DC operating point, we can use the expression of the drain current valid in the
saturation mode:
kn
ID  VGS  VTN 2 .
2
We thus obtain gm  k n VGS0  VTN  . For the amplifier consider here, we have gm = 4 mS.
At this stage, it is interesting to compare the transconductance of a MOSFET with that of a BJT.
---------------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------------
The transconductance of a BJT is given by

ic i i  I I
gm   c b  F  F B0  C0 .
v be ib v be h11 VT VT
The BJT transconductance is thus proportional to the DC collector current I C0, and we have
gm 1
 , where VT designates the thermal voltage (VT  25 mV at room temperature).
IC0 VT
As for the MOS transconductance, we can also show that it depends on the drain current ID0. In
gm
fact, the ratio is given by
ID0
gm k V  VTN  2
 n GS0  .
k VGS 0  VTN
ID0 n
VGS0  VTN 2
2
Since the term VGS0 – VTN is typically much larger than the thermal voltage VT, we conclude that,
for a given DC output current IC0 or ID0, the BJT transconductance tends to be much larger than
the MOS transconductance. Therefore, a given variation of the input voltage (vbe, vgs) tends to
produce a much larger variation of the output current (ic, id) with a BJT than with a MOSFET. In
other words, bipolar transistors seem to be inherently more suitable than MOSFETS for the
design of high-gain amplifiers.
 Small-Signal Analysis of our Common-Source Amplifier
We can now replace the NMOS transistor with its small-signal model in order to determine the
expressions of the voltage gain, input resistance, and output resistance of our common-source
amplifier.
+
vin(t) R1 R2 vgs gmvgs RD vout(t)
-
GND
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
We recall the values of the various parameters: R1 = 5 M, R2 = 1 M, gm = 4 mS, and RD = 3 k.
We can show that v out t   RD gm v gs . Therefore, we obtain v out t   gm RD v in t  .
The voltage gain of our common-source amplifier is thus given by

v out t 
Av    gm RD = -12.
v in t 
This voltage gain is significantly lower than those typically achieved with a common-emitter
bipolar amplifier (because of the lower transconductances).
R1 R 2
The input resistance is given by rin   833 k. The input resistance of a MOS amplifier is
R1  R 2
typically much higher than that of a BJT amplifier due to the infinite input resistance of MOSFETs.
The output resistance is given by rout  RD = 3 k. There is here no noticeable difference between
common-emitter bipolar amplifiers and common-source MOS amplifiers.
Itest
R1 R2 vgs = 0 gmvgs = 0 RD Vtest

-
GND
---------------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------------
Tutorial 6 – Amplifier Circuits using MOSFETs
Question 1
VDD = 6 V
R1 = 5 M RD = 3 k
+
vin(t) Vout(t)
R2 = 1 M RS = 1 k
-
GND
The only difference with the amplifier circuit described in the lecture notes is that we have added a
source resistance RS. The presence of this source resistance implements a negative feedback
effect.
Perform the DC and AC analysis of this amplifier. Assume the use of an NMOS transistor with a
threshold voltage VTN = 0.5 V and a gain factor kn = 8 mA/V2.
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
Question 2
VDD = 10 V
R1 = 8 M
+
vin(t)
R2 = 2 M RS = 2 k Vout(t)
-
GND
The drain is connected directly to the voltage supply. The input signal is applied between the gate
and ground, while the output signal is measured between the source and ground. This
arrangement is a common-drain amplifier.
Perform the DC and AC analysis of this amplifier. Assume the use of an NMOS transistor with a
threshold voltage VTN = 1 V and a gain factor kn = 8 mA/V2.
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---------------------------------------------------------------------------------------------------------------------------------------------------------------
8. Operational Amplifiers
 Basic Concept
The operational amplifier (op-amp) is an “ultimate” voltage amplifier in the sense that its
characteristics are ideal (at least in theory). We recall that the equivalent circuit of a voltage
amplifier is as follows:
Input current Iin(t) Output current Iout(t)

Rout
+
Voltage gain
Input voltage (without load) Output voltage
Rin
Vin(t) AvVin(t) Vout(t)
-
The characteristics of the op-amp are:

- Infinite input resistance (very high in practice);
- Zero output resistance (very small in practice);
- Infinite voltage gain (very high in practice).
The op-amp was initially designed to perform mathematical operations. Although now superseded
in that area by the digital computer, op-amps remain a common feature of analogue electronic
circuits.
The open-loop voltage gain AOL, for a typical op-amp, ranges from 103 to 106. Such open-loop
gain is too large to be useful since noise would cause the circuit to clip. Feedback must thus be
used to control and stabilize the amplifier gain. Stabilization is obtained by feeding the output back
into the input (feedback loop). In this way, the closed-loop gain does not depend on the amplifier
characteristics.
---------------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------------
The figure below shows a complete diagram of an op-amp. Typical values for the supply voltages
are V++ = 15 V and V-- = -15 V. The positive and negative voltage supplies are necessary to
allow the amplification of both positive and negative signals without special biasing.
V-- = - 15 V
Inverting input V- -
Output
Non-inverting input V+ + Vout(t) = AOL(V+ - V-)
V++ = + 15 V
We are now going to study several “classical” circuits that employ operational amplifiers.
 Inverting Amplifier
R2
R1
-
vin(t) +
vout(t)
Ground
Vout t  R
The gain, G, of such device is given by G   2 .
Vin t  R1
---------------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------------
 Summing Amplifier
R1
V1(t)
R2 R4
V2(t)
R3
V3(t) -
+
Vout(t)
Ground
 R4  R  R 
The output signal is given by Vout t    V1t    4 V2 t    4 V3 t  .
 R1   R2   R3 
If R1 = R2 = R3 = R, we have Vout t   
R4
V1t   V2 t   V3 t  , and the output voltage is then
R
proportional to the sum of the input voltages.
For only one input and a constant reference voltage Vref, we obtain
R  R 
Vout t    4 V1t    4 Vref ,
 R1   R2 
where the second term represents an offset voltage. This provides a convenient method for
obtaining an output signal with any required voltage offset.
---------------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------------
 Differentiation Circuit
To obtain a differentiation circuit, we replace the input resistor of the inverting amplifier with a
capacitor.
vin(t) +
vout(t)
Ground
dVin t 
The output signal is expressed as Vout t   RC , and is therefore proportional to the
dt
derivative of the input signal.
 Integration Circuit
Integration is obtained by reversing the resistor and the capacitor. The capacitor is now in the
feedback loop.
R
-
vin(t) +
vout(t)
Ground
dVout t 
Vin t   Vout t    Vin t  dt . The output signal is proportional to the
1 1
We have
dt

RC RC 
integral of the input signal.
---------------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------------
 Differential Amplifiers
The differential amplifier amplifies the difference between two input signals (-) and (+). It forms the
central basis of more sophisticated instrumentation amplifier circuits.
R1 R2
V1(t)
V3(t)
-
V3(t) +
vout(t)
V2(t)
Ground
R1 R2
R 2 V2 t 
The voltage divider rule tells us that V3 t   .
R1  R 2
V1t   V3 t  Vout t   V3 t 
 0 , which yields Vout t   2 V2 t   V1t  .
R
In addition, we have 
R1 R2 R1
Such differential amplifier is usually limited in its performance by its low input impedance. Two
buffer amplifiers are commonly added to remove this limitation as follows:
---------------------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------------
-
R1 R2
V1(t) +
-
+
vout(t)
- R1 R2
Ground
V2(t) +
- END -
---------------------------------------------------------------------------------------------------------------------------------------------------------------

EEE1002 EEE1010 Lecture Notes

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EEE1002/EEE1010 - Electronics I

Lecturer for Analogue Electronics: S Le Goff (module leader)

Analogue Electronics: 24 hours of lectures and tutorials (12 weeks  2 hours/week)

Assessment for analogue electronics:

Z Element No. of electrons/shell

Si Si Si Electrons on the outer

We obtained a semiconductor material by introducing a 5-electron impurity into a matrix of 4-

2. The PN Junction (Diode)

Mobile negative charges

N-type silicon P-type silicon

Bound positive charges Bound negative charges

N-type silicon P-type silicon

N-type silicon P-type silicon

Reverse bias V 0 volt

N-type silicon P-type silicon

The depletion region

Forward bias V 0 volt

N-type silicon P-type silicon

The depletion region becomes narrower as V

 Current-Voltage Characteristic of a Diode

Reverse bias Forward bias

Tutorial 1 – Diode Circuits

V Two modes of operation

Question 1: Half-Wave Rectifier

Question 2: Half-Wave Rectifier with Capacitor

Question 3: Diode Clipping

Question 4: Power-Supply Circuit using a Full-Wave Bridge Rectifier

Consider the circuit shown below.

3. The Bipolar Junction Transistor

A replica of the first working transistor

Emitter (E) Collector (C)

Simplified cross section of a planar NPN bipolar junction transistor

VBE  0.7 V VBC < 0.7 V

This current amplification phenomenon is known as the transistor effect.

 Common-Emitter Configuration of a BJT

Output of the BJT

Input of the BJT VBE

 The Four Different Modes of Operation of a Transistor

We can write the general equations for the Ebers-Moll model:

Arrows showing the flows of electrons

A BJT has four modes of operation.

Two depletion regions

Arrows showing the flows of electrons

In the forward active mode, we have IR  0 , which yields IB  1  F  IF , IC  F IF , and IE  IF . By

combining those three expressions, we obtain IC  F IF  F IB  F IB .

Arrows showing the flows of electrons

In the reverse active mode, we have IF  0 , which yields IB  1  R  IR , IC  IR , and

VCE  0 volt => No reverse mode

Arrows showing the flows of electrons

Strictly speaking, the

Output characteristic of a BJT

Tutorial 2 – Bipolar Junction Transistors

Three modes of operation

Cut-off Forward active Saturated

Question 1: The BJT as a Logic Inverter

Consider the circuit depicted below. VCC

Question 2: Design of a Linear Common-Emitter Amplifier

Signal source Load