SN54/74LS73A

DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These
dual flip-flops are designed so that when the clock goes HIGH, the inputs are
enabled and data will be accepted. The logic level of the J and K inputs may DUAL JK NEGATIVE
be allowed to change when the clock pulse is HIGH and the bistable will per- EDGE-TRIGGERED FLIP-FLOP
form according to the truth table as long as minimum set-up times are ob-
served. Input data is transferred to the outputs on the negative-going edge of LOW POWER SCHOTTKY
the clock pulse.

LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX

CERAMIC
CASE 632-08
14
1
Q Q
13 (8) 12 (9)

N SUFFIX
CLEAR PLASTIC
2 (6)
K 14 CASE 646-06
J
3 (10) 14 (7) 1

1 (15)
CLOCK (CP)
D SUFFIX
SOIC
14
1 CASE 751A-02

ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC
MODE SELECT — TRUTH TABLE
INPUTS OUTPUTS
OPERATING MODE
CD J K Q Q
LOGIC SYMBOL
Reset (Clear) L X X L H
Toggle H h h q q
Load “0” (Reset) H l h L H
Load “1” (Set) H h l H L 14 J Q 12 7 J Q 9
Hold H l l q q
1 CP 5 CP
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
3 K C Q 13 10 K C Q 8
X = Don’t Care D D
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
l, h (q) = prior to the HIGH to LOW clock transition. 2 6
VCC = PIN 4
GND = PIN 11

FAST AND LS TTL DATA

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 SN54/74LS73A

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input LOW Voltage for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table

J, K 20
Clear 60 µA VCC = MAX, VIN = 2.7 V
Clock 80
IIH Input HIGH Current
J, K 0.1
Clear 0.3 mA VCC = MAX, VIN = 7.0 V
Clock 0.4
J, K – 0.4
IIL Input LOW Current mA VCC = MAX, VIN = 0.4 V
Clear, Clock – 0.8
IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX
ICC Power Supply Current 6.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
fMAX Maximum Clock Frequency 30 45 MHz Figure 1
VCC = 5.0 V
tPLH Propagation Delay, 15 20 ns
Figure 1 CL = 15 pF
tPHL Clock to Output 15 20 ns

AC SETUP REQUIREMENTS (TA = 25°C)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tW Clock Pulse Width High 20 ns Figure 1
tW Clear Pulse Width 25 ns Figure 2
VCC = 5.0 V
ts Setup Time 20 ns
Figure 1
th Hold Time 0 ns

FAST AND LS TTL DATA

5-69
 SN54/74LS73A

AC WAVEFORMS

J or K * 1.3 V

th(L) = 0 th(H) = 0
ts(L) ts(H)
tW(L)
CP
1.3 V 1.3 V 1.3 V
tW(H)
1
tPHL fMAX tPLH
Q
1.3 V 1.3 V

tPLH tPHL

1.3 V 1.3 V
Q

*The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 1. Clock to Output Delays, Data

Set-Up and Hold Times, Clock Pulse Width

tW

SET
1.3 V 1.3 V

tW

CLEAR
1.3 V 1.3 V

tPLH tPHL

1.3 V 1.3 V
Q

tPHL tPLH

Q
1.3 V 1.3 V

Figure 2. Set and Clear to Output Delays,

Set and Clear Pulse Widths

FAST AND LS TTL DATA

5-70