ICEE Tutorial 2014 PDF

Compact Modeling of
Semiconductor Devices: MOSFET
Yogesh S. Chauhan
Assistant Professor and Ramanujan Fellow
Nanolab, Department of Electrical Engineering
IIT Kanpur
Email: [email protected]
Homepage – http://home.iitk.ac.in/~chauhan/
Outline
• Compact Modeling
• MOSFET
• Drain Current in MOSFET
• Smoothing Functions
• Terminal Charges
• Scaling
• FinFET
12/3/2014 Yogesh S. Chauhan, IIT Kanpur 2

Compact Modeling or SPICE Modeling
Medium of
information
exchange
 Good model should be • Excellent Convergence

 Accurate: Trustworthy simulations.
 Simple: Parameter extraction is
• Simulation Time – ~µsec
easy. • Accuracy requirements
 Balance between accuracy and
simplicity depends on end application
– ~ 1% RMS error after fitting
• Example: BSIM6, BSIM-
CMG
Industry Standard Compact Models
• Standardization Body – Compact Model Coalition
• CMC Members – EDA Vendors, Foundries, IDMs,

Fabless, Research Institutions/Consortia
• CMC is by the industry and for the industry

What is MOSFET?
• MOSFET is a transistor used for amplifying or
switching electronic signals.
Gate
Drain
Source
Introduction to MOSFET
• Building block of Gb memory chips, GHz
microprocessors, analog, and RF circuits.
Basic MOSFET structure
and IV characteristics Polysilicon gate & SiO2

How can we simulate MOSFET based
circuits?
• We need
– Currents
𝐼𝐼𝑑𝑑𝑑𝑑 = 𝑊𝑊. 𝑄𝑄𝑖𝑖𝑖𝑖𝑖𝑖 . 𝜈𝜈 = 𝑊𝑊. 𝑄𝑄𝑖𝑖𝑖𝑖𝑖𝑖 . 𝜇𝜇𝑛𝑛𝑛𝑛 𝐸𝐸
𝑑𝑑𝑑𝑑𝑐𝑐𝑐
𝐼𝐼𝑑𝑑𝑑𝑑 = 𝑊𝑊. 𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝑔𝑔𝑔𝑔 − 𝑉𝑉𝑡𝑡 . 𝜇𝜇𝑛𝑛𝑛𝑛
𝑑𝑑𝑑𝑑
– Charges (for capacitance)

Energy Band Diagram in Equilibrium

Depletion and Inversion
Surface is depleted of holes Surface is inverted

Threshold Condition and Threshold Voltage
Threshold (of inversion):
ns = Na , or
(Ec–Ef)surface= (Ef – Ev)bulk , or
 A=B, and C = D
𝑘𝑘𝑘𝑘 𝑁𝑁𝑎𝑎
𝜓𝜓𝑠𝑠𝑡𝑡 = 2𝜙𝜙𝑏𝑏 = 2 𝑙𝑙𝑙𝑙
𝑞𝑞 𝑛𝑛𝑖𝑖
Amount of band bending
qN a 2ε s 2φB at surface is called
Vox = “Surface Potential”.
Cox
𝑉𝑉𝑔𝑔 = 𝑉𝑉𝑓𝑓𝑓𝑓 + 𝜓𝜓𝑠𝑠 + 𝑉𝑉𝑜𝑜𝑜𝑜

qN a 2ε s 2φB
Vt = Vg at threshold = V fb + 2φB +
Cox
Inversion Layer Charge
• Applied Gate Voltage
Qdep Qinv
V g = V fb + 2φ B − −
C ox C ox
qN a 2ε s 2φ B Qinv
= V fb + 2φ B + −
C ox C ox
Qinv
= Vt −
C ox
Inversion Layer Charge Qinv = −C ox (V g − Vt )

MOSFET Vt and the Body Effect
• Two capacitors => two εs
charge components
Cdep =
Wd max
Qinv = −Coxe (Vgs − Vt ) + CdepVsb

Cdep
= −Coxe (Vgs − (Vt + Vsb ))
Coxe Coxe
• Redefine Vt as
Cdep
Cdep
Vt (Vsb ) = Vt 0 + Vsb = Vt 0 + αVsb
Coxe

Uniform Body Doping
• In earlier generations of MOSFETs, the body
doping density is more or less uniform and Wdmax
varies with Vsb.
• In that case, the theory for the body effect is more
complicated.
qN a 2ε s
Vt = Vt 0 + ( 2φ B + Vsb − 2φ B )
Coxe
≡ Vt 0 + γ ( 2φ B + Vsb − 2φ B )
γ is the body-effect parameter.

Threshold Voltage Modeling
• Long/Wide Channel Model With Uniform
Doping
– VFB=flat band voltage

– VTH0=threshold voltage of device at zero substrate
bias
– γ is the body bias coefficient given by

• As channel length gets shorter Vth shows a greater dependence on
– Short-channel effect  Higher Off Current Leakage
– DIBL  Higher Off Current Leakage at high Vds

• The complete Vth model implemented in
SPICE as

Surface Mobility
Vg = Vdd , Vgs = Vdd
Vds > 0
I ds = W ×Qinv ×v = WQinv µ nsE
Ids = WQinv µ nsVds / L
= WCoxe (Vgs − Vt ) µ nsVds / L
• Scattering mechanisms
– Phonon scattering
– Coulomb scattering
– Interface roughness scattering
Surface Mobility
• Mobility is a function of the average of the fields at the
bottom and the top of the inversion charge layer, Eb and Et .
From Gauss’s Law, Eb = – Qdep/εs
Vg = V fb + ψ s + Vox Vt = V fb + φ st − Qdep / Coxe
Coxe
Therefore, Eb = (Vt − V fb − φ st )
εs
E t = −(Qdep + Qinv ) / ε s 1 Coxe
∴ E
( b + Et)
= (Vgs + Vt − 2V fb − 2φ st )
= Eb − Qinv / ε s = Eb +
Coxe
(Vgs − Vt ) 2 2ε s
εs Coxe
≈ (Vgs + Vt + 0.2 V)
=
Coxe
(Vgs − V fb − φ st ) 2ε s
εs NMOS with n+ poly-Si gate
Vgs + Vt + 0.2 V
Vfb≈-0.5 and ψst≈0.4
12/3/2014 Yogesh S. Chauhan, IIT Kanpur
= 18
6Toxe
Universal Surface Mobilities
•Surface roughness scattering is
Surface mobility (cm2/V-s)
stronger (mobility is lower) at

higher Vg, higher Vt, and thinner
Toxe.
Empirical fitting

Mobility Modeling in BSIM4
Vgs + Vt
Eeff =
6Toxe
Vgs − Vt + 2Vt
Eeff =
6Toxe
Vgsteff + 2Vt
Eeff =
6Toxe

Current in subthreshold region
• Subthreshold conduction
– Transistor is in depletion
• Surface potential is determined by
depletion under the gate, which is
constant everywhere (ψS≈ ψsa).
2
 γ γ 2 
ψ sa ≈ ψ sa 
= − + + VGB − VFB 
 2 4 
 
2 qε s N A  VGCnφ−VM  dVCB
Q =−
' φ e t  I ds ( x) = µ eff WQi
I
2 2φ f + VCB
'  t 
  dx
• Integrating from source to drain,
L L
∫I
0
ds ( x)dx = ∫ µ eff ⋅ W ⋅ Qi ⋅ dVCB
0
VDB
W
I ds = µ eff
L ∫ Q ⋅ dV
VSB
i CB

W  2qε s N A
VDB
 VGB −VCB −VTH 

e  ⋅ dV
∫
φ
I ds = µ eff  φ n t

L VSB 2 2φ f + VCB  ' t
  CB
 
 VGSn−ϕVTH VGD −VTH
 VGS −VTH
 V
− DS 

I ds = I 0 e t
−e nϕ t  I = I e nϕ t  1 − e nϕ t 
  ds 0
 
12/3/2014   IIT Kanpur
Yogesh S. Chauhan,  22
VGS −VTH
 V
− DS 
I ds = I 0 e nϕ t  1 − e nϕ t 
 
 
• Note – VTH is a function of body bias.

– If VB increases in negative direction, VTH
increases.
VTH = VT 0 + γ (φ 0 + VSB − φ0 )
Subthreshold slope
• It is defined as the amount of gate voltage
required to change the gate current by 1-decade.
dVGS
S=
d (log I ds )
At room temperature
 Cdep   Cdep 
S = (25.85)(2.30)1 +  ≈ 60mV 1 + 
 Cox   Cox 
Drain Current and Qinv in MOSFET
• Channel voltage
Vc=Vs at x = 0 and
Vc=Vd at x = L.
QI' = −Cox' (VGC − VTH ) = −Cox' (VGC − Vt 0 − αVcb )
• Qinv = – Cox(Vgs – Vcs – Vt0 – α (Vsb+Vcs)

• = – Cox(Vgs – Vcs – (Vt0 +α Vsb) – α Vcs)
• Qinv = – Cox(Vgs – mVcs – Vt)
•
• m ≡ 1 +α = 1 + 3Toxe/Wdmax ≈1.2
• m is called the body-effect factor or bulk-charge factor.
Drain Current Calculation
Now,
Ids = WCoxe(Vgs– mVcs – Vt)μnsdVcs/dx
Integrating the above equation over the channel length L, gives

the current voltage relation as follows:
L Vds
∫ 0
I ds dx = WCoxe µ ns ∫ (Vgs − mVcs − Vt )dVcs
0
IdsL = WCoxeµns(Vgs – Vt – mVds/2)Vds
W  m 
I ds = µ ns Coxe Vgs − Vt − Vds Vds
L  2 
I-V characteristics
dI ds
=0
dVds Linear Region Saturation region
W
Coxe μns (Vgs − Vt − mVdsat ) = 0
L
Vgs − Vt
Vdsat =
m
Vds ˂ Vdsat Linear Region Drain current in saturation regio

W
Vds ≥ Vdsat Saturation region I dsat = C µ
oxe ns (V gs − V t ) 2
2mL
W
• transconductance: gm= dIds/dVgs g msat = Coxe µ ns (Vgs − Vt )
12/3/2014 Yogesh S. Chauhan, IIT Kanpur mL 27
I-V characteristics
What happens at Vds=Vdsat & why Ids remains
constant beyond Vdsat
At Vds=Vdsat , Qinv near the drain end of the

channel becomes zero ! i.e. Pinch off.
Ids = WQinvµnsE (Large E and and negligible Qinv)
At Vds >Vdsat , A very short region near the drain
end where the Qinv = 0, a very high electric field
exist due to the drop of the additional Vds - Vdsat .
Velocity Saturation
• At low E ν = μnsE
• The inversion-layer electron velocity saturates
at high field
µ ns ξ
ν=
1 + ξ / ξ sat
ν = µ ns ξ , ξ << ξsat
ν = ν sat = µ nsξ sat , ξ ≥ ξsat
ξ sat is the field at which velocity
saturation becomes dominant.
Velocity Saturation and I-V Model
µ ns ξ
Ids = WQinvν ν=
1 + ξ / ξ sat
dVcs
µ ns
I ds = WC oxe (Vgs − mVcs − Vt ) dx
dVcs
1 + dx
ξ sat
L Vds
 WC µ (V − mV − V ) − I ds  dV
∫
0
I ds dx = ∫
0  oxe ns gs cs t ξ sat  cs
W  m 
Coxe µ ns Vgs − Vds − Vt Vds
I ds =
L  2 
V
Drain current 1 + ds
Lξ sat
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when Yogesh S. Chauhan, IIT Kanpur 30
Vds
• If L is large then will be negligible, then:
Lξsat
W m It is called the long
I ds = Coxe µ s (Vgs − Vt − Vds )Vds channel I-V model
L 2
• Effect of velocity saturation on Ids:
Vds
Ids = (Long channel Ids)/(1 + Lξsat
)
Vds
• In short channel devices 1+ >1
Lξ sat

• Drain current for Vds ≥Vdsat
W (V − V ) 2
I dsat = C oxe µ ns =Long channel Idsat/( 1 + Vgs − Vt )

gs t
2mL Vgs − Vt mξsat L

1+
mξ sat L
Very short channel case: Long channel case:
Esat L << Vgs − Vt Esat L >> Vgs − Vt
I dsat = Wvsat Coxe (Vgs − Vt − mEsat L )
Coxe µ ns (Vgs − Vt )
W
≈
2
I dsat ≈ Wvsat Coxe (Vgs − Vt )

I dsat
2mL
• Idsat is proportional to Vgs–Vt rather than
(Vgs – Vt)2 ,
•Not as sensitive to L as than long channel
case (∝1/L).

I-V Characteristics
• Long Channel Short Channel
• Ids ∝ (Vgs-Vt)2 Ids ∝ Vgs-Vt DITS

+CLM+ DIBL
I-V Characteristics
Curves for a
particular gate
voltage
Curves for a
different gate
voltages

Compact Modeling is
Art based on Science

Smoothing function and I-V Model
• Smoothing function is required for a smooth
transition between two functions.
– This stems from the need to have a single equation
valid in all regions of operation.
• BSIM3 introduced use of smoothing functions
to get single equation valid in all regions of
biases.
– This gave continuous and smooth I-V and C-V
making it popular model for analog design.
Linear to Saturation transition
• First generation SPICE models used this kind of equation,
𝑊𝑊 ′ 𝑚𝑚 2
𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝐷𝐷𝐷𝐷 , 𝑉𝑉𝐷𝐷𝐷𝐷 < 𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠
𝐿𝐿 2
𝐼𝐼𝐷𝐷 = 𝑊𝑊 ′ (𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 )2
𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 , 𝑉𝑉𝐷𝐷𝐷𝐷 ≥ 𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠
𝐿𝐿 2𝑚𝑚
𝑑𝑑𝐼𝐼𝐷𝐷
𝐼𝐼𝐷𝐷 and are continuous at
𝑑𝑑𝑉𝑉𝐷𝐷𝐷𝐷
𝑑𝑑 2 𝐼𝐼𝐷𝐷
𝑉𝑉𝐷𝐷𝐷𝐷 = 𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠 but 2 is not.
𝑑𝑑𝑉𝑉𝐷𝐷𝐷𝐷

Linear to Saturation transition
• For numerical robustness, the derivatives of arbitrary order must be
continuous at all voltage values of interest. This property is sometimes
referred to as ∞-differentiability.
• Single equation approach used in BSIM3. Define an effective drain-
source bias VDSeff,
1
𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒 = 𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠 − 𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠 − 𝑉𝑉𝐷𝐷𝐷𝐷 − Δ + (𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠 − 𝑉𝑉𝐷𝐷𝐷𝐷 − Δ)2 +4Δ𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠
2
• 𝑉𝑉𝐷𝐷𝐷𝐷 ≪ 𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠 , 𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒 ≈ 𝑉𝑉𝐷𝐷𝐷𝐷
• For 𝑉𝑉𝐷𝐷𝐷𝐷 ≫ 𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠 , 𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒 ≈ 𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠
• Drain current equation becomes (VGS>VT),

𝑊𝑊
′ 𝑚𝑚 2 Increasing Δ
• 𝐼𝐼𝐷𝐷 = 𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒 − 𝑉𝑉
𝐿𝐿 2 𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒
• Derivatives are continuous.
Δ determines the degree
of smoothness.

Sub-threshold to strong inversion transition
• For 𝑉𝑉𝐺𝐺𝐺𝐺 ≪ 𝑉𝑉𝑇𝑇 ,
(𝑉𝑉𝐺𝐺𝐺𝐺 −𝑉𝑉𝑇𝑇 −𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 ) 𝑉𝑉
− 𝐷𝐷𝐷𝐷
𝐼𝐼𝐷𝐷 = 𝐼𝐼0 𝑒𝑒 𝑛𝑛𝑛𝑛𝑛𝑛/𝑞𝑞 1− 𝑒𝑒 𝑘𝑘𝑘𝑘/𝑞𝑞
– This is not valid in strong inversion. It leads to excessively high current for
𝑉𝑉𝐺𝐺𝐺𝐺 ≫ 𝑉𝑉𝑇𝑇
• For 𝑉𝑉𝐺𝐺𝐺𝐺 ≫ 𝑉𝑉𝑇𝑇
𝐼𝐼𝐷𝐷 = 𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒 − 𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒
𝐿𝐿 2
– This is not valid in sub-threshold and leads to negative current for 𝑉𝑉𝐺𝐺𝐺𝐺 < 𝑉𝑉𝑇𝑇
• First method – Single equation:
𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠 + 𝐼𝐼𝐷𝐷,𝑖𝑖𝑖𝑖𝑖𝑖
• Good enough for Digital

applications, but the derivatives
are discontinuous making it
unsuitable for Analog cases.
Sub-threshold to strong inversion transition
• Second method – Single equation: Use effective
𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 as
2𝑛𝑛𝑛𝑛𝑛𝑛 𝑉𝑉 − 𝑉𝑉𝑇𝑇
𝑙𝑙𝑙𝑙 1 + exp 𝐺𝐺𝐺𝐺
𝑞𝑞 2𝑛𝑛𝑛𝑛𝑛𝑛/𝑞𝑞
𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒 =
𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 − 2𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜
1 + 2𝑛𝑛 𝑒𝑒𝑒𝑒𝑒𝑒 −
2𝑛𝑛𝑛𝑛𝑛𝑛/𝑞𝑞
• 𝑛𝑛 is the ideality factor and lies between 1 and 2.
• Voff is a parameter for fringing from width side.
Assume Voff=0 for further analysis.
• For 𝑉𝑉𝐺𝐺𝐺𝐺 ≫ 𝑉𝑉𝑇𝑇 , the exponential term inside ln() is
larger than 1 making 𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒 = 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇
• For 𝑉𝑉𝐺𝐺𝐺𝐺 ≪ 𝑉𝑉𝑇𝑇 ,
𝑘𝑘𝑘𝑘 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇
𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒 ≈ 𝑒𝑒𝑒𝑒𝑒𝑒
𝑞𝑞 𝑛𝑛𝑛𝑛𝑛𝑛/𝑞𝑞

Single equation for drain current
𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒 +2𝑘𝑘𝑘𝑘/𝑞𝑞
• Use 𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠 = , where 2𝑘𝑘𝑘𝑘/𝑞𝑞 is added for numerical stability
𝑚𝑚
when 𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒 ≪ 2𝑘𝑘𝑘𝑘/𝑞𝑞.
• We have written ID as follows valid from linear to saturation-
𝐼𝐼𝐷𝐷 = 𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇 𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒 − 𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒
𝐿𝐿 2
𝑊𝑊 ′ 𝑚𝑚
𝐼𝐼𝐷𝐷 = 𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺𝑇𝑇,𝑒𝑒𝑒𝑒𝑒𝑒 − 𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒 𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒
𝐿𝐿 2
• Now drain current becomes,
𝑊𝑊 ′ 𝑚𝑚 𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒
𝐼𝐼𝐷𝐷 = 𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒 − 𝑉𝑉𝐷𝐷𝑆𝑆,𝑒𝑒𝑒𝑒𝑒𝑒 𝑉𝑉
𝐿𝐿 2 𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒 + 2𝑘𝑘𝑘𝑘/𝑞𝑞 𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒
𝑊𝑊 ′ 𝑚𝑚 𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒
𝐼𝐼𝐷𝐷 = 𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒 1 − 𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒
𝐿𝐿 2 𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒 + 2𝑘𝑘𝑘𝑘/𝑞𝑞
• This is valid for all Vgs and Vds.

Terminal Charges and Charge Partition
• AC and Transient simulation
need capacitances.
• Quasi-static approximation
– The Channel charge is assumed
to respond instantaneously to
any change in the bias voltage.
• From 𝑄𝑄𝑖𝑖′ , we need to find QG,
QB, QS and QD.

Total inversion charge
• Before delving into QG, QS and QD. Let us find the total
inversion charge in the channel, 𝑄𝑄𝑖𝑖 .
• The charge per unit area, 𝑄𝑄𝐼𝐼′ , is given as
𝑄𝑄𝐼𝐼′ = −𝐶𝐶𝑜𝑜𝑜𝑜
′ 𝑉𝑉 − 𝑉𝑉 − 𝑚𝑚𝑉𝑉
𝐺𝐺𝐺𝐺 𝑇𝑇 𝐶𝐶𝐶𝐶 𝑥𝑥
• We need to know 𝑉𝑉𝐶𝐶𝐶𝐶 𝑥𝑥 =?
𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒 𝑉𝑉𝐷𝐷𝐷𝐷,𝑒𝑒𝑒𝑒𝑒𝑒
• Define α = 1 − which gives, = 1 − α,
𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠 𝑉𝑉𝐷𝐷𝐷𝐷,𝑠𝑠𝑠𝑠𝑠𝑠
Thus
𝑽𝑽𝑮𝑮𝑮𝑮𝑮𝑮,𝒆𝒆𝒆𝒆𝒆𝒆 𝒙𝒙
𝑽𝑽𝑪𝑪𝑪𝑪 = 𝟏𝟏 − 𝟏𝟏 − 𝟏𝟏 − 𝜶𝜶 𝟐𝟐
𝒎𝒎 𝑳𝑳

Total inversion charge
• The charge per unit area, 𝑄𝑄𝐼𝐼′ , is given as
𝑄𝑄𝐼𝐼′ = −𝐶𝐶𝑜𝑜𝑜𝑜
′ 𝑉𝑉 − 𝑉𝑉 − 𝑚𝑚𝑉𝑉
𝐺𝐺𝐺𝐺 𝑇𝑇 𝐶𝐶𝐶𝐶 𝑥𝑥
′ ′
𝑥𝑥
𝑄𝑄𝐼𝐼 = −𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒 1 − 1 − 𝛼𝛼 2
𝐿𝐿
• Thus total inversion charge
𝐿𝐿
′
𝑥𝑥
𝑄𝑄𝐼𝐼 = −𝑊𝑊𝐶𝐶𝑜𝑜𝑜𝑜 � 𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒 1 − 1 − 𝛼𝛼 2 𝑑𝑑𝑑𝑑
0 𝐿𝐿
• Total inversion charge

2 2
′ 𝑉𝑉
1 + 𝛼𝛼 + 𝛼𝛼
𝑄𝑄𝐼𝐼 = − 𝑊𝑊𝑊𝑊𝐶𝐶𝑜𝑜𝑜𝑜 𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒
3 1 + 𝛼𝛼
Source-Drain charge partitioning
• We know, 𝑄𝑄𝐼𝐼 = 𝑄𝑄𝑆𝑆 + 𝑄𝑄𝐷𝐷 but not the exact share of each.
• The assignment of the channel charge to the source and
drain charges is called charge partition.
• Charge partitioning
– 50/50 partition: Arbitrarily assign 50% of 𝑄𝑄𝐼𝐼 to 𝑄𝑄𝑆𝑆 and 50% to
𝑄𝑄𝐷𝐷 .This is valid only when 𝑉𝑉𝐷𝐷𝐷𝐷 is small. For 𝑉𝑉𝐷𝐷𝐷𝐷 ~0, MOSFET
is symmetrical and 𝑄𝑄𝑆𝑆 ~𝑄𝑄𝐷𝐷 ~𝑄𝑄𝐼𝐼 /2.
– 0/100 partition: This is based on the logic that in saturation, the
pinch off region implies that 𝑄𝑄𝐷𝐷 = 0, which is actually not
correct.
– 40/60 partition: This is a more physical distribution of charges.
One should note that the charge distribution under this scheme is
40/60 only in saturation. However this partition scheme is valid
in all regions.

Source-Drain charge
• Ward-Dutton partitioning scheme
𝐿𝐿 𝑥𝑥 ′ 𝐿𝐿 𝑥𝑥
𝑄𝑄𝐷𝐷 = 𝑊𝑊 ∫0 𝑄𝑄𝐼𝐼 𝑑𝑑𝑑𝑑 ,
𝑄𝑄𝑆𝑆 = 1 − 𝑄𝑄𝐼𝐼′ 𝑑𝑑𝑑𝑑
𝑊𝑊 ∫0
𝐿𝐿 𝐿𝐿
• Drain charge
𝐿𝐿 𝐿𝐿
𝑥𝑥 ′ ′
𝑥𝑥 𝑥𝑥
𝑄𝑄𝐷𝐷 = 𝑊𝑊 � 𝑄𝑄𝐼𝐼 𝑑𝑑𝑑𝑑 = −𝑊𝑊𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒 � 1 − 1 − 𝛼𝛼 2 𝑑𝑑𝑑𝑑
0 𝐿𝐿 0 𝐿𝐿 𝐿𝐿
2 3 + 6𝛼𝛼 2 + 4𝛼𝛼 + 2
′ 𝑉𝑉
3𝛼𝛼
𝑄𝑄𝐷𝐷 = − 𝑊𝑊𝑊𝑊𝐶𝐶𝑜𝑜𝑜𝑜 𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒
15 (1 + 𝛼𝛼)2
• Similarly,
𝐿𝐿 𝑥𝑥 ′ 2 ′ 2𝛼𝛼3 +4𝛼𝛼2 +6𝛼𝛼+3
𝑄𝑄𝑆𝑆 = 𝑊𝑊 ∫0 1 − 𝑄𝑄𝐼𝐼 𝑑𝑑𝑑𝑑 = − 𝑊𝑊𝑊𝑊𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒
𝐿𝐿 15 1+𝛼𝛼 2
Ref.: S.-Y. OH, D. E. WARD and, A. W. DUTTON, “Transient Analysis of MOS Transistors,” IEEE JOURNAL OF SOLID-STATE
CIRCUITS, VOL. SC-15, NO. 4, AUGUST 1980.
Gate and Bulk charge
• Total gate charge
′
𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺,𝑒𝑒𝑒𝑒𝑒𝑒 2 1 + 𝛼𝛼 + 𝛼𝛼 2
𝑄𝑄𝐺𝐺 = 𝑊𝑊𝑊𝑊𝐶𝐶𝑜𝑜𝑜𝑜 � 𝑚𝑚 − 1 + ∙
𝑚𝑚 3 1 + 𝛼𝛼
+ 2 𝑚𝑚 − 1 2𝜙𝜙𝐹𝐹 − 𝑉𝑉𝐵𝐵𝐵𝐵 �
• Finally Bulk charge,
𝑄𝑄𝐵𝐵 = − 𝑄𝑄𝐺𝐺 − 𝑄𝑄𝐼𝐼
𝜕𝜕𝑄𝑄𝑚𝑚
• Capacitance 𝐶𝐶𝑚𝑚𝑚𝑚 =
𝜕𝜕𝑉𝑉𝑛𝑛
Charge and Capacitance plots

Real Device Effects

Parasitic Source-Drain Resistance
• The main effect of the parasitic resistance is
that Vgs in the Ids equations is reduced by Rs·Ids
I dsat 0
I dsat ≈
I dsat 0 Rs
1+
(Vgs − Vt )
High-Frequency performance
D High-frequency performance is limited
Rd by input R and/or C.
Rin
G
Low Frequency
Model Rs
S Rin = Rg −electrode + Rii
Gate-electrode resistance Intrinsic input resistance

Gate-Electrode Resistance
Drain
Source
Multi-finger layout greatly reduces
Rg-electrode the gate electrode resistance
Rg −electrode = ρW / 12Tg Lg N f
2
ρ : resistivity of gate material,

Wf : width of each gate finger,
Tg : gate thickness,
Lg : gate length,
Nf : number of fingers.

Bulk MOSFET
• Drain current in MOSFET (ON operation)
𝑊𝑊
𝐼𝐼𝑂𝑂𝑂𝑂 = 𝜇𝜇 𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑇𝑇𝐻𝐻 2
𝐿𝐿
• Drain current in MOSFET (OFF operation)
𝑉𝑉𝐺𝐺𝐺𝐺 −𝑉𝑉𝑇𝑇𝐻𝐻
𝐼𝐼𝑂𝑂𝑂𝑂𝑂𝑂 ∝ 10 𝑆𝑆
Cox=εox/tox=oxide cap.
• Desired S – Subthreshold slope
• High ION (↓L, ↑Cox, ↑VDD-VTH)

• Low IOFF (↑VTH, ↑S)
Technology Scaling
• Each time the minimum
line width is reduced,
we say that a new
technology node is
introduced.
• Example: 90 nm, 65
nm, 45 nm
– Numbers refer to the
minimum metal line
width.
– Poly-Si gate length may
be even smaller.
Figure source - Wikipedia
Technology Scaling
• Scaling – At each new node, all geometrical
features are reduced in size to 70% of the
previous node.
• Reward – Reduction of circuit size by half. (~50%
reduction in area, i.e., 0.7 × 0.7 = 0.49.)
– Twice number of circuits on each wafer
– Cost per circuit is reduced significantly.
• Ultimately – Scaling drives down the cost of

ICs.

Scaling and Moore’s Law
• Number of components per IC function will double every
two years – April 19, 1965 (Electronics Magazine)
• Shorthand for rapid technological change!
Still working!

Source: http://www.intel.com/pressroom/kits/events/moores_law_40th/
Threshold Voltage Roll-Off
Energy band diagram from source to Vt decreases at very small Lg. It determines the
drain when Vgs=0V and Vgs=Vt. minimum acceptable Lg because Ioff is too large
A-b long channel; c-d short channel. when Vt becomes too low or too sensitive to Lg.

Source: Chenming Hu – Modern Semiconductor Devices for Integrated Circuits
Channel
Esat
Length Modulation
Em
Pinch off point moves
towards the source as
Vds increases
 ∆L   Vds − Vdsat 
∆ ∝ VDS − VDSsat I Dsat= I Dsat 0 1 + = I Dsat 0 1 + 
 L   V A 
long channel Short channel
Av reduces
C.Hu, Modern Semiconductor Devices for IC, 2009 Prentice Hall
Performance
Technology Trend
Product

Source : www.intel.com
Wasn’t that smooth ride?
• Where is the bottleneck?
𝑊𝑊 2
𝐼𝐼𝑂𝑂𝑂𝑂 = 𝜇𝜇 𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑇𝑇𝑇𝑇
𝐿𝐿
• VTH can’t be decreased – why?

• Subthreshold slope gets worse!
Thin Depletion Layer - Problem
Gate
Cg Oxide
Source Drain
• QG = Qi+Qb
Body • Charge sharing

Short Channel – Big Problem
Gate
Cg Oxide
Source Drain
Cd
MOSFET becomes “resistor” at small L.

Chenming Hu, “Modern Semiconductor Devices for ICs” 2010, Pearson
Making Oxide Thin is Not Enough
Gate
Source Drain
Leakage Path
Gate cannot control the leakage

current paths that are far from the gate.

What can we do?
Gate
Source Drain
Leakage Path

May 4, 2011
The New York Times Front Page
• Intel will use 3D
FinFET at 22nm
• Most radical change in

decades
• There is a competing
SOI technology
One Way to Eliminate Si Far from Gate
Thin body controlled
Gate Length
Gate Length
By multiple gates.
Source
Gate
Source Drain
Gate
Drain
FinFET body Fin Height
is a thin Fin. Fin Width
N. Lindert et al., DRC paper II.A.6, 2001
40nm FinFET – 1999
30nm Fin allows 2.7nm SiO2 & undoped body
ridding random dopant fluctuation.
66mV/dec
X. Huang et al., IEDM, p. 67, 1999

Introduced New Scaling Rule
Leakage is well suppressed if
Fin thickness < Lg
10nm Lg AMD 5nm Lg TSMC 3nm Lg KAIST
2002 IEDM 2004 VLSI 2006 VLSI

Two Improvements Since 1999
• 2002 FinFET with thin
oxide on Fin top
F.L.Yang et al. (TSMC) 2002 IEDM, p.
225.
• 2003 FinFET on bulk

substrate
T. Park et al. (Samsung) 2003 VLSI Symp.
p. 135.

State-of-the-Art 14nm FinFET
Taller and Thinner Fins for increased

drive current and performance
Source: Anandtech
BSIM Family of Compact Device Models
1990 1995 1998 2000 2005 2010
BSIM3
Conventional
BSIM4 MOSFET
New BSIM6
Silicon on Insulator
BSIMSOI MOSFET
BSIM-CMG & BSIM-IMG
Multi-Gate
MOSFET
BSIM: Berkeley Short-channel IGFET Model

BSIM-CMG and BSIM-IMG
• Berkeley Short-channel IGFET Model
• First industry standard SPICE model for IC

simulation
• Used by hundreds of companies for IC

design since 1997
• BSIM FinFET model became industry

standard in March 2012
It’s Free
Common-Multi-Gate Modeling
• Common Multi-gate (BSIM-CMG):
– All gates tied together
– Surface-potential-based core I-V and C-V model

– Supports double-gate, triple-gate, quadruple-gate,
cylindrical-gate; Bulk and SOI substrates

BSIM-CMG Model
Vg
 Surface potential obtained by
solving the 1D Poisson’s
equation n+ y n+
Vs x NA Vd
∂ 2ψ qni  qψ qφ
− B
qV
− ch
qφB
 Vg
= ⋅  e
kT
⋅ e
kT
⋅e  + e
kT
 
kT
∂x 2
εSi  Inversion Carriers Body Doping 
 A Perturbation approach is used to handle finite

body doping M. V. Dunga et al.,TED 2006
ψ
=
 ψinv + ψ pert
 
Net Surface Potential Inversion Carriers only Perturbation due to finite doping

BSIM-CMG Model
• Drain current derived from drift-diffusion
Na = 3e18cm-3 1m Na = 3e18 cm-3
Drain Current (A)

1m Vd = 0.1
Drain Current (A)
Vg = 1.5V Vd = 0.2
Vd = 0.4
500µ Vd = 0.6
500µ
Vg = 1.2V
Vg = 0.9V
0 0
0.0 0.5 1.0 1.5 0.0 0.5 1.0 1.5
Drain Voltage (V) Gate Voltage (V)
12/3/2014 Yogesh S.M. V. Dunga,

Chauhan, UCB
IIT Kanpur Ph.D. Thesis 75
BSIM-CMG
Global fitting with 30nm–10µm FinFETs

Modeling of Germanium FinFETs @10nm
• Ge FinFET may be used in 10nm node for
better P-FinFET.
• Industry standard BSIM FinFET model can
now model Ge FinFET.
• Early availability of a unified Si/Ge FinFET
model facilitates technology-circuits co-
development.

Modeling of Germanium FinFETs @10nm
20nm
• Due to the lower m* of holes in Ge the charge-centroid is

farther away from the oxide interface resulting in a weaker SR
scattering.
• Ge mobility has a weaker dependence on Eeff up-to ∼0.5 MV/cm
as the impact of SR scattering is only seen at much higher Eeff in
Ge as compared to Si.
S. Khandelwal et. al., "Modeling 20nm Germanium FinFET with the Industry
Standard FinFET Model", IEEE Electron Device Letters, July 2014.
Modeling of InGaAs FinFET @10nm
L = 20 nm, H = 30 nm, W = 20 nm, Nfin = 4. Data from: J. J. Gu et al. IEDM 2012
S. Khandelwal et. al., "InGaAs FinFET Modeling Using Industry Standard Compact Model BSIM-CMG", Workshop on
Compact
12/3/2014Modeling, Washington D.C., USA, June 2014.
Yogesh S. Chauhan, IIT Kanpur 79
Transistor Pathway

Source: Applied Materials
FinFET Modeling for IC Simulation and Design:
Using the BSIM-CMG Standard
Book
Authors Chapters
Yogesh Singh Chauhan, IITK 1. FinFET- from Device Concept to Standard
Darsen D Lu, IBM Compact Model
Navid Payvadosi, Intel 2. Analog/RF behavior of FinFET
Juan Pablo Duarte, UCB 3. Core Model for FinFETs
Sriramkumar Vanugopalan, 4. Channel Current and Real Device Effects
Samsung 5. Leakage Currents
Sourabh Khandelwal, UCB 6. Charge, Capacitance and Non-Quasi-Static
Ai Niknejad, UCB Effect
Chenming Hu, UCB 7. Parasitic Resistances and Capacitances
8. Noise
9. Junction Diode Current and Capacitance
10. Benchmark tests for Compact Models
11. BSIM-CMG Model Parameter Extraction
12. Temperature Effects
Acknowledgement
• My students
• BSIM team
• CMC members

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Compact Modeling of

Semiconductor Devices: MOSFET

12/3/2014 Yogesh S. Chauhan, IIT Kanpur 2

 Good model should be • Excellent Convergence

• CMC Members – EDA Vendors, Foundries, IDMs,

• CMC is by the industry and for the industry

12/3/2014 Yogesh S. Chauhan, IIT Kanpur 4

12/3/2014 Yogesh S. Chauhan, IIT Kanpur 6

– Charges (for capacitance)

12/3/2014 Yogesh S. Chauhan, IIT Kanpur 7

12/3/2014 Yogesh S. Chauhan, IIT Kanpur 8

12/3/2014 Yogesh S. Chauhan, IIT Kanpur 9

𝑉𝑉𝑔𝑔 = 𝑉𝑉𝑓𝑓𝑓𝑓 + 𝜓𝜓𝑠𝑠 + 𝑉𝑉𝑜𝑜𝑜𝑜

Inversion Layer Charge Qinv = −C ox (V g − Vt )

Qinv = −Coxe (Vgs − Vt ) + CdepVsb

12/3/2014 Yogesh S. Chauhan, IIT Kanpur 12

γ is the body-effect parameter.

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– VFB=flat band voltage

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= WCoxe (Vgs − Vt ) µ nsVds / L

stronger (mobility is lower) at

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• Note – VTH is a function of body bias.

QI' = −Cox' (VGC − VTH ) = −Cox' (VGC − Vt 0 − αVcb )

• Qinv = – Cox(Vgs – Vcs – Vt0 – α (Vsb+Vcs)

Integrating the above equation over the channel length L, gives

IdsL = WCoxeµns(Vgs – Vt – mVds/2)Vds

Vds ˂ Vdsat Linear Region Drain current in saturation regio

At Vds=Vdsat , Qinv near the drain end of the

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I dsat = C oxe µ ns =Long channel Idsat/( 1 + Vgs − Vt )

2mL Vgs − Vt mξsat L

I dsat ≈ Wvsat Coxe (Vgs − Vt )

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• Ids ∝ (Vgs-Vt)2 Ids ∝ Vgs-Vt DITS

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• Drain current equation becomes (VGS>VT),

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• Good enough for Digital

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• This is valid for all Vgs and Vds.

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• Total inversion charge

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S Rin = Rg −electrode + Rii

Gate-electrode resistance Intrinsic input resistance

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ρ : resistivity of gate material,

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