Jess Totorica

ECE 311
Section 52
1 November 2018
Lab 8: MOSFET Amplifier Biasing and Design
Objective
The goal of this lab was to design and simulate three MOSFET amplifier topologies
which include a common-source amplifier, a common gate amplifier, and a common-drain
amplifier. Another objective of this lab also included physically constructing the common-source
amplifier using discrete components and then measuring and quantifying its performance and
outputs.

Procedure
The first step in this lab was to design and simulate the following circuit shown in the
figure below.

Circuit 1. Common-Source Amplifier

In order to achieve the required 3mA current through the MOSFET (IDS), R2 and R1 must be set
to 6.78 kΩ and 3.22 kΩ respectively. Also, to achieve a VOUT(DC) of approximately 2.55 V the
resistor RD must be set to 817 Ω. The capacitors can be set to 10 pF (for all amplifiers), the load
resistor to 100kΩ and the voltage source to 5V. Once these components are set to the correct
values, the circuit can be simulated and evaluated. First simulate the circuit using a small signal
in order to evaluate the gain value of the amplifier. Once this is complete, the common drain
amplifier can be designed and simulated. This is constructed as follows.
 Circuit 2. Common-Drain Amplifier

To get the required 10mA current through the MOSFET as well as an output voltage of
approximately 2.41 V in this circuit, the resistors R1, R2, and RS must be set to 8.21 kΩ, 1.79 kΩ,
and 241 Ω respectively. Keeping the voltage source, load resistor, and capacitor values the same,
this circuit is ready to be simulated. Once again this must be done feeding a small signal into Vin
and observing the gain of Vout. After this is done the common gate circuit can be designed and
simulated. This is built like the following.

Circuit 3. Common-Gate Amplifier

The desired current IDS in this circuit is 3mA with a dc output voltage of approximately 2.7 V.
To achieve these values R1 and R2 must be set to 3.82 kΩ and 6.18 kΩ respectively. Also, the
drain and source resistors RD and RS must both be set to 100 Ω as well. When these components
are set to the correct value an AC simulation can be run using a small signal input voltage and
the gain of the amplifier can be observed. Once all circuits have been simulated and their
behaviors and parameters have been recorded, the next step is to physically construct the
Common-Source Amplifier shown in circuit 1 on a breadboard. For this process, instead of using
two resistors for R1 and R2, use a 10 kΩ trimmer in order to allow for easier adjustment. Do the
same for RD as well. After setting these close to the values used in simulation, connect the DC
voltage sources and begin to measure the current IDS as well as the output voltage Vout(DC). Using
these measurements, the trimmers can be adjusted until these values match the current of 3mA
and the DC output voltage of 2.55 V. Once these measurements reach the correct values, two
capacitors of 5.6 𝜇F or more can be placed at Vin and Vout nodes. Then a small alternating signal
at 50 kHz with a 10mV peak can be applied across Vin. Using this signal as reference, the output
signal must be observed in order to find the gain of the amplifier. Once this value is recorded,
measure and record the gain for approximately 20 points from 1kHz to 1MHz and produce a plot
of the gain AV versus the input signal frequency.

Calculations

Given parameter values of the MOSFET.

VTH =1.512 V, KPn=0.653 A/V2, 𝜆=.000195, 𝛽=.326

Common-Source Amplifier

Specified Biasing Values: IDS = 3 mA

2 𝐼 .003
𝐼𝐷𝑆 = 𝛽𝑉𝑂𝐷  𝑉𝑂𝐷 = √ 𝐷𝑆 = √  VOD = .0959 V
𝛽 .326

𝑉𝑂𝐷 = 𝑉𝐺𝑆 − 𝑉𝑇𝐻  𝑉𝐺𝑆 = 𝑉𝑂𝐷 + 𝑉𝑇𝐻 = .0959 + 1.512  VGS =VIN(DC) =1.608 V

𝑅
1 10000𝑉𝐼𝑁(𝐷𝐶)
𝑉𝐼𝑁(𝐷𝐶) = 5(10000)  𝑅1 = = 2000(1.608)  R1 = 3.22 kΩ
5
R2 = 6.78 kΩ
𝑉𝐴𝐴 +𝑉𝑂𝐷 5+.0959
𝑉𝑂𝑈𝑇(𝐷𝐶) = =  VOUT(DC)=2.547 V
2 2

𝑉𝐴𝐴 −𝑉𝑂𝑈𝑇(𝐷𝐶)
𝑉𝑂𝑈𝑇(𝐷𝐶) = 𝑉𝐴𝐴 − 𝐼𝐷𝑆 𝑅𝐷  𝑅𝐷 =  RD = 817.4 Ω
𝐼𝐷𝑆

Common Gate Amplifier

Specified Biasing Values: IDS = 3 mA, VIN(DC) = 300 mV

2 𝐼 .003
𝐼𝐷𝑆 = 𝛽𝑉𝑂𝐷  𝑉𝑂𝐷 = √ 𝐷𝑆 = √.326  VOD = .0959 V
𝛽

𝑉𝑂𝐷 = 𝑉𝐺𝑆 − 𝑉𝑇𝐻  𝑉𝐺𝑆 = 𝑉𝑂𝐷 + 𝑉𝑇𝐻 = .0959 + 1.512  VGS = 1.608 V
𝑉𝐺𝑆 = 𝑉𝐵𝐼𝐴𝑆 − 𝑉𝐼𝑁(𝐷𝐶)  𝑉𝐵𝐼𝐴𝑆 = 𝑉𝐺𝑆 + 𝑉𝐼𝑁(𝐷𝐶) = 1.608 + .3  VBIAS = 1.908 V

𝑉𝐴𝐴 𝑅1
𝑉𝐵𝐼𝐴𝑆 =  𝑅1 = 2000 𝑉𝐵𝐼𝐴𝑆  R1= 3.82 kΩ
10000
R2= 6.18 kΩ
𝑉𝐼𝑁(𝐷𝐶) +𝑉𝐴𝐴 +𝑉𝑂𝐷1 (.3+5+.0959)
𝑉𝑂𝑈𝑇(𝐷𝐶) = =  VOUT(DC) = 2.698 V
2 2

𝑉𝐴𝐴 −𝑉𝑂𝑈𝑇(𝐷𝐶)
𝑅𝐷 =  RD = 100 Ω
𝐼𝐷𝑆

𝑉𝐼𝑁(𝐷𝐶)
𝑅𝑆 =  RS = 100 Ω
𝐼𝐷𝑆

Common Drain Amplifier

Specified Biasing Values: 10 mA

2 𝐼 .01
𝐼𝐷𝑆 = 𝛽𝑉𝑂𝐷  𝑉𝑂𝐷 = √ 𝐷𝑆 = √.326  VOD = .1751 V
𝛽

𝑉𝐴𝐴 −𝑉𝑂𝐷 5−.1751

𝑉𝑂𝑈𝑇(𝐷𝐶) = =  VOUT(DC) = 2.412 V
2 2

𝑉𝑂𝑈𝑇(𝐷𝐶)
𝑅𝑆 =  RS = 241 Ω
𝐼𝐷𝑆

𝑉𝐼𝑁(𝐷𝐶) = 𝑉𝑂𝐷 + 𝐼𝐷𝑆 𝑅𝑆 + 𝑉𝑇𝐻 = .1751 + .01(241) + 1.512  VIN(DC) = 4.1 V

10000𝑉𝐼𝑁(𝐷𝐶)
𝑅1 =  R1 = 8.21 kΩ
𝑉𝐴𝐴
R2 = 1.79 kΩ

Results

Table 1. Measured vs Calculated Circuit Parameters

R1 (Ω) R2 (Ω) RL (Ω) Cin (𝜇F) Cout(𝜇F) IDS (mA) VOUT(DC)
Calculated 3.22 6.78 100 10 10 3 2.55
Value
Measured 4.47 6.45 98.3 10.7 11.4 3.07 2.43
Value

Table 2. Measured vs Simulated Circuit Biasing and Gain Values

VIN(DC) (V) VOUT(DC) (V) IDS (mA) Max. Voltage
Gain AV
Simulated Value 1.611 2.572 2.99 50.2
Measured Value 2.046 2.433 3.07 11
 Table 3. Measured Voltages and Gain at Different Frequencies
fin (kHz) (Vin)p (V) (Vout)p (V) AV (Gain)
1 0.01 0.1 10
2 0.01 0.105 10.5
4 0.01 0.11 11
7 0.01 0.11 11
10 0.01 0.11 11
20 0.01 0.11 11
40 0.01 0.11 11
70 0.01 0.11 11
100 0.01 0.105 10.5
200 0.01 0.095 9.5
400 0.01 0.09 9
700 0.01 0.075 7.5
1000 0.01 0.07 7
2000 0.01 0.05 5
4000 0.01 0.027 2.7
5000 0.01 0.015 1.5
6000 0.01 0.01 1
7000 0.01 0.01 1
10000 0.01 0.01 1

Graph 1. Voltage Gain vs. Input Frequency

AV vs Fin
12

10

8
Av

0
1 10 100 1000 10000
Fin(kHz)
Conclusion
While the circuit did produce a voltage gain, it did not meet the expectations predicted by
simulations. In the simulations I was able to find a maximum gain of 50.2, which is quite far
from the real measured gain of only 11. This puts the simulated value at a percent error of
356.3%. This huge error likely stemmed from a few sources. For one, this circuit is highly
subject to change due to small differences in biasing values, and it is difficult to set these at exact
values. For example, the IDS value was extremely sensitive, and 3.07 mA was the closest it could
get to 3 mA. Another issue is that the actual MOSFET used in lab has different parameters than
the simulated MOSFET. This can be noticed when looking at the measured and calculated
VIN(DC). In order to set the IDS near 3mA, the measured DC input voltage had to be set at 2.046 V,
while the calculated is only 1.611 V. This indicates that the threshold voltage of the MOSFET
used in lab may be significantly larger than the value used by the simulator. Thus, differences in
parameter values such as this may have also contributed to the large error margin. While the gain
values are largely different, the amplifier circuit did still follow similar behavior to the simulated
circuit. We can see in the gain vs input frequency that the measured gain follows a similar
pattern to the gain seen in the simulated AC response graph. In both graphs the gain reaches peak
value at around 1000Hz and then begins to decline again at around 100 kHz. All in all, the circuit
did not perform to expectations but did follow the patterns demonstrated in simulation.