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VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur – 603 203

DEPARTMENT OF
ELECTRICAL AND ELECTRONICS ENGINEERING

QUESTION BANK

III SEMESTER

EE8351 - DIGITAL LOGIC CIRCUITS

Regulation – 2017

Academic Year 2018-2019

Prepared by

Dr.G.UdhayaKumar, Associate Prof./EEE

Ms. P. Bency, Assistant Professor/EEE

Ms.K.Durgadevi, Assistant Professor /EEE

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VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur – 603 203.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

QUESTION BANK
SUBJECT : DIGITAL LOGIC CIRCUITS
SEM / YEAR: III/II

UNIT I - NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES

Review of number systems, binary codes, error detection and correction codes
(Parity and Hamming code) –Digital Logic Families- comparison of RTL, DTL,
TTL, ECL and MOS families-operation, characteristics of digital logic family.
PART – A
Q.No Questions BT Competence
Convert Level
(a) (475.25)8 to its decimal equivalent BTL1 Remember
1.
(b) (549.B4)16 to its binary equivalent
BTL 1 Remember
2. Define propagation delay.
3. BTL 2 Understand
Determine (377)10 in Octal and Hexa-Decimal equivalent.
4. Compare the totem-pole output with open-collector output? BTL 4 Analyze

5. Give examples for weighted codes. BTL 1 Remember

BTL 1 Remember
6. What is meant by non-weighted codes?
Convert 14316 into its binary and binary coded decimal BTL 1 Remember
7.
equivalent.
8. Convert 11510 and 23510 to hexadecimal numbers. BTL 2 Understand

List the factors used for measuring the performance of BTL 2 Understand
9.
digital logic families.
10. What is grey code and mention its advantages. BTL 1 Remember

Briefly explain the stream lined method of converting BTL 5 Evaluate

11.
binary to decimal number with example.
BTL 3 Apply
12. Give the Gray code for the binary number (111)2
13. When can RTL be used to represent digital systems? BTL 3 Apply

14. State the important characteristics of TTL family BTL 3 Apply

Analyze
Convert (a) 10010011101011012 BTL 4
15.
(b) 10010001011.001011102 to hexadecimal.
Summarize the advantages of ECL as compared to TTL BTL 2 Understand
16.
logic family.
Classify the basic families that belong to the bipolar BTL 5 Evaluatee
17.
families and to the MOS families.
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Which is faster TTL or ECL? Which requires more power BTL 6 Create
18.
to operate?
19. Define noise margin. BTL 1 Remember

Convert the following Excess 3 numbers into decimal

BTL 6 Create
20. numbers.
(a)1011 (b)1001 0011 0111

PART – B
(i)Perform the following addition using BCD and Excess-3 (7) BTL 3 Apply
addition (205+569)
1.
(ii)Encode the binary word 1011 into seven bit even parity (6)
BTL 6 Create
hamming code
(i)With circuit schematic, explain the operation of a two (8) BTL 4 Analyze
port TTL NAND gate with totem-pole output.
2.
(ii)Compare totem pole and open collector outputs. BTL 4
(5)
BTL 1
(i)Explain hamming code with an example. State its (7) BTL 5 Evaluate
advantage over parity codes.
3.
(ii)Design a TTL logic circuit for a 3 input NAND gate. BTL 5
(6)
4. Discuss about TTL parameters. (13) BTL 2 Understand
With neat sketch explain the circuit diagram of CMOS (13) BTL 1 Remember
5. (8) BTL 3 Apply
NOR gate.
6. Name and explain the characteristics of TTL family. (13) BTL 1 Evaluate
Remember
Explain the characteristics and implementation of the (4)
(5) BTL 5
4 Analyze
7. following digital logic families. (6)
(a) CMOS (b) ECL (c) TTL (3)
(i)Explain the classifications of binary codes. (7) BTL 5 Evaluate
8. (ii)Explain about error detection and correction codes (6) BTL 5 Evaluate

(i)Assume that the even parity hamming code is 0110011 is (7) BTL 4 Analyse
transmitted and that 0100011 is received. The receiver does BTL 1 Remember

not know what is transmitted. Determine the bit location

9. where error has occurred using received code.
(ii)Draw the MOS logic circuit for NOT gate and explain
its operation. (6) BTL 1 Remember

Write short notes on following: (13) BTL 4 Analyze

Remember
10.
(a)RTL (b) DTL (c) TTL and (d) ECL
Explain in detail about error detection and error correcting (13) BTL 3 Apply
11. codes. BTL 1

12. With neat sketch explain the operation of MOS family. (13) BTL 2 Understand
BTL 3

BTL 2
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(i)Perform the following addition using BCD and Excess-3 (7) BTL 3 Apply
addition (502+965)
13.
(ii) Encode the binary word 1001 into seven bit even parity (6)
BTL 6 Create
hamming code
(i)Design a odd parity hamming code generator and (7) BTL 2 Understand
detector for 4-bit data and explain their logic.
14.
(ii) Convert FACE16 into its binary, octal, and decimal (6)
equivalent.
PART – C
(i) Explain in detail the usage of hamming codes for error (12) BTL
BTL 4
4 Analyze
detection and error correction with an example considering
1. the data bits as 0101
(ii) Convert 23.62510 to octal(base 8) (3)
(i) Using 16’s complement method design the subtraction (8) BTL 5 Evaluate
procedure and find C1416 from 69B16
2.
(ii) Using 2’s complement method design the subtraction (7) BTL 5
procedure and find 110001 from 100101
(i) Explain with an aid of circuit diagram the operation of
2 input CMOS NAND gate and list out its advantages over (12)
3. other logic families.
BTL 5 Evaluate
(ii) Given the 2 binary numbers X=1010100 and (3)
Y=1000011 perform the subtraction Y-X by using 2’s
complements
Design a CMOS inverter and explain its operation.
4. Comment on its characteristics such as Fan-in, Fan-out
power dissipation, propagation delay and noise margin.
Compare its advantages over other logic families. (15) BTL 4 Analyse

UNIT II - COMBINATIONAL CIRCUITS

Combinational logic- representation of logic functions- SOP and POS forms, K-

map representations- minimization using K maps- simplification and
implementation of combinational logic- multiplexers and de multiplexers- code
converters, adders, subtractors, Encoders and Decoders.
PART – A
Q.No Questions BT Competence
Convert the given expression in canonical SOP form BTL
Level4 Remember
1. Y=A’C+AB+BC’
2. Simplify the expression Z=AB’+AB.(A’C’)’ BTL 3 Apply
Given F=B’+A’B+A’C’ : Identify the redundant term using BTL 4 Analyze
3. K- map
4. Simplify : xy+x’z+yz BTL 3 Apply
Judge that (a) a+a’b=a+b; (b) x’y’z+x’yz+xy’=x’z+xy’ BTL 6 Create
5.
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Write the POS form of the SOP expression f(x,y,z) = x’yz + BTL 6 Create
6. xyz’ + xy’z.
Draw the circuit of the function F=∑(0,6) with NAND BTL 4 Analyze
7. gates
How does don’t care condition in K-map help for circuit BTL 5 Evaluate
8.
simplification?
9. What are the basic digital logic gates? BTL 1 Remember

10. What is a Logic gate? BTL 1 Remember

11. Define combinational logic BTL 1 Remember

What is a karnaugh map? Interpret the limitations of BTL 2 Understand
12. karnaugh map.
13. Construct OR gate using only NAND gates. BTL 3 Apply

14. What is meant by priority encoder? BTL 2 Understand

15. Draw the logic diagram of a half adder. BTL 1 Remember

16. Draw the truth table of 2:1 MUX BTL 5 Evaluate

17. Define multiplexer. BTL 1 Remember

18. What is the difference between decoder and demultiplexer? BTL 2 Understand

19. Why is MUX called as data selector? BTL 2 Understand

20. Design a half subtractor. BTL 1 Remember

PART – B
(i) Explain briefly about SOP and POS forms with (7) BTL 6 Create
example.
(6) BTL 3
1. (ii) Plot the logical expression ABCD + AB’ C’ D’ + AB’C + Apply
AB on a 4 variable K-map. Obtain the simplified
expression from the map.
(i)Reduce the following function using K-map (7) BTL 1 Remember
f(A,B,C,D)=ΠM(0,2,3,8,9,12,13,15)
2. (ii) Minimize the function F(a,b,c,d)=∑(0,4,6,8,9,10,12)
with d=∑(2,13). Implement the function using only NOR BTL 4
(6) Analyze
gates.
With the use of Maps, Find the simplest form in SOP of the (13) BTL 2
function F=f.g, where f and g are given by Understand
3. f = wxy’+y’z+w’yz’+x’yz’
g= (w+x+y’+z’)(x’+y’+z)(w’+y+z’)
(i)Prove that F=A’.B+A.B’ is exclusive OR operation and (7) BTL 1 Remember
it equals = (((A.B)’.A)’.((A.B)’.B)’)’
4. (ii) Prove that for constructing XOR from NANDs we need BTL 1 Remember
(6)
four NAND GATES
(i) State and prove De-Morgan’s theorem (4) BTL1 Remember
(ii) Simplify the following Boolean expression using K-
5. map f (x,y,z)=x y’z’+xyz+xyz’+x y’ z+xyz’ (9) BTL 1 Remember
f(A,B,C,D)=∑(0,1,5,6,7,10,12,14)+∑(3,9)
Reduce the Boolean function using k-map technique and (13) BTL 2
6. implement using gates f(w,x,y,z)= ∑m(0,1,4,8,9,10) which Understand
has the don’t cares condition d(w,x,y,z)= ∑m(2,11).

BTL 3
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(i)Express the function F=A+B C in Canonical SOP form (7) BTL 4 Analyse
& Canonical POS form
7. (ii) Simplify using K map F(A,B,C,D)=
(6) BTL 2 Understand
∑m(7,8,9)+d(10,11,12,13,14,15)
(i)Express the function Y = A+B’ C in canonical SOP and (7) BTL 3 Apply

8. canonical POS form.

(ii) Design BCD to Excess 3 code converter. (6) BTL 5
Evaluate
(i) Implement the following Boolean function using 8:1 (7) BTL 1 Remember
Mux: F(A,B,C,D)=∑m(0,1,3,4,8,9,15)
9. (6) BTL 6 Create
(ii)Design a full subtractor using half subtractors.

(i) Design a full adder using NOR gates BTL 1 Remember

10. (ii)Design a 3*8 decoder and explain its operation as a (7)
(6) BTL 1 Remember
minterm generator.
(i) Explain about combinational logic (7) BTL 4 Analyse
11. (ii) Design a 3 bit magnitude comparator using gates (6) BTL 4

(i) Draw the logic diagram of a 4 bit carry look ahead adder Apply
and explain how this adder is advantageous over the (8) BTL
BTL 4
3 Analyse
12. ripple carry adder
(ii) Explain with the suitable example how a multiplexer is (5) BTL 4
used to implement the Boolean function
(i) Write the step by step procedure for converting SOP and (7) BTL 3 Apply
POS to standard SOP and POS forms. (6) BTL 3
13.
(ii) Design a 4-bit Binary to Gray code converter and
implement it using logic gates.
(i) Design a full subtractor and implement it using logic (7) BTL 4 Analyze
gates.
14. BTL 6 Create
(ii) Design a full adder using two half adders and an OR (6)
gate.
PART – C
(i) Implement using NOR gates Y=(AB+C’)D+EF (8) BTL 5 Evaluate
1. (ii) Reduce and design the following function using K- (7) BTL 4 Analyze
map f(A,B,C,D)= ΠM(0,3,4,7,8,10,12,14)+d(2,6)

2. Simplify the logical expression using K-map in SOP and (15) BTL 5 Evaluate
POS forms F(A,B,C,D)= ∑m(0,2,3,6,7)+d(8,10,11,15)
(i) Reduce the following minterms using K-Map. (7) BTL 6 Create
3. F(w,x,y,z) = ∑m (0,1,3,5,6,7,8,12,14) + ∑d (9,15).
(ii)Implement the following function using suitable
multiplexer. F(a,b,c) = ∑m(3,7,4,5). (6)

4. Design a full adder using 4X1 multiplexer; also write its (15) BTL 6 Create
truth table and logical diagram.

BTL 4
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UNIT III - SYNCHRONOUS SEQUENTIAL CIRCUITS
Sequential logic-SR, JK, D and T flip flops- level triggering and edge triggering
- counters- asynchronous and synchronous type-Modulo counters –Shift
registers- design of synchronous sequential circuits – Moore and Melay models -
Counters, state diagram; state reduction; state assignment.
PART – A
Q.No Questions BT Competence
1. Convert T Flip Flop to D Flip Flop. BTL
Level4 Analyze
2. State the rules for state assignment. BTL 1 Remember

3. What is state assignment problem? BTL 1 Remember

4. What are the benefits of state reduction? BTL 1 Remember

Show how the JK flip-flop can be modified into a D flip- BTL 3 Apply
5.
flop or a T flip-flop
6. Differentiate Mealy and Moore models. BTL 4 Analyse
What are the disadvantages of asynchronous sequential BTL 1 Remember
7. circuit?
Give the characteristic equation and state diagram of JK BTL 2 Understand
8. flip-flop.
9. What is a self-starting counter? BTL 4 Analyze

10. Compare combinational and sequential circuits BTL 5 Evaluate

11. Examine the drawback of RS flip-flop? BTL 3 Apply

12. Implement T flip-flop using JK flip-flop. BTL 3 Apply

13. What is a preset table counter and ripple counter? BTL 1 Remember

14. Interpret the drawback of SR flip-flop? BTL 2 Understand

15. What is synchronous sequential circuit? BTL 1 Remember

16. What is meant by state assignment? BTL 6 Create

17. Define truth table for JK flip-flop. BTL 2 Understand

Give the characteristic equation and characteristic table of T BTL 5 Evaluate
18.
flip flop.
19. What is race around condition in flip-flops? BTL 2 Understand
BTL 6 Create
20. Design the excitation table for JK flip-flop.
PART – B
Design a counter for the following state diagram (13)

BTL 6 Create
1.

Estimate a sequential circuit for the following state (13) BTL 2

Understand
2. equations A(t+1)= C⊕D; B(t+1) = A; C(t+1) = B;
D(t+1)=C.
BTL 4
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BTL 2
Explain the operation, state diagram and characteristics of T (13) Understand
3.
flip flop and master slave JK flip flop.
(7) BTL 4
(i)Draw the logic diagram of 4-bit synchronous counter. (4) BTL 2
Explain the operation of the counter using the timing Analyze
4.
diagram
(ii)Explain the universal shift register in detail (6) BTL 4

(7) BTL 1
(i) Construct a JK flip-flop using a JK flip-flop, a 2*1 MUX
and an inverter.
Remember
(ii) A sequential circuit has two JK flip-flop A and B, two (6) BTL 1
5. inputs x and y, and one output z. the equations are
JA=Bx+B’y’; KA= B’xy’ Remember
JB= A’x; KB=A+xy’
Z=Ax’y’+Bx’y.
Draw the logic diagram and state table.
(i) Estimate a sequential circuit with two D-flip-flops A and (7) BTL 2
B and one output x. When x=0, the state of the circuit goes
through the state transitions from 00 01 11 10 00 Understand
6.
and repeats.
(6) BTL 2
(ii) Estimate mod 7 counter using D flip-flops.
A sequential circuit has two JK flip-flops A and B. The flip-
flop input functions are:
JA=B; JB=x
(4) BTL 1 Remember
7. KA= B x ; KB=A⊕x
(i)Draw the logic diagram of the circuit BTL 1
(ii)Tabulate the state table (6)
(iii)Draw the state diagram (3) BTL 1
8. Using JK flip-flops, design a synchronous counter which (13) BTL 5 Evaluate
8. counts in the sequence ,
000,001,010,011,100,101,110,111,000
Construct reduced state diagram for the following state (13)
diagram.

BTL 3 Apply
9.

10. Design a 3 bit binary counter using T flip-flop. (13) BTL 3 Apply

BTL 4
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Using partitioning minimization procedure reduce the (13)
following state table:
BTL 2
PRESENT NEXT STATE OUTPUT
STATE
W=0 W=1 Z

A B C 1 Understand
11.
B D F 1

C F E 0

E F C 0

F E D 0

12. G
Differentiate F
asynchronous andGsynchronous type
0 counters. (13) BTL 2 Understand

(i)Draw and explain the operation of Master-Slave JK (7) BTL 4

Create
13. flipflop (6)
(ii)Design a 5-bit ring counter and mention its applications.
14. Illustrate about 4-bit BCD ripple counters. (13) BTL 4 Analyze
PART – C
(6) BTL 2
1. What is meant by race-around condition? Discuss in detail (15) BTL 5 Evaluate
about master and slave JK flipflop
Design a sequential circuit using T-flip-flop. The state table (15)
of the circuit is as given below.
PRESENT NEXT STATE OUTPUT BTL 4
STATE x=0 x=1 x=0 x=1
a f b 0 0 BTL 6 Create
2. b d c 0 0
c f e 0 0
d g a 1 0
e d c 0 0
f f b 1 1
g g h 0 1
h g a 1 0
(15) BTL 4 Analyse
3. Explain in detail about different shift registers.

(i) Explain the realisation of JK flipflop from T flipflop (15) BTL 6

4. Create
(ii)Write short notes on SIPO and draw the output
waveforms.
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UNIT IV - ASYNCHRONOUS SYNCHRONOUS SEQUENTIAL CIRCUITS AND
PROGRAMMABLE LOGIC DEVICES
Asynchronous sequential logic circuits- Transition tablity, flow tablility-race conditions,
hazards & errors in digital circuits; analysis of asynchronous sequential logic circuits-
introduction to Programmablility Logic Devices: PROM–PLA–PAL,CPLD-FPGA.
PART - A
Q.No Questions BT Competence
Level

1. Define racing BTL-1 Remember

2. What is critical race? BTL-1 Remember

3. What is meant by transition table? BTL-1 Remember

4. Estimate the types of hazards BTL-5 Evaluate

5. What is the difference between flow table and transition BTL-4 Analyze
table?

6. Define races in Asynchronous sequential circuit. BTL-1 Remember

7. Predict the hazards in asynchronous sequential circuits? BTL-2 Understand

8. Show what is fundamental mode of operation in BTL-3 Apply

asynchronous sequential circuits?

9. What is static hazard and dynamic hazard? BTL-4 Analyze

10. Define asynchronous sequential machine. BTL-1 Remember

11. Predict what is a PROM? BTL-5 Evaluate

12. State the difference between static 0 and static 1 hazard BTL-2 Understand

13. Compose about secondary variable and excitation BTL-6 Create

variables.

14. Compare critical race and non critical race. BTL-3 Apply

15. What is flow table? Give example. BTL-6 Create

16. What is a deadlock condition? BTL-1 Remember

17. Deduce the demerits in designing asynchronous sequential BTL-2 Understand

machines.

18. State the difference between PROM, PAL, PLA and BTL-3 Apply
EPROM.
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19. What is a PLA? BTL-2 Understand

20. Point out the definition for flow table in asynchronous BTL-4 Analyze
sequential circuit.

PART B
1. Design an asynchronous sequential circuit has two (13) BTL-6 Create
inputs X2 and X1 and one output Z. When X1=0, the
output Z is 0. The first change in X2 that occurs while
X1 is 1 will cause output Z to be 1. The output Z will
remain 1 until X1 returns to 0.
2. (i) Implement the following function using PLA: (7) BTL-5 Evaluate
F(x,y,z) = ∑m(1,2,4,6)
(ii) For the given Boolean function, obtain the hazard-free
circuit. (6)
F(A,B,C,D)=∑m(1,3,6,7,13,15)
3. (i) Obtain the PLA program table for a combinational (7) BTL-1 Remember
circuit that squares a 3 bit number. Minimize the number
of product terms.
(ii) A combinational circuit is defined by the functions.
(6) BTL-2 Understand
(a) F1(a,b,c)= ∑m(3,5,6,7)
(b) F2(a,b,c)= ∑m(0,2,4,5,7)
4. Explain the various types of hazards in sequential (13) BTL-4 Analyze
circuit design and the methods to eliminate them. Give
suitable examples.

5. Describe with reasons, the effect of races in (13) BTL-2 Understan

asynchronous sequential circuit design. Explain its types d
with illustrations. Show the method of race-free state
assignments with examples.

6. (i)Discover asynchronous BCD counter using JK flip- (7) BTL-1 Remembe

flops. r
(ii) An asynchronous sequential circuit is described by
Y=x1x’2+(x1 + x’2) y; z=y. Draw the logic diagram, (6) BTL-4
transition table and output map. Analyze

7. (i) Find a circuit that has no static hazards and implement (7) BTL-2 Understan
Boolean function d
F(A,B,C,D)= ∑(0,2,6,7,8,10,12)

(ii) Explain the different types of programmable logic (6) BTL-4

devices with neat sketch and compare them. Analyze

8. Derive the transition table and primitive flow table for the (13) BTL-2 Understan
functional mode asynchronous sequential circuit shown in d
fig
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9. Implement the following function in PLA (7) BTL-3 Apply

(i) F1=∑m(1,2,4,6); F2= ∑m(0,1,6,7); F3=∑m(2,6)

(ii) F1=∑m(3,5,8,9); F2= ∑m(2,3,5,8,); F3=∑m(0,1) (6)

10. (i) Illustrate the following logic and analyse for the (7) BTL-4 Analyze
pressure of any hazard f=x1x2+x’1x3. If hazard is present
briefly explain the type of hazard and design a hazard-free
circuit.
(ii) Illustrate the following function in PLA
(6)
f1(x,y,z) = ∑m(0,1,3,5,7)
f2(x,y,z) = ∑m(2,4,6)
11. Discover an asynchronous sequential circuit with 2 (13) BTL-1 Remember
inputs T and C. The output attains a value of 1 when T=1
& C moves from 1 to 0. Otherwise the output is 0.
12. Discover an asynchronous BCD counter. (13) BTL-1 Remember

13. Describe the steps involved in design of asynchronous (13) BTL-3 Apply
sequential circuit in detail with an example.

14. (i) How do you get output specifications (4) BTL-1 Remember
from a flow table in asynchronous sequential
circuit operating in fundamental mode?

(ii) When do you get the critical and non- BTL-1 Remember
critical races? How will you obtain race free (9)
conditions?

PART C
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1. (i) Design a PLA structure using AND and OR logic for the (12) BTL-6 Create
following function.
F1=∑m(0,1,2,3,4,7,8,11,12,15)
F2=∑m(2,3,6,7,8,9,12,13)
F3=∑(1,3,7,8,11,12,15)
F4=∑(0,1,4,8,11,12,15) (3) BTL-2
(ii) Compare PLA and PAL Circuits Understand

2. A combinational circuit is defined by the functions (15) BTL-6 Create

F1=∑m(3,5,6,7) and F2=∑m(0,2,4,7). Implement the circuit
with PLA and PAL design.

3. Design an asynchronous circuit that has two inputs x1 and (15) BTL-6 Create
x2 and one output z. the circuit is required to give an output
whenever the input sequence (0,0),(0,1) and (1,1) received
but only in that order.

4. An asynchronous sequential circuit is described by the BTL-4 Analyze

following excitation and the output function
Y=x1x2+(x1+x2)y.
(4)
(i) Draw the logic diagram of the circuit.
(8)
(ii) Derive the transition table and output map.
(iii) Describe the behaviour of the circuit. (3)
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UNIT V - VHDL
RTL Design –combinational logic –Sequential circuit –Operators –Introduction to Packages –
Subprograms– Test bench. (Simulation/Tutorial Examples: adders, counters, flip flops,
Multiplexers & De multiplexers).
PART - A
Q.No Questions BT Competence
1. What is a package in VHDL? Level
BTL-1 Remember

2. Write the VHDL behavioural model for D-flip-flop. BTL-1 Remember

3. Write the VHDL code for a logical gate which gives high output BTL-1 Remember
only when both the inputs are high.
4. Name any four hardware description language test benches. BTL-1 Remember

5. Give the syntax for package declaration and package body in BTL-1 Remember
VHDL
6. Write VHDL code for 2*1 MUX using behavioural modeling BTL-1 Remember

7. Deduce what is test bench? BTL-4 Analyze

8. Compose the operators used in VHDL BTL-6 Create

9. Compile VHDL code for half adder in data flow model. BTL-6 Create

10. Analyze the merits of hardware languages. BTL-5 Evaluate

11. What is the function of wait statement in VHDL package? BTL-2 Understand

12. Predict the need for VHDL. BTL-4 Analyze

13. Prepare the VHDL code for AND gate. BTL-5 Evaluate

14. Give the test bench for AND gate. BTL-2 Understand

15. Show the meaning of the following RTL statement? BTL-3 Apply

16. Categorize different test bench. BTL-4 Analyze

17. What is subprogram overloading? BTL-2 Understand

18. Expand the following acronyms. (a)VHDL (b)VHLSI BTL-3 Apply

19. What are the languages that are combined together to get VHDL BTL-3 Apply
language?
20. Write the VHDL code for full subtractor in data flow model. BTL-2 Understand

PART - B
1. Write the VHDL code to realize a full adder using (i) Behavioral (7+6) BTL-1 Remembe
modeling. (ii) Structural modeling. r
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2. Write the VHDL code to realize a 3-bit gray code counter using (13) BTL-1 Remembe
case statement. r

3. Write VHDL code for Binary UP/ DOWN counter using JK flip- (13) BTL-1 Remembe
flops. r

4. Design a 3 bit magnitude comparator and write the VHDL coding (13) BTL-2 Understan
to realize it using structural modelling. d

5. (i)Explain the digital system design flow sequence with the help (7) BTL-4 Analyze
of a flow chart.
Analyze
(ii) Estimate a VHDL code for a 4 bit universal shift register. (6) BTL-4
6. Explain in detail the concept of Structural modelling in VHDL (13) BTL-5 Evaluate
with an example of full adder.
7. (i) Explain in detail the various programming constructs used in (7) BTL-4 Analyze
VHDL for designing a logic circuit.
(ii) Discuss the various packages. Write a VHDL code for the (6) BTL-4 Analyze
implementation of decoder/de-multiplexer.

8. (i) Write VHDL code for4 bit synchronous UP/DOWN counter (8) BTL-1 Remember
and explain.

ii) Write short notes on subprograms used for implementation of Remember

(5) BTL-1
adders.
9. Design a VHDL code for full adder and 8*1 MUX (13) BTL-6 Create

10. Illustrate the VHDL code for JK master slave flip-flops and (5+8) BTL-4 Analyze
using JK FF as structural elements write code for 4 bit
asynchronous counter.

11. Interpret the structural VHDL description for a 2 to 4 decoder in (13) BTL-3 Apply
detail.
12. Discover a VHDL code for 6 bit comparator and also explain the (13) BTL-2 Understan
design procedure. d

13. Discover a VHDL code for 4 bit binary counter with parallel load (13) Understan
and explain. BTL-2 d

14. (i)Explain the design procedure of RTL using VHDL. (8) BTL-3 Apply

(ii)Write a note on VHDL test benches. (5) BTL-3 Apply

PART - C

1. Design a 4 X 4 array multiplier and write the VHDL coding to (15) BTL-6 Create
realize it using structural modelling.

2. (i) Discover the VHDL code for 3 to 8 decoder. (8) BTL-6 Create
(ii) Discover the VHDL code for 4:1 multiplexer. (7)
 www.rejinpaul.com
3. (i) Discuss briefly the packages in VHDL (7) BTL-5 Evaluate
(ii) Write an VHDL coding for realization of clocked S-R flip
flop. (8)
4. i) Write short notes on built-in operators used in VHDL (7) BTL-3 Apply
programming.
ii) Write VHDL coding for 4 X 1 Multiplexer (8)