LM5071 Power Over Ethernet PD Controller with Auxiliary Power Interface

April 2006

LM5071
Power Over Ethernet PD Controller with Auxiliary Power
Interface
General Description n Detection Resistor Disconnect Function
n Programmable Classification Current
The LM5071 power interface port and pulse width modula-
n Programmable Under-voltage Lockout with
tion (PWM) controller provides a complete integrated solu-
Programmable Hysteresis
tion for Powered Devices (PD) that connect into Power over
Ethernet (PoE) systems. The LM5071 is specifically de- n Thermal Shutdown Protection
signed for the PD that must accept power from auxiliary n Auxiliary Power Enable Pin
sources such as ac adapters. The auxiliary power inter- n Current Mode Pulse Width Modulator
face of the LM5071 activates the PWM controller when the n Supports both Isolated and Non-Isolated Applications
ac adapter is connected to power the PD when PoE network n Error Amplifier and Reference for Non-Isolated
power is unavailable. The LM5071 integrates an 80V, Applications
400mA line connection switch and associated control for a n Programmable Oscillator Frequency
fully IEEE 802.3af compliant interface with a full featured n Programmable Soft-start
current mode pulse width modulator dc-dc converter. All
n 80% Maximum Duty Cycle Limiter, Slope Compensation
power sequencing requirements between the controller in-
(-80 device)
terface and switch mode power supply (SMPS) are inte-
n 50% Maximum Duty Cycle Limiter, No Slope
grated into the IC.
Compensation (-50 device)

Features Packages
n Compatible with 12V ac adapters
n TSSOP-16
n Fully Compliant 802.3af Power Interface Port
n 80V, 1Ω, 400 mA Internal MOSFET

Block Diagram

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© 2006 National Semiconductor Corporation DS201684 www.national.com

LM5071
Block Diagram (Continued)

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FIGURE 1. Simplified Block Diagram

Connection Diagram

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16 Lead TSSOP

Ordering Information
NSC Package Type /
Order Number Description Drawing Supplied As
LM5071MT-50 50% Duty Cycle Limit TSSOP-16/MTC-16 92 units per rail
LM5071MTX-50 50% Duty Cycle Limit TSSOP-16/MTC-16 2500 units on tape and reel
LM5071MT-80 80% Duty Cycle Limit TSSOP-16/MTC-16 92 units per rail
LM5071MTX-80 80% Duty Cycle Limit TSSOP-16/MTC-16 2500 units on tape and reel

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 LM5071
Pin Descriptions
Pin Name Description Application Information
1 VIN System high potential input. The diode “OR” of several lines entering the PD, it is the more
positive input potential.
2 RSIG Signature resistor pin. Connect a resistor from VIN to this pin for signature detection. The
resistor is in parallel with the UVLO resistors and should be valued
accordingly.
3 RCLASS Classification resistor pin. Connect the classification programming resistor from this pin to VEE.
4 AUX Auxiliary input power startup pin. A resistor divider between the AUX voltage input to VEE programs
the startup levels with a 2.5V threshold. A high value ( > 300kΩ)
internal pull down resistor is present to pull the pin low if it is left
open. In practice, the divider voltage should be set well above 2.5V
by the programming resistors.
5 UVLO Line under-voltage lockout. An external resistor divider from VIN to UVLORTN programs the
shutdown levels with a 2.00V threshold at the UVLO pin. Hysteresis
is set by a switched internal 10uA current source that forces
additional current into the resistor divider.
6 UVLORTN Return for the external UVLO resistors. Connect the bottom resistor of the resistor divider between the
UVLO pin and this pin.
7 VEE System low potential input. Diode “OR’d” to the RJ45 connector and PSE’s –48V supply, it is
the more negative input potential.
8 RTN System return for the PWM converter. The drain of the internal current limiting power MOSFET which
connects VEE to the return path of the dc-dc converter.
9 OUT Output of the PWM controller. DC-DC converter gate driver output with 800mA peak sink current
capability.
10 VCC Output of the internal high voltage When the auxiliary transformer winding (if used) raises the voltage
series pass regulator. Regulated output on this pin above the regulation set point, the internal series pass
voltage is nominally 7.8V. regulator will shutdown, reducing the controller power dissipation.
11 FB Feedback signal. Inverting input of the internal error amplifier. The non-inverting input
is internally connected to a 1.25V reference.
12 COMP The output of the error amplifier and COMP pull-up is provided by an internal 5K resistor which may be
input to the Pulse Width Modulator. used to bias an opto-coupler transistor.
13 CS Current sense input. Current sense input for current mode control and over-current
protection. Current limiting is accomplished using a dedicated
current sense comparator. If the CS pin voltage exceeds 0.5V the
OUT pin switches low for cycle-by-cycle current limiting. CS is held
low for 50ns after OUT switches high to blank leading edge current
spikes.
14 RT / SYNC Oscillator timing resistor pin and An external resistor connected from RT to ARTN sets the oscillator
synchronization input. frequency. This pin will also accept narrow ac-coupled
synchronization pulses from an external clock.
15 SS Soft-start input. An external capacitor and an internal 10uA current source set the
soft-start ramp rate.
16 ARTN Analog PWM supply return. RTN for sensitive analog circuitry including the SMPS current limit
amplifier.

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LM5071
Absolute Maximum Ratings (Note 1) ESD Rating
If Military/Aerospace specified devices are required, Human Body Model 2000V
please contact the National Semiconductor Sales Office/ Lead Temperature (Note 2)
Distributors for availability and specifications. Wave (4 seconds) 260˚C
VIN ,RTN to VEE -0.3V to 80V Infrared (10 seconds) 240˚C
RSIG to VIN -12V to 0V Vapor Phase (75 seconds) 219˚C
AUX to VEE -0.3V to 57V
UVLO to VEE -0.3V to 13V Operating Ratings
RCLASS to VEE -0.3V to 7V
VIN voltage 1.8V to 60V
ARTN to RTN -0.3V to 0.3V
External voltage applied to VCC 8.1V to 15V
VCC, OUT to ARTN -0.3V to 16V
Operating Junction Temperature -40˚C to 125˚C
All other inputs to ARTN -0.3V to 7V

Electrical Characteristics (Note 3)

Specifications in standard type face are for TJ = +25˚C and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified: VIN = 48V, VCC = 10V, RT = 30.3kΩ.
Symbol Parameter Conditions Min Typ Max Units
Powered Interface
IOS Offset Current VIN < 10.0V 10 uA
VCLSS(ON) Signature Resistor Disable / VIN with respect to VEE 10.0 11.5 12.5 V
Classification Current Turn On
VCLSS(OFF) Classification Current Turn Off VIN with respect to VEE 23.5 25.0 26.5 V
Classification Voltage With respect to VEE 1.43 1.5 1.57 V
ICLASS Supply Current During VIN =17V 0.5 1.0 mA
Classification
IDC Supply Current During Normal OUT floating 1 1.9 mA
Operation
UVLO Pin Reference Voltage VIN > 27V 1.95 2.00 2.05 V
UVLO Hysteresis Current VIN > UVLO 8.0 10 11.5 uA
Softstart Release RTN falling with respect to VEE 1.2 1.45 1.7 V
Softstart Release Hysteresis RTN rising with respect to VEE 0.8 1.1 1.3 V
RDS(ON) PowerFET Resistance I = 350mA, 1 2.2 Ω
VIN = 48V
ILEAK SMPS Bias Current VEE = 0V, VIN = RTN = 57V 100 uA
AUX Pin Threshold AUX pin rising with respect to 2.4 2.5 2.65 V
VEE
AUX Pin Threshold Hysteresis AUX pin falling with respect to 0.4 0.5 0.6 V
VEE
ZAUX AUX Pin Input Impedance AUX = 0.5V 350 kΩ
IINRUSH Inrush Current Limit VEE = 0V, RTN = 3.0V 70 100 130 mA
ILIM DC Current Limit VEE = 0V, RTN = 3.0V, 350 390 420 mA
Temp = 0˚C to 85˚C
ILIM DC Current Limit VEE = 0V, RTN = 3.0V, 325 390 420 mA
Temp = -40˚C to 125˚C
Startup Regulator
VinMin Operational VIN Input Voltage AUX = 5V, Vcc = Vin (Note 6) 9.5 V
VccReg VCC Regulation Open ckt 7.5 7.8 8.1 V
VCC Current Limit (Note 4) 15 20 mA

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 LM5071
Electrical Characteristics (Note 3) (Continued)
Specifications in standard type face are for TJ = +25˚C and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified: VIN = 48V, VCC = 10V, RT = 30.3kΩ.
Symbol Parameter Conditions Min Typ Max Units
VCC Supply
VCC UVLO (Rising) VccReg VccReg –
– 100mV
300mV
VCC UVLO (Falling) 5.9 6.25 6.6 V
Supply Current (Icc) Cload = 0 1.5 3 mA
Error Amplifier
GBW Gain Bandwidth 4 MHz
DC Gain 75 dB
Input Voltage FB = COMP 1.219 1.281 V
1.212 1.288
COMP Sink Capability FB=1.5V COMP=1V 5 20 mA
Current Limit
ILIM Delay to Output CS step from 0 to 0.6V, time to 20 ns
onset of OUT transition (90%)
Cycle by Cycle Current Limit 0.44 0.5 0.56 V
Threshold Voltage
Leading Edge Blanking Time 55 ns
CS Sink Impedance (clocked) 25 55 Ω
Softstart
Softstart Current Source 7 10 13 uA
Oscillator(Note 5)
Frequency1 175 200 225 KHz
(RT = 30.3K)
Frequency2 505 580 665 KHz
(RT = 10.5K)
Sync threshold 3.1 3.8 V
PWM Comparator
Delay to Output COMP set to 2V 25 ns
CS stepped 0 to 0.4V, time to
onset of OUT transition low
Min Duty Cycle COMP=0V 0 %
Max Duty Cycle (-80 Device) 80 %
Max Duty Cycle (-50 Device) 50 %
COMP to PWM Comparator 0.33
Gain
COMP Open Circuit Voltage 4.5 5.4 6.3 V
COMP Short Circuit Current COMP= 0V 0.6 1.1 1.5 mA
Slope Compensation
Slope Comp Amplitude Delta increase at PWM 105 mV
(LM5071-80 Device Only) Comparator to CS
Output Section
Output High Saturation Iout = 50mA, 0.25 0.75 V
VCC - VOUT
Output Low Saturation Iout = 100mA 0.25 0.75 V
Rise time Cload = 1nF 15 ns
Fall time Cload = 1nF 15 ns

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LM5071
Electrical Characteristics (Note 3) (Continued)
Specifications in standard type face are for TJ = +25˚C and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified: VIN = 48V, VCC = 10V, RT = 30.3kΩ.
Symbol Parameter Conditions Min Typ Max Units
Thermal Shutdown
Tsd Thermal Shutdown Temp. 165 ˚C
Thermal Shutdown 25 ˚C
Hysteresis
Thermal Resistance
θJA Junction to Ambient MT Package 125 ˚C/W

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. The absolute maximum rating of VIN, RTN to VEE
is derated to (-0.3V to 76V) at -40˚C.
Note 2: For detailed information on soldering the plastic TSSOP package, refer to the Packaging Databook available from National Semiconductor.
Note 3: Min and Max limits are 100% production tested at 25 ˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 4: Device thermal limitations may limit usable range.
Note 5: Specification applies to the oscillator frequency. The operational frequency of the LM5071-50 devices is divided by two.
Note 6: The Vcc regulator requires an external source whenever the Vin pin is below 13V with respect to RTN. An external load on Vcc increases this startup voltage
requirement.

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 LM5071
Typical Performance Characteristics
Default Current Limit vs Temperature Oscillator Frequency vs RT Resistance

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UVLO Hysteresis Current vs Temperature Softstart Current vs Temperature

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Oscillator Frequency vs Temperature

Error Amp Input Voltage vs temperature RT = 15.2 kΩ

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LM5071
Typical Performance Characteristics (Continued)

VCC vs ICC Input Current vs Input Voltage

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UVLO Threshold vs Temperature

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 LM5071
Specialized Block Diagrams

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FIGURE 2. Top Level Block Diagram

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FIGURE 3. PWM Controller Block Diagram

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LM5071
Detailed Operating Description age, the internal power MOSFET is enabled to deliver a
constant current to charge the input capacitor of the dc-dc
The LM5071 power interface port and pulse width modula- converter. When the MOSFET Vds voltage falls below 1.5V,
tion (PWM) controller provides a complete integrated solu- the internal Power Good signal enables the SMPS controller.
tion for Powered Devices (PD) that connect into Power over The LM5071 is specified to operate with an input voltage as
Ethernet (PoE) systems. Major features of the PD interface high as 60.0V. The SMPS controller and internal MOSFET
portion of the IC include detection, classification, thermal are disabled when VIN falls to the lower UVLO threshold.
limit, programmable undervoltage lockout, and current limit
monitoring. The device also includes a high-voltage start-up
bias regulator that operates over a wide input range up to
Detection Signature
60V. The switch mode power supply (SMPS) control portion To detect a potential powered device candidate, the PSE
of the IC includes power good sensing, VCC regulator under- (Power Sourcing Equipment) will apply a voltage from 2.8V
voltage lockout, cycle-by-cycle current limit, error amplifier, to 10V across the input terminals of the PD. The voltage can
slope compensation, softstart, and oscillator sync capability. be of either polarity so a diode barrel network is required on
This high speed BiCMOS IC has total propagation delays both lines to ensure this capability. The PSE will take two
less than 100ns and a 1MHz capable oscillator programmed measurements, separated by at least 1V and 2ms of time.
by a single external resistor. The LM5071 PWM controller The voltage ramp between measurement points will not
provides current-mode control for dc-dc converter topologies exceed 0.1V/us. The delta voltage / delta current calculation
requiring a single drive output, such as Flyback and Forward is then performed; if the detected impedance is above
topologies. The LM5071 PWM enables all of the advantages 23.75kΩ and below 26.25kΩ, the PSE will consider a PD to
of current-mode control including line feed-forward, cycle-by- be present. If the impedance is less than 15kΩ or greater
cycle current limit and simplified loop compensation. The than 33kΩ a PD will be considered not present and will not
oscillator ramp is internally buffered and added to the PWM receive power. Impedances between these values may or
comparator input ramp to provide slope compensation nec- may not indicate the presence of a valid PD. The LM5071
essary for current mode control at duty cycles greater than will enable the signature resistor at a controller input voltage
50% (-80 suffix only). of 1.5V to take into account the diode voltage drops. An
external signature resistor should be placed between the
Modes of Operation VIN and RSIG pins. The signature resistor is in parallel with
the external UVLO resistor divider, and its value should be
The LM5071 PD interface is designed to provide a fully calculated accordingly. Targeting 24.5kΩ increases margin in
compliant IEEE 802.3af system. As such, the modes of the signature design as the input bridge rectifier diodes
operation take into account the barrel rectifiers often utilized contribute to the series resistance measured at the PD input
to correctly polarize the dc input from the Ethernet cable. terminals. The PSE will tolerate no more than 1.9V of offset
Table 1 shows the LM5071 operating modes and associated voltage (caused by the external diodes) or more than 10uA
input voltage range. of offset current (bias current). The input capacitance must
be greater than 0.05uF and less than 0.12uF. To increase
TABLE 1. Operating Modes With Respect to Input efficiency, the signature resistor is disabled by the LM5071
Voltage controller once the input voltage is above the detection
range ( > 11V).
Input Voltage Mode of
VIN wrt VEE Operation Classification
1.8V to 10.0V Detection
To classify the PD, the PSE will present a voltage between
(Signature) 14.5V and 20.5V to the PD. The LM5071 enables classifica-
12.5V to 25.0V Classification tion mode at a nominal input voltage of 11.5V. An internal
25.0V to UVLO Awaiting Full 1.5V linear regulator and an external resistor connected to
the RCLASS pin provide classification programming current.
Rising Vth Power
Table 2 shows the external classification resistor required for
60V to UVLO Normal Powered a particular class.
Falling Vth Operation The classification current flows through the IC into the clas-
sification resistor. The suggested resistor values take into
An external signature resistor is connected to VEE when VIN account the bias current flowing into the IC. A different
exceeds 1.8V, initiating detection mode. During detection desired RCLASS can be calculated by dividing 1.5V by the
mode, quiescent current drawn by the LM5071 is less than desired classification current.
10uA. Between 10.0V and 12.5V, the device enters classifi-
cation mode and the signature resistor is disabled. The Per the IEEE 802.3af specification, classification is optional,
nominal range for classification mode is 11.5V to 25.0V. The and the PSE will default to class 0 if a valid classification
classification current is turned off once the classification current is not detected. If PD classification is not desired
range voltage is exceeded, to reduce power dissipation. (i.e., Class 0), simply leave the RCLASS pin open. The
Between 25.0V and UVLO release, the device is in a classification time period may not last longer than 75ms as
standby state, awaiting the input voltage to reach the opera- per IEEE 802.3af. The LM5071 will remain in classification
tional range to complete the power up sequence. Once the mode until VIN is greater than 25V.
VIN voltage increases above the upper UVLO threshold volt-

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 LM5071
Classification (Continued) of the UVLO set point divider. When the UVLO threshold is
exceeded, the current source is activated to instantly raise
TABLE 2. Classification Levels and Required External the voltage at the UVLO pin. When the UVLO pin voltage
Resistors falls below the 2.00V threshold, the current source is turned
off, causing the voltage at the UVLO pin to fall. The LM5071
Class PMIN PMAX ICLASS ICLASS RCLASS UVLO thresholds cannot be programmed lower than 25V,
(MIN) (MAX) the AUX pin should be used to force UVLO release below
0 0.44W 12.95W 0mA 4mA Open 25V.
1 0.44W 3.84W 9mA 12mA 150Ω There are many additional uses for the UVLO pin. The UVLO
function can also be used to implement a remote enable /
2 3.84W 6.49W 17mA 20mA 82.5Ω
disable function. Pulling the UVLO pin down below the
3 6.49W 12.95W 26mA 30mA 54.9Ω UVLO threshold disables the interface and SMPS controller
4 Reserved Reserved 36mA 44mA 38.3Ω unless forced on via AUX pin operation.

AUX Pin Operation

Undervoltage Lockout (UVLO)
The AUX pin can be used to force operation (UVLO release)
The IEEE 802.3af specification states that the PSE will of the interface and switching regulator at any input voltage
supply power to the PD within 400ms after completion of above 9.5V. This is especially useful for auxiliary input (wall
detection. The LM5071 contains a programmable line Under transformer) input voltages. The pin has a 2.5V threshold
Voltage Lock Out (UVLO) circuit. The first resistor should be (0.5V hysteresis) and an input impedance of approximately
connected between the VIN to UVLO pins; the bottom resis- 350kΩ. The input resistor provides a defined pull down
tor in the divider should be connected between the UVLO impedance if the pin is left open by the user. An external pull
and UVLORTN pins. down resistor should be used to provide additional noise
The divider must be designed such that the voltage at the immunity. The resultant pin voltage from the external resistor
UVLO pin equals 2.0V when VIN reaches the desired mini- divider should be well above the 2.5V threshold to ensure
mum operating level. If the UVLO threshold is not met, the proper auxiliary operation. See Figure 4 for an example of a
interface control and SMPS control will remain in standby. simple yet robust auxiliary configuration.
UVLO hysteresis is accomplished with an internal 10uA
current source that is switched on and off into the impedance

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FIGURE 4. Simplified Schematic Showing Auxiliary Implementation

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LM5071
Power Supply Operation tance range for the VCC regulator output is 0.1uF to 10uF.
When the voltage on the VCC pin reaches the regulation
Once the UVLO threshold has been satisfied, the interface point of 7.8V, the controller output is enabled. The controller
controller of the LM5071 will charge up the SMPS input will remain enabled until VCC falls below 6.25V.
capacitor through the internal power MOSFET. This load
In typical applications, a transformer auxiliary winding is
capacitance provides input filtering for the power converter
diode connected to the VCC pin. This winding should raise
section and must be at least 5uF per the IEEE 802.3af
the VCC voltage above 8.1V to shut off the internal startup
specification. To accomplish the charging in a controlled
regulator. Though not required, powering VCC from an aux-
manner, the power MOSFET is current limited to 100mA.
iliary winding improves conversion efficiency while reducing
The SMPS controller will not initiate operation until the load the power dissipated in the controller. The external VCC
capacitor is completely charged. The power sequencing be- capacitor must be selected such that the capacitor maintains
tween the interface circuitry and the SMPS controller occurs the VCC voltage greater than the VCC UVLO falling threshold
automatically within the LM5071. Detection circuitry monitors (6.25V) during the initial start-up. During a fault condition
the RTN pin to detect interface startup completion. When the when the converter auxiliary winding is inactive, external
RTN pin potential drops below 1.5V with respect to VEE, the current draw on the VCC line should be limited such that the
VCC regulator of the SMPS controller is enabled. The soft- power dissipated in the start-up regulator does not exceed
start function is enabled once the VCC regulator achieves the maximum power dissipation capability of the LM5071
minimum operating voltage. The inrush current limit only package.
applies to the initial charging phase. The interface power
If the VCC auxiliary winding is used with a low voltage aux-
MOSFET current limit will revert to the default protection
iliary supply (wall transformer), the VCC pin could back feed
current limit of 390mA once the SMPS is powered up and the
through the LM5071 to the VIN pin. A diode from VCC to VIN
soft-start pin sequence begins.
should be used to clamp the VCC pin and prevent this
internal back feed. The winding voltage will remain the same
High Voltage Start-up Regulator and extra power will be dissipated in the series resistor. Also,
The LM5071 contains an internal high voltage startup regu- note that when using a very low voltage auxiliary supply
lator that allows the input pin (VIN) to be connected directly to ( < 14V), a diode from the AUX supply to the VCC pin should
line voltages as high as 60V. The regulator output is inter- be used to ensure VCC startup.
nally current limited to 15mA. The recommended capaci-

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FIGURE 5. Simplified Schematic Showing Low Voltage Auxiliary Supply

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 LM5071
Error Amplifier
An internal high gain error amplifier is provided within the
LM5071. The amplifier’s non-inverting reference is set to a
fixed reference voltage of 1.25V. The inverting input is con-
nected to the FB pin. In non-isolated applications, the power LM5071-50:
converter output is connected to the FB pin via voltage
scaling resistors. Loop compensation components are con-
nected between the COMP and FB pins. For most isolated
applications the error amplifier function is implemented on
the secondary side of the converter and the internal error
amplifier is not used. The internal error amplifier is config-
The LM5071 can also be synchronized to an external clock.
ured as an open drain output and can be disabled by con-
The external clock must have a higher frequency than the
necting the FB pin to ARTN. An internal 5K pull-up resistor
free running oscillator frequency set by the RT resistor. The
between a 5V reference and COMP can be used as the
clock signal should be capacitively coupled into the RT pin
pull-up for an optocoupler in isolated applications.
with a 100pF capacitor. A peak voltage level greater than 3.7
volts at the RT pin is required for detection of the sync pulse.
Current Limit / Current Sense The sync pulse width should be set between 15 to 150ns by
The LM5071 provides a cycle-by-cycle over current protec- the external components. The RT resistor is always required,
tion function. Current limit is accomplished by an internal whether the oscillator is free running or externally synchro-
current sense comparator. If the voltage at the current sense nized. The voltage at the RT pin is internally regulated to a 2
comparator input CS exceeds 0.5V with respect to RTN/ volts. The RT resistor should be located very close to the
ARTN, the output pulse will be immediately terminated. A device and connected directly to the pins of the controller
small RC filter, located near the CS pin of the controller, is (RT and ARTN).
recommended to filter noise from the current sense signal.
The CS input has an internal MOSFET which discharges the PWM Comparator / Slope
CS pin capacitance at the conclusion of every cycle. The
discharge device remains on an additional 50ns after the Compensation
beginning of the new cycle to attenuate the leading edge The PWM comparator compares the current ramp signal
spike on the current sense signal. with the loop error voltage derived from the error amplifier
The LM5071 current sense and PWM comparators are very output. The error amplifier output voltage at the COMP pin is
fast, and may respond to short duration noise pulses. Layout offset by 1.4V and then further attenuated by a 3:1 resistor
considerations are critical for the current sense filter and divider. The PWM comparator polarity is such that 0 Volts on
sense resistor. The capacitor associated with the CS filter the COMP pin will result in zero duty cycle at the controller
must be located very close to the device and connected output. For duty cycles greater than 50 percent, current
directly to the pins of the controller (CS and ARTN). If a mode control circuits are subject to sub-harmonic oscillation.
current sense transformer is used, both leads of the trans- By adding an additional fixed slope voltage ramp signal
former secondary should be routed to the sense resistor and (slope compensation) to the current sense signal, this oscil-
the current sense filter network. A sense resistor located in lation can be avoided. The LM5071-80 integrates this slope
the source of the primary power MOSFET may be used for compensation by summing a current ramp generated by the
current sensing, but a low inductance resistor is required. oscillator with the current sense signal. Additional slope
When designing with a current sense resistor, all of the noise compensation may be added by increasing the source im-
sensitive low power ground connections should be con- pedance of the current sense signal (with an external resis-
nected together local to the controller and a single connec- tor between the CS pin and current sense resistor). Since
tion should be made to the high current power return (sense the LM5071-50 is not capable of duty cycles greater than
resistor ground point). 50%, there is no slope compensation feature in this device.

Oscillator, Shutdown and Sync Softstart

Capability The softstart feature allows the power converter to gradually
reach the initial steady state operating point, thereby reduc-
A single external resistor connected between the RT and ing start-up stresses, output overshoot and current surges.
ARTN pins sets the LM5071 oscillator frequency. Internal to At power on, after the VCC undervoltage lockout threshold is
the LM5071–50 device (50% duty cycle limited option) is an satisfied, an internal 10µA current source charges an exter-
oscillator divide by two circuit. This divide by two circuit nal capacitor connected to the SS pin. The capacitor voltage
creates an exact 50% duty cycle clock which is used inter- will ramp up slowly and will limit the COMP pin voltage and
nally to create a precise 50% duty cycle limit function. Be- the duty cycle of the output pulses.
cause of this divide by two, the internal oscillator actually
operates at twice the frequency of the output (OUT). For the
LM5071–80 device the oscillator frequency and the opera-
Gate Driver and Maximum Duty
tional output frequency are the same. To set a desired output Cycle Limit
operational frequency (F), the RT resistor can be calculated The LM5071 provides an internal gate driver (OUT), which
from: can source and sink a peak current of 800mA. The LM5071
LM5071-80: is available in two duty cycle limit options. The maximum
output duty cycle is typically 80% for the LM5071-80 option
and precisely equal to 50% for the LM5071-50 option. The
maximum duty cycle function for the LM5071-50 is accom-

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LM5071
Gate Driver and Maximum Duty perature is exceeded. This feature prevents catastrophic
failures from accidental device overheating. When activated,
Cycle Limit (Continued) typically at 165 degrees Celsius, the controller is forced into
a low power standby state, disabling the output driver, bias
plished with an internal toggle flip-flop which ensures an
regulator, main interface pass MOSFET, and classification
accurate duty cycle limit. The internal oscillator frequency of
regulator if enabled. After the temperature is reduced (typical
the LM5071-50 is therefore twice the operating frequency of
hysteresis = 25˚C ) the VCC regulator will be enabled and a
the PWM controller (OUT pin).
softstart sequence initiated.
The 80% maximum duty cycle limit of the LM5071-80 is
Thermal shutdown is not enabled during auxiliary power
determined by the internal oscillator and varies more than
operation as the power MOSFET is not running any current
the 50% limit of the LM5071-50. For the LM5071-80, the
and should not experience an over-temperature condition. If
internal oscillator frequency and the operational frequency of
the drain of the MOSFET exceeds 2.5V with respect to VEE
the PWM controller are equal.
(internal Power Good de-assertion), PoE UVLO becomes
de-asserted (insertion of PoE or other 48V supply), or the
Thermal Protection auxiliary power is removed, thermal limit will be re-enabled
Internal thermal shutdown circuitry is provided to protect the immediately.
integrated circuit in the event the maximum junction tem-

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 LM5071 Application Circuit Diagrams

15
20168424

FIGURE 6. Single Isolated Output with Diode Rectification and 12V Auxiliary Supply

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LM5071
 LM5071

LM5071 Application Circuit Diagrams (Continued)

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20168425

FIGURE 7. Dual Isolated Output with Diode Rectification

 LM5071 Application Circuit Diagrams (Continued)

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20168426

FIGURE 8. Non-Isolated Output Buck with Diode Rectification

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LM5071
LM5071 Power Over Ethernet PD Controller with Auxiliary Power Interface
Physical Dimensions inches (millimeters) unless otherwise noted

Package Number MTC16

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