MICROPROCESSOR 8086

Genesis: Microprocessor
 1971: First Generation Microprocessor Intel
4004, four bit
 1972: First generation Microprocessor Intel 8008,
8 bit, PMOS (slower)
 1973: Second generation microprocessor Intel
8080, 8 bit, NMOS (faster)
 1975: Second generation microprocessor Intel
8085, 8 bit, NMOS, Single power pin (+5 V)
 1978: Third generation microprocessor Intel
8086 and 8088, 16 bit
 Fourth Generation Microprocessor: 80386, 32 bit
 Fifth Generation: Intel Pentium

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FEATURES

 40 PIN DIL HMOS WITH 29000 Transistors, INTEL IC, +5V, 3rd Generation, 1978, for
PCs
 Clock Frequency: 5-10 MHz (8086A: 10MHz) with 33% Duty cycle. Needs external
clock generator IC Intel 8284.
 16 bit 3rd Generation ALU (Signed number range: -32768d to 32767d, Unsigned
number range: 0-65535d)
 Address Bus 20 Bit-> 1MB memory can be interfaced
 Follows logical Addressing scheme (Memory segmentation, Multiprogramming,
Dynamic relocation)
 Multiprocessor mode
 Instruction Queue for prefetching instruction bytes and fetch execution overlap,
leading to much higher execution speed as compared to 8085
 External physical Memory interfaced in two memory banks

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 DIFFERENCES WITH INTEL 8085
8085 MICROPROCESSOR 8086 MICROPROCESSOR

40 Pin IC, NMOS 6200 Transistors 40 Pin IC, HMOS 29,000 Transistors

Clock frequency is 3-5 MHz. 50% Duty Clock frequency is 5-10 MHz. It does not
cycle Internal crystal oscillator have an internal oscillator, needs and
external clock generator IC 8284 to
generate clock pulses. Needs a clock
pulse of duty cycle 33%
Data Bus width: 8 bits Data Bus width: 16 bits

Address bus width: 16 bits. Hence Address bus width: 20 bits. Hence
maximum memory that can be connected maximum memory that can be interfaced
is of 64 KB is 1 MB
Memory ICs or IO ports with word size of 8 Memory ICs or IO ports with word size of 8
bits are connected with the 8 bit data bus bits are connected with 16 bit data bus of
of microprocessor in single bank microprocessor in 2 banks (high and low
banks) 4
 DIFFERENCES WITH INTEL 8085
8085 MICROPROCESSOR 8086 MICROPROCESSOR

IO port address is of 8 bits (00H to FFH). IO port address is of 16 bits from 0000H to
Thus 256 IO devices can be connected FFFFH. Hence theoretically 65535 IO ports
can be implemented
Memory access follows physical addressing Memory access follows logical addressing
scheme scheme
Physical memory is not divided into Physical memory is divided into 4 logical
segments segments namely; Code memory segment
(CMS), data memory segment (DMS), Extra
memory segment (EMS) and Stack Memory
segment (SMS)
Do Not contain instruction queue. Hence Contains six registers of 8 bits in an
fetch and execute overlap of instructions instruction queue. Hence there is fetch
is very limited execute overlap leading to very fast
program execution
Used in single processor system Designed to operate in multiprocessor
environment (minimum and maximum
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mode)
 DIFFERENCES WITH INTEL 8085
8085 MICROPROCESSOR 8086 MICROPROCESSOR

It is slower It is faster

Instruction set is less powerful Instruction set is more powerful with

multiplication, division, ASCII adjuster
instructions, iteration control and string
instructions

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CPU ARCHITECTURE

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Architecture

 Vonn Neumann Architecture, 3rd generation ALU, Instruction Queue, Logical

addressing
 Contains two independent Units: Bus Interface Unit (BIU) and Execution Unit
(EU)
 BIU Handles all the data and address transfers for execution unit
 EU performs instruction execution and also tells BIU where to fetch
instructions and data during different machine cycles

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BUS INTERFACE UNIT (BIU)

 Handles Data and Address Transfer for EU:

 Contains: PAG, Seg. Reg., IP and IQ
 Functions of BIU
 Generates 20 bit physical address from the contents of Seg reg and memory pointer
registers in EU
 Loads the 20 bit physical address on address bus during (i) memory/IO Read/write
machine cycle
 Issues control signals like RD-bar, WR-bar, DEN-bar, DT/R-bar in corresponding
machine cycles
 Carries out data transfer through data lines

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EXECUTION UNIT (EU)

 Performs instruction execution and also tells BIU where to fetch instructions
and data during different machine cycles
 Reads instruction opcodes from register 1 of IQ and decodes and executes this
instruction
 Performs internal arithmetic, logical and data transfer operations
 Tells to BIU the memory address from where the data or next instruction
needs to be fetched as a part of instruction execution during OF and Memory
read/Write machine cycles.

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ARITHMETIC AND LOGIC UNIT (ALU)

 16 bit 3rd generation ALU

 Arithmetic operations supported:
 Addition, subtraction, multiplication, division of 8/16 bit binary numbers
 Adjuster instructions for BCD and ASCII operands during addition, subtraction,
multiplication and division operations
 Comparison of signed/unsigned, 8/16 bit numbers
 Increment/ Decrement of 8/16 bit binary numbers
 Twos complement of binary numbers
 Logical operations:
 AND, OR, NOT (complement), EXOR
 Rotate/ shift, of 8/16 bit data with/without carry flag

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REGISTERS

 SEGMENT REGISTERS: CS, DS, ES, SS

 GENERAL PURPOSE DATA REGISTERS: AX, BX, CX, DX
 MEMORY POINTERS: IP, SP, BP, SI, DI
 Index Registers: SI, DI
 Base Registers: BX, BP
 Pointer Registers: IP, SP
 Instruction Queue (IQ)
 FLAG REGISTER

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GENERAL PURPOSE REGISTERS

 AX: 8 (AL)/16 bit accumulator

 BX: Base register used to store 16 bit address during memory related
addressing modes, besides the regular use to store 16 bit data
 CX: Counter register
 CL: 8 bit counter for shift/rotate instructions
 CX: 16 bit counter for iteration control instructions
 DX: Data register used to hold 16 bit data and also to hold 16 bit Port address
during execution of IN/OUT instructions

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 Effective DEFAULT
Physical Logical address SEGMENT
MEMORY REGISTERS address MEMORY POINTER
Address (SBA:EA) REGISTER

Memory segmentation
(EA) REGISTER
00000H
00001H

From Segment Register 10000H 1000:0000H 0000H

10001H CMS (64KB) 1000:0001H 0001H
*****H 1000:**EA** **EA** CS=1000H IP
1FFFEH 1000:FFFEH FFFEH
IFFFFH 1000:FFFFh FFFFH

SEGMENT BASE ADDRESS (16 BITS) 0000B

30000H 3000:0000H 0000H

+ EFFECTIVE ADDRESS 30001H DMS (64KB) 3000:0001H 0001H

*****H 3000:**EA** **EA** DS=3000H BX/SI/DI
PHYSICAL ADDRESS 3FFFEH 3000:FFFEH FFFEH
3FFFFH 3000:FFFFh FFFFH

50000H 5000:0000H 0000H

From memory pointer DI (for
50001H EMS (64KB) 5000:0001H 0001H
string
Register *****H 5000:**EA** **EA** ES=5000H
instruction
5FFFEH 5000:FFFEH FFFEH
s)
5FFFFH 5000:FFFFh FFFFH

A0000H A000:0000H 0000H

To Address Bus A0001H SMS (64KB) A000:0001H 0001H
A19-AD0 *****H A000:**EA** **EA** SS=A000H SP/BP
AFFFEH A000:FFFEH FFFEH
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AFFFFH A000:FFFFh FFFFH

FFFFFH
Different types of addresses
 Physical Address: The 20 bit address that is physically loaded on the address bus
of 8086 system.
 Segment Base address (SBA): Upper 16 bits of the 20 bit physical address of the
starting location of a memory segment. SBA is available from the designated
segment register of the memory segment to be accessed.
 Base address: The physical address of the starting location of a memory segment.
The last 4 bits of the base address is always 0000 binary.
 Effective address/Displacement address (EA): The number of memory locations
after which a given memory register occurs from the starting location of a memory
segment. In other words, the displacement of a given memory location with
respect to the base address of a memory segment is known as effective address.
EA is available either from the designated memory pointer register dedicated for a
given task (e.g. code fetch/PUSH-POP/Data read-write operation) or as mentioned
in the instruction being executed.
 A program refers to a memory location as logical address pairs; i.e. in terms of
SBA and EA (symbolically denoted as: SBA:EA)
 During execution of the program, the Physical address generator (PAG) converts
the logical address into 20 bit physical address; that is loaded on address bus.
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Pin Diagram of 8086
 Common pins/signals
 AD15-AD0, A19/S6, A18/S5, A17/S4,
A16/S3, CLK, GnD, Vss, NMI, INTR, BHE-
bar/S7, MN/MX-bar, RD-bar, TEST-bar,
READY, RESET
 Minimum mode signals/pins
 HOLD, HLDA, WR-bar, M/IO-bar, DT/R-
bar, DEN-bar, ALE, INTA-bar
 Maximum mode signals/Pins
 RQ0-bar/GT0-bar, RQ1-bar/GT1-bar,
LOCK-bar, S2-bar, S1-bar, S0-bar, QS0,
QS1

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de-multiplexing of Address data and
Control pins using ALE
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DT/R-bar
and DEN-
bar signals
used for
buffered
systems

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Deriving Active low extended memory control
signals (using M/IO-bar, WR-bar and RD-bar)
M/IO-bar RD-bar WR-bar Control
Operation
0 0 1 I/O Read
0 1 0 I/O Write
1 0 1 Memory Read
1 1 0 Memory write

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20
The 8086
Minimum
Mode system

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Bus activity/Timing
diagram for the
minimum mode
operation of 8086
(MRMC and MWMC) with
one WAIT state in each
bus cycle (observe
READY=0).
The M/IO-bar signal has
logic state 1 and is not
shown in the diagram

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 BHE-bar/S7
 Bank High Enable/Bus High  The S7 state is always 0 for 8086 and
enable available from T2 onwards
 During T1 clock state, the BHE-  The BHE signal is used to enable data onto
bar/S7 pin carries BHE-bar signal the most significant half of the data bus:
that varies according to D15-D8
following rule:  The eight bit oriented devices tied to the
upper half of the data bus uses BHE signal
to derive chip select signals

Case No Data Address of Least BHE A0 Machine Bank to Active

Size Significant Byte bar Cycles be Data Bus
required selected

1 Byte Odd 0 1 1 Odd D15-D8

2 Byte Even 1 0 1 Even D7-D0

3 Word Even 0 0 1 Both D15-D0

4 Odd 0 1 1 Odd
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D15-D8
Word
Even 1 0 1 Even D7-D0
CS bar from BHE/S7

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 HOLD and HLDA HOLD HRQ

1. Direct data transfer between memory and HLDA HLDA

IO device without the intervention of

microprocessor is called Direct memory
Access (DMA) Microprocessor DMA Controller
2. IC 8237/8257 are called DMA controller ICs 8085/8086 8237/8257

as they control and facilitate the data

transfer process between IO Devices and
memory on behalf of microprocessor
3. To start DMA operation 8257 will make HRQ
pin high, thus HOLD pin of microprocessor
is driven high
4. Microprocessor check the status of HOLD pin
at every positive edge of each clock pulse.
5. If HOLD is found high, then:
1. Microprocessor will complete the System Bus (ADDRESS, DATA AND CONTROL BUS)
current machine cycle
2. Then microprocessor will enter HOLD
state (except: for word transfer from
odd address, INTA bar machine cycle
and if LOCK instruction is processed)
3. In HOLD state microprocessor will not MEMORY
IO DEVICES AND IO
perform any operation and its PORTS

address, data and control pins (local 25

bus) are driven to high impedence

state
HOLD and HLDA pins
 After microprocessor 8086 enters the hold state it issues HLDA=1, which
indicates that microprocessor has gone in HOLD state (BIU stops its fetching
operation and EU may continue execution until it does not require system
bus, after which EU also stops execution)
 On receiving HLDA=1, DMA controller will use the system bus to carry out data
transfer between memory and IO devices.
 After the DMA controller finishes its operation it will drive HOLD pin of
microprocessor LOW.
 In response to HOLD=0, microprocessor will come out of HOLD state and will
drive its HLDA output LOW again.
 The microprocessor regains the control on system bus when it comes out of
HOLD state

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LOCK bar pin (output)

 LOCK is a prefix instruction.

 When any instruction of microprocessor is prefixed with LOCK instruction
 Eg: LOCK XCHG
 Then microprocessor will drive LOCK-bar pin LOW while the prefixed
instruction is being executed
 The LOCK-bar pin of microprocessor is connected to bus controller (master)
 On receiving logic LOW on LOCK pin of 8086, the bus controller will keep the
system bus locked with microprocessor 8086.
 In other words, Bus controller will not allocate the system bus to any other
processor till the lock prefixed instruction is executed completely.

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