PD Interview

Q 1.What is physical design?
A. The physical design is the process of transforming a

circuit description into the physical layout which describes
position of the cells and routs for the interconnections
between them.
Q 2.which design is more complicated 10MHZ or

100MHz?
A. 100mhz. because high frequency means low time
period.So it is difficult to handle the violations in low time
period.
Q 3.what is floor planing?

A. The floor plan is a process of determining the macro
placement,power grid generation and I/O placement.
Q 4.If you have both IR drop and congestion how will

you fix it?
A. a) Spreed macros.
b) Spreed standard cells.
c) Increase strap width.
d) Increase no.of straps.
e) Use proper blockage.
Q 5.What are the Tie-high and Tie-low cells?

A. These are used to connect the gate of transistor to
either power or ground.It avoid direct connection between
power and gate of transistor.
Tie-high:- One terminal is connected to vdd and another
terminal is connected to gate of transistor.
Tie-low:- One terminal is connected to vss and another
terminal is connected to gate of transistor.
Q 6.What are the checks to be done before cts?

A. a) Placement -completed.
b) Power ground nets -pre-routed.
c) Estimated congestion -acceptable.
d) Estimated timing -acceptable.
e) Estimated max transition/capacitance -no violations.
f) High fan-out nets.
Q 7.What are the power gating cells?

A. The power gating is to avoid static power
dissipation.The power gating cells are
a) Power switches.
b) Level sifters.
c) Retention registers.
d) Isolation cells.
e) Power controller.
Q 8.What is HFNS(high fan-out net synthesis)?

A. HFNS is the process of buffering the high fan-out nets
to balance the load.
Q 9.Where HFNS is used?

A. Generally at placement stage HFNS is performed.it is
also performed at synthesis step using design compiler.
Q 10.What is Electromigration(EM)?
A. When high current density continuously flows through a
metal due to the high current the atoms moving with
kinetic energy and they transfer the energy to another
atoms and increases the temperature due to these the
metal will damage.
Q 11.Is zero skew is possible?
A. Practically it is not possible because all the flip flops are
not getting the same clock.The skew is exist when the two
different clocks are present.Zero skew means all clocks
are same practically it is not possible.
Q 12.How to reduce latchup problem?

A. a) Increase spacing between p-well and n-well.
b) Increase well/substrate doping concentration.
c) Use ground rings around device.
Q 13.What are the check list after cts?

A. a) Skew report.
b) Clock tree report.
c) Timing reports for setup and hold.
d) Power and area report.
Q 14.What is synthesis?
A. It is a process to convert RTL code into design
implementation.
Q 15.which metal layer will be used for clock in 7

metal layer design.why?
A. Metal 4 and 5.because the clock nets will consume 30
to 40% of power in the design.So to reduce the IR drop we
are using low resistance metal.top 6,7 metal layers for
power connection and 5,4 for clock nets.
Q 16.What is antenna effect?

A. Increasing net length can accumulate more changes
while manufacturing of the device due to the ionization
process.If this net is connected to gate of the MOSFET it
can damage dielectric property of gate and causing
damage to MOSFET.
Q 17.What is cloning and buffering?

A. Cloning:-it is a method of optimization that decrease the
load of heavily loaded cell by replacing the cell.
Buffering:-it is a method of optimization that is used to
insert buffer in high fan out nets to decrease the delay.
Q 18.Why NAND gate is preferred than NOR?

A. At transistor level the mobility of electrons is normally
three times that of holes compared to nor and NAND gate
is faster,less leakage.
Q 19.What is LVS(layout vs schematic)?

A. It is a class of EDA software that determines whether a
particular IC layout corresponds to the original schematic
of design.
Q 20.What is shielding?
A. Placing ground net in between aggressor and victim
nets then voltage discharge on ground net.This will reduce
the cross-talk.
Q 21.What is isolation cell?

A. These are special cells required at the interface
between blocks which are shutdown and always on.It is
necessary to isolate the floating inputs.

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Q 1.What is physical design?

A. The physical design is the process of transforming a

Q 2.which design is more complicated 10MHZ or

Q 3.what is floor planing?

Q 4.If you have both IR drop and congestion how will

Q 5.What are the Tie-high and Tie-low cells?

Q 6.What are the checks to be done before cts?

Q 7.What are the power gating cells?

Q 8.What is HFNS(high fan-out net synthesis)?

Q 9.Where HFNS is used?

Q 12.How to reduce latchup problem?

Q 13.What are the check list after cts?

Q 15.which metal layer will be used for clock in 7

Q 16.What is antenna effect?

Q 17.What is cloning and buffering?

Q 18.Why NAND gate is preferred than NOR?

Q 19.What is LVS(layout vs schematic)?

Q 21.What is isolation cell?

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